spi: Add SPI master controller for OCTEON SOCs.

Add the driver, link it into the kbuild system and provide device tree
binding documentation.

Signed-off-by: David Daney <david.daney@cavium.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Patchwork: http://patchwork.linux-mips.org/patch/4292/
Signed-off-by: John Crispin <blogic@openwrt.org>

1 files changed, 33 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/spi/spi-octeon.txt b/Documentation/devicetree/bindings/spi/spi-octeon.txt
new file mode 100644
index 000000000000..431add192342
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-octeon.txt
@@ -0,0 +1,33 @@
+Cavium, Inc. OCTEON SOC SPI master controller.
+
+Required properties:
+- compatible : "cavium,octeon-3010-spi"
+- reg : The register base for the controller.
+- interrupts : One interrupt, used by the controller.
+- #address-cells : <1>, as required by generic SPI binding.
+- #size-cells : <0>, also as required by generic SPI binding.
+
+Child nodes as per the generic SPI binding.
+
+Example:
+
+        spi@1070000001000 {
+                compatible = "cavium,octeon-3010-spi";
+                reg = <0x10700 0x00001000 0x0 0x100>;
+                interrupts = <0 58>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                eeprom@0 {
+                        compatible = "st,m95256", "atmel,at25";
+                        reg = <0>;
+                        spi-max-frequency = <5000000>;
+                        spi-cpha;
+                        spi-cpol;
+
+                        pagesize = <64>;
+                        size = <32768>;
+                        address-width = <16>;
+                };
+        };
+