diff options
| author | HighPoint Linux Team <linux@highpoint-tech.com> | 2012-10-24 20:41:52 -0400 |
|---|---|---|
| committer | James Bottomley <JBottomley@Parallels.com> | 2012-11-26 23:59:43 -0500 |
| commit | 286aa031664ba5223bcb3dfd49a9e2d89d6b3aec (patch) | |
| tree | 3d1adf4d0440dffb1dda053a10b9c45b0fd8c5bb /Documentation/scsi | |
| parent | b83908ce845311061eaabf2d8dc9b182907dbc5f (diff) | |
[SCSI] hptiop: Support HighPoint RR4520/RR4522 HBA
Support IOP RR4520/RR4522 which are based on Marvell frey.
Signed-off-by: HighPoint Linux Team <linux@highpoint-tech.com>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>
Diffstat (limited to 'Documentation/scsi')
| -rw-r--r-- | Documentation/scsi/hptiop.txt | 69 |
1 files changed, 65 insertions, 4 deletions
diff --git a/Documentation/scsi/hptiop.txt b/Documentation/scsi/hptiop.txt index 9605179711f4..4a4f47e759cd 100644 --- a/Documentation/scsi/hptiop.txt +++ b/Documentation/scsi/hptiop.txt | |||
| @@ -37,7 +37,7 @@ For Intel IOP based adapters, the controller IOP is accessed via PCI BAR0: | |||
| 37 | 0x40 Inbound Queue Port | 37 | 0x40 Inbound Queue Port |
| 38 | 0x44 Outbound Queue Port | 38 | 0x44 Outbound Queue Port |
| 39 | 39 | ||
| 40 | For Marvell IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1: | 40 | For Marvell not Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1: |
| 41 | 41 | ||
| 42 | BAR0 offset Register | 42 | BAR0 offset Register |
| 43 | 0x20400 Inbound Doorbell Register | 43 | 0x20400 Inbound Doorbell Register |
| @@ -55,9 +55,31 @@ For Marvell IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1: | |||
| 55 | 0x40-0x1040 Inbound Queue | 55 | 0x40-0x1040 Inbound Queue |
| 56 | 0x1040-0x2040 Outbound Queue | 56 | 0x1040-0x2040 Outbound Queue |
| 57 | 57 | ||
| 58 | For Marvell Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1: | ||
| 58 | 59 | ||
| 59 | I/O Request Workflow | 60 | BAR0 offset Register |
| 60 | ---------------------- | 61 | 0x0 IOP configuration information. |
| 62 | |||
| 63 | BAR1 offset Register | ||
| 64 | 0x4000 Inbound List Base Address Low | ||
| 65 | 0x4004 Inbound List Base Address High | ||
| 66 | 0x4018 Inbound List Write Pointer | ||
| 67 | 0x402C Inbound List Configuration and Control | ||
| 68 | 0x4050 Outbound List Base Address Low | ||
| 69 | 0x4054 Outbound List Base Address High | ||
| 70 | 0x4058 Outbound List Copy Pointer Shadow Base Address Low | ||
| 71 | 0x405C Outbound List Copy Pointer Shadow Base Address High | ||
| 72 | 0x4088 Outbound List Interrupt Cause | ||
| 73 | 0x408C Outbound List Interrupt Enable | ||
| 74 | 0x1020C PCIe Function 0 Interrupt Enable | ||
| 75 | 0x10400 PCIe Function 0 to CPU Message A | ||
| 76 | 0x10420 CPU to PCIe Function 0 Message A | ||
| 77 | 0x10480 CPU to PCIe Function 0 Doorbell | ||
| 78 | 0x10484 CPU to PCIe Function 0 Doorbell Enable | ||
| 79 | |||
| 80 | |||
| 81 | I/O Request Workflow of Not Marvell Frey | ||
| 82 | ------------------------------------------ | ||
| 61 | 83 | ||
| 62 | All queued requests are handled via inbound/outbound queue port. | 84 | All queued requests are handled via inbound/outbound queue port. |
| 63 | A request packet can be allocated in either IOP or host memory. | 85 | A request packet can be allocated in either IOP or host memory. |
| @@ -101,6 +123,45 @@ register 0. An outbound message with the same value indicates the completion | |||
| 101 | of an inbound message. | 123 | of an inbound message. |
| 102 | 124 | ||
| 103 | 125 | ||
| 126 | I/O Request Workflow of Marvell Frey | ||
| 127 | -------------------------------------- | ||
| 128 | |||
| 129 | All queued requests are handled via inbound/outbound list. | ||
| 130 | |||
| 131 | To send a request to the controller: | ||
| 132 | |||
| 133 | - Allocate a free request in host DMA coherent memory. | ||
| 134 | |||
| 135 | Requests allocated in host memory must be aligned on 32-bytes boundary. | ||
| 136 | |||
| 137 | - Fill the request with index of the request in the flag. | ||
| 138 | |||
| 139 | Fill a free inbound list unit with the physical address and the size of | ||
| 140 | the request. | ||
| 141 | |||
| 142 | Set up the inbound list write pointer with the index of previous unit, | ||
| 143 | round to 0 if the index reaches the supported count of requests. | ||
| 144 | |||
| 145 | - Post the inbound list writer pointer to IOP. | ||
| 146 | |||
| 147 | - The IOP process the request. When the request is completed, the flag of | ||
| 148 | the request with or-ed IOPMU_QUEUE_MASK_HOST_BITS will be put into a | ||
| 149 | free outbound list unit and the index of the outbound list unit will be | ||
| 150 | put into the copy pointer shadow register. An outbound interrupt will be | ||
| 151 | generated. | ||
| 152 | |||
| 153 | - The host read the outbound list copy pointer shadow register and compare | ||
| 154 | with previous saved read ponter N. If they are different, the host will | ||
| 155 | read the (N+1)th outbound list unit. | ||
| 156 | |||
| 157 | The host get the index of the request from the (N+1)th outbound list | ||
| 158 | unit and complete the request. | ||
| 159 | |||
| 160 | Non-queued requests (reset communication/reset/flush etc) can be sent via PCIe | ||
| 161 | Function 0 to CPU Message A register. The CPU to PCIe Function 0 Message register | ||
| 162 | with the same value indicates the completion of message. | ||
| 163 | |||
| 164 | |||
| 104 | User-level Interface | 165 | User-level Interface |
| 105 | --------------------- | 166 | --------------------- |
| 106 | 167 | ||
| @@ -112,7 +173,7 @@ The driver exposes following sysfs attributes: | |||
| 112 | 173 | ||
| 113 | 174 | ||
| 114 | ----------------------------------------------------------------------------- | 175 | ----------------------------------------------------------------------------- |
| 115 | Copyright (C) 2006-2009 HighPoint Technologies, Inc. All Rights Reserved. | 176 | Copyright (C) 2006-2012 HighPoint Technologies, Inc. All Rights Reserved. |
| 116 | 177 | ||
| 117 | This file is distributed in the hope that it will be useful, | 178 | This file is distributed in the hope that it will be useful, |
| 118 | but WITHOUT ANY WARRANTY; without even the implied warranty of | 179 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
