Merge branch 'for-4.12/asus' into for-linus

204 files changed, 3553 insertions, 424 deletions

diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt
index 9b2b41ab6817..c246cd2730d9 100644
--- a/Documentation/devicetree/bindings/arm/amlogic.txt
+++ b/Documentation/devicetree/bindings/arm/amlogic.txt
@@ -40,6 +40,8 @@ Board compatible values:
   - "hardkernel,odroid-c2" (Meson gxbb)
   - "amlogic,p200" (Meson gxbb)
   - "amlogic,p201" (Meson gxbb)
+  - "wetek,hub" (Meson gxbb)
+  - "wetek,play2" (Meson gxbb)
   - "amlogic,p212" (Meson gxl s905x)
   - "amlogic,p230" (Meson gxl s905d)
   - "amlogic,p231" (Meson gxl s905d)
diff --git a/Documentation/devicetree/bindings/arm/axentia.txt b/Documentation/devicetree/bindings/arm/axentia.txt
new file mode 100644
index 000000000000..ea3fb96ae465
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/axentia.txt
@@ -0,0 +1,19 @@
+Device tree bindings for Axentia ARM devices
+============================================
+
+Linea CPU module
+----------------
+
+Required root node properties:
+compatible = "axentia,linea",
+             "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
+and following the rules from atmel-at91.txt for a sama5d31 SoC.
+
+
+TSE-850 v3 board
+----------------
+
+Required root node properties:
+compatible = "axentia,tse850v3", "axentia,linea",
+             "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
+and following the rules from above for the axentia,linea CPU module.
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index a1bcfeed5f24..698ad1f097fa 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -158,6 +158,7 @@ nodes to be present and contain the properties described below.
                             "arm,cortex-a53"
                             "arm,cortex-a57"
                             "arm,cortex-a72"
+                            "arm,cortex-a73"
                             "arm,cortex-m0"
                             "arm,cortex-m0+"
                             "arm,cortex-m1"
@@ -202,6 +203,7 @@ nodes to be present and contain the properties described below.
                             "marvell,armada-380-smp"
                             "marvell,armada-390-smp"
                             "marvell,armada-xp-smp"
+                            "marvell,98dx3236-smp"
                             "mediatek,mt6589-smp"
                             "mediatek,mt81xx-tz-smp"
                             "qcom,gcc-msm8660"
diff --git a/Documentation/devicetree/bindings/arm/davinci.txt b/Documentation/devicetree/bindings/arm/davinci.txt
index f0841ce725b5..715622c36260 100644
--- a/Documentation/devicetree/bindings/arm/davinci.txt
+++ b/Documentation/devicetree/bindings/arm/davinci.txt
@@ -13,6 +13,10 @@ EnBW AM1808 based CMC board
 Required root node properties:
     - compatible = "enbw,cmc", "ti,da850;
 
+LEGO MINDSTORMS EV3 (AM1808 based)
+Required root node properties:
+    - compatible = "lego,ev3", "ti,da850";
+
 Generic DaVinci Boards
 ----------------------
 
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index d6ee9c6e1dbb..c9c567ae227f 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -108,7 +108,7 @@ status.
   - compatible: Should contain a chip-specific compatible string,
         Chip-specific strings are of the form "fsl,<chip>-scfg",
         The following <chip>s are known to be supported:
-        ls1021a, ls1043a, ls1046a, ls2080a.
+        ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
 
   - reg: should contain base address and length of SCFG memory-mapped registers
 
@@ -126,7 +126,7 @@ core start address and release the secondary core from holdoff and startup.
   - compatible: Should contain a chip-specific compatible string,
         Chip-specific strings are of the form "fsl,<chip>-dcfg",
         The following <chip>s are known to be supported:
-        ls1021a, ls1043a, ls1046a, ls2080a.
+        ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
 
   - reg : should contain base address and length of DCFG memory-mapped registers
 
@@ -139,6 +139,22 @@ Example:
 Freescale ARMv8 based Layerscape SoC family Device Tree Bindings
 ----------------------------------------------------------------
 
+LS1012A SoC
+Required root node properties:
+    - compatible = "fsl,ls1012a";
+
+LS1012A ARMv8 based RDB Board
+Required root node properties:
+    - compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
+
+LS1012A ARMv8 based FRDM Board
+Required root node properties:
+    - compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
+
+LS1012A ARMv8 based QDS Board
+Required root node properties:
+    - compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
+
 LS1043A SoC
 Required root node properties:
     - compatible = "fsl,ls1043a";
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 7df79a715611..f1c1e21a8110 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -1,5 +1,9 @@
 Hisilicon Platforms Device Tree Bindings
 ----------------------------------------------------
+Hi3660 SoC
+Required root node properties:
+        - compatible = "hisilicon,hi3660";
+
 Hi4511 Board
 Required root node properties:
         - compatible = "hisilicon,hi3620-hi4511";
diff --git a/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
new file mode 100644
index 000000000000..26eb9d3aa630
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
@@ -0,0 +1,16 @@
+Resume Control
+--------------
+Available on Marvell SOCs: 98DX3336 and 98DX4251
+
+Required properties:
+
+- compatible: must be "marvell,98dx3336-resume-ctrl"
+
+- reg: Should contain resume control registers location and length
+
+Example:
+
+resume@20980 {
+        compatible = "marvell,98dx3336-resume-ctrl";
+        reg = <0x20980 0x10>;
+};
diff --git a/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt b/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt
new file mode 100644
index 000000000000..64e8c73fc5ab
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt
@@ -0,0 +1,23 @@
+Marvell 98DX3236, 98DX3336 and 98DX4251 Platforms Device Tree Bindings
+----------------------------------------------------------------------
+
+Boards with a SoC of the Marvell 98DX3236, 98DX3336 and 98DX4251 families
+shall have the following property:
+
+Required root node property:
+
+compatible: must contain "marvell,armadaxp-98dx3236"
+
+In addition, boards using the Marvell 98DX3336 SoC shall have the
+following property:
+
+Required root node property:
+
+compatible: must contain "marvell,armadaxp-98dx3336"
+
+In addition, boards using the Marvell 98DX4251 SoC shall have the
+following property:
+
+Required root node property:
+
+compatible: must contain "marvell,armadaxp-98dx4251"
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
index 05f95c3ed7d4..8219b2c6bb29 100644
--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
@@ -151,6 +151,9 @@ Boards:
 - AM335X SBC-T335 : single board computer, built around the Sitara AM3352/4
   compatible = "compulab,sbc-t335", "compulab,cm-t335", "ti,am33xx"
 
+- AM335X phyCORE-AM335x: Development kit
+  compatible = "phytec,am335x-pcm-953", "phytec,am335x-phycore-som", "ti,am33xx"
+
 - OMAP5 EVM : Evaluation Module
   compatible = "ti,omap5-evm", "ti,omap5"
 
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index 253bf9b86690..c9502634316d 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -75,7 +75,7 @@ Boards:
     compatible = "renesas,rskrza1", "renesas,r7s72100"
   - Salvator-X (RTP0RC7795SIPB0010S)
     compatible = "renesas,salvator-x", "renesas,r8a7795";
-  - Salvator-X
+  - Salvator-X (RTP0RC7796SIPB0011S)
     compatible = "renesas,salvator-x", "renesas,r8a7796";
   - SILK (RTP0RC7794LCB00011S)
     compatible = "renesas,silk", "renesas,r8a7794"
diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
index 4d6467cc2aa2..d2c46449b4eb 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -12,6 +12,7 @@ using one of the following compatible strings:
   allwinner,sun8i-a23
   allwinner,sun8i-a33
   allwinner,sun8i-a83t
+  allwinner,sun8i-h2-plus
   allwinner,sun8i-h3
   allwinner,sun9i-a80
   allwinner,sun50i-a64
diff --git a/Documentation/devicetree/bindings/ata/ahci-da850.txt b/Documentation/devicetree/bindings/ata/ahci-da850.txt
new file mode 100644
index 000000000000..5f8193417725
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/ahci-da850.txt
@@ -0,0 +1,18 @@
+Device tree binding for the TI DA850 AHCI SATA Controller
+---------------------------------------------------------
+
+Required properties:
+  - compatible: must be "ti,da850-ahci"
+  - reg: physical base addresses and sizes of the two register regions
+         used by the controller: the register map as defined by the
+         AHCI 1.1 standard and the Power Down Control Register (PWRDN)
+         for enabling/disabling the SATA clock receiver
+  - interrupts: interrupt specifier (refer to the interrupt binding)
+
+Example:
+
+        sata: sata@218000 {
+                compatible = "ti,da850-ahci";
+                reg = <0x218000 0x2000>, <0x22c018 0x4>;
+                interrupts = <67>;
+        };
diff --git a/Documentation/devicetree/bindings/bus/qcom,ebi2.txt b/Documentation/devicetree/bindings/bus/qcom,ebi2.txt
index 920681f552db..5a7d567f6833 100644
--- a/Documentation/devicetree/bindings/bus/qcom,ebi2.txt
+++ b/Documentation/devicetree/bindings/bus/qcom,ebi2.txt
@@ -51,7 +51,7 @@ Required properties:
 - compatible: should be one of:
   "qcom,msm8660-ebi2"
   "qcom,apq8060-ebi2"
-- #address-cells: shoule be <2>: the first cell is the chipselect,
+- #address-cells: should be <2>: the first cell is the chipselect,
   the second cell is the offset inside the memory range
 - #size-cells: should be <1>
 - ranges: should be set to:
@@ -64,7 +64,7 @@ Required properties:
 - reg: two ranges of registers: EBI2 config and XMEM config areas
 - reg-names: should be "ebi2", "xmem"
 - clocks: two clocks, EBI_2X and EBI
-- clock-names: shoule be "ebi2x", "ebi2"
+- clock-names: should be "ebi2x", "ebi2"
 
 Optional subnodes:
 - Nodes inside the EBI2 will be considered device nodes.
@@ -100,7 +100,7 @@ Optional properties arrays for FAST chip selects:
   assertion, with respect to the cycle where ADV (address valid) is asserted.
   2 means 2 cycles between ADV and OE. Valid values 0, 1, 2 or 3.
 - qcom,xmem-read-hold-cycles: the length in cycles of the first segment of a
-  read transfer. For a single read trandfer this will be the time from CS
+  read transfer. For a single read transfer this will be the time from CS
   assertion to OE assertion. Valid values 0 thru 15.
 
 
diff --git a/Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt b/Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt
index e56a1df3a9d3..dd906db34b32 100644
--- a/Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt
+++ b/Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt
@@ -16,7 +16,20 @@ Required properties:
 - #clock-cells: Should be <1>. The permitted clock-specifier values can be
                   found in include/dt-bindings/clock/bcm2835.h
 - reg:          Specifies base physical address and size of the registers
-- clocks:       The external oscillator clock phandle
+- clocks:       phandles to the parent clocks used as input to the module, in
+                  the following order:
+
+                  - External oscillator
+                  - DSI0 byte clock
+                  - DSI0 DDR2 clock
+                  - DSI0 DDR clock
+                  - DSI1 byte clock
+                  - DSI1 DDR2 clock
+                  - DSI1 DDR clock
+
+                  Only external oscillator is required.  The DSI clocks may
+                  not be present, in which case their children will be
+                  unusable.
 
 Example:
 
diff --git a/Documentation/devicetree/bindings/clock/exynos4415-clock.txt b/Documentation/devicetree/bindings/clock/exynos4415-clock.txt
deleted file mode 100644
index 847d98bae8cf..000000000000
--- a/Documentation/devicetree/bindings/clock/exynos4415-clock.txt
+++ /dev/null
@@ -1,38 +0,0 @@
-* Samsung Exynos4415 Clock Controller
-
-The Exynos4415 clock controller generates and supplies clock to various
-consumer devices within the Exynos4415 SoC.
-
-Required properties:
-
-- compatible: should be one of the following:
-  - "samsung,exynos4415-cmu" - for the main system clocks controller
-    (CMU_LEFTBUS, CMU_RIGHTBUS, CMU_TOP, CMU_CPU clock domains).
-  - "samsung,exynos4415-cmu-dmc" - for the Exynos4415 SoC DRAM Memory
-    Controller (DMC) domain clock controller.
-
-- reg: physical base address of the controller and length of memory mapped
-  region.
-
-- #clock-cells: should be 1.
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume.
-
-All available clocks are defined as preprocessor macros in
-dt-bindings/clock/exynos4415.h header and can be used in device
-tree sources.
-
-Example 1: An example of a clock controller node is listed below.
-
-        cmu: clock-controller@10030000 {
-                compatible = "samsung,exynos4415-cmu";
-                reg = <0x10030000 0x18000>;
-                #clock-cells = <1>;
-        };
-
-        cmu-dmc: clock-controller@105C0000 {
-                compatible = "samsung,exynos4415-cmu-dmc";
-                reg = <0x105C0000 0x3000>;
-                #clock-cells = <1>;
-        };
diff --git a/Documentation/devicetree/bindings/clock/hi3660-clock.txt b/Documentation/devicetree/bindings/clock/hi3660-clock.txt
new file mode 100644
index 000000000000..cc9b86c35758
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/hi3660-clock.txt
@@ -0,0 +1,42 @@
+* Hisilicon Hi3660 Clock Controller
+
+The Hi3660 clock controller generates and supplies clock to various
+controllers within the Hi3660 SoC.
+
+Required Properties:
+
+- compatible: the compatible should be one of the following strings to
+        indicate the clock controller functionality.
+
+        - "hisilicon,hi3660-crgctrl"
+        - "hisilicon,hi3660-pctrl"
+        - "hisilicon,hi3660-pmuctrl"
+        - "hisilicon,hi3660-sctrl"
+        - "hisilicon,hi3660-iomcu"
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in <dt-bindings/clock/hi3660-clock.h>.
+
+Examples:
+        crg_ctrl: clock-controller@fff35000 {
+                compatible = "hisilicon,hi3660-crgctrl", "syscon";
+                reg = <0x0 0xfff35000 0x0 0x1000>;
+                #clock-cells = <1>;
+        };
+
+        uart0: serial@fdf02000 {
+                compatible = "arm,pl011", "arm,primecell";
+                reg = <0x0 0xfdf02000 0x0 0x1000>;
+                interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
+                         <&crg_ctrl HI3660_PCLK>;
+                clock-names = "uartclk", "apb_pclk";
+                status = "disabled";
+        };
diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt b/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
new file mode 100644
index 000000000000..87e9c47a89a3
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
@@ -0,0 +1,65 @@
+Binding for IDT VersaClock5 programmable i2c clock generator.
+
+The IDT VersaClock5 are programmable i2c clock generators providing
+from 3 to 12 output clocks.
+
+==I2C device node==
+
+Required properties:
+- compatible:   shall be one of "idt,5p49v5923" , "idt,5p49v5933".
+- reg:          i2c device address, shall be 0x68 or 0x6a.
+- #clock-cells: from common clock binding; shall be set to 1.
+- clocks:       from common clock binding; list of parent clock handles,
+                - 5p49v5923: (required) either or both of XTAL or CLKIN
+                                        reference clock.
+                - 5p49v5933: (optional) property not present (internal
+                                        Xtal used) or CLKIN reference
+                                        clock.
+- clock-names:  from common clock binding; clock input names, can be
+                - 5p49v5923: (required) either or both of "xin", "clkin".
+                - 5p49v5933: (optional) property not present or "clkin".
+
+==Mapping between clock specifier and physical pins==
+
+When referencing the provided clock in the DT using phandle and
+clock specifier, the following mapping applies:
+
+5P49V5923:
+        0 -- OUT0_SEL_I2CB
+        1 -- OUT1
+        2 -- OUT2
+
+5P49V5933:
+        0 -- OUT0_SEL_I2CB
+        1 -- OUT1
+        2 -- OUT4
+
+==Example==
+
+/* 25MHz reference crystal */
+ref25: ref25m {
+        compatible = "fixed-clock";
+        #clock-cells = <0>;
+        clock-frequency = <25000000>;
+};
+
+i2c-master-node {
+
+        /* IDT 5P49V5923 i2c clock generator */
+        vc5: clock-generator@6a {
+                compatible = "idt,5p49v5923";
+                reg = <0x6a>;
+                #clock-cells = <1>;
+
+                /* Connect XIN input to 25MHz reference */
+                clocks = <&ref25m>;
+                clock-names = "xin";
+        };
+};
+
+/* Consumer referencing the 5P49V5923 pin OUT1 */
+consumer {
+        ...
+        clocks = <&vc5 1>;
+        ...
+}
diff --git a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
index 520562a7dc2a..c7b4e3a6b2c6 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
@@ -7,6 +7,7 @@ Required properties:
 - compatible : must be "marvell,armada-370-corediv-clock",
                        "marvell,armada-375-corediv-clock",
                        "marvell,armada-380-corediv-clock",
+                       "marvell,mv98dx3236-corediv-clock",
 
 - reg : must be the register address of Core Divider control register
 - #clock-cells : from common clock binding; shall be set to 1
diff --git a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
index 99c214660bdc..7f28506eaee7 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
@@ -3,6 +3,7 @@ Device Tree Clock bindings for cpu clock of Marvell EBU platforms
 Required properties:
 - compatible : shall be one of the following:
         "marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
+        "marvell,mv98dx3236-cpu-clock" - cpu clocks for 98DX3236 SoC
 - reg : Address and length of the clock complex register set, followed
         by address and length of the PMU DFS registers
 - #clock-cells : should be set to 1.
diff --git a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
index cb8542d910b3..5142efc8099d 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
@@ -117,7 +117,7 @@ ID	Clock	Peripheral
 25      tdm     Time Division Mplx
 28      xor1    XOR DMA 1
 29      sata1lnk
-30      sata1   SATA Host 0
+30      sata1   SATA Host 1
 
 The following is a list of provided IDs for Dove:
 ID      Clock   Peripheral
diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
index 87d3714b956a..a7235e9e1c97 100644
--- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
@@ -11,6 +11,7 @@ Required properties :
                compatible "qcom,rpmcc" should be also included.
 
                         "qcom,rpmcc-msm8916", "qcom,rpmcc"
+                        "qcom,rpmcc-msm8974", "qcom,rpmcc"
                         "qcom,rpmcc-apq8064", "qcom,rpmcc"
 
 - #clock-cells : shall contain 1
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index df9cb5ac5f72..aa3526f229a7 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -31,6 +31,7 @@ Required properties:
         * "fsl,t4240-clockgen"
         * "fsl,b4420-clockgen"
         * "fsl,b4860-clockgen"
+        * "fsl,ls1012a-clockgen"
         * "fsl,ls1021a-clockgen"
         * "fsl,ls1043a-clockgen"
         * "fsl,ls1046a-clockgen"
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
index c46919412953..f4f944d81308 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
@@ -42,6 +42,10 @@ Required Properties:
         Domain bindings in
         Documentation/devicetree/bindings/power/power_domain.txt.
 
+  - #reset-cells: Must be 1
+      - The single reset specifier cell must be the module number, as defined
+        in the datasheet.
+
 
 Examples
 --------
@@ -55,6 +59,7 @@ Examples
                 clock-names = "extal", "extalr";
                 #clock-cells = <2>;
                 #power-domain-cells = <0>;
+                #reset-cells = <1>;
         };
 
 
@@ -69,5 +74,6 @@ Examples
                 dmas = <&dmac1 0x13>, <&dmac1 0x12>;
                 dma-names = "tx", "rx";
                 power-domains = <&cpg>;
+                resets = <&cpg 310>;
                 status = "disabled";
         };
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt
new file mode 100644
index 000000000000..e71c675ba5da
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt
@@ -0,0 +1,57 @@
+* Rockchip RK3328 Clock and Reset Unit
+
+The RK3328 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: should be "rockchip,rk3328-cru"
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+  If missing pll rates are not changeable, due to the missing pll lock status.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be
+used in device tree sources. Similar macros exist for the reset sources in
+these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "clkin_i2s" - external I2S clock - optional,
+ - "gmac_clkin" - external GMAC clock - optional
+ - "phy_50m_out" - output clock of the pll in the mac phy
+
+Example: Clock controller node:
+
+        cru: clock-controller@ff440000 {
+                compatible = "rockchip,rk3328-cru";
+                reg = <0x0 0xff440000 0x0 0x1000>;
+                rockchip,grf = <&grf>;
+
+                #clock-cells = <1>;
+                #reset-cells = <1>;
+        };
+
+Example: UART controller node that consumes the clock generated by the clock
+  controller:
+
+        uart0: serial@ff120000 {
+                compatible = "snps,dw-apb-uart";
+                reg = <0xff120000 0x100>;
+                interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+                reg-shift = <2>;
+                reg-io-width = <4>;
+                clocks = <&cru SCLK_UART0>;
+        };
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
index 3888dd33fcbd..3bc56fae90ac 100644
--- a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
@@ -13,6 +13,12 @@ Required Properties:
 - #clock-cells: should be 1.
 - #reset-cells: should be 1.
 
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files".
+  It is used for GRF muxes, if missing any muxes present in the GRF will not
+  be available.
+
 Each clock is assigned an identifier and client nodes can use this identifier
 to specify the clock which they consume. All available clocks are defined as
 preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
diff --git a/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
index 0532d815dae3..b240121d2ac9 100644
--- a/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
+++ b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
@@ -10,6 +10,7 @@ Required properties:
 - compatible: Should be:
   "st,stm32f42xx-rcc"
   "st,stm32f469-rcc"
+  "st,stm32f746-rcc"
 - reg: should be register base and length as documented in the
   datasheet
 - #reset-cells: 1, see below
@@ -17,6 +18,9 @@ Required properties:
   property, containing a phandle to the clock device node, an index selecting
   between gated clocks and other clocks and an index specifying the clock to
   use.
+- clocks: External oscillator clock phandle
+  - high speed external clock signal (HSE)
+  - external I2S clock (I2S_CKIN)
 
 Example:
 
@@ -25,6 +29,7 @@ Example:
                 #clock-cells = <2>
                 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
                 reg = <0x40023800 0x400>;
+                clocks = <&clk_hse>, <&clk_i2s_ckin>;
         };
 
 Specifying gated clocks
@@ -66,6 +71,38 @@ The secondary index is bound with the following magic numbers:
 
         0       SYSTICK
         1       FCLK
+        2       CLK_LSI         (low-power clock source)
+        3       CLK_LSE         (generated from a 32.768 kHz low-speed external
+                                 crystal or ceramic resonator)
+        4       CLK_HSE_RTC     (HSE division factor for RTC clock)
+        5       CLK_RTC         (real-time clock)
+        6       PLL_VCO_I2S     (vco frequency of I2S pll)
+        7       PLL_VCO_SAI     (vco frequency of SAI pll)
+        8       CLK_LCD         (LCD-TFT)
+        9       CLK_I2S         (I2S clocks)
+        10      CLK_SAI1        (audio clocks)
+        11      CLK_SAI2
+        12      CLK_I2SQ_PDIV   (post divisor of pll i2s q divisor)
+        13      CLK_SAIQ_PDIV   (post divisor of pll sai q divisor)
+
+        14      CLK_HSI         (Internal ocscillator clock)
+        15      CLK_SYSCLK      (System Clock)
+        16      CLK_HDMI_CEC    (HDMI-CEC clock)
+        17      CLK_SPDIF       (SPDIF-Rx clock)
+        18      CLK_USART1      (U(s)arts clocks)
+        19      CLK_USART2
+        20      CLK_USART3
+        21      CLK_UART4
+        22      CLK_UART5
+        23      CLK_USART6
+        24      CLK_UART7
+        25      CLK_UART8
+        26      CLK_I2C1        (I2S clocks)
+        27      CLK_I2C2
+        28      CLK_I2C3
+        29      CLK_I2C4
+        30      CLK_LPTIMER     (LPTimer1 clock)
+)
 
 Example:
 
diff --git a/Documentation/devicetree/bindings/clock/stericsson,abx500.txt b/Documentation/devicetree/bindings/clock/stericsson,abx500.txt
new file mode 100644
index 000000000000..dbaa886b223e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/stericsson,abx500.txt
@@ -0,0 +1,20 @@
+Clock bindings for ST-Ericsson ABx500 clocks
+
+Required properties :
+- compatible : shall contain the following:
+  "stericsson,ab8500-clk"
+- #clock-cells should be <1>
+
+The ABx500 clocks need to be placed as a subnode of an AB8500
+device node, see mfd/ab8500.txt
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/ste-ab8500.h header and can be used in device
+tree sources.
+
+Example:
+
+clock-controller {
+        compatible = "stericsson,ab8500-clk";
+        #clock-cells = <1>;
+};
diff --git a/Documentation/devicetree/bindings/clock/sun9i-de.txt b/Documentation/devicetree/bindings/clock/sun9i-de.txt
new file mode 100644
index 000000000000..fb18f327b97a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sun9i-de.txt
@@ -0,0 +1,28 @@
+Allwinner A80 Display Engine Clock Control Binding
+--------------------------------------------------
+
+Required properties :
+- compatible: must contain one of the following compatibles:
+                - "allwinner,sun9i-a80-de-clks"
+
+- reg: Must contain the registers base address and length
+- clocks: phandle to the clocks feeding the display engine subsystem.
+          Three are needed:
+  - "mod": the display engine module clock
+  - "dram": the DRAM bus clock for the system
+  - "bus": the bus clock for the whole display engine subsystem
+- clock-names: Must contain the clock names described just above
+- resets: phandle to the reset control for the display engine subsystem.
+- #clock-cells : must contain 1
+- #reset-cells : must contain 1
+
+Example:
+de_clocks: clock@3000000 {
+        compatible = "allwinner,sun9i-a80-de-clks";
+        reg = <0x03000000 0x30>;
+        clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>;
+        clock-names = "mod", "dram", "bus";
+        resets = <&ccu RST_BUS_DE>;
+        #clock-cells = <1>;
+        #reset-cells = <1>;
+};
diff --git a/Documentation/devicetree/bindings/clock/sun9i-usb.txt b/Documentation/devicetree/bindings/clock/sun9i-usb.txt
new file mode 100644
index 000000000000..3564bd4f2a20
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sun9i-usb.txt
@@ -0,0 +1,24 @@
+Allwinner A80 USB Clock Control Binding
+---------------------------------------
+
+Required properties :
+- compatible: must contain one of the following compatibles:
+                - "allwinner,sun9i-a80-usb-clocks"
+
+- reg: Must contain the registers base address and length
+- clocks: phandle to the clocks feeding the USB subsystem. Two are needed:
+  - "bus": the bus clock for the whole USB subsystem
+  - "hosc": the high frequency oscillator (usually at 24MHz)
+- clock-names: Must contain the clock names described just above
+- #clock-cells : must contain 1
+- #reset-cells : must contain 1
+
+Example:
+usb_clocks: clock@a08000 {
+        compatible = "allwinner,sun9i-a80-usb-clks";
+        reg = <0x00a08000 0x8>;
+        clocks = <&ccu CLK_BUS_USB>, <&osc24M>;
+        clock-names = "bus", "hosc";
+        #clock-cells = <1>;
+        #reset-cells = <1>;
+};
diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
index 74d44a4273f2..bae5668cf427 100644
--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
@@ -7,6 +7,8 @@ Required properties :
                 - "allwinner,sun8i-a23-ccu"
                 - "allwinner,sun8i-a33-ccu"
                 - "allwinner,sun8i-h3-ccu"
+                - "allwinner,sun8i-v3s-ccu"
+                - "allwinner,sun9i-a80-ccu"
                 - "allwinner,sun50i-a64-ccu"
 
 - reg: Must contain the registers base address and length
diff --git a/Documentation/devicetree/bindings/clock/ti,cdce925.txt b/Documentation/devicetree/bindings/clock/ti,cdce925.txt
index 4c7669ad681b..0d01f2d5cc36 100644
--- a/Documentation/devicetree/bindings/clock/ti,cdce925.txt
+++ b/Documentation/devicetree/bindings/clock/ti,cdce925.txt
@@ -1,15 +1,22 @@
-Binding for TO CDCE925 programmable I2C clock synthesizers.
+Binding for TI CDCE913/925/937/949 programmable I2C clock synthesizers.
 
 Reference
 This binding uses the common clock binding[1].
 
 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] http://www.ti.com/product/cdce925
+[2] http://www.ti.com/product/cdce913
+[3] http://www.ti.com/product/cdce925
+[4] http://www.ti.com/product/cdce937
+[5] http://www.ti.com/product/cdce949
 
 The driver provides clock sources for each output Y1 through Y5.
 
 Required properties:
- - compatible: Shall be "ti,cdce925"
+ - compatible: Shall be one of the following:
+        - "ti,cdce913": 1-PLL, 3 Outputs
+        - "ti,cdce925": 2-PLL, 5 Outputs
+        - "ti,cdce937": 3-PLL, 7 Outputs
+        - "ti,cdce949": 4-PLL, 9 Outputs
  - reg: I2C device address.
  - clocks: Points to a fixed parent clock that provides the input frequency.
  - #clock-cells: From common clock bindings: Shall be 1.
@@ -18,7 +25,7 @@ Optional properties:
  - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a
                  board, or to compensate for external influences.
 
-For both PLL1 and PLL2 an optional child node can be used to specify spread
+For all PLL1, PLL2, ... an optional child node can be used to specify spread
 spectrum clocking parameters for a board.
   - spread-spectrum: SSC mode as defined in the data sheet.
   - spread-spectrum-center: Use "centered" mode instead of "max" mode. When
diff --git a/Documentation/devicetree/bindings/clock/zx296718-clk.txt b/Documentation/devicetree/bindings/clock/zx296718-clk.txt
index 8c18b7b237bf..4ad703808407 100644
--- a/Documentation/devicetree/bindings/clock/zx296718-clk.txt
+++ b/Documentation/devicetree/bindings/clock/zx296718-clk.txt
@@ -13,6 +13,9 @@ Required properties:
         "zte,zx296718-lsp1crm":
                 zx296718 device level clock selection and gating
 
+        "zte,zx296718-audiocrm":
+                zx296718 audio clock selection, divider and gating
+
 - reg: Address and length of the register set
 
 The clock consumer should specify the desired clock by having the clock
diff --git a/Documentation/devicetree/bindings/crypto/brcm,spu-crypto.txt b/Documentation/devicetree/bindings/crypto/brcm,spu-crypto.txt
new file mode 100644
index 000000000000..29b6007568eb
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/brcm,spu-crypto.txt
@@ -0,0 +1,22 @@
+The Broadcom Secure Processing Unit (SPU) hardware supports symmetric
+cryptographic offload for Broadcom SoCs. A SoC may have multiple SPU hardware
+blocks.
+
+Required properties:
+- compatible: Should be one of the following:
+  brcm,spum-crypto - for devices with SPU-M hardware
+  brcm,spu2-crypto - for devices with SPU2 hardware
+  brcm,spu2-v2-crypto - for devices with enhanced SPU2 hardware features like SHA3
+  and Rabin Fingerprint support
+  brcm,spum-nsp-crypto - for the Northstar Plus variant of the SPU-M hardware
+
+- reg: Should contain SPU registers location and length.
+- mboxes: The mailbox channel to be used to communicate with the SPU.
+  Mailbox channels correspond to DMA rings on the device.
+
+Example:
+        crypto@612d0000 {
+                compatible = "brcm,spum-crypto";
+                reg = <0 0x612d0000 0 0x900>;
+                mboxes = <&pdc0 0>;
+        };
diff --git a/Documentation/devicetree/bindings/crypto/mediatek-crypto.txt b/Documentation/devicetree/bindings/crypto/mediatek-crypto.txt
new file mode 100644
index 000000000000..c204725e5873
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/mediatek-crypto.txt
@@ -0,0 +1,27 @@
+MediaTek cryptographic accelerators
+
+Required properties:
+- compatible: Should be "mediatek,eip97-crypto"
+- reg: Address and length of the register set for the device
+- interrupts: Should contain the five crypto engines interrupts in numeric
+        order. These are global system and four descriptor rings.
+- clocks: the clock used by the core
+- clock-names: the names of the clock listed in the clocks property. These are
+        "ethif", "cryp"
+- power-domains: Must contain a reference to the PM domain.
+
+
+Example:
+        crypto: crypto@1b240000 {
+                compatible = "mediatek,eip97-crypto";
+                reg = <0 0x1b240000 0 0x20000>;
+                interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
+                             <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
+                             <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
+                             <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
+                             <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
+                clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
+                         <&ethsys CLK_ETHSYS_CRYPTO>;
+                clock-names = "ethif","cryp";
+                power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
+        };
diff --git a/Documentation/devicetree/bindings/display/arm,pl11x.txt b/Documentation/devicetree/bindings/display/arm,pl11x.txt
index 3e3039a8a253..ef89ab46b2c9 100644
--- a/Documentation/devicetree/bindings/display/arm,pl11x.txt
+++ b/Documentation/devicetree/bindings/display/arm,pl11x.txt
@@ -22,7 +22,7 @@ Required properties:
 
 - clocks: contains phandle and clock specifier pairs for the entries
         in the clock-names property. See
-        Documentation/devicetree/binding/clock/clock-bindings.txt
+        Documentation/devicetree/bindings/clock/clock-bindings.txt
 
 Optional properties:
 
diff --git a/Documentation/devicetree/bindings/display/brcm,bcm-vc4.txt b/Documentation/devicetree/bindings/display/brcm,bcm-vc4.txt
index e2768703ac2b..34c7fddcea39 100644
--- a/Documentation/devicetree/bindings/display/brcm,bcm-vc4.txt
+++ b/Documentation/devicetree/bindings/display/brcm,bcm-vc4.txt
@@ -56,6 +56,18 @@ Required properties for V3D:
 - interrupts:   The interrupt number
                   See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
 
+Required properties for DSI:
+- compatible:   Should be "brcm,bcm2835-dsi0" or "brcm,bcm2835-dsi1"
+- reg:          Physical base address and length of the DSI block's registers
+- interrupts:   The interrupt number
+                  See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
+- clocks:       a) phy: The DSI PLL clock feeding the DSI analog PHY
+                b) escape: The DSI ESC clock from CPRMAN
+                c) pixel: The DSI pixel clock from CPRMAN
+- clock-output-names:
+                The 3 clocks output from the DSI analog PHY: dsi[01]_byte,
+                dsi[01]_ddr2, and dsi[01]_ddr
+
 [1] Documentation/devicetree/bindings/media/video-interfaces.txt
 
 Example:
@@ -99,6 +111,29 @@ dpi: dpi@7e208000 {
         };
 };
 
+dsi1: dsi@7e700000 {
+        compatible = "brcm,bcm2835-dsi1";
+        reg = <0x7e700000 0x8c>;
+        interrupts = <2 12>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        #clock-cells = <1>;
+
+        clocks = <&clocks BCM2835_PLLD_DSI1>,
+                 <&clocks BCM2835_CLOCK_DSI1E>,
+                 <&clocks BCM2835_CLOCK_DSI1P>;
+        clock-names = "phy", "escape", "pixel";
+
+        clock-output-names = "dsi1_byte", "dsi1_ddr2", "dsi1_ddr";
+
+        pitouchscreen: panel@0 {
+                compatible = "raspberrypi,touchscreen";
+                reg = <0>;
+
+                <...>
+        };
+};
+
 vec: vec@7e806000 {
         compatible = "brcm,bcm2835-vec";
         reg = <0x7e806000 0x1000>;
diff --git a/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt b/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt
index 6532a59c9b43..00ea670b8c4d 100644
--- a/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt
+++ b/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt
@@ -38,10 +38,22 @@ The following input format properties are required except in "rgb 1x" and
 - adi,input-justification: The input bit justification ("left", "evenly",
   "right").
 
+- avdd-supply: A 1.8V supply that powers up the AVDD pin on the chip.
+- dvdd-supply: A 1.8V supply that powers up the DVDD pin on the chip.
+- pvdd-supply: A 1.8V supply that powers up the PVDD pin on the chip.
+- dvdd-3v-supply: A 3.3V supply that powers up the pin called DVDD_3V
+  on the chip.
+- bgvdd-supply: A 1.8V supply that powers up the BGVDD pin. This is
+  needed only for ADV7511.
+
 The following properties are required for ADV7533:
 
 - adi,dsi-lanes: Number of DSI data lanes connected to the DSI host. It should
   be one of 1, 2, 3 or 4.
+- a2vdd-supply: 1.8V supply that powers up the A2VDD pin on the chip.
+- v3p3-supply: A 3.3V supply that powers up the V3P3 pin on the chip.
+- v1p2-supply: A supply that powers up the V1P2 pin on the chip. It can be
+  either 1.2V or 1.8V.
 
 Optional properties:
 
diff --git a/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt b/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
index 4a0f4f7682ad..0c7473dd0e51 100644
--- a/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
+++ b/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
@@ -33,7 +33,7 @@ Optional properties for dp-controller:
                 in Documentation/devicetree/bindings/media/video-interfaces.txt,
                 please refer to the SoC specific binding document:
                 * Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
-                * Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
+                * Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
 
 [1]: Documentation/devicetree/bindings/media/video-interfaces.txt
 -------------------------------------------------------------------------------
diff --git a/Documentation/devicetree/bindings/video/bridge/anx7814.txt b/Documentation/devicetree/bindings/display/bridge/anx7814.txt
index b2a22c28c9b3..b2a22c28c9b3 100644
--- a/Documentation/devicetree/bindings/video/bridge/anx7814.txt
+++ b/Documentation/devicetree/bindings/display/bridge/anx7814.txt
diff --git a/Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt b/Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt
index 5e9a84d6e5f1..33bf981fbe33 100644
--- a/Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt
+++ b/Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt
@@ -1,52 +1,33 @@
-DesignWare HDMI bridge bindings
-
-Required properties:
-- compatible: platform specific such as:
-   * "snps,dw-hdmi-tx"
-   * "fsl,imx6q-hdmi"
-   * "fsl,imx6dl-hdmi"
-   * "rockchip,rk3288-dw-hdmi"
-- reg: Physical base address and length of the controller's registers.
-- interrupts: The HDMI interrupt number
-- clocks, clock-names : must have the phandles to the HDMI iahb and isfr clocks,
-  as described in Documentation/devicetree/bindings/clock/clock-bindings.txt,
-  the clocks are soc specific, the clock-names should be "iahb", "isfr"
--port@[X]: SoC specific port nodes with endpoint definitions as defined
-   in Documentation/devicetree/bindings/media/video-interfaces.txt,
-   please refer to the SoC specific binding document:
-    * Documentation/devicetree/bindings/display/imx/hdmi.txt
-    * Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
-
-Optional properties
-- reg-io-width: the width of the reg:1,4, default set to 1 if not present
-- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing,
-  if the property is omitted, a functionally reduced I2C bus
-  controller on DW HDMI is probed
-- clocks, clock-names: phandle to the HDMI CEC clock, name should be "cec"
-
-Example:
-        hdmi: hdmi@0120000 {
-                compatible = "fsl,imx6q-hdmi";
-                reg = <0x00120000 0x9000>;
-                interrupts = <0 115 0x04>;
-                gpr = <&gpr>;
-                clocks = <&clks 123>, <&clks 124>;
-                clock-names = "iahb", "isfr";
-                ddc-i2c-bus = <&i2c2>;
-
-                port@0 {
-                        reg = <0>;
-
-                        hdmi_mux_0: endpoint {
-                                remote-endpoint = <&ipu1_di0_hdmi>;
-                        };
-                };
-
-                port@1 {
-                        reg = <1>;
-
-                        hdmi_mux_1: endpoint {
-                                remote-endpoint = <&ipu1_di1_hdmi>;
-                        };
-                };
-        };
+Synopsys DesignWare HDMI TX Encoder
+===================================
+
+This document defines device tree properties for the Synopsys DesignWare HDMI
+TX Encoder (DWC HDMI TX). It doesn't constitue a device tree binding
+specification by itself but is meant to be referenced by platform-specific
+device tree bindings.
+
+When referenced from platform device tree bindings the properties defined in
+this document are defined as follows. The platform device tree bindings are
+responsible for defining whether each property is required or optional.
+
+- reg: Memory mapped base address and length of the DWC HDMI TX registers.
+
+- reg-io-width: Width of the registers specified by the reg property. The
+  value is expressed in bytes and must be equal to 1 or 4 if specified. The
+  register width defaults to 1 if the property is not present.
+
+- interrupts: Reference to the DWC HDMI TX interrupt.
+
+- clocks: References to all the clocks specified in the clock-names property
+  as specified in Documentation/devicetree/bindings/clock/clock-bindings.txt.
+
+- clock-names: The DWC HDMI TX uses the following clocks.
+
+  - "iahb" is the bus clock for either AHB and APB (mandatory).
+  - "isfr" is the internal register configuration clock (mandatory).
+  - "cec" is the HDMI CEC controller main clock (optional).
+
+- ports: The connectivity of the DWC HDMI TX with the rest of the system is
+  expressed in using ports as specified in the device graph bindings defined
+  in Documentation/devicetree/bindings/graph.txt. The numbering of the ports
+  is platform-specific.
diff --git a/Documentation/devicetree/bindings/video/bridge/sil-sii8620.txt b/Documentation/devicetree/bindings/display/bridge/sil-sii8620.txt
index 9409d9c6a260..9409d9c6a260 100644
--- a/Documentation/devicetree/bindings/video/bridge/sil-sii8620.txt
+++ b/Documentation/devicetree/bindings/display/bridge/sil-sii8620.txt
diff --git a/Documentation/devicetree/bindings/display/bridge/ti,ths8135.txt b/Documentation/devicetree/bindings/display/bridge/ti,ths8135.txt
new file mode 100644
index 000000000000..6ec1a880ac18
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/ti,ths8135.txt
@@ -0,0 +1,46 @@
+THS8135 Video DAC
+-----------------
+
+This is the binding for Texas Instruments THS8135 Video DAC bridge.
+
+Required properties:
+
+- compatible: Must be "ti,ths8135"
+
+Required nodes:
+
+This device has two video ports. Their connections are modelled using the OF
+graph bindings specified in Documentation/devicetree/bindings/graph.txt.
+
+- Video port 0 for RGB input
+- Video port 1 for VGA output
+
+Example
+-------
+
+vga-bridge {
+        compatible = "ti,ths8135";
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@0 {
+                        reg = <0>;
+
+                        vga_bridge_in: endpoint {
+                                remote-endpoint = <&lcdc_out_vga>;
+                        };
+                };
+
+                port@1 {
+                        reg = <1>;
+
+                        vga_bridge_out: endpoint {
+                                remote-endpoint = <&vga_con_in>;
+                        };
+                };
+        };
+};
diff --git a/Documentation/devicetree/bindings/display/cirrus,clps711x-fb.txt b/Documentation/devicetree/bindings/display/cirrus,clps711x-fb.txt
index e9c65746e2f1..b0e506610400 100644
--- a/Documentation/devicetree/bindings/display/cirrus,clps711x-fb.txt
+++ b/Documentation/devicetree/bindings/display/cirrus,clps711x-fb.txt
@@ -6,7 +6,7 @@ Required properties:
               location and size of the framebuffer memory.
 - clocks    : phandle + clock specifier pair of the FB reference clock.
 - display   : phandle to a display node as described in
-              Documentation/devicetree/bindings/display/display-timing.txt.
+              Documentation/devicetree/bindings/display/panel/display-timing.txt.
               Additionally, the display node has to define properties:
   - bits-per-pixel: Bits per pixel.
   - ac-prescale   : LCD AC bias frequency. This frequency is the required
diff --git a/Documentation/devicetree/bindings/display/exynos/exynos7-decon.txt b/Documentation/devicetree/bindings/display/exynos/exynos7-decon.txt
index 3938caacf11c..9e2e7f6f7609 100644
--- a/Documentation/devicetree/bindings/display/exynos/exynos7-decon.txt
+++ b/Documentation/devicetree/bindings/display/exynos/exynos7-decon.txt
@@ -33,12 +33,12 @@ Required properties:
 - i80-if-timings: timing configuration for lcd i80 interface support.
 
 Optional Properties:
-- samsung,power-domain: a phandle to DECON power domain node.
+- power-domains: a phandle to DECON power domain node.
 - display-timings: timing settings for DECON, as described in document [1].
                 Can be used in case timings cannot be provided otherwise
                 or to override timings provided by the panel.
 
-[1]: Documentation/devicetree/bindings/display/display-timing.txt
+[1]: Documentation/devicetree/bindings/display/panel/display-timing.txt
 
 Example:
 
diff --git a/Documentation/devicetree/bindings/display/exynos/samsung-fimd.txt b/Documentation/devicetree/bindings/display/exynos/samsung-fimd.txt
index c7c6b9af87ac..18645e0228b0 100644
--- a/Documentation/devicetree/bindings/display/exynos/samsung-fimd.txt
+++ b/Documentation/devicetree/bindings/display/exynos/samsung-fimd.txt
@@ -83,7 +83,7 @@ in [2]. The following are properties specific to those nodes:
                 3 - for parallel output,
                 4 - for write-back interface
 
-[1]: Documentation/devicetree/bindings/display/display-timing.txt
+[1]: Documentation/devicetree/bindings/display/panel/display-timing.txt
 [2]: Documentation/devicetree/bindings/media/video-interfaces.txt
 
 Example:
diff --git a/Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt b/Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt
index 38dc9d60eef8..305a0e72a900 100644
--- a/Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt
+++ b/Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt
@@ -16,7 +16,7 @@ Required properties:
   "clk_ade_core" for the ADE core clock.
   "clk_codec_jpeg" for the media NOC QoS clock, which use the same clock with
   jpeg codec.
-  "clk_ade_pix" for the ADE pixel clok.
+  "clk_ade_pix" for the ADE pixel clock.
 - assigned-clocks: Should contain "clk_ade_core" and "clk_codec_jpeg" clocks'
   phandle + clock-specifier pairs.
 - assigned-clock-rates: clock rates, one for each entry in assigned-clocks.
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx-fb.txt b/Documentation/devicetree/bindings/display/imx/fsl,imx-fb.txt
index 00d5f8ea7ec6..7a5c0e204c8e 100644
--- a/Documentation/devicetree/bindings/display/imx/fsl,imx-fb.txt
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx-fb.txt
@@ -9,7 +9,7 @@ Required properties:
 
 Required nodes:
 - display: Phandle to a display node as described in
-        Documentation/devicetree/bindings/display/display-timing.txt
+        Documentation/devicetree/bindings/display/panel/display-timing.txt
         Additional, the display node has to define properties:
         - bits-per-pixel: Bits per pixel
         - fsl,pcr: LCDC PCR value
diff --git a/Documentation/devicetree/bindings/display/imx/hdmi.txt b/Documentation/devicetree/bindings/display/imx/hdmi.txt
index 1b756cf9afb0..66a8f86e5d12 100644
--- a/Documentation/devicetree/bindings/display/imx/hdmi.txt
+++ b/Documentation/devicetree/bindings/display/imx/hdmi.txt
@@ -1,29 +1,36 @@
-Device-Tree bindings for HDMI Transmitter
+Freescale i.MX6 DWC HDMI TX Encoder
+===================================
 
-HDMI Transmitter
-================
+The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
+with a companion PHY IP.
+
+These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
+Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
+following device-specific properties.
 
-The HDMI Transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
-with accompanying PHY IP.
 
 Required properties:
- - #address-cells : should be <1>
- - #size-cells : should be <0>
- - compatible : should be "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi".
- - gpr : should be <&gpr>.
-   The phandle points to the iomuxc-gpr region containing the HDMI
-   multiplexer control register.
- - clocks, clock-names : phandles to the HDMI iahb and isrf clocks, as described
-   in Documentation/devicetree/bindings/clock/clock-bindings.txt and
-   Documentation/devicetree/bindings/clock/imx6q-clock.txt.
- - port@[0-4]: Up to four port nodes with endpoint definitions as defined in
-   Documentation/devicetree/bindings/media/video-interfaces.txt,
-   corresponding to the four inputs to the HDMI multiplexer.
-
-Optional properties:
- - ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
-
-example:
+
+- compatible : Shall be one of "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi".
+- reg: See dw_hdmi.txt.
+- interrupts: HDMI interrupt number
+- clocks: See dw_hdmi.txt.
+- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
+- ports: See dw_hdmi.txt. The DWC HDMI shall have between one and four ports,
+  numbered 0 to 3, corresponding to the four inputs of the HDMI multiplexer.
+  Each port shall have a single endpoint.
+- gpr : Shall contain a phandle to the iomuxc-gpr region containing the HDMI
+  multiplexer control register.
+
+Optional properties
+
+- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
+  or the functionally-reduced I2C master contained in the DWC HDMI. When
+  connected to a system I2C master this property contains a phandle to that
+  I2C master controller.
+
+
+Example:
 
         gpr: iomuxc-gpr@020e0000 {
                 /* ... */
diff --git a/Documentation/devicetree/bindings/display/imx/ldb.txt b/Documentation/devicetree/bindings/display/imx/ldb.txt
index a407462c885e..38c637fa39dd 100644
--- a/Documentation/devicetree/bindings/display/imx/ldb.txt
+++ b/Documentation/devicetree/bindings/display/imx/ldb.txt
@@ -64,7 +64,7 @@ Required properties:
 Optional properties (required if display-timings are used):
  - ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
  - display-timings : A node that describes the display timings as defined in
-   Documentation/devicetree/bindings/display/display-timing.txt.
+   Documentation/devicetree/bindings/display/panel/display-timing.txt.
  - fsl,data-mapping : should be "spwg" or "jeida"
                       This describes how the color bits are laid out in the
                       serialized LVDS signal.
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
index db6e77edbea8..708f5664a316 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
@@ -55,7 +55,7 @@ Required properties (DMA function blocks):
         "mediatek,<chip>-disp-rdma"
         "mediatek,<chip>-disp-wdma"
 - larb: Should contain a phandle pointing to the local arbiter device as defined
-  in Documentation/devicetree/bindings/soc/mediatek/mediatek,smi-larb.txt
+  in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
 - iommus: Should point to the respective IOMMU block with master port as
   argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
   for details.
diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt
index 6b1cab17f52d..fa00e62e1cf6 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi.txt
+++ b/Documentation/devicetree/bindings/display/msm/dsi.txt
@@ -108,7 +108,7 @@ Optional properties:
 - qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
   regulator is wanted.
 
-[1] Documentation/devicetree/bindings/clocks/clock-bindings.txt
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
 [2] Documentation/devicetree/bindings/graph.txt
 [3] Documentation/devicetree/bindings/media/video-interfaces.txt
 [4] Documentation/devicetree/bindings/display/panel/
diff --git a/Documentation/devicetree/bindings/display/msm/edp.txt b/Documentation/devicetree/bindings/display/msm/edp.txt
index 3a20f6ea5898..e63032be5401 100644
--- a/Documentation/devicetree/bindings/display/msm/edp.txt
+++ b/Documentation/devicetree/bindings/display/msm/edp.txt
@@ -10,7 +10,7 @@ Required properties:
 - interrupts: The interrupt signal from the eDP block.
 - power-domains: Should be <&mmcc MDSS_GDSC>.
 - clocks: device clocks
-  See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
+  See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
 - clock-names: the following clocks are required:
   * "core_clk"
   * "iface_clk"
diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt
index 67d0a58dbb77..43fac0fe09bb 100644
--- a/Documentation/devicetree/bindings/display/msm/gpu.txt
+++ b/Documentation/devicetree/bindings/display/msm/gpu.txt
@@ -1,23 +1,19 @@
 Qualcomm adreno/snapdragon GPU
 
 Required properties:
-- compatible: "qcom,adreno-3xx"
+- compatible: "qcom,adreno-XYZ.W", "qcom,adreno"
+    for example: "qcom,adreno-306.0", "qcom,adreno"
+  Note that you need to list the less specific "qcom,adreno" (since this
+  is what the device is matched on), in addition to the more specific
+  with the chip-id.
 - reg: Physical base address and length of the controller's registers.
 - interrupts: The interrupt signal from the gpu.
 - clocks: device clocks
   See ../clocks/clock-bindings.txt for details.
 - clock-names: the following clocks are required:
-  * "core_clk"
-  * "iface_clk"
-  * "mem_iface_clk"
-- qcom,chipid: gpu chip-id.  Note this may become optional for future
-  devices if we can reliably read the chipid from hw
-- qcom,gpu-pwrlevels: list of operating points
-  - compatible: "qcom,gpu-pwrlevels"
-  - for each qcom,gpu-pwrlevel:
-    - qcom,gpu-freq: requested gpu clock speed
-    - NOTE: downstream android driver defines additional parameters to
-      configure memory bandwidth scaling per OPP.
+  * "core"
+  * "iface"
+  * "mem_iface"
 
 Example:
 
@@ -25,28 +21,18 @@ Example:
         ...
 
         gpu: qcom,kgsl-3d0@4300000 {
-                compatible = "qcom,adreno-3xx";
+                compatible = "qcom,adreno-320.2", "qcom,adreno";
                 reg = <0x04300000 0x20000>;
                 reg-names = "kgsl_3d0_reg_memory";
                 interrupts = <GIC_SPI 80 0>;
                 interrupt-names = "kgsl_3d0_irq";
                 clock-names =
-                    "core_clk",
-                    "iface_clk",
-                    "mem_iface_clk";
+                    "core",
+                    "iface",
+                    "mem_iface";
                 clocks =
                     <&mmcc GFX3D_CLK>,
                     <&mmcc GFX3D_AHB_CLK>,
                     <&mmcc MMSS_IMEM_AHB_CLK>;
-                qcom,chipid = <0x03020100>;
-                qcom,gpu-pwrlevels {
-                        compatible = "qcom,gpu-pwrlevels";
-                        qcom,gpu-pwrlevel@0 {
-                                qcom,gpu-freq = <450000000>;
-                        };
-                        qcom,gpu-pwrlevel@1 {
-                                qcom,gpu-freq = <27000000>;
-                        };
-                };
         };
 };
diff --git a/Documentation/devicetree/bindings/display/msm/hdmi.txt b/Documentation/devicetree/bindings/display/msm/hdmi.txt
index 2ad578984fcf..2d306f402d18 100644
--- a/Documentation/devicetree/bindings/display/msm/hdmi.txt
+++ b/Documentation/devicetree/bindings/display/msm/hdmi.txt
@@ -49,7 +49,7 @@ Required properties:
     * "hdmi_tx_l4"
 - power-domains: Should be <&mmcc MDSS_GDSC>.
 - clocks: device clocks
-  See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
+  See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
 - core-vdda-supply: phandle to vdda regulator device node
 
 Example:
diff --git a/Documentation/devicetree/bindings/display/multi-inno,mi0283qt.txt b/Documentation/devicetree/bindings/display/multi-inno,mi0283qt.txt
new file mode 100644
index 000000000000..eed48c3d4875
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/multi-inno,mi0283qt.txt
@@ -0,0 +1,27 @@
+Multi-Inno MI0283QT display panel
+
+Required properties:
+- compatible:   "multi-inno,mi0283qt".
+
+The node for this driver must be a child node of a SPI controller, hence
+all mandatory properties described in ../spi/spi-bus.txt must be specified.
+
+Optional properties:
+- dc-gpios:     D/C pin. The presence/absence of this GPIO determines
+                the panel interface mode (IM[3:0] pins):
+                - present: IM=x110 4-wire 8-bit data serial interface
+                - absent:  IM=x101 3-wire 9-bit data serial interface
+- reset-gpios:  Reset pin
+- power-supply: A regulator node for the supply voltage.
+- backlight:    phandle of the backlight device attached to the panel
+- rotation:     panel rotation in degrees counter clockwise (0,90,180,270)
+
+Example:
+        mi0283qt@0{
+                compatible = "multi-inno,mi0283qt";
+                reg = <0>;
+                spi-max-frequency = <32000000>;
+                rotation = <90>;
+                dc-gpios = <&gpio 25 0>;
+                backlight = <&backlight>;
+        };
diff --git a/Documentation/devicetree/bindings/display/panel/boe,nv101wxmn51.txt b/Documentation/devicetree/bindings/display/panel/boe,nv101wxmn51.txt
new file mode 100644
index 000000000000..b258d6a91ec6
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/boe,nv101wxmn51.txt
@@ -0,0 +1,7 @@
+BOE OPTOELECTRONICS TECHNOLOGY 10.1" WXGA TFT LCD panel
+
+Required properties:
+- compatible: should be "boe,nv101wxmn51"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/Documentation/devicetree/bindings/display/panel/netron-dy,e231732.txt b/Documentation/devicetree/bindings/display/panel/netron-dy,e231732.txt
new file mode 100644
index 000000000000..c6d06b5eab51
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/netron-dy,e231732.txt
@@ -0,0 +1,7 @@
+Netron-DY E231732 7.0" WSVGA TFT LCD panel
+
+Required properties:
+- compatible: should be "netron-dy,e231732"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/Documentation/devicetree/bindings/display/panel/panel-dpi.txt b/Documentation/devicetree/bindings/display/panel/panel-dpi.txt
index b52ac52757df..d4add13e592d 100644
--- a/Documentation/devicetree/bindings/display/panel/panel-dpi.txt
+++ b/Documentation/devicetree/bindings/display/panel/panel-dpi.txt
@@ -12,7 +12,7 @@ Optional properties:
 
 Required nodes:
 - "panel-timing" containing video timings
-  (Documentation/devicetree/bindings/display/display-timing.txt)
+  (Documentation/devicetree/bindings/display/panel/display-timing.txt)
 - Video port for DPI input
 
 Example
diff --git a/Documentation/devicetree/bindings/display/panel/panel.txt b/Documentation/devicetree/bindings/display/panel/panel.txt
new file mode 100644
index 000000000000..e2e6867852b8
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/panel.txt
@@ -0,0 +1,4 @@
+Common display properties
+-------------------------
+
+- rotation:     Display rotation in degrees counter clockwise (0,90,180,270)
diff --git a/Documentation/devicetree/bindings/display/panel/samsung,ld9040.txt b/Documentation/devicetree/bindings/display/panel/samsung,ld9040.txt
index fc595d9b985b..354d4d1df4ff 100644
--- a/Documentation/devicetree/bindings/display/panel/samsung,ld9040.txt
+++ b/Documentation/devicetree/bindings/display/panel/samsung,ld9040.txt
@@ -20,7 +20,7 @@ The device node can contain one 'port' child node with one child
 'endpoint' node, according to the bindings defined in [3]. This
 node should describe panel's video bus.
 
-[1]: Documentation/devicetree/bindings/display/display-timing.txt
+[1]: Documentation/devicetree/bindings/display/panel/display-timing.txt
 [2]: Documentation/devicetree/bindings/spi/spi-bus.txt
 [3]: Documentation/devicetree/bindings/media/video-interfaces.txt
 
diff --git a/Documentation/devicetree/bindings/display/panel/samsung,s6e8aa0.txt b/Documentation/devicetree/bindings/display/panel/samsung,s6e8aa0.txt
index 25701c81b5e0..9e766c5f86da 100644
--- a/Documentation/devicetree/bindings/display/panel/samsung,s6e8aa0.txt
+++ b/Documentation/devicetree/bindings/display/panel/samsung,s6e8aa0.txt
@@ -21,7 +21,7 @@ The device node can contain one 'port' child node with one child
 'endpoint' node, according to the bindings defined in [2]. This
 node should describe panel's video bus.
 
-[1]: Documentation/devicetree/bindings/display/display-timing.txt
+[1]: Documentation/devicetree/bindings/display/panel/display-timing.txt
 [2]: Documentation/devicetree/bindings/media/video-interfaces.txt
 
 Example:
diff --git a/Documentation/devicetree/bindings/display/panel/tianma,tm070jdhg30.txt b/Documentation/devicetree/bindings/display/panel/tianma,tm070jdhg30.txt
new file mode 100644
index 000000000000..eb9501a82e25
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/tianma,tm070jdhg30.txt
@@ -0,0 +1,7 @@
+Tianma Micro-electronics TM070JDHG30 7.0" WXGA TFT LCD panel
+
+Required properties:
+- compatible: should be "tianma,tm070jdhg30"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
index 01cced1c2a18..47665a12786f 100644
--- a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
@@ -35,7 +35,7 @@ Optional property for different chips:
                Required elements: "grf"
 
 For the below properties, please refer to Analogix DP binding document:
- * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
+ * Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
 - phys (required)
 - phy-names (required)
 - hpd-gpios (optional)
diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
index 668091f27674..046076c6b277 100644
--- a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
@@ -1,24 +1,39 @@
-Rockchip specific extensions to the Synopsys Designware HDMI
-================================
+Rockchip DWC HDMI TX Encoder
+============================
+
+The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
+with a companion PHY IP.
+
+These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
+Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
+following device-specific properties.
+
 
 Required properties:
-- compatible: "rockchip,rk3288-dw-hdmi";
-- reg: Physical base address and length of the controller's registers.
-- clocks: phandle to hdmi iahb and isfr clocks.
-- clock-names: should be "iahb" "isfr"
-- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
+
+- compatible: Shall contain "rockchip,rk3288-dw-hdmi".
+- reg: See dw_hdmi.txt.
+- reg-io-width: See dw_hdmi.txt. Shall be 4.
 - interrupts: HDMI interrupt number
-- ports: contain a port node with endpoint definitions as defined in
-  Documentation/devicetree/bindings/media/video-interfaces.txt. For
-  vopb,set the reg = <0> and set the reg = <1> for vopl.
-- reg-io-width: the width of the reg:1,4, the value should be 4 on
-  rk3288 platform
+- clocks: See dw_hdmi.txt.
+- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
+- ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0
+  corresponding to the video input of the controller. The port shall have two
+  endpoints, numbered 0 and 1, connected respectively to the vopb and vopl.
+- rockchip,grf: Shall reference the GRF to mux vopl/vopb.
 
 Optional properties
-- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
-- clocks, clock-names: phandle to the HDMI CEC clock, name should be "cec"
+
+- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
+  or the functionally-reduced I2C master contained in the DWC HDMI. When
+  connected to a system I2C master this property contains a phandle to that
+  I2C master controller.
+- clock-names: See dw_hdmi.txt. The "cec" clock is optional.
+- clock-names: May contain "cec" as defined in dw_hdmi.txt.
+
 
 Example:
+
 hdmi: hdmi@ff980000 {
         compatible = "rockchip,rk3288-dw-hdmi";
         reg = <0xff980000 0x20000>;
diff --git a/Documentation/devicetree/bindings/display/ssd1307fb.txt b/Documentation/devicetree/bindings/display/ssd1307fb.txt
index eb31ed47a283..209d931ef16c 100644
--- a/Documentation/devicetree/bindings/display/ssd1307fb.txt
+++ b/Documentation/devicetree/bindings/display/ssd1307fb.txt
@@ -8,14 +8,15 @@ Required properties:
          0x3c or 0x3d
   - pwm: Should contain the pwm to use according to the OF device tree PWM
          specification [0]. Only required for the ssd1307.
-  - reset-gpios: Should contain the GPIO used to reset the OLED display
   - solomon,height: Height in pixel of the screen driven by the controller
   - solomon,width: Width in pixel of the screen driven by the controller
   - solomon,page-offset: Offset of pages (band of 8 pixels) that the screen is
     mapped to.
 
 Optional properties:
-  - reset-active-low: Is the reset gpio is active on physical low?
+  - reset-gpios: The GPIO used to reset the OLED display, if available. See
+                 Documentation/devicetree/bindings/gpio/gpio.txt for details.
+  - vbat-supply: The supply for VBAT
   - solomon,segment-no-remap: Display needs normal (non-inverted) data column
                               to segment mapping
   - solomon,com-seq: Display uses sequential COM pin configuration
diff --git a/Documentation/devicetree/bindings/display/tilcdc/panel.txt b/Documentation/devicetree/bindings/display/tilcdc/panel.txt
index f20b31cdc59a..808216310ea2 100644
--- a/Documentation/devicetree/bindings/display/tilcdc/panel.txt
+++ b/Documentation/devicetree/bindings/display/tilcdc/panel.txt
@@ -15,7 +15,7 @@ Required properties:
  - display-timings: typical videomode of lcd panel.  Multiple video modes
    can be listed if the panel supports multiple timings, but the 'native-mode'
    should be the preferred/default resolution.  Refer to
-   Documentation/devicetree/bindings/display/display-timing.txt for display
+   Documentation/devicetree/bindings/display/panel/display-timing.txt for display
    timing binding details.
 
 Optional properties:
diff --git a/Documentation/devicetree/bindings/display/zte,vou.txt b/Documentation/devicetree/bindings/display/zte,vou.txt
index 740e5bd2e4f7..9c356284232b 100644
--- a/Documentation/devicetree/bindings/display/zte,vou.txt
+++ b/Documentation/devicetree/bindings/display/zte,vou.txt
@@ -49,6 +49,15 @@ Required properties:
         "osc_clk"
         "xclk"
 
+* TV Encoder output device
+
+Required properties:
+ - compatible: should be "zte,zx296718-tvenc"
+ - reg: Physical base address and length of the TVENC device IO region
+ - zte,tvenc-power-control: the phandle to SYSCTRL block followed by two
+   integer cells.  The first cell is the offset of SYSCTRL register used
+   to control TV Encoder DAC power, and the second cell is the bit mask.
+
 Example:
 
 vou: vou@1440000 {
@@ -81,4 +90,10 @@ vou: vou@1440000 {
                          <&topcrm HDMI_XCLK>;
                 clock-names = "osc_cec", "osc_clk", "xclk";
         };
+
+        tvenc: tvenc@2000 {
+                compatible = "zte,zx296718-tvenc";
+                reg = <0x2000 0x1000>;
+                zte,tvenc-power-control = <&sysctrl 0x170 0x10>;
+        };
 };
diff --git a/Documentation/devicetree/bindings/eeprom/eeprom.txt b/Documentation/devicetree/bindings/eeprom/eeprom.txt
index 735bc94444bb..5696eb508e95 100644
--- a/Documentation/devicetree/bindings/eeprom/eeprom.txt
+++ b/Documentation/devicetree/bindings/eeprom/eeprom.txt
@@ -10,6 +10,8 @@ Required properties:
 
         "catalyst,24c32"
 
+        "microchip,24c128"
+
         "ramtron,24c64"
 
         "renesas,r1ex24002"
diff --git a/Documentation/devicetree/bindings/gpio/cortina,gemini-gpio.txt b/Documentation/devicetree/bindings/gpio/cortina,gemini-gpio.txt
new file mode 100644
index 000000000000..5c9246c054e5
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/cortina,gemini-gpio.txt
@@ -0,0 +1,24 @@
+Cortina Systems Gemini GPIO Controller
+
+Required properties:
+
+- compatible : Must be "cortina,gemini-gpio"
+- reg : Should contain registers location and length
+- interrupts : Should contain the interrupt line for the GPIO block
+- gpio-controller : marks this as a GPIO controller
+- #gpio-cells : Should be 2, see gpio/gpio.txt
+- interrupt-controller : marks this as an interrupt controller
+- #interrupt-cells : a standard two-cell interrupt flag, see
+  interrupt-controller/interrupts.txt
+
+Example:
+
+gpio@4d000000 {
+        compatible = "cortina,gemini-gpio";
+        reg = <0x4d000000 0x100>;
+        interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+        gpio-controller;
+        #gpio-cells = <2>;
+        interrupt-controller;
+        #interrupt-cells = <2>;
+};
diff --git a/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt b/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt
index 08dd15f89ba9..e63935710011 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt
@@ -29,6 +29,10 @@ Required properties:
         onsemi,pca9654
         exar,xra1202
 
+Optional properties:
+ - reset-gpios: GPIO specification for the RESET input. This is an
+                active low signal to the PCA953x.
+
 Example:
 
 
diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt
index 68d28f62a6f4..84ede036f73d 100644
--- a/Documentation/devicetree/bindings/gpio/gpio.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio.txt
@@ -187,10 +187,10 @@ gpio-controller's driver probe function.
 
 Each GPIO hog definition is represented as a child node of the GPIO controller.
 Required properties:
-- gpio-hog:   A property specifying that this child node represent a GPIO hog.
-- gpios:      Store the GPIO information (id, flags, ...). Shall contain the
-              number of cells specified in its parent node (GPIO controller
-              node).
+- gpio-hog:   A property specifying that this child node represents a GPIO hog.
+- gpios:      Store the GPIO information (id, flags, ...) for each GPIO to
+              affect. Shall contain an integer multiple of the number of cells
+              specified in its parent node (GPIO controller node).
 Only one of the following properties scanned in the order shown below.
 This means that when multiple properties are present they will be searched
 in the order presented below and the first match is taken as the intended
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
new file mode 100644
index 000000000000..476f5ea6c627
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
@@ -0,0 +1,81 @@
+ARM Mali Utgard GPU
+===================
+
+Required properties:
+  - compatible
+    * Must be one of the following:
+      + "arm,mali-300"
+      + "arm,mali-400"
+      + "arm,mali-450"
+    * And, optionally, one of the vendor specific compatible:
+      + allwinner,sun4i-a10-mali
+      + allwinner,sun7i-a20-mali
+      + amlogic,meson-gxbb-mali
+      + amlogic,meson-gxl-mali
+      + stericsson,db8500-mali
+
+  - reg: Physical base address and length of the GPU registers
+
+  - interrupts: an entry for each entry in interrupt-names.
+    See ../interrupt-controller/interrupts.txt for details.
+
+  - interrupt-names:
+    * ppX: Pixel Processor X interrupt (X from 0 to 7)
+    * ppmmuX: Pixel Processor X MMU interrupt (X from 0 to 7)
+    * pp: Pixel Processor broadcast interrupt (mali-450 only)
+    * gp: Geometry Processor interrupt
+    * gpmmu: Geometry Processor MMU interrupt
+
+  - clocks: an entry for each entry in clock-names
+  - clock-names:
+    * bus: bus clock for the GPU
+    * core: clock driving the GPU itself
+
+Optional properties:
+  - interrupt-names and interrupts:
+    * pmu: Power Management Unit interrupt, if implemented in hardware
+
+Vendor-specific bindings
+------------------------
+
+The Mali GPU is integrated very differently from one SoC to
+another. In order to accomodate those differences, you have the option
+to specify one more vendor-specific compatible, among:
+
+  - allwinner,sun4i-a10-mali
+    Required properties:
+      * resets: phandle to the reset line for the GPU
+
+  - allwinner,sun7i-a20-mali
+    Required properties:
+      * resets: phandle to the reset line for the GPU
+
+  - stericsson,db8500-mali
+    Required properties:
+      * interrupt-names and interrupts:
+        + combined: combined interrupt of all of the above lines
+
+Example:
+
+mali: gpu@1c40000 {
+        compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
+        reg = <0x01c40000 0x10000>;
+        interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "gp",
+                          "gpmmu",
+                          "pp0",
+                          "ppmmu0",
+                          "pp1",
+                          "ppmmu1",
+                          "pmu";
+        clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
+        clock-names = "bus", "core";
+        resets = <&ccu RST_BUS_GPU>;
+};
+
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt b/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt
index cf53d5fba20a..aa097045a10e 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt
@@ -19,7 +19,14 @@ Optional Properties:
   - i2c-mux-idle-disconnect: Boolean; if defined, forces mux to disconnect all
     children in idle state. This is necessary for example, if there are several
     multiplexers on the bus and the devices behind them use same I2C addresses.
-
+  - interrupt-parent: Phandle for the interrupt controller that services
+    interrupts for this device.
+  - interrupts: Interrupt mapping for IRQ.
+  - interrupt-controller: Marks the device node as an interrupt controller.
+  - #interrupt-cells : Should be two.
+    - first cell is the pin number
+    - second cell is used to specify flags.
+    See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
 
 Example:
 
@@ -29,6 +36,11 @@ Example:
                 #size-cells = <0>;
                 reg = <0x74>;
 
+                interrupt-parent = <&ipic>;
+                interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+
                 i2c@2 {
                         #address-cells = <1>;
                         #size-cells = <0>;
diff --git a/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt b/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt
index 7716acc55dec..ae9c2a735f39 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt
@@ -10,6 +10,7 @@ Required properties:
                         - "renesas,iic-r8a7793" (R-Car M2-N)
                         - "renesas,iic-r8a7794" (R-Car E2)
                         - "renesas,iic-r8a7795" (R-Car H3)
+                        - "renesas,iic-r8a7796" (R-Car M3-W)
                         - "renesas,iic-sh73a0" (SH-Mobile AG5)
                         - "renesas,rcar-gen2-iic" (generic R-Car Gen2 compatible device)
                         - "renesas,rcar-gen3-iic" (generic R-Car Gen3 compatible device)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-stm32.txt b/Documentation/devicetree/bindings/i2c/i2c-stm32.txt
new file mode 100644
index 000000000000..78eaf7b718ed
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-stm32.txt
@@ -0,0 +1,33 @@
+* I2C controller embedded in STMicroelectronics STM32 I2C platform
+
+Required properties :
+- compatible : Must be "st,stm32f4-i2c"
+- reg : Offset and length of the register set for the device
+- interrupts : Must contain the interrupt id for I2C event and then the
+  interrupt id for I2C error.
+- resets: Must contain the phandle to the reset controller.
+- clocks: Must contain the input clock of the I2C instance.
+- A pinctrl state named "default" must be defined to set pins in mode of
+  operation for I2C transfer
+- #address-cells = <1>;
+- #size-cells = <0>;
+
+Optional properties :
+- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified,
+  the default 100 kHz frequency will be used. As only Normal and Fast modes
+  are supported, possible values are 100000 and 400000.
+
+Example :
+
+        i2c@40005400 {
+                compatible = "st,stm32f4-i2c";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0x40005400 0x400>;
+                interrupts = <31>,
+                             <32>;
+                resets = <&rcc 277>;
+                clocks = <&rcc 0 149>;
+                pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>;
+                pinctrl-names = "default";
+        };
diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt b/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt
new file mode 100644
index 000000000000..ab240e10debc
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt
@@ -0,0 +1,42 @@
+NVIDIA Tegra186 BPMP I2C controller
+
+In Tegra186, the BPMP (Boot and Power Management Processor) owns certain HW
+devices, such as the I2C controller for the power management I2C bus. Software
+running on other CPUs must perform IPC to the BPMP in order to execute
+transactions on that I2C bus. This binding describes an I2C bus that is
+accessed in such a fashion.
+
+The BPMP I2C node must be located directly inside the main BPMP node. See
+../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding.
+
+This node represents an I2C controller. See ../i2c/i2c.txt for details of the
+core I2C binding.
+
+Required properties:
+- compatible:
+    Array of strings.
+    One of:
+    - "nvidia,tegra186-bpmp-i2c".
+- #address-cells: Address cells for I2C device address.
+    Single-cell integer.
+    Must be <1>.
+- #size-cells:
+    Single-cell integer.
+    Must be <0>.
+- nvidia,bpmp-bus-id:
+    Single-cell integer.
+    Indicates the I2C bus number this DT node represent, as defined by the
+    BPMP firmware.
+
+Example:
+
+bpmp {
+        ...
+
+        i2c {
+                compatible = "nvidia,tegra186-bpmp-i2c";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                nvidia,bpmp-bus-id = <5>;
+        };
+};
diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
index cdd7b48826c3..ad10fbe61562 100644
--- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt
+++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
@@ -36,6 +36,7 @@ dallas,ds1775		Tiny Digital Thermometer and Thermostat
 dallas,ds3232           Extremely Accurate I²C RTC with Integrated Crystal and SRAM
 dallas,ds4510           CPU Supervisor with Nonvolatile Memory and Programmable I/O
 dallas,ds75             Digital Thermometer and Thermostat
+devantech,srf08         Devantech SRF08 ultrasonic ranger
 dlg,da9053              DA9053: flexible system level PMIC with multicore support
 dlg,da9063              DA9063: system PMIC for quad-core application processors
 domintech,dmard09       DMARD09: 3-axis Accelerometer
diff --git a/Documentation/devicetree/bindings/iio/accel/lis302.txt b/Documentation/devicetree/bindings/iio/accel/lis302.txt
index 2a19bff9693f..dfdce67826ba 100644
--- a/Documentation/devicetree/bindings/iio/accel/lis302.txt
+++ b/Documentation/devicetree/bindings/iio/accel/lis302.txt
@@ -5,7 +5,7 @@ that apply in on the generic device (independent from the bus).
 
 
 Required properties for the SPI bindings:
- - compatible:          should be set to "st,lis3lv02d_spi"
+ - compatible:          should be set to "st,lis3lv02d-spi"
  - reg:                 the chipselect index
  - spi-max-frequency:   maximal bus speed, should be set to 1000000 unless
                         constrained by external circuitry
diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
new file mode 100644
index 000000000000..f9e3ff2c656e
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
@@ -0,0 +1,32 @@
+* Amlogic Meson SAR (Successive Approximation Register) A/D converter
+
+Required properties:
+- compatible:   depending on the SoC this should be one of:
+                        - "amlogic,meson-gxbb-saradc" for GXBB
+                        - "amlogic,meson-gxl-saradc" for GXL
+                        - "amlogic,meson-gxm-saradc" for GXM
+                along with the generic "amlogic,meson-saradc"
+- reg:          the physical base address and length of the registers
+- clocks:       phandle and clock identifier (see clock-names)
+- clock-names:  mandatory clocks:
+                        - "clkin" for the reference clock (typically XTAL)
+                        - "core" for the SAR ADC core clock
+                optional clocks:
+                        - "sana" for the analog clock
+                        - "adc_clk" for the ADC (sampling) clock
+                        - "adc_sel" for the ADC (sampling) clock mux
+- vref-supply:  the regulator supply for the ADC reference voltage
+- #io-channel-cells: must be 1, see ../iio-bindings.txt
+
+Example:
+        saradc: adc@8680 {
+                compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
+                #io-channel-cells = <1>;
+                reg = <0x0 0x8680 0x0 0x34>;
+                clocks = <&xtal>,
+                         <&clkc CLKID_SAR_ADC>,
+                         <&clkc CLKID_SANA>,
+                         <&clkc CLKID_SAR_ADC_CLK>,
+                         <&clkc CLKID_SAR_ADC_SEL>;
+                clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+        };
diff --git a/Documentation/devicetree/bindings/iio/adc/avia-hx711.txt b/Documentation/devicetree/bindings/iio/adc/avia-hx711.txt
new file mode 100644
index 000000000000..b3629405f568
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/avia-hx711.txt
@@ -0,0 +1,18 @@
+* AVIA HX711 ADC chip for weight cells
+  Bit-banging driver
+
+Required properties:
+ - compatible:  Should be "avia,hx711"
+ - sck-gpios:   Definition of the GPIO for the clock
+ - dout-gpios:  Definition of the GPIO for data-out
+                See Documentation/devicetree/bindings/gpio/gpio.txt
+ - avdd-supply: Definition of the regulator used as analog supply
+
+Example:
+weight@0 {
+        compatible = "avia,hx711";
+        sck-gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;
+        dout-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
+        avdd-suppy = <&avdd>;
+};
+
diff --git a/Documentation/devicetree/bindings/iio/adc/max11100.txt b/Documentation/devicetree/bindings/iio/adc/max11100.txt
new file mode 100644
index 000000000000..b7f7177b8aca
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/max11100.txt
@@ -0,0 +1,18 @@
+* Maxim max11100 Analog to Digital Converter (ADC)
+
+Required properties:
+  - compatible: Should be "maxim,max11100"
+  - reg: the adc unit address
+  - vref-supply: phandle to the regulator that provides reference voltage
+
+Optional properties:
+  - spi-max-frequency: SPI maximum frequency
+
+Example:
+
+max11100: adc@0 {
+        compatible = "maxim,max11100";
+        reg = <0>;
+        vref-supply = <&adc0_vref>;
+        spi-max-frequency = <240000>;
+};
diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,pm8xxx-xoadc.txt b/Documentation/devicetree/bindings/iio/adc/qcom,pm8xxx-xoadc.txt
new file mode 100644
index 000000000000..53cd146d8096
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/qcom,pm8xxx-xoadc.txt
@@ -0,0 +1,149 @@
+Qualcomm's PM8xxx voltage XOADC
+
+The Qualcomm PM8xxx PMICs contain a HK/XO ADC (Housekeeping/Crystal
+oscillator ADC) encompassing PM8018, PM8038, PM8058 and PM8921.
+
+Required properties:
+
+- compatible: should be one of:
+  "qcom,pm8018-adc"
+  "qcom,pm8038-adc"
+  "qcom,pm8058-adc"
+  "qcom,pm8921-adc"
+
+- reg: should contain the ADC base address in the PMIC, typically
+  0x197.
+
+- xoadc-ref-supply: should reference a regulator that can supply
+  a reference voltage on demand. The reference voltage may vary
+  with PMIC variant but is typically something like 2.2 or 1.8V.
+
+The following required properties are standard for IO channels, see
+iio-bindings.txt for more details:
+
+- #address-cells: should be set to <1>
+
+- #size-cells: should be set to <0>
+
+- #io-channel-cells: should be set to <1>
+
+- interrupts: should refer to the parent PMIC interrupt controller
+  and reference the proper ADC interrupt.
+
+Required subnodes:
+
+The ADC channels are configured as subnodes of the ADC. Since some of
+them are used for calibrating the ADC, these nodes are compulsory:
+
+adc-channel@c {
+        reg = <0x0c>;
+};
+
+adc-channel@d {
+        reg = <0x0d>;
+};
+
+adc-channel@f {
+        reg = <0x0f>;
+};
+
+These three nodes are used for absolute and ratiometric calibration
+and only need to have these reg values: they are by hardware definition
+1:1 ratio converters that sample 625, 1250 and 0 milliV and create
+an interpolation calibration for all other ADCs.
+
+Optional subnodes: any channels other than channel 0x0c, 0x0d and
+0x0f are optional.
+
+Required channel node properties:
+
+- reg: should contain the hardware channel number in the range
+  0 .. 0x0f (4 bits). The hardware only supports 16 channels.
+
+Optional channel node properties:
+
+- qcom,decimation:
+  Value type: <u32>
+  Definition: This parameter is used to decrease the ADC sampling rate.
+          Quicker measurements can be made by reducing the decimation ratio.
+          Valid values are 512, 1024, 2048, 4096.
+          If the property is not found, a default value of 512 will be used.
+
+- qcom,ratiometric:
+  Value type: <u32>
+  Definition: Channel calibration type. If this property is specified
+          VADC will use a special voltage references for channel
+          calibration. The available references are specified in the
+          as a u32 value setting (see below) and it is compulsory
+          to also specify this reference if ratiometric calibration
+          is selected.
+
+          If the property is not found, the channel will be
+          calibrated with the 0.625V and 1.25V reference channels, also
+          known as an absolute calibration.
+  The reference voltage pairs when using ratiometric calibration:
+          0 = XO_IN/XOADC_GND
+          1 = PMIC_IN/XOADC_GND
+          2 = PMIC_IN/BMS_CSP
+          3 (invalid)
+          4 = XOADC_GND/XOADC_GND
+          5 = XOADC_VREF/XOADC_GND
+
+Example:
+
+xoadc: xoadc@197 {
+        compatible = "qcom,pm8058-adc";
+        reg = <0x197>;
+        interrupt-parent = <&pm8058>;
+        interrupts = <76 1>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        #io-channel-cells = <1>;
+
+        vcoin: adc-channel@0 {
+                reg = <0x00>;
+        };
+        vbat: adc-channel@1 {
+                reg = <0x01>;
+        };
+        dcin: adc-channel@2 {
+                reg = <0x02>;
+        };
+        ichg: adc-channel@3 {
+                reg = <0x03>;
+        };
+        vph_pwr: adc-channel@4 {
+                reg = <0x04>;
+        };
+        usb_vbus: adc-channel@a {
+                reg = <0x0a>;
+        };
+        die_temp: adc-channel@b {
+                reg = <0x0b>;
+        };
+        ref_625mv: adc-channel@c {
+                reg = <0x0c>;
+        };
+        ref_1250mv: adc-channel@d {
+                reg = <0x0d>;
+        };
+        ref_325mv: adc-channel@e {
+                reg = <0x0e>;
+        };
+        ref_muxoff: adc-channel@f {
+                reg = <0x0f>;
+        };
+};
+
+
+/* IIO client node */
+iio-hwmon {
+        compatible = "iio-hwmon";
+        io-channels = <&xoadc 0x01>, /* Battery */
+                    <&xoadc 0x02>, /* DC in (charger) */
+                    <&xoadc 0x04>, /* VPH the main system voltage */
+                    <&xoadc 0x0b>, /* Die temperature */
+                    <&xoadc 0x0c>, /* Reference voltage 1.25V */
+                    <&xoadc 0x0d>, /* Reference voltage 0.625V */
+                    <&xoadc 0x0e>; /* Reference voltage 0.325V */
+};
diff --git a/Documentation/devicetree/bindings/iio/adc/renesas,gyroadc.txt b/Documentation/devicetree/bindings/iio/adc/renesas,gyroadc.txt
new file mode 100644
index 000000000000..f5b0adae6010
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/renesas,gyroadc.txt
@@ -0,0 +1,99 @@
+* Renesas RCar GyroADC device driver
+
+The GyroADC block is a reduced SPI block with up to 8 chipselect lines,
+which supports the SPI protocol of a selected few SPI ADCs. The SPI ADCs
+are sampled by the GyroADC block in a round-robin fashion and the result
+presented in the GyroADC registers.
+
+Required properties:
+- compatible:   Should be "<soc-specific>", "renesas,rcar-gyroadc".
+                The <soc-specific> should be one of:
+                renesas,r8a7791-gyroadc - for the GyroADC block present
+                                          in r8a7791 SoC
+                renesas,r8a7792-gyroadc - for the GyroADC with interrupt
+                                          block present in r8a7792 SoC
+- reg:          Address and length of the register set for the device
+- clocks:       References to all the clocks specified in the clock-names
+                property as specified in
+                Documentation/devicetree/bindings/clock/clock-bindings.txt.
+- clock-names:  Shall contain "fck" and "if". The "fck" is the GyroADC block
+                clock, the "if" is the interface clock.
+- power-domains: Must contain a reference to the PM domain, if available.
+- #address-cells: Should be <1> (setting for the subnodes) for all ADCs
+                except for "fujitsu,mb88101a". Should be <0> (setting for
+                only subnode) for "fujitsu,mb88101a".
+- #size-cells:  Should be <0> (setting for the subnodes)
+
+Sub-nodes:
+You must define subnode(s) which select the connected ADC type and reference
+voltage for the GyroADC channels.
+
+Required properties for subnodes:
+- compatible:   Should be either of:
+                "fujitsu,mb88101a"
+                        - Fujitsu MB88101A compatible mode,
+                          12bit sampling, up to 4 channels can be sampled in
+                          round-robin fashion. One Fujitsu chip supplies four
+                          GyroADC channels with data as it contains four ADCs
+                          on the chip and thus for 4-channel operation, single
+                          MB88101A is required. The Cx chipselect lines of the
+                          MB88101A connect directly to two CHS lines of the
+                          GyroADC, no demuxer is required. The data out line
+                          of each MB88101A connects to a shared input pin of
+                          the GyroADC.
+                "ti,adcs7476" or "ti,adc121" or "adi,ad7476"
+                        - TI ADCS7476 / TI ADC121 / ADI AD7476 compatible mode,
+                          15bit sampling, up to 8 channels can be sampled in
+                          round-robin fashion. One TI/ADI chip supplies single
+                          ADC channel with data, thus for 8-channel operation,
+                          8 chips are required. A 3:8 chipselect demuxer is
+                          required to connect the nCS line of the TI/ADI chips
+                          to the GyroADC, while MISO line of each TI/ADI ADC
+                          connects to a shared input pin of the GyroADC.
+                "maxim,max1162" or "maxim,max11100"
+                        - Maxim MAX1162 / Maxim MAX11100 compatible mode,
+                          16bit sampling, up to 8 channels can be sampled in
+                          round-robin fashion. One Maxim chip supplies single
+                          ADC channel with data, thus for 8-channel operation,
+                          8 chips are required. A 3:8 chipselect demuxer is
+                          required to connect the nCS line of the MAX chips
+                          to the GyroADC, while MISO line of each Maxim ADC
+                          connects to a shared input pin of the GyroADC.
+- reg:          Should be the number of the analog input. Should be present
+                for all ADCs except "fujitsu,mb88101a".
+- vref-supply:  Reference to the channel reference voltage regulator.
+
+Example:
+        vref_max1162: regulator-vref-max1162 {
+                compatible = "regulator-fixed";
+
+                regulator-name = "MAX1162 Vref";
+                regulator-min-microvolt = <4096000>;
+                regulator-max-microvolt = <4096000>;
+        };
+
+        adc@e6e54000 {
+                compatible = "renesas,r8a7791-gyroadc", "renesas,rcar-gyroadc";
+                reg = <0 0xe6e54000 0 64>;
+                clocks = <&mstp9_clks R8A7791_CLK_GYROADC>, <&clk_65m>;
+                clock-names = "fck", "if";
+                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+
+                pinctrl-0 = <&adc_pins>;
+                pinctrl-names = "default";
+
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                adc@0 {
+                        reg = <0>;
+                        compatible = "maxim,max1162";
+                        vref-supply = <&vref_max1162>;
+                };
+
+                adc@1 {
+                        reg = <1>;
+                        compatible = "maxim,max1162";
+                        vref-supply = <&vref_max1162>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt
index 49ed82e89870..5dfc88ec24a4 100644
--- a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt
+++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt
@@ -53,6 +53,11 @@ Required properties:
 - #io-channel-cells = <1>: See the IIO bindings section "IIO consumers" in
   Documentation/devicetree/bindings/iio/iio-bindings.txt
 
+Optional properties:
+- dmas: Phandle to dma channel for this ADC instance.
+  See ../../dma/dma.txt for details.
+- dma-names: Must be "rx" when dmas property is being used.
+
 Example:
         adc: adc@40012000 {
                 compatible = "st,stm32f4-adc-core";
@@ -77,6 +82,8 @@ Example:
                         interrupt-parent = <&adc>;
                         interrupts = <0>;
                         st,adc-channels = <8>;
+                        dmas = <&dma2 0 0 0x400 0x0>;
+                        dma-names = "rx";
                 };
                 ...
                 other adc child nodes follow...
diff --git a/Documentation/devicetree/bindings/iio/adc/ti-ads7950.txt b/Documentation/devicetree/bindings/iio/adc/ti-ads7950.txt
new file mode 100644
index 000000000000..e77a6f7e1001
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/ti-ads7950.txt
@@ -0,0 +1,23 @@
+* Texas Instruments ADS7950 family of A/DC chips
+
+Required properties:
+ - compatible: Must be one of "ti,ads7950", "ti,ads7951", "ti,ads7952",
+   "ti,ads7953", "ti,ads7954", "ti,ads7955", "ti,ads7956", "ti,ads7957",
+   "ti,ads7958", "ti,ads7959", "ti,ads7960", or "ti,ads7961"
+ - reg: SPI chip select number for the device
+ - #io-channel-cells: Must be 1 as per ../iio-bindings.txt
+ - vref-supply: phandle to a regulator node that supplies the 2.5V or 5V
+   reference voltage
+
+Recommended properties:
+ - spi-max-frequency: Definition as per
+                Documentation/devicetree/bindings/spi/spi-bus.txt
+
+Example:
+adc@0 {
+        compatible = "ti,ads7957";
+        reg = <0>;
+        #io-channel-cells = <1>;
+        vref-supply = <&refin_supply>;
+        spi-max-frequency = <10000000>;
+};
diff --git a/Documentation/devicetree/bindings/iio/imu/bmi160.txt b/Documentation/devicetree/bindings/iio/imu/bmi160.txt
new file mode 100644
index 000000000000..ae0112c7debc
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/imu/bmi160.txt
@@ -0,0 +1,36 @@
+Bosch BMI160 - Inertial Measurement Unit with Accelerometer, Gyroscope
+and externally connectable Magnetometer
+
+https://www.bosch-sensortec.com/bst/products/all_products/bmi160
+
+Required properties:
+ - compatible : should be "bosch,bmi160"
+ - reg : the I2C address or SPI chip select number of the sensor
+ - spi-max-frequency : set maximum clock frequency (only for SPI)
+
+Optional properties:
+ - interrupt-parent : should be the phandle of the interrupt controller
+ - interrupts : interrupt mapping for IRQ, must be IRQ_TYPE_LEVEL_LOW
+ - interrupt-names : set to "INT1" if INT1 pin should be used as interrupt
+   input, set to "INT2" if INT2 pin should be used instead
+
+Examples:
+
+bmi160@68 {
+        compatible = "bosch,bmi160";
+        reg = <0x68>;
+
+        interrupt-parent = <&gpio4>;
+        interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+        interrupt-names = "INT1";
+};
+
+bmi160@0 {
+        compatible = "bosch,bmi160";
+        reg = <0>;
+        spi-max-frequency = <10000000>;
+
+        interrupt-parent = <&gpio2>;
+        interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+        interrupt-names = "INT2";
+};
diff --git a/Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt b/Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt
new file mode 100644
index 000000000000..cf81afdf7803
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt
@@ -0,0 +1,26 @@
+* ST_LSM6DSx driver for STM 6-axis (acc + gyro) imu Mems sensors
+
+Required properties:
+- compatible: must be one of:
+  "st,lsm6ds3"
+  "st,lsm6dsm"
+- reg: i2c address of the sensor / spi cs line
+
+Optional properties:
+- st,drdy-int-pin: the pin on the package that will be used to signal
+  "data ready" (valid values: 1 or 2).
+- interrupt-parent: should be the phandle for the interrupt controller
+- interrupts: interrupt mapping for IRQ. It should be configured with
+  flags IRQ_TYPE_LEVEL_HIGH or IRQ_TYPE_EDGE_RISING.
+
+  Refer to interrupt-controller/interrupts.txt for generic interrupt
+  client node bindings.
+
+Example:
+
+lsm6dsm@6b {
+        compatible = "st,lsm6dsm";
+        reg = <0x6b>;
+        interrupt-parent = <&gpio0>;
+        interrupts = <0 IRQ_TYPE_EDGE_RISING>;
+};
diff --git a/Documentation/devicetree/bindings/iio/light/cm3605.txt b/Documentation/devicetree/bindings/iio/light/cm3605.txt
new file mode 100644
index 000000000000..56331a79f9ab
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/light/cm3605.txt
@@ -0,0 +1,41 @@
+Capella Microsystems CM3605
+Ambient Light and Short Distance Proximity Sensor
+
+The CM3605 is an entirely analog part which however require quite a bit of
+software logic to interface a host operating system.
+
+This ALS and proximity sensor was one of the very first deployed in mobile
+handsets, notably it is used in the very first Nexus One Android phone from
+2010.
+
+Required properties:
+- compatible: must be: "capella,cm3605"
+- aset-gpios: GPIO line controlling the ASET line (drive low
+  to activate the ALS, should be flagged GPIO_ACTIVE_LOW)
+- interrupts: the IRQ line (such as a GPIO) that is connected to
+  the POUT (proximity sensor out) line. The edge detection must
+  be set to IRQ_TYPE_EDGE_BOTH so as to detect movements toward
+  and away from the proximity sensor.
+- io-channels: the ADC channel used for converting the voltage from
+  AOUT to a digital representation.
+- io-channel-names: must be "aout"
+
+Optional properties:
+- vdd-supply: regulator supplying VDD power to the component.
+- capella,aset-resistance-ohms: the sensitivity calibration resistance,
+  in Ohms. Valid values are: 50000, 100000, 300000 and 600000,
+  as these are the resistance values that we are supplied with
+  calibration curves for. If not supplied, 100 kOhm will be assumed
+  but it is strongly recommended to supply this.
+
+Example:
+
+cm3605 {
+        compatible = "capella,cm3605";
+        vdd-supply = <&foo_reg>;
+        aset-gpios = <&foo_gpio 1 GPIO_ACTIVE_LOW>;
+        capella,aset-resistance-ohms = <100000>;
+        interrupts = <1 IRQ_TYPE_EDGE_BOTH>;
+        io-channels = <&adc 0x01>;
+        io-channel-names = "aout";
+};
diff --git a/Documentation/devicetree/bindings/iio/potentiometer/max5481.txt b/Documentation/devicetree/bindings/iio/potentiometer/max5481.txt
new file mode 100644
index 000000000000..6a91b106e076
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/potentiometer/max5481.txt
@@ -0,0 +1,23 @@
+* Maxim Linear-Taper Digital Potentiometer MAX5481-MAX5484
+
+The node for this driver must be a child node of a SPI controller, hence
+all mandatory properties described in
+
+        Documentation/devicetree/bindings/spi/spi-bus.txt
+
+must be specified.
+
+Required properties:
+        - compatible:   Must be one of the following, depending on the
+                        model:
+                        "maxim,max5481"
+                        "maxim,max5482"
+                        "maxim,max5483"
+                        "maxim,max5484"
+
+Example:
+max548x: max548x@0 {
+        compatible = "maxim,max5482";
+        spi-max-frequency = <7000000>;
+        reg = <0>; /* chip-select */
+};
diff --git a/Documentation/devicetree/bindings/iio/st-sensors.txt b/Documentation/devicetree/bindings/iio/st-sensors.txt
index c040c9ad1889..eaa8fbba34e2 100644
--- a/Documentation/devicetree/bindings/iio/st-sensors.txt
+++ b/Documentation/devicetree/bindings/iio/st-sensors.txt
@@ -27,6 +27,8 @@ standard bindings from pinctrl/pinctrl-bindings.txt.
 Valid compatible strings:
 
 Accelerometers:
+- st,lis3lv02d (deprecated, use st,lis3lv02dl-accel)
+- st,lis302dl-spi (deprecated, use st,lis3lv02dl-accel)
 - st,lis3lv02dl-accel
 - st,lsm303dlh-accel
 - st,lsm303dlhc-accel
diff --git a/Documentation/devicetree/bindings/iio/temperature/tmp007.txt b/Documentation/devicetree/bindings/iio/temperature/tmp007.txt
new file mode 100644
index 000000000000..b63aba91ef03
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/temperature/tmp007.txt
@@ -0,0 +1,35 @@
+* TI TMP007 - IR thermopile sensor with integrated math engine
+
+Link to datasheet: http://www.ti.com/lit/ds/symlink/tmp007.pdf
+
+Required properties:
+
+  - compatible: should be "ti,tmp007"
+  - reg: the I2C address of the sensor (changeable via ADR pins)
+                ------------------------------
+                |ADR1 | ADR0 | Device Address|
+                ------------------------------
+                   0      0        0x40
+                   0      1        0x41
+                   0     SDA       0x42
+                   0     SCL       0x43
+                   1      0        0x44
+                   1      1        0x45
+                   1     SDA       0x46
+                   1     SCL       0x47
+
+Optional properties:
+
+  - interrupt-parent: should be the phandle for the interrupt controller
+
+  - interrupts: interrupt mapping for GPIO IRQ (level active low)
+
+Example:
+
+tmp007@40 {
+        compatible = "ti,tmp007";
+        reg = <0x40>;
+        interrupt-parent = <&gpio0>;
+        interrupts = <5 0x08>;
+};
+
diff --git a/Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt b/Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt
new file mode 100644
index 000000000000..55a653d15303
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt
@@ -0,0 +1,23 @@
+STMicroelectronics STM32 Timers IIO timer bindings
+
+Must be a sub-node of an STM32 Timers device tree node.
+See ../mfd/stm32-timers.txt for details about the parent node.
+
+Required parameters:
+- compatible:   Must be "st,stm32-timer-trigger".
+- reg:          Identify trigger hardware block.
+
+Example:
+        timers@40010000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "st,stm32-timers";
+                reg = <0x40010000 0x400>;
+                clocks = <&rcc 0 160>;
+                clock-names = "clk_int";
+
+                timer@0 {
+                        compatible = "st,stm32-timer-trigger";
+                        reg = <0>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/input/cypress,tm2-touchkey.txt b/Documentation/devicetree/bindings/input/cypress,tm2-touchkey.txt
new file mode 100644
index 000000000000..635f62c756ee
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/cypress,tm2-touchkey.txt
@@ -0,0 +1,27 @@
+Samsung tm2-touchkey
+
+Required properties:
+- compatible: must be "cypress,tm2-touchkey"
+- reg: I2C address of the chip.
+- interrupt-parent: a phandle for the interrupt controller (see interrupt
+        binding[0]).
+- interrupts: interrupt to which the chip is connected (see interrupt
+        binding[0]).
+- vcc-supply : internal regulator output. 1.8V
+- vdd-supply : power supply for IC 3.3V
+
+[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
+
+Example:
+        &i2c0 {
+                /* ... */
+
+                touchkey@20 {
+                        compatible = "cypress,tm2-touchkey";
+                        reg = <0x20>;
+                        interrupt-parent = <&gpa3>;
+                        interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+                        vcc-supply=<&ldo32_reg>;
+                        vdd-supply=<&ldo33_reg>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/input/mpr121-touchkey.txt b/Documentation/devicetree/bindings/input/mpr121-touchkey.txt
new file mode 100644
index 000000000000..b7c61ee5841b
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/mpr121-touchkey.txt
@@ -0,0 +1,30 @@
+* Freescale MPR121 Controllor
+
+Required Properties:
+- compatible:           Should be "fsl,mpr121-touchkey"
+- reg:                  The I2C slave address of the device.
+- interrupts:           The interrupt number to the cpu.
+- vdd-supply:           Phandle to the Vdd power supply.
+- linux,keycodes:       Specifies an array of numeric keycode values to
+                        be used for reporting button presses. The array can
+                        contain up to 12 entries.
+
+Optional Properties:
+- wakeup-source:        Use any event on keypad as wakeup event.
+- autorepeat:           Enable autorepeat feature.
+
+Example:
+
+#include "dt-bindings/input/input.h"
+
+        touchkey: mpr121@5a {
+                compatible = "fsl,mpr121-touchkey";
+                reg = <0x5a>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <28 2>;
+                autorepeat;
+                vdd-supply = <&ldo4_reg>;
+                linux,keycodes = <KEY_0>, <KEY_1>, <KEY_2>, <KEY_3>,
+                                <KEY_4> <KEY_5>, <KEY_6>, <KEY_7>,
+                                <KEY_8>, <KEY_9>, <KEY_A>, <KEY_B>;
+        };
diff --git a/Documentation/devicetree/bindings/input/pwm-beeper.txt b/Documentation/devicetree/bindings/input/pwm-beeper.txt
index be332ae4f2d6..529408b4431a 100644
--- a/Documentation/devicetree/bindings/input/pwm-beeper.txt
+++ b/Documentation/devicetree/bindings/input/pwm-beeper.txt
@@ -5,3 +5,19 @@ Registers a PWM device as beeper.
 Required properties:
 - compatible: should be "pwm-beeper"
 - pwms: phandle to the physical PWM device
+
+Optional properties:
+- amp-supply: phandle to a regulator that acts as an amplifier for the beeper
+
+Example:
+
+beeper_amp: amplifier {
+        compatible = "fixed-regulator";
+        gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
+};
+
+beeper {
+        compatible = "pwm-beeper";
+        pwms = <&pwm0>;
+        amp-supply = <&beeper_amp>;
+};
diff --git a/Documentation/devicetree/bindings/input/touchscreen/zet6223.txt b/Documentation/devicetree/bindings/input/touchscreen/zet6223.txt
new file mode 100644
index 000000000000..fe6a1feef703
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/touchscreen/zet6223.txt
@@ -0,0 +1,32 @@
+Zeitec ZET6223 I2C touchscreen controller
+
+Required properties:
+- compatible              : "zeitec,zet6223"
+- reg                     : I2C slave address of the chip (0x76)
+- interrupt-parent        : a phandle pointing to the interrupt controller
+                            serving the interrupt for this chip
+- interrupts              : interrupt specification for the zet6223 interrupt
+
+Optional properties:
+
+- vio-supply              : Specification for VIO supply (1.8V or 3.3V,
+                            depending on system interface needs).
+- vcc-supply              : Specification for 3.3V VCC supply.
+- touchscreen-size-x      : See touchscreen.txt
+- touchscreen-size-y      : See touchscreen.txt
+- touchscreen-inverted-x  : See touchscreen.txt
+- touchscreen-inverted-y  : See touchscreen.txt
+- touchscreen-swapped-x-y : See touchscreen.txt
+
+Example:
+
+i2c@00000000 {
+
+        zet6223: touchscreen@76 {
+                compatible = "zeitec,zet6223";
+                reg = <0x76>;
+                interrupt-parent = <&pio>;
+                interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>
+        };
+
+};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
index 5393e2a45a42..560d8a727b8f 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
@@ -111,7 +111,7 @@ Example:
                 #interrupt-cells = <3>;
                 interrupt-controller;
                 reg = <0x2c001000 0x1000>,
-                      <0x2c002000 0x1000>,
+                      <0x2c002000 0x2000>,
                       <0x2c004000 0x2000>,
                       <0x2c006000 0x2000>;
                 interrupts = <1 9 0xf04>;
diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt
index 944657684d73..8b46a34e05f1 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt
@@ -8,15 +8,11 @@ Properties:
 - compatible: "snps,archs-idu-intc"
 - interrupt-controller: This is an interrupt controller.
 - interrupt-parent: <reference to parent core intc>
-- #interrupt-cells: Must be <2>.
-- interrupts: <...> specifies the upstream core irqs
+- #interrupt-cells: Must be <1>.
 
-  First cell specifies the "common" IRQ from peripheral to IDU
-  Second cell specifies the irq distribution mode to cores
-     0=Round Robin; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
-
-  The second cell in interrupts property is deprecated and may be ignored by
-  the kernel.
+  Value of the cell specifies the "common" IRQ from peripheral to IDU. Number N
+  of the particular interrupt line of IDU corresponds to the line N+24 of the
+  core interrupt controller.
 
   intc accessed via the special ARC AUX register interface, hence "reg" property
   is not specified.
@@ -32,18 +28,10 @@ Example:
                 compatible = "snps,archs-idu-intc";
                 interrupt-controller;
                 interrupt-parent = <&core_intc>;
-
-                /*
-                 * <hwirq  distribution>
-                 * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
-                 */
-                #interrupt-cells = <2>;
-
-                /* upstream core irqs: downstream these are "COMMON" irq 0,1..  */
-                interrupts = <24 25 26 27 28 29 30 31>;
+                #interrupt-cells = <1>;
         };
 
         some_device: serial@c0fc1000 {
                 interrupt-parent = <&idu_intc>;
-                interrupts = <0 0>;     /* upstream idu IRQ #24, Round Robin */
+                interrupts = <0>;       /* upstream idu IRQ #24 */
         };
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
index e862d1485205..6cdf32d037fc 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
@@ -36,15 +36,15 @@ conditions.
                   combined interrupt, it must be listed multiple times.
 
 - #iommu-cells  : See Documentation/devicetree/bindings/iommu/iommu.txt
-                  for details. With a value of 1, each "iommus" entry
+                  for details. With a value of 1, each IOMMU specifier
                   represents a distinct stream ID emitted by that device
                   into the relevant SMMU.
 
                   SMMUs with stream matching support and complex masters
-                  may use a value of 2, where the second cell represents
-                  an SMR mask to combine with the ID in the first cell.
-                  Care must be taken to ensure the set of matched IDs
-                  does not result in conflicts.
+                  may use a value of 2, where the second cell of the
+                  IOMMU specifier represents an SMR mask to combine with
+                  the ID in the first cell.  Care must be taken to ensure
+                  the set of matched IDs does not result in conflicts.
 
 ** System MMU optional properties:
 
diff --git a/Documentation/devicetree/bindings/mfd/as3722.txt b/Documentation/devicetree/bindings/mfd/as3722.txt
index 4f64b2a73169..0b2a6099aa20 100644
--- a/Documentation/devicetree/bindings/mfd/as3722.txt
+++ b/Documentation/devicetree/bindings/mfd/as3722.txt
@@ -122,8 +122,7 @@ Following are properties of regulator subnode.
 
 Power-off:
 =========
-AS3722 supports the system power off by turning off all its rail. This
-is provided through pm_power_off.
+AS3722 supports the system power off by turning off all its rails.
 The device node should have the following properties to enable this
 functionality
 ams,system-power-controller: Boolean, to enable the power off functionality
diff --git a/Documentation/devicetree/bindings/mfd/aspeed-gfx.txt b/Documentation/devicetree/bindings/mfd/aspeed-gfx.txt
new file mode 100644
index 000000000000..aea5370efd97
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/aspeed-gfx.txt
@@ -0,0 +1,17 @@
+* Device tree bindings for Aspeed SoC Display Controller (GFX)
+
+The Aspeed SoC Display Controller primarily does as its name suggests, but also
+participates in pinmux requests on the g5 SoCs. It is therefore considered a
+syscon device.
+
+Required properties:
+- compatible:           "aspeed,ast2500-gfx", "syscon"
+- reg:                  contains offset/length value of the GFX memory
+                        region.
+
+Example:
+
+gfx: display@1e6e6000 {
+        compatible = "aspeed,ast2500-gfx", "syscon";
+        reg = <0x1e6e6000 0x1000>;
+};
diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
new file mode 100644
index 000000000000..514d82ced95b
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
@@ -0,0 +1,137 @@
+======================================================================
+Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller
+======================================================================
+
+The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
+peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The
+primary use case of the Aspeed LPC controller is as a slave on the bus
+(typically in a Baseboard Management Controller SoC), but under certain
+conditions it can also take the role of bus master.
+
+The LPC controller is represented as a multi-function device to account for the
+mix of functionality it provides. The principle split is between the register
+layout at the start of the I/O space which is, to quote the Aspeed datasheet,
+"basically compatible with the [LPC registers from the] popular BMC controller
+H8S/2168[1]", and everything else, where everything else is an eclectic
+collection of functions with a esoteric register layout. "Everything else",
+here labeled the "host" portion of the controller, includes, but is not limited
+to:
+
+* An IPMI Block Transfer[2] Controller
+
+* An LPC Host Controller: Manages LPC functions such as host vs slave mode, the
+  physical properties of some LPC pins, configuration of serial IRQs, and
+  APB-to-LPC bridging amonst other functions.
+
+* An LPC Host Interface Controller: Manages functions exposed to the host such
+  as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
+  management and bus snoop configuration.
+
+* A set of SuperIO[3] scratch registers: Enables implementation of e.g. custom
+  hardware management protocols for handover between the host and baseboard
+  management controller.
+
+Additionally the state of the LPC controller influences the pinmux
+configuration, therefore the host portion of the controller is exposed as a
+syscon as a means to arbitrate access.
+
+[0] http://www.intel.com/design/chipsets/industry/25128901.pdf
+[1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c88837454702128622bee53acbda8f4
+[2] http://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf
+[3] https://en.wikipedia.org/wiki/Super_I/O
+
+Required properties
+===================
+
+- compatible:   One of:
+                "aspeed,ast2400-lpc", "simple-mfd"
+                "aspeed,ast2500-lpc", "simple-mfd"
+
+- reg:          contains the physical address and length values of the Aspeed
+                LPC memory region.
+
+- #address-cells: <1>
+- #size-cells:  <1>
+- ranges:       Maps 0 to the physical address and length of the LPC memory
+                region
+
+Required LPC Child nodes
+========================
+
+BMC Node
+--------
+
+- compatible:   One of:
+                "aspeed,ast2400-lpc-bmc"
+                "aspeed,ast2500-lpc-bmc"
+
+- reg:          contains the physical address and length values of the
+                H8S/2168-compatible LPC controller memory region
+
+Host Node
+---------
+
+- compatible:   One of:
+                "aspeed,ast2400-lpc-host", "simple-mfd", "syscon"
+                "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"
+
+- reg:          contains the address and length values of the host-related
+                register space for the Aspeed LPC controller
+
+- #address-cells: <1>
+- #size-cells:  <1>
+- ranges:       Maps 0 to the address and length of the host-related LPC memory
+                region
+
+Example:
+
+lpc: lpc@1e789000 {
+        compatible = "aspeed,ast2500-lpc", "simple-mfd";
+        reg = <0x1e789000 0x1000>;
+
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges = <0x0 0x1e789000 0x1000>;
+
+        lpc_bmc: lpc-bmc@0 {
+                compatible = "aspeed,ast2500-lpc-bmc";
+                reg = <0x0 0x80>;
+        };
+
+        lpc_host: lpc-host@80 {
+                compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
+                reg = <0x80 0x1e0>;
+                reg-io-width = <4>;
+
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0x0 0x80 0x1e0>;
+        };
+};
+
+Host Node Children
+==================
+
+LPC Host Controller
+-------------------
+
+The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour
+between the host and the baseboard management controller. The registers exist
+in the "host" portion of the Aspeed LPC controller, which must be the parent of
+the LPC host controller node.
+
+Required properties:
+
+- compatible:   One of:
+                "aspeed,ast2400-lhc";
+                "aspeed,ast2500-lhc";
+
+- reg:          contains offset/length values of the LHC memory regions. In the
+                AST2400 and AST2500 there are two regions.
+
+Example:
+
+lhc: lhc@20 {
+        compatible = "aspeed,ast2500-lhc";
+        reg = <0x20 0x24 0x48 0x8>;
+};
diff --git a/Documentation/devicetree/bindings/mfd/mfd.txt b/Documentation/devicetree/bindings/mfd/mfd.txt
index af9d6931a1a2..bcb6abb9d413 100644
--- a/Documentation/devicetree/bindings/mfd/mfd.txt
+++ b/Documentation/devicetree/bindings/mfd/mfd.txt
@@ -19,12 +19,22 @@ Optional properties:
 
 - compatible : "simple-mfd" - this signifies that the operating system should
   consider all subnodes of the MFD device as separate devices akin to how
-  "simple-bus" inidicates when to see subnodes as children for a simple
+  "simple-bus" indicates when to see subnodes as children for a simple
   memory-mapped bus. For more complex devices, when the nexus driver has to
   probe registers to figure out what child devices exist etc, this should not
   be used. In the latter case the child devices will be determined by the
   operating system.
 
+- ranges: Describes the address mapping relationship to the parent. Should set
+  the child's base address to 0, the physical address within parent's address
+  space, and the length of the address map.
+
+- #address-cells: Specifies the number of cells used to represent physical base
+  addresses. Must be present if ranges is used.
+
+- #size-cells: Specifies the number of cells used to represent the size of an
+  address. Must be present if ranges is used.
+
 Example:
 
 foo@1000 {
diff --git a/Documentation/devicetree/bindings/mfd/motorola-cpcap.txt b/Documentation/devicetree/bindings/mfd/motorola-cpcap.txt
new file mode 100644
index 000000000000..15bc885f9df4
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/motorola-cpcap.txt
@@ -0,0 +1,31 @@
+Motorola CPCAP PMIC device tree binding
+
+Required properties:
+- compatible            : One or both of "motorola,cpcap" or "ste,6556002"
+- reg                   : SPI chip select
+- interrupt-parent      : The parent interrupt controller
+- interrupts            : The interrupt line the device is connected to
+- interrupt-controller  : Marks the device node as an interrupt controller
+- #interrupt-cells      : The number of cells to describe an IRQ, should be 2
+- #address-cells        : Child device offset number of cells, should be 1
+- #size-cells           : Child device size number of cells, should be 0
+- spi-max-frequency     : Typically set to 3000000
+- spi-cs-high           : SPI chip select direction
+
+Example:
+
+&mcspi1 {
+        cpcap: pmic@0 {
+                compatible = "motorola,cpcap", "ste,6556002";
+                reg = <0>;      /* cs0 */
+                interrupt-parent = <&gpio1>;
+                interrupts = <7 IRQ_TYPE_EDGE_RISING>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                spi-max-frequency = <3000000>;
+                spi-cs-high;
+        };
+};
+
diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt b/Documentation/devicetree/bindings/mfd/mt6397.txt
index 949c85f8d02c..c568d52af5af 100644
--- a/Documentation/devicetree/bindings/mfd/mt6397.txt
+++ b/Documentation/devicetree/bindings/mfd/mt6397.txt
@@ -34,6 +34,10 @@ Optional subnodes:
 - clk
         Required properties:
                 - compatible: "mediatek,mt6397-clk"
+- led
+        Required properties:
+                - compatible: "mediatek,mt6323-led"
+        see Documentation/devicetree/bindings/leds/leds-mt6323.txt
 
 Example:
         pwrap: pwrap@1000f000 {
diff --git a/Documentation/devicetree/bindings/mfd/omap-usb-host.txt b/Documentation/devicetree/bindings/mfd/omap-usb-host.txt
index 4721b2d521e4..aa1eaa59581b 100644
--- a/Documentation/devicetree/bindings/mfd/omap-usb-host.txt
+++ b/Documentation/devicetree/bindings/mfd/omap-usb-host.txt
@@ -64,8 +64,8 @@ Required properties if child node exists:
 Properties for children:
 
 The OMAP HS USB Host subsystem contains EHCI and OHCI controllers.
-See Documentation/devicetree/bindings/usb/omap-ehci.txt and
-omap3-ohci.txt
+See Documentation/devicetree/bindings/usb/ehci-omap.txt and
+Documentation/devicetree/bindings/usb/ohci-omap3.txt.
 
 Example for OMAP4:
 
diff --git a/Documentation/devicetree/bindings/mfd/qcom-rpm.txt b/Documentation/devicetree/bindings/mfd/qcom-rpm.txt
index 485bc59fcc48..3c91ad430eea 100644
--- a/Documentation/devicetree/bindings/mfd/qcom-rpm.txt
+++ b/Documentation/devicetree/bindings/mfd/qcom-rpm.txt
@@ -234,7 +234,7 @@ see regulator.txt - with additional custom properties described below:
 - qcom,switch-mode-frequency:
         Usage: required
         Value type: <u32>
-        Definition: Frequency (Hz) of the swith mode power supply;
+        Definition: Frequency (Hz) of the switch mode power supply;
                     must be one of:
                     19200000, 9600000, 6400000, 4800000, 3840000, 3200000,
                     2740000, 2400000, 2130000, 1920000, 1750000, 1600000,
diff --git a/Documentation/devicetree/bindings/mfd/stm32-timers.txt b/Documentation/devicetree/bindings/mfd/stm32-timers.txt
new file mode 100644
index 000000000000..bbd083f5600a
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/stm32-timers.txt
@@ -0,0 +1,46 @@
+STM32 Timers driver bindings
+
+This IP provides 3 types of timer along with PWM functionality:
+- advanced-control timers consist of a 16-bit auto-reload counter driven by a programmable
+  prescaler, break input feature, PWM outputs and complementary PWM ouputs channels.
+- general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a
+  programmable prescaler and PWM outputs.
+- basic timers consist of a 16-bit auto-reload counter driven by a programmable prescaler.
+
+Required parameters:
+- compatible: must be "st,stm32-timers"
+
+- reg:                  Physical base address and length of the controller's
+                        registers.
+- clock-names:          Set to "int".
+- clocks:               Phandle to the clock used by the timer module.
+                        For Clk properties, please refer to ../clock/clock-bindings.txt
+
+Optional parameters:
+- resets:               Phandle to the parent reset controller.
+                        See ../reset/st,stm32-rcc.txt
+
+Optional subnodes:
+- pwm:                  See ../pwm/pwm-stm32.txt
+- timer:                See ../iio/timer/stm32-timer-trigger.txt
+
+Example:
+        timers@40010000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "st,stm32-timers";
+                reg = <0x40010000 0x400>;
+                clocks = <&rcc 0 160>;
+                clock-names = "clk_int";
+
+                pwm {
+                        compatible = "st,stm32-pwm";
+                        pinctrl-0       = <&pwm1_pins>;
+                        pinctrl-names   = "default";
+                };
+
+                timer@0 {
+                        compatible = "st,stm32-timer-trigger";
+                        reg = <0>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/misc/atmel-ssc.txt b/Documentation/devicetree/bindings/misc/atmel-ssc.txt
index efc98ea1f23d..f8629bb73945 100644
--- a/Documentation/devicetree/bindings/misc/atmel-ssc.txt
+++ b/Documentation/devicetree/bindings/misc/atmel-ssc.txt
@@ -24,6 +24,8 @@ Optional properties:
        this parameter to choose where the clock from.
      - By default the clock is from TK pin, if the clock from RK pin, this
        property is needed.
+  - #sound-dai-cells: Should contain <0>.
+     - This property makes the SSC into an automatically registered DAI.
 
 Examples:
 - PDC transfer:
diff --git a/Documentation/devicetree/bindings/misc/idt_89hpesx.txt b/Documentation/devicetree/bindings/misc/idt_89hpesx.txt
new file mode 100644
index 000000000000..b9093b79ab7d
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/idt_89hpesx.txt
@@ -0,0 +1,44 @@
+EEPROM / CSR SMBus-slave interface of IDT 89HPESx devices
+
+Required properties:
+  - compatible : should be "<manufacturer>,<type>"
+                 Basically there is only one manufacturer: idt, but some
+                 compatible devices may be produced in future. Following devices
+                 are supported: 89hpes8nt2, 89hpes12nt3, 89hpes24nt6ag2,
+                 89hpes32nt8ag2, 89hpes32nt8bg2, 89hpes12nt12g2, 89hpes16nt16g2,
+                 89hpes24nt24g2, 89hpes32nt24ag2, 89hpes32nt24bg2;
+                 89hpes12n3, 89hpes12n3a, 89hpes24n3, 89hpes24n3a;
+                 89hpes32h8, 89hpes32h8g2, 89hpes48h12, 89hpes48h12g2,
+                 89hpes48h12ag2, 89hpes16h16, 89hpes22h16, 89hpes22h16g2,
+                 89hpes34h16, 89hpes34h16g2, 89hpes64h16, 89hpes64h16g2,
+                 89hpes64h16ag2;
+                 89hpes12t3g2, 89hpes24t3g2, 89hpes16t4, 89hpes4t4g2,
+                 89hpes10t4g2, 89hpes16t4g2, 89hpes16t4ag2, 89hpes5t5,
+                 89hpes6t5, 89hpes8t5, 89hpes8t5a, 89hpes24t6, 89hpes6t6g2,
+                 89hpes24t6g2, 89hpes16t7, 89hpes32t8, 89hpes32t8g2,
+                 89hpes48t12, 89hpes48t12g2.
+  - reg :        I2C address of the IDT 89HPESx device.
+
+Optionally there can be EEPROM-compatible subnode:
+  - compatible:  There are five EEPROM devices supported: 24c32, 24c64, 24c128,
+                 24c256 and 24c512 differed by size.
+  - reg:         Custom address of EEPROM device (If not specified IDT 89HPESx
+    (optional)   device will try to communicate with EEPROM sited by default
+                 address - 0x50)
+  - read-only :  Parameterless property disables writes to the EEPROM
+    (optional)
+
+Example:
+        idt@60 {
+                compatible = "idt,89hpes32nt8ag2";
+                reg = <0x74>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                eeprom@50 {
+                        compatible = "onsemi,24c64";
+                        reg = <0x50>;
+                        read-only;
+                };
+        };
+
diff --git a/Documentation/devicetree/bindings/net/brcm,bcm7445-switch-v4.0.txt b/Documentation/devicetree/bindings/net/brcm,bcm7445-switch-v4.0.txt
index fb40891ee606..9a734d808aa7 100644
--- a/Documentation/devicetree/bindings/net/brcm,bcm7445-switch-v4.0.txt
+++ b/Documentation/devicetree/bindings/net/brcm,bcm7445-switch-v4.0.txt
@@ -2,7 +2,7 @@
 
 Required properties:
 
-- compatible: should be "brcm,bcm7445-switch-v4.0"
+- compatible: should be "brcm,bcm7445-switch-v4.0" or "brcm,bcm7278-switch-v4.0"
 - reg: addresses and length of the register sets for the device, must be 6
   pairs of register addresses and lengths
 - interrupts: interrupts for the devices, must be two interrupts
@@ -41,6 +41,13 @@ Optional properties:
   Admission Control Block supports reporting the number of packets in-flight in a
   switch queue
 
+Port subnodes:
+
+Optional properties:
+
+- brcm,use-bcm-hdr: boolean property, if present, indicates that the switch
+  port has Broadcom tags enabled (per-packet metadata)
+
 Example:
 
 switch_top@f0b00000 {
@@ -114,6 +121,7 @@ switch_top@f0b00000 {
                         port@0 {
                                 label = "gphy";
                                 reg = <0>;
+                                brcm,use-bcm-hdr;
                         };
                         ...
                 };
diff --git a/Documentation/devicetree/bindings/net/brcm,systemport.txt b/Documentation/devicetree/bindings/net/brcm,systemport.txt
index 877da34145b0..83f29e0e11ba 100644
--- a/Documentation/devicetree/bindings/net/brcm,systemport.txt
+++ b/Documentation/devicetree/bindings/net/brcm,systemport.txt
@@ -1,7 +1,10 @@
 * Broadcom BCM7xxx Ethernet Systemport Controller (SYSTEMPORT)
 
 Required properties:
-- compatible: should be one of "brcm,systemport-v1.00" or "brcm,systemport"
+- compatible: should be one of:
+              "brcm,systemport-v1.00"
+              "brcm,systemportlite-v1.00" or
+              "brcm,systemport"
 - reg: address and length of the register set for the device.
 - interrupts: interrupts for the device, first cell must be for the rx
   interrupts, and the second cell should be for the transmit queues. An
diff --git a/Documentation/devicetree/bindings/net/btusb.txt b/Documentation/devicetree/bindings/net/btusb.txt
new file mode 100644
index 000000000000..01fa2d4188d4
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/btusb.txt
@@ -0,0 +1,43 @@
+Generic Bluetooth controller over USB (btusb driver)
+---------------------------------------------------
+
+Required properties:
+
+  - compatible : should comply with the format "usbVID,PID" specified in
+                 Documentation/devicetree/bindings/usb/usb-device.txt
+                 At the time of writing, the only OF supported devices
+                 (more may be added later) are:
+
+                  "usb1286,204e" (Marvell 8997)
+
+Also, vendors that use btusb may have device additional properties, e.g:
+Documentation/devicetree/bindings/net/marvell-bt-8xxx.txt
+
+Optional properties:
+
+  - interrupt-parent: phandle of the parent interrupt controller
+  - interrupt-names: (see below)
+  - interrupts : The interrupt specified by the name "wakeup" is the interrupt
+                 that shall be used for out-of-band wake-on-bt. Driver will
+                 request this interrupt for wakeup. During system suspend, the
+                 irq will be enabled so that the bluetooth chip can wakeup host
+                 platform out of band. During system resume, the irq will be
+                 disabled to make sure unnecessary interrupt is not received.
+
+Example:
+
+Following example uses irq pin number 3 of gpio0 for out of band wake-on-bt:
+
+&usb_host1_ehci {
+    status = "okay";
+    #address-cells = <1>;
+    #size-cells = <0>;
+
+    mvl_bt1: bt@1 {
+        compatible = "usb1286,204e";
+        reg = <1>;
+        interrupt-parent = <&gpio0>;
+        interrupt-name = "wakeup";
+        interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+    };
+};
diff --git a/Documentation/devicetree/bindings/net/cpsw.txt b/Documentation/devicetree/bindings/net/cpsw.txt
index ebda7c93453a..7cc15c96ea95 100644
--- a/Documentation/devicetree/bindings/net/cpsw.txt
+++ b/Documentation/devicetree/bindings/net/cpsw.txt
@@ -23,7 +23,6 @@ Required properties:
 
 Optional properties:
 - ti,hwmods             : Must be "cpgmac0"
-- no_bd_ram             : Must be 0 or 1
 - dual_emac             : Specifies Switch to act as Dual EMAC
 - syscon                : Phandle to the system control device node, which is
                           the control module device of the am33x
@@ -70,7 +69,6 @@ Examples:
                 cpdma_channels = <8>;
                 ale_entries = <1024>;
                 bd_ram_size = <0x2000>;
-                no_bd_ram = <0>;
                 rx_descs = <64>;
                 mac_control = <0x20>;
                 slaves = <2>;
@@ -99,7 +97,6 @@ Examples:
                 cpdma_channels = <8>;
                 ale_entries = <1024>;
                 bd_ram_size = <0x2000>;
-                no_bd_ram = <0>;
                 rx_descs = <64>;
                 mac_control = <0x20>;
                 slaves = <2>;
diff --git a/Documentation/devicetree/bindings/net/dsa/dsa.txt b/Documentation/devicetree/bindings/net/dsa/dsa.txt
index a4a570fb2494..cfe8f64eca4f 100644
--- a/Documentation/devicetree/bindings/net/dsa/dsa.txt
+++ b/Documentation/devicetree/bindings/net/dsa/dsa.txt
@@ -34,13 +34,9 @@ Required properties:
 
 Each port children node must have the following mandatory properties:
 - reg                   : Describes the port address in the switch
-- label                 : Describes the label associated with this port, which
-                          will become the netdev name. Special labels are
-                          "cpu" to indicate a CPU port and "dsa" to
-                          indicate an uplink/downlink port between switches in
-                          the cluster.
 
-A port labelled "dsa" has the following mandatory property:
+An uplink/downlink port between switches in the cluster has the following
+mandatory property:
 
 - link                  : Should be a list of phandles to other switch's DSA
                           port. This port is used as the outgoing port
@@ -48,12 +44,17 @@ A port labelled "dsa" has the following mandatory property:
                           information must be given, not just the one hop
                           routes to neighbouring switches.
 
-A port labelled "cpu" has the following mandatory property:
+A CPU port has the following mandatory property:
 
 - ethernet              : Should be a phandle to a valid Ethernet device node.
                           This host device is what the switch port is
                           connected to.
 
+A user port has the following optional property:
+
+- label                 : Describes the label associated with this port, which
+                          will become the netdev name.
+
 Port child nodes may also contain the following optional standardised
 properties, described in binding documents:
 
@@ -107,7 +108,6 @@ linked into one DSA cluster.
 
                         switch0port5: port@5 {
                                 reg = <5>;
-                                label = "dsa";
                                 phy-mode = "rgmii-txid";
                                 link = <&switch1port6
                                         &switch2port9>;
@@ -119,7 +119,6 @@ linked into one DSA cluster.
 
                         port@6 {
                                 reg = <6>;
-                                label = "cpu";
                                 ethernet = <&fec1>;
                                 fixed-link {
                                         speed = <100>;
@@ -165,7 +164,6 @@ linked into one DSA cluster.
 
                         switch1port5: port@5 {
                                 reg = <5>;
-                                label = "dsa";
                                 link = <&switch2port9>;
                                 phy-mode = "rgmii-txid";
                                 fixed-link {
@@ -176,7 +174,6 @@ linked into one DSA cluster.
 
                         switch1port6: port@6 {
                                 reg = <6>;
-                                label = "dsa";
                                 phy-mode = "rgmii-txid";
                                 link = <&switch0port5>;
                                 fixed-link {
@@ -255,7 +252,6 @@ linked into one DSA cluster.
 
                         switch2port9: port@9 {
                                 reg = <9>;
-                                label = "dsa";
                                 phy-mode = "rgmii-txid";
                                 link = <&switch1port5
                                         &switch0port5>;
diff --git a/Documentation/devicetree/bindings/net/dsa/marvell.txt b/Documentation/devicetree/bindings/net/dsa/marvell.txt
index b3dd6b40e0de..7ef9dbb08957 100644
--- a/Documentation/devicetree/bindings/net/dsa/marvell.txt
+++ b/Documentation/devicetree/bindings/net/dsa/marvell.txt
@@ -14,9 +14,9 @@ The properties described here are those specific to Marvell devices.
 Additional required and optional properties can be found in dsa.txt.
 
 Required properties:
-- compatible           : Should be one of "marvell,mv88e6085" or
-                         "marvell,mv88e6190"
-- reg                  : Address on the MII bus for the switch.
+- compatible            : Should be one of "marvell,mv88e6085" or
+                          "marvell,mv88e6190"
+- reg                   : Address on the MII bus for the switch.
 
 Optional properties:
 
@@ -26,30 +26,67 @@ Optional properties:
 - interrupt-controller  : Indicates the switch is itself an interrupt
                           controller. This is used for the PHY interrupts.
 #interrupt-cells = <2>  : Controller uses two cells, number and flag
-- mdio                  : container of PHY and devices on the switches MDIO
-                          bus
+- mdio                  : Container of PHY and devices on the switches MDIO
+                          bus.
+- mdio?         : Container of PHYs and devices on the external MDIO
+                          bus. The node must contains a compatible string of
+                          "marvell,mv88e6xxx-mdio-external"
+
 Example:
 
-       mdio {
-               #address-cells = <1>;
-               #size-cells = <0>;
-               interrupt-parent = <&gpio0>;
-               interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
-               interrupt-controller;
-               #interrupt-cells = <2>;
-
-               switch0: switch@0 {
-                       compatible = "marvell,mv88e6085";
-                       reg = <0>;
-                       reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
-               };
-               mdio {
-                       #address-cells = <1>;
-                       #size-cells = <0>;
-                       switch1phy0: switch1phy0@0 {
-                               reg = <0>;
-                               interrupt-parent = <&switch0>;
-                               interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
-                       };
-               };
-       };
+        mdio {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                interrupt-parent = <&gpio0>;
+                interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+
+                switch0: switch@0 {
+                        compatible = "marvell,mv88e6085";
+                        reg = <0>;
+                        reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
+                };
+                mdio {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        switch1phy0: switch1phy0@0 {
+                                reg = <0>;
+                                interrupt-parent = <&switch0>;
+                                interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+                };
+        };
+
+        mdio {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                interrupt-parent = <&gpio0>;
+                interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+
+                switch0: switch@0 {
+                        compatible = "marvell,mv88e6390";
+                        reg = <0>;
+                        reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
+                };
+                mdio {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        switch1phy0: switch1phy0@0 {
+                                reg = <0>;
+                                interrupt-parent = <&switch0>;
+                                interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+                };
+
+                mdio1 {
+                        compatible = "marvell,mv88e6xxx-mdio-external";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        switch1phy9: switch1phy0@9 {
+                                reg = <9>;
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/net/ethernet.txt b/Documentation/devicetree/bindings/net/ethernet.txt
index 05150957ecfd..3a6916909d90 100644
--- a/Documentation/devicetree/bindings/net/ethernet.txt
+++ b/Documentation/devicetree/bindings/net/ethernet.txt
@@ -29,6 +29,9 @@ The following properties are common to the Ethernet controllers:
   * "smii"
   * "xgmii"
   * "trgmii"
+  * "2000base-x",
+  * "2500base-x",
+  * "rxaui"
 - phy-connection-type: the same as "phy-mode" property but described in ePAPR;
 - phy-handle: phandle, specifies a reference to a node representing a PHY
   device; this property is described in ePAPR and so preferred;
diff --git a/Documentation/devicetree/bindings/net/marvell,prestera.txt b/Documentation/devicetree/bindings/net/marvell,prestera.txt
new file mode 100644
index 000000000000..5fbab29718e8
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/marvell,prestera.txt
@@ -0,0 +1,50 @@
+Marvell Prestera Switch Chip bindings
+-------------------------------------
+
+Required properties:
+- compatible: one of the following
+        "marvell,prestera-98dx3236",
+        "marvell,prestera-98dx3336",
+        "marvell,prestera-98dx4251",
+- reg: address and length of the register set for the device.
+- interrupts: interrupt for the device
+
+Optional properties:
+- dfx: phandle reference to the "DFX Server" node
+
+Example:
+
+switch {
+        compatible = "simple-bus";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
+
+        packet-processor@0 {
+                compatible = "marvell,prestera-98dx3236";
+                reg = <0 0x4000000>;
+                interrupts = <33>, <34>, <35>;
+                dfx = <&dfx>;
+        };
+};
+
+DFX Server bindings
+-------------------
+
+Required properties:
+- compatible: must be "marvell,dfx-server"
+- reg: address and length of the register set for the device.
+
+Example:
+
+dfx-registers {
+        compatible = "simple-bus";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
+
+        dfx: dfx@0 {
+                compatible = "marvell,dfx-server";
+                reg = <0 0x100000>;
+        };
+};
diff --git a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
index 7aa840c8768d..ae4234ca4ee4 100644
--- a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
+++ b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
@@ -1,7 +1,7 @@
 * Marvell Armada 370 / Armada XP / Armada 3700 Ethernet Controller (NETA)
 
 Required properties:
-- compatible: could be one of the followings
+- compatible: could be one of the following:
         "marvell,armada-370-neta"
         "marvell,armada-xp-neta"
         "marvell,armada-3700-neta"
diff --git a/Documentation/devicetree/bindings/net/marvell-bt-sd8xxx.txt b/Documentation/devicetree/bindings/net/marvell-bt-8xxx.txt
index 6a9a63cb0543..9be1059ff03f 100644
--- a/Documentation/devicetree/bindings/net/marvell-bt-sd8xxx.txt
+++ b/Documentation/devicetree/bindings/net/marvell-bt-8xxx.txt
@@ -1,16 +1,21 @@
-Marvell 8897/8997 (sd8897/sd8997) bluetooth SDIO devices
+Marvell 8897/8997 (sd8897/sd8997) bluetooth devices (SDIO or USB based)
 ------
+The 8997 devices supports multiple interfaces. When used on SDIO interfaces,
+the btmrvl driver is used and when used on USB interface, the btusb driver is
+used.
 
 Required properties:
 
   - compatible : should be one of the following:
-        * "marvell,sd8897-bt"
-        * "marvell,sd8997-bt"
+        * "marvell,sd8897-bt" (for SDIO)
+        * "marvell,sd8997-bt" (for SDIO)
+        * "usb1286,204e"      (for USB)
 
 Optional properties:
 
   - marvell,cal-data: Calibration data downloaded to the device during
                       initialization. This is an array of 28 values(u8).
+                      This is only applicable to SDIO devices.
 
   - marvell,wakeup-pin: It represents wakeup pin number of the bluetooth chip.
                         firmware will use the pin to wakeup host system (u16).
@@ -18,10 +23,15 @@ Optional properties:
                       platform. The value will be configured to firmware. This
                       is needed to work chip's sleep feature as expected (u16).
   - interrupt-parent: phandle of the parent interrupt controller
-  - interrupts : interrupt pin number to the cpu. Driver will request an irq based
-                 on this interrupt number. During system suspend, the irq will be
-                 enabled so that the bluetooth chip can wakeup host platform under
-                 certain condition. During system resume, the irq will be disabled
+  - interrupt-names: Used only for USB based devices (See below)
+  - interrupts : specifies the interrupt pin number to the cpu. For SDIO, the
+                 driver will use the first interrupt specified in the interrupt
+                 array. For USB based devices, the driver will use the interrupt
+                 named "wakeup" from the interrupt-names and interrupt arrays.
+                 The driver will request an irq based on this interrupt number.
+                 During system suspend, the irq will be enabled so that the
+                 bluetooth chip can wakeup host platform under certain
+                 conditions. During system resume, the irq will be disabled
                  to make sure unnecessary interrupt is not received.
 
 Example:
@@ -29,7 +39,9 @@ Example:
 IRQ pin 119 is used as system wakeup source interrupt.
 wakeup pin 13 and gap 100ms are configured so that firmware can wakeup host
 using this device side pin and wakeup latency.
-calibration data is also available in below example.
+
+Example for SDIO device follows (calibration data is also available in
+below example).
 
 &mmc3 {
         status = "okay";
@@ -54,3 +66,21 @@ calibration data is also available in below example.
                 marvell,wakeup-gap-ms = /bits/ 16 <0x64>;
         };
 };
+
+Example for USB device:
+
+&usb_host1_ohci {
+    status = "okay";
+    #address-cells = <1>;
+    #size-cells = <0>;
+
+    mvl_bt1: bt@1 {
+        compatible = "usb1286,204e";
+        reg = <1>;
+        interrupt-parent = <&gpio0>;
+        interrupt-names = "wakeup";
+        interrupts = <119 IRQ_TYPE_LEVEL_LOW>;
+        marvell,wakeup-pin = /bits/ 16 <0x0d>;
+        marvell,wakeup-gap-ms = /bits/ 16 <0x64>;
+    };
+};
diff --git a/Documentation/devicetree/bindings/net/marvell-pp2.txt b/Documentation/devicetree/bindings/net/marvell-pp2.txt
index aa4f4230bfd7..4754364df4c6 100644
--- a/Documentation/devicetree/bindings/net/marvell-pp2.txt
+++ b/Documentation/devicetree/bindings/net/marvell-pp2.txt
@@ -27,9 +27,7 @@ Optional properties (port):
 
 - marvell,loopback: port is loopback mode
 - phy: a phandle to a phy node defining the PHY address (as the reg
-  property, a single integer). Note: if this property isn't present,
-  then fixed link is assumed, and the 'fixed-link' property is
-  mandatory.
+  property, a single integer).
 
 Example:
 
diff --git a/Documentation/devicetree/bindings/net/meson-dwmac.txt b/Documentation/devicetree/bindings/net/meson-dwmac.txt
index 89e62ddc69ca..0703ad3f3c1e 100644
--- a/Documentation/devicetree/bindings/net/meson-dwmac.txt
+++ b/Documentation/devicetree/bindings/net/meson-dwmac.txt
@@ -25,6 +25,22 @@ Required properties on Meson8b and newer:
                 - "clkin0" - first parent clock of the internal mux
                 - "clkin1" - second parent clock of the internal mux
 
+Optional properties on Meson8b and newer:
+- amlogic,tx-delay-ns:  The internal RGMII TX clock delay (provided
+                        by this driver) in nanoseconds. Allowed values
+                        are: 0ns, 2ns, 4ns, 6ns.
+                        When phy-mode is set to "rgmii" then the TX
+                        delay should be explicitly configured. When
+                        not configured a fallback of 2ns is used.
+                        When the phy-mode is set to either "rgmii-id"
+                        or "rgmii-txid" the TX clock delay is already
+                        provided by the PHY. In that case this
+                        property should be set to 0ns (which disables
+                        the TX clock delay in the MAC to prevent the
+                        clock from going off because both PHY and MAC
+                        are adding a delay).
+                        Any configuration is ignored when the phy-mode
+                        is set to "rmii".
 
 Example for Meson6:
 
diff --git a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
index bdefefc66594..0eedabe22cc3 100644
--- a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
+++ b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
@@ -27,6 +27,14 @@ Optional properties:
                           'vddmac'.
                           Default value is 0%.
                           Ref: Table:1 - Edge rate change (below).
+- vsc8531,led-0-mode    : LED mode. Specify how the LED[0] should behave.
+                          Allowed values are define in
+                          "include/dt-bindings/net/mscc-phy-vsc8531.h".
+                          Default value is VSC8531_LINK_1000_ACTIVITY (1).
+- vsc8531,led-1-mode    : LED mode. Specify how the LED[1] should behave.
+                          Allowed values are define in
+                          "include/dt-bindings/net/mscc-phy-vsc8531.h".
+                          Default value is VSC8531_LINK_100_ACTIVITY (2).
 
 Table: 1 - Edge rate change
 ----------------------------------------------------------------|
@@ -60,4 +68,6 @@ Example:
                 compatible = "ethernet-phy-id0007.0570";
                 vsc8531,vddmac          = <3300>;
                 vsc8531,edge-slowdown   = <7>;
+                vsc8531,led-0-mode      = <LINK_1000_ACTIVITY>;
+                vsc8531,led-1-mode      = <LINK_100_ACTIVITY>;
         };
diff --git a/Documentation/devicetree/bindings/net/phy.txt b/Documentation/devicetree/bindings/net/phy.txt
index fb5056b22685..b55857696fc3 100644
--- a/Documentation/devicetree/bindings/net/phy.txt
+++ b/Documentation/devicetree/bindings/net/phy.txt
@@ -39,6 +39,10 @@ Optional Properties:
 - enet-phy-lane-swap: If set, indicates the PHY will swap the TX/RX lanes to
   compensate for the board being designed with the lanes swapped.
 
+- enet-phy-lane-no-swap: If set, indicates that PHY will disable swap of the
+  TX/RX lanes. This property allows the PHY to work correcly after e.g. wrong
+  bootstrap configuration caused by issues in PCB layout design.
+
 - eee-broken-100tx:
 - eee-broken-1000t:
 - eee-broken-10gt:
diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
index 95383c5131fc..8f427550720a 100644
--- a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
+++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
@@ -6,6 +6,7 @@ Required properties:
  - compatible: should be "rockchip,<name>-gamc"
    "rockchip,rk3228-gmac": found on RK322x SoCs
    "rockchip,rk3288-gmac": found on RK3288 SoCs
+   "rockchip,rk3328-gmac": found on RK3328 SoCs
    "rockchip,rk3366-gmac": found on RK3366 SoCs
    "rockchip,rk3368-gmac": found on RK3368 SoCs
    "rockchip,rk3399-gmac": found on RK3399 SoCs
diff --git a/Documentation/devicetree/bindings/net/snps,dwc-qos-ethernet.txt b/Documentation/devicetree/bindings/net/snps,dwc-qos-ethernet.txt
index d93f71ce8346..21d27aa4c68c 100644
--- a/Documentation/devicetree/bindings/net/snps,dwc-qos-ethernet.txt
+++ b/Documentation/devicetree/bindings/net/snps,dwc-qos-ethernet.txt
@@ -1,5 +1,8 @@
 * Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC)
 
+This binding is deprecated, but it continues to be supported, but new
+features should be preferably added to the stmmac binding document.
+
 This binding supports the Synopsys Designware Ethernet QoS (Quality Of Service)
 IP block. The IP supports multiple options for bus type, clocking and reset
 structure, and feature list. Consequently, a number of properties and list
diff --git a/Documentation/devicetree/bindings/net/stmmac.txt b/Documentation/devicetree/bindings/net/stmmac.txt
index 128da752fec9..d3bfc2b30fb5 100644
--- a/Documentation/devicetree/bindings/net/stmmac.txt
+++ b/Documentation/devicetree/bindings/net/stmmac.txt
@@ -49,6 +49,8 @@ Optional properties:
 - snps,force_sf_dma_mode        Force DMA to use the Store and Forward
                                 mode for both tx and rx. This flag is
                                 ignored if force_thresh_dma_mode is set.
+- snps,en-tx-lpi-clockgating    Enable gating of the MAC TX clock during
+                                TX low-power mode
 - snps,multicast-filter-bins:   Number of multicast filter hash bins
                                 supported by this device instance
 - snps,perfect-filter-entries:  Number of perfect filter entries supported
@@ -65,7 +67,6 @@ Optional properties:
         - snps,wr_osr_lmt: max write outstanding req. limit
         - snps,rd_osr_lmt: max read outstanding req. limit
         - snps,kbbe: do not cross 1KiB boundary.
-        - snps,axi_all: align address
         - snps,blen: this is a vector of supported burst length.
         - snps,fb: fixed-burst
         - snps,mb: mixed-burst
diff --git a/Documentation/devicetree/bindings/net/wireless/ieee80211.txt b/Documentation/devicetree/bindings/net/wireless/ieee80211.txt
new file mode 100644
index 000000000000..f6442b1397f5
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/wireless/ieee80211.txt
@@ -0,0 +1,24 @@
+Common IEEE 802.11 properties
+
+This provides documentation of common properties that are valid for all wireless
+devices.
+
+Optional properties:
+ - ieee80211-freq-limit : list of supported frequency ranges in KHz. This can be
+        used for devices that in a given config support less channels than
+        normally. It may happen chipset supports a wide wireless band but it is
+        limited to some part of it due to used antennas or power amplifier.
+        An example case for this can be tri-band wireless router with two
+        identical chipsets used for two different 5 GHz subbands. Using them
+        incorrectly could not work or decrease performance noticeably.
+
+Example:
+
+pcie@0,0 {
+        reg = <0x0000 0 0 0 0>;
+        wifi@0,0 {
+                reg = <0x0000 0 0 0 0>;
+                ieee80211-freq-limit = <2402000 2482000>,
+                                       <5170000 5250000>;
+        };
+};
diff --git a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
index 383d5889e95a..966a72ecc6bd 100644
--- a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
+++ b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
@@ -1,13 +1,15 @@
 Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings
 
 This binding represents the on-chip eFuse OTP controller found on
-i.MX6Q/D, i.MX6DL/S, i.MX6SL, and i.MX6SX SoCs.
+i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX and i.MX6UL SoCs.
 
 Required properties:
 - compatible: should be one of
         "fsl,imx6q-ocotp" (i.MX6Q/D/DL/S),
         "fsl,imx6sl-ocotp" (i.MX6SL), or
-        "fsl,imx6sx-ocotp" (i.MX6SX), followed by "syscon".
+        "fsl,imx6sx-ocotp" (i.MX6SX),
+        "fsl,imx6ul-ocotp" (i.MX6UL),
+        followed by "syscon".
 - reg: Should contain the register base and length.
 - clocks: Should contain a phandle pointing to the gated peripheral clock.
 
diff --git a/Documentation/devicetree/bindings/opp/opp.txt b/Documentation/devicetree/bindings/opp/opp.txt
index 9f5ca4457b5f..63725498bd20 100644
--- a/Documentation/devicetree/bindings/opp/opp.txt
+++ b/Documentation/devicetree/bindings/opp/opp.txt
@@ -136,7 +136,7 @@ Optional properties:
   larger OPP table, based on what version of the hardware we are running on. We
   still can't have multiple nodes with the same opp-hz value in OPP table.
 
-  It's an user defined array containing a hierarchy of hardware version numbers,
+  It's a user defined array containing a hierarchy of hardware version numbers,
   supported by the OPP. For example: a platform with hierarchy of three levels
   of versions (A, B and C), this field should be like <X Y Z>, where X
   corresponds to Version hierarchy A, Y corresponds to version hierarchy B and Z
@@ -188,14 +188,14 @@ Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states together.
 
                 opp@1000000000 {
                         opp-hz = /bits/ 64 <1000000000>;
-                        opp-microvolt = <970000 975000 985000>;
+                        opp-microvolt = <975000 970000 985000>;
                         opp-microamp = <70000>;
                         clock-latency-ns = <300000>;
                         opp-suspend;
                 };
                 opp@1100000000 {
                         opp-hz = /bits/ 64 <1100000000>;
-                        opp-microvolt = <980000 1000000 1010000>;
+                        opp-microvolt = <1000000 980000 1010000>;
                         opp-microamp = <80000>;
                         clock-latency-ns = <310000>;
                 };
@@ -267,14 +267,14 @@ independently.
 
                 opp@1000000000 {
                         opp-hz = /bits/ 64 <1000000000>;
-                        opp-microvolt = <970000 975000 985000>;
+                        opp-microvolt = <975000 970000 985000>;
                         opp-microamp = <70000>;
                         clock-latency-ns = <300000>;
                         opp-suspend;
                 };
                 opp@1100000000 {
                         opp-hz = /bits/ 64 <1100000000>;
-                        opp-microvolt = <980000 1000000 1010000>;
+                        opp-microvolt = <1000000 980000 1010000>;
                         opp-microamp = <80000>;
                         clock-latency-ns = <310000>;
                 };
@@ -343,14 +343,14 @@ DVFS state together.
 
                 opp@1000000000 {
                         opp-hz = /bits/ 64 <1000000000>;
-                        opp-microvolt = <970000 975000 985000>;
+                        opp-microvolt = <975000 970000 985000>;
                         opp-microamp = <70000>;
                         clock-latency-ns = <300000>;
                         opp-suspend;
                 };
                 opp@1100000000 {
                         opp-hz = /bits/ 64 <1100000000>;
-                        opp-microvolt = <980000 1000000 1010000>;
+                        opp-microvolt = <1000000 980000 1010000>;
                         opp-microamp = <80000>;
                         clock-latency-ns = <310000>;
                 };
@@ -369,7 +369,7 @@ DVFS state together.
 
                 opp@1300000000 {
                         opp-hz = /bits/ 64 <1300000000>;
-                        opp-microvolt = <1045000 1050000 1055000>;
+                        opp-microvolt = <1050000 1045000 1055000>;
                         opp-microamp = <95000>;
                         clock-latency-ns = <400000>;
                         opp-suspend;
@@ -382,7 +382,7 @@ DVFS state together.
                 };
                 opp@1500000000 {
                         opp-hz = /bits/ 64 <1500000000>;
-                        opp-microvolt = <1010000 1100000 1110000>;
+                        opp-microvolt = <1100000 1010000 1110000>;
                         opp-microamp = <95000>;
                         clock-latency-ns = <400000>;
                         turbo-mode;
@@ -424,9 +424,9 @@ Example 4: Handling multiple regulators
 
                 opp@1000000000 {
                         opp-hz = /bits/ 64 <1000000000>;
-                        opp-microvolt = <970000 975000 985000>, /* Supply 0 */
-                                        <960000 965000 975000>, /* Supply 1 */
-                                        <960000 965000 975000>; /* Supply 2 */
+                        opp-microvolt = <975000 970000 985000>, /* Supply 0 */
+                                        <965000 960000 975000>, /* Supply 1 */
+                                        <965000 960000 975000>; /* Supply 2 */
                         opp-microamp =  <70000>,                /* Supply 0 */
                                         <70000>,                /* Supply 1 */
                                         <70000>;                /* Supply 2 */
@@ -437,9 +437,9 @@ Example 4: Handling multiple regulators
 
                 opp@1000000000 {
                         opp-hz = /bits/ 64 <1000000000>;
-                        opp-microvolt = <970000 975000 985000>, /* Supply 0 */
-                                        <960000 965000 975000>, /* Supply 1 */
-                                        <960000 965000 975000>; /* Supply 2 */
+                        opp-microvolt = <975000 970000 985000>, /* Supply 0 */
+                                        <965000 960000 975000>, /* Supply 1 */
+                                        <965000 960000 975000>; /* Supply 2 */
                         opp-microamp =  <70000>,                /* Supply 0 */
                                         <0>,                    /* Supply 1 doesn't need this */
                                         <70000>;                /* Supply 2 */
@@ -474,7 +474,7 @@ Example 5: opp-supported-hw
                          */
                         opp-supported-hw = <0xF 0xFFFFFFFF 0xFFFFFFFF>
                         opp-hz = /bits/ 64 <600000000>;
-                        opp-microvolt = <900000 915000 925000>;
+                        opp-microvolt = <915000 900000 925000>;
                         ...
                 };
 
@@ -487,7 +487,7 @@ Example 5: opp-supported-hw
                          */
                         opp-supported-hw = <0x20 0xff0000ff 0x0000f4f0>
                         opp-hz = /bits/ 64 <800000000>;
-                        opp-microvolt = <900000 915000 925000>;
+                        opp-microvolt = <915000 900000 925000>;
                         ...
                 };
         };
@@ -512,18 +512,18 @@ Example 6: opp-microvolt-<name>, opp-microamp-<name>:
 
                 opp@1000000000 {
                         opp-hz = /bits/ 64 <1000000000>;
-                        opp-microvolt-slow = <900000 915000 925000>;
-                        opp-microvolt-fast = <970000 975000 985000>;
+                        opp-microvolt-slow = <915000 900000 925000>;
+                        opp-microvolt-fast = <975000 970000 985000>;
                         opp-microamp-slow =  <70000>;
                         opp-microamp-fast =  <71000>;
                 };
 
                 opp@1200000000 {
                         opp-hz = /bits/ 64 <1200000000>;
-                        opp-microvolt-slow = <900000 915000 925000>, /* Supply vcc0 */
-                                              <910000 925000 935000>; /* Supply vcc1 */
-                        opp-microvolt-fast = <970000 975000 985000>, /* Supply vcc0 */
-                                             <960000 965000 975000>; /* Supply vcc1 */
+                        opp-microvolt-slow = <915000 900000 925000>, /* Supply vcc0 */
+                                              <925000 910000 935000>; /* Supply vcc1 */
+                        opp-microvolt-fast = <975000 970000 985000>, /* Supply vcc0 */
+                                             <965000 960000 975000>; /* Supply vcc1 */
                         opp-microamp =  <70000>; /* Will be used for both slow/fast */
                 };
         };
diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
index 59c2f47aa303..b7fa3b97986d 100644
--- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
@@ -42,3 +42,40 @@ Hip05 Example (note that Hip06 is the same except compatible):
                                  0x0 0 0 4 &mbigen_pcie 4 13>;
                 status = "ok";
         };
+
+HiSilicon Hip06/Hip07 PCIe host bridge DT (almost-ECAM) description.
+The properties and their meanings are identical to those described in
+host-generic-pci.txt except as listed below.
+
+Properties of the host controller node that differ from
+host-generic-pci.txt:
+
+- compatible     : Must be "hisilicon,pcie-almost-ecam"
+
+- reg            : Two entries: First the ECAM configuration space for any
+                   other bus underneath the root bus. Second, the base
+                   and size of the HiSilicon host bridge registers include
+                   the RC's own config space.
+
+Example:
+        pcie0: pcie@a0090000 {
+                compatible = "hisilicon,pcie-almost-ecam";
+                reg = <0 0xb0000000 0 0x2000000>,  /*  ECAM configuration space */
+                      <0 0xa0090000 0 0x10000>; /* host bridge registers */
+                bus-range = <0  31>;
+                msi-map = <0x0000 &its_dsa 0x0000 0x2000>;
+                msi-map-mask = <0xffff>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+                device_type = "pci";
+                dma-coherent;
+                ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0 0x5ff0000
+                          0x01000000 0 0 0 0xb7ff0000 0 0x10000>;
+                #interrupt-cells = <1>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4
+                                 0x0 0 0 2 &mbigen_pcie0 650 4
+                                 0x0 0 0 3 &mbigen_pcie0 650 4
+                                 0x0 0 0 4 &mbigen_pcie0 650 4>;
+                status = "ok";
+        };
diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
index 08c716b2c6b6..2de6f65ecfb1 100644
--- a/Documentation/devicetree/bindings/pci/mvebu-pci.txt
+++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
@@ -78,7 +78,8 @@ and the following optional properties:
   multiple lanes. If this property is not found, we assume that the
   value is 0.
 - reset-gpios: optional gpio to PERST#
-- reset-delay-us: delay in us to wait after reset de-assertion
+- reset-delay-us: delay in us to wait after reset de-assertion, if not
+  specified will default to 100ms, as required by the PCIe specification.
 
 Example:
 
diff --git a/Documentation/devicetree/bindings/pci/pci-iommu.txt b/Documentation/devicetree/bindings/pci/pci-iommu.txt
index 56c829621b9a..0def586fdcdf 100644
--- a/Documentation/devicetree/bindings/pci/pci-iommu.txt
+++ b/Documentation/devicetree/bindings/pci/pci-iommu.txt
@@ -32,17 +32,17 @@ PCI root complex
 Optional properties
 -------------------
 
-- iommu-map: Maps a Requester ID to an IOMMU and associated iommu-specifier
+- iommu-map: Maps a Requester ID to an IOMMU and associated IOMMU specifier
   data.
 
   The property is an arbitrary number of tuples of
   (rid-base,iommu,iommu-base,length).
 
   Any RID r in the interval [rid-base, rid-base + length) is associated with
-  the listed IOMMU, with the iommu-specifier (r - rid-base + iommu-base).
+  the listed IOMMU, with the IOMMU specifier (r - rid-base + iommu-base).
 
 - iommu-map-mask: A mask to be applied to each Requester ID prior to being
-  mapped to an iommu-specifier per the iommu-map property.
+  mapped to an IOMMU specifier per the iommu-map property.
 
 
 Example (1)
diff --git a/Documentation/devicetree/bindings/pci/rcar-pci.txt b/Documentation/devicetree/bindings/pci/rcar-pci.txt
index eee518db90b9..34712d6fd253 100644
--- a/Documentation/devicetree/bindings/pci/rcar-pci.txt
+++ b/Documentation/devicetree/bindings/pci/rcar-pci.txt
@@ -6,6 +6,7 @@ compatible: "renesas,pcie-r8a7779" for the R8A7779 SoC;
             "renesas,pcie-r8a7791" for the R8A7791 SoC;
             "renesas,pcie-r8a7793" for the R8A7793 SoC;
             "renesas,pcie-r8a7795" for the R8A7795 SoC;
+            "renesas,pcie-r8a7796" for the R8A7796 SoC;
             "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 compatible device.
             "renesas,pcie-rcar-gen3" for a generic R-Car Gen3 compatible device.
 
diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt
index 71aeda1ca055..1453a734c2f5 100644
--- a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt
@@ -43,6 +43,8 @@ Required properties:
 - interrupt-map-mask and interrupt-map: standard PCI properties
 
 Optional Property:
+- aspm-no-l0s: RC won't support ASPM L0s. This property is needed if
+        using 24MHz OSC for RC's PHY.
 - ep-gpios: contain the entry for pre-reset gpio
 - num-lanes: number of lanes to use
 - vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
index 4f9d23d2ed67..7d3b09474657 100644
--- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
@@ -7,8 +7,19 @@ Required properties:
 - compatible: "samsung,exynos5440-pcie"
 - reg: base addresses and lengths of the pcie controller,
         the phy controller, additional register for the phy controller.
+        (Registers for the phy controller are DEPRECATED.
+         Use the PHY framework.)
+- reg-names : First name should be set to "elbi".
+        And use the "config" instead of getting the confgiruation address space
+        from "ranges".
+        NOTE: When use the "config" property, reg-names must be set.
 - interrupts: A list of interrupt outputs for level interrupt,
         pulse interrupt, special interrupt.
+- phys: From PHY binding. Phandle for the Generic PHY.
+        Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt
+
+Other common properties refer to
+        Documentation/devicetree/binding/pci/designware-pcie.txt
 
 Example:
 
@@ -54,6 +65,24 @@ SoC specific DT Entry:
                 num-lanes = <4>;
         };
 
+With using PHY framework:
+        pcie_phy0: pcie-phy@270000 {
+                ...
+                reg = <0x270000 0x1000>, <0x271000 0x40>;
+                reg-names = "phy", "block";
+                ...
+        };
+
+        pcie@290000 {
+                ...
+                reg = <0x290000 0x1000>, <0x40000000 0x1000>;
+                reg-names = "elbi", "config";
+                phys = <&pcie_phy0>;
+                ranges = <0x81000000 0 0          0x60001000 0 0x00010000
+                          0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>;
+                ...
+        };
+
 Board specific DT Entry:
 
         pcie@290000 {
diff --git a/Documentation/devicetree/bindings/phy/brcm,nsp-usb3-phy.txt b/Documentation/devicetree/bindings/phy/brcm,nsp-usb3-phy.txt
new file mode 100644
index 000000000000..e68ae5dec9c9
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/brcm,nsp-usb3-phy.txt
@@ -0,0 +1,39 @@
+Broadcom USB3 phy binding for northstar plus SoC
+The USB3 phy is internal to the SoC and is accessed using mdio interface.
+
+Required mdio bus properties:
+- reg: Should be 0x0 for SoC internal USB3 phy
+- #address-cells: must be 1
+- #size-cells: must be 0
+
+Required USB3 PHY properties:
+- compatible: should be "brcm,nsp-usb3-phy"
+- reg: USB3 Phy address on SoC internal MDIO bus and it should be 0x10.
+- usb3-ctrl-syscon: handler of syscon node defining physical address
+  of usb3 control register.
+- #phy-cells: must be 0
+
+Required usb3 control properties:
+- compatible: should be "brcm,nsp-usb3-ctrl"
+- reg: offset and length of the control registers
+
+Example:
+
+        mdio@0 {
+                reg = <0x0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                usb3_phy: usb-phy@10 {
+                        compatible = "brcm,nsp-usb3-phy";
+                        reg = <0x10>;
+                        usb3-ctrl-syscon = <&usb3_ctrl>;
+                        #phy-cells = <0>;
+                        status = "disabled";
+                };
+        };
+
+        usb3_ctrl: syscon@104408 {
+                compatible = "brcm,nsp-usb3-ctrl", "syscon";
+                reg = <0x104408 0x3fc>;
+        };
diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-hs-phy.txt b/Documentation/devicetree/bindings/phy/qcom,usb-hs-phy.txt
new file mode 100644
index 000000000000..b3b75c1e6285
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,usb-hs-phy.txt
@@ -0,0 +1,84 @@
+Qualcomm's USB HS PHY
+
+PROPERTIES
+
+- compatible:
+    Usage: required
+    Value type: <string>
+    Definition: Should contain "qcom,usb-hs-phy" and more specifically one of the
+                following:
+
+                        "qcom,usb-hs-phy-apq8064"
+                        "qcom,usb-hs-phy-msm8916"
+                        "qcom,usb-hs-phy-msm8974"
+
+- #phy-cells:
+    Usage: required
+    Value type: <u32>
+    Definition: Should contain 0
+
+- clocks:
+    Usage: required
+    Value type: <prop-encoded-array>
+    Definition: Should contain clock specifier for the reference and sleep
+                clocks
+
+- clock-names:
+    Usage: required
+    Value type: <stringlist>
+    Definition: Should contain "ref" and "sleep" for the reference and sleep
+                clocks respectively
+
+- resets:
+    Usage: required
+    Value type: <prop-encoded-array>
+    Definition: Should contain the phy and POR resets
+
+- reset-names:
+    Usage: required
+    Value type: <stringlist>
+    Definition: Should contain "phy" and "por" for the phy and POR resets
+                respectively
+
+- v3p3-supply:
+    Usage: required
+    Value type: <phandle>
+    Definition: Should contain a reference to the 3.3V supply
+
+- v1p8-supply:
+    Usage: required
+    Value type: <phandle>
+    Definition: Should contain a reference to the 1.8V supply
+
+- extcon:
+    Usage: optional
+    Value type: <prop-encoded-array>
+    Definition: Should contain the vbus extcon
+
+- qcom,init-seq:
+    Usage: optional
+    Value type: <u8 array>
+    Definition: Should contain a sequence of ULPI address and value pairs to
+                program into the ULPI_EXT_VENDOR_SPECIFIC area. This is related
+                to Device Mode Eye Diagram test. The addresses are offsets
+                from the ULPI_EXT_VENDOR_SPECIFIC address, for example,
+                <0x1 0x53> would mean "write the value 0x53 to address 0x81".
+
+EXAMPLE
+
+otg: usb-controller {
+        ulpi {
+                phy {
+                        compatible = "qcom,usb-hs-phy-msm8974", "qcom,usb-hs-phy";
+                        #phy-cells = <0>;
+                        clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
+                        clock-names = "ref", "sleep";
+                        resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
+                        reset-names = "phy", "por";
+                        v3p3-supply = <&pm8941_l24>;
+                        v1p8-supply = <&pm8941_l6>;
+                        extcon = <&smbb>;
+                        qcom,init-seq = /bits/ 8 <0x1 0x63>;
+                };
+        };
+};
diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.txt b/Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.txt
new file mode 100644
index 000000000000..3c7cb2be4b12
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.txt
@@ -0,0 +1,65 @@
+Qualcomm's USB HSIC PHY
+
+PROPERTIES
+
+- compatible:
+    Usage: required
+    Value type: <string>
+    Definition: Should contain "qcom,usb-hsic-phy" and more specifically one of the
+                following:
+
+                        "qcom,usb-hsic-phy-mdm9615"
+                        "qcom,usb-hsic-phy-msm8974"
+
+- #phy-cells:
+    Usage: required
+    Value type: <u32>
+    Definition: Should contain 0
+
+- clocks:
+    Usage: required
+    Value type: <prop-encoded-array>
+    Definition: Should contain clock specifier for phy, calibration and
+                a calibration sleep clock
+
+- clock-names:
+    Usage: required
+    Value type: <stringlist>
+    Definition: Should contain "phy, "cal" and "cal_sleep"
+
+- pinctrl-names:
+    Usage: required
+    Value type: <stringlist>
+    Definition: Should contain "init" and "default" in that order
+
+- pinctrl-0:
+    Usage: required
+    Value type: <prop-encoded-array>
+    Definition: List of pinctrl settings to apply to keep HSIC pins in a glitch
+                free state
+
+- pinctrl-1:
+    Usage: required
+    Value type: <prop-encoded-array>
+    Definition: List of pinctrl settings to apply to mux out the HSIC pins
+
+EXAMPLE
+
+usb-controller {
+        ulpi {
+                phy {
+                        compatible = "qcom,usb-hsic-phy-msm8974",
+                                     "qcom,usb-hsic-phy";
+                        #phy-cells = <0>;
+                        pinctrl-names = "init", "default";
+                        pinctrl-0 = <&hsic_sleep>;
+                        pinctrl-1 = <&hsic_default>;
+                        clocks = <&gcc GCC_USB_HSIC_CLK>,
+                                 <&gcc GCC_USB_HSIC_IO_CAL_CLK>,
+                                 <&gcc GCC_USB_HSIC_IO_CAL_SLEEP_CLK>;
+                        clock-names = "phy", "cal", "cal_sleep";
+                        assigned-clocks = <&gcc GCC_USB_HSIC_IO_CAL_CLK>;
+                        assigned-clock-rates = <960000>;
+                };
+        };
+};
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 9872ba8546bd..ab80bfe31cb3 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -191,3 +191,20 @@ Example:
                 usbdrdphy0 = &usb3_phy0;
                 usbdrdphy1 = &usb3_phy1;
         };
+
+Samsung Exynos SoC series PCIe PHY controller
+--------------------------------------------------
+Required properties:
+- compatible : Should be set to "samsung,exynos5440-pcie-phy"
+- #phy-cells : Must be zero
+- reg : a register used by phy driver.
+        - First is for phy register, second is for block register.
+- reg-names : Must be set to "phy" and "block".
+
+Example:
+        pcie_phy0: pcie-phy@270000 {
+                #phy-cells = <0>;
+                compatible = "samsung,exynos5440-pcie-phy";
+                reg = <0x270000 0x1000>, <0x271000 0x40>;
+                reg-names = "phy", "block";
+        };
diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
index 287150db6db4..e42334258185 100644
--- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
@@ -10,6 +10,7 @@ Required properties:
   * allwinner,sun8i-a23-usb-phy
   * allwinner,sun8i-a33-usb-phy
   * allwinner,sun8i-h3-usb-phy
+  * allwinner,sun8i-v3s-usb-phy
   * allwinner,sun50i-a64-usb-phy
 - reg : a list of offset + length pairs
 - reg-names :
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 7c85dca4221a..2fd688c8dbdb 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -6,7 +6,7 @@ the first two functions being GPIO in and out. The configuration on
 the pins includes drive strength and pull-up.
 
 Required properties:
-- compatible: Should be one of the followings (depending on you SoC):
+- compatible: Should be one of the following (depending on your SoC):
   "allwinner,sun4i-a10-pinctrl"
   "allwinner,sun5i-a10s-pinctrl"
   "allwinner,sun5i-a13-pinctrl"
diff --git a/Documentation/devicetree/bindings/power/pd-samsung.txt b/Documentation/devicetree/bindings/power/pd-samsung.txt
index 4e947372a693..549f7dee9b9d 100644
--- a/Documentation/devicetree/bindings/power/pd-samsung.txt
+++ b/Documentation/devicetree/bindings/power/pd-samsung.txt
@@ -6,12 +6,15 @@ to gate power to one or more peripherals on the processor.
 Required Properties:
 - compatible: should be one of the following.
     * samsung,exynos4210-pd - for exynos4210 type power domain.
+    * samsung,exynos5433-pd - for exynos5433 type power domain.
 - reg: physical base address of the controller and length of memory mapped
     region.
 - #power-domain-cells: number of cells in power domain specifier;
     must be 0.
 
 Optional Properties:
+- label: Human readable string with domain name. Will be visible in userspace
+        to let user to distinguish between multiple domains in SoC.
 - clocks: List of clock handles. The parent clocks of the input clocks to the
         devices in this power domain are set to oscclk before power gating
         and restored back after powering on a domain. This is required for
@@ -20,7 +23,7 @@ Optional Properties:
 - clock-names: The following clocks can be specified:
         - oscclk: Oscillator clock.
         - clkN: Input clocks to the devices in this power domain. These clocks
-                will be reparented to oscclk before swithing power domain off.
+                will be reparented to oscclk before switching power domain off.
                 Their original parent will be brought back after turning on
                 the domain. Maximum of 4 clocks (N = 0 to 3) are supported.
         - asbN: Clocks required by asynchronous bridges (ASB) present in
@@ -38,6 +41,7 @@ Example:
                 compatible = "samsung,exynos4210-pd";
                 reg = <0x10023C00 0x10>;
                 #power-domain-cells = <0>;
+                label = "LCD0";
         };
 
         mfc_pd: power-domain@10044060 {
@@ -46,6 +50,7 @@ Example:
                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>;
                 clock-names = "oscclk", "clk0";
                 #power-domain-cells = <0>;
+                label = "MFC";
         };
 
 See Documentation/devicetree/bindings/power/power_domain.txt for description
diff --git a/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt b/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt
index d4eab9227ea4..e62d53d844cc 100644
--- a/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt
+++ b/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt
@@ -2,12 +2,12 @@ Driver a GPIO line that can be used to turn the power off.
 
 The driver supports both level triggered and edge triggered power off.
 At driver load time, the driver will request the given gpio line and
-install a pm_power_off handler. If the optional properties 'input' is
-not found, the GPIO line will be driven in the inactive
+install a handler to power off the system. If the optional properties
+'input' is not found, the GPIO line will be driven in the inactive
 state. Otherwise its configured as an input.
 
-When the pm_power_off is called, the gpio is configured as an output,
-and drive active, so triggering a level triggered power off
+When the power-off handler is called, the gpio is configured as an
+output, and drive active, so triggering a level triggered power off
 condition. This will also cause an inactive->active edge condition, so
 triggering positive edge triggered power off. After a delay of 100ms,
 the GPIO is set to inactive, thus causing an active->inactive edge,
@@ -24,7 +24,7 @@ Required properties:
 
 Optional properties:
 - input : Initially configure the GPIO line as an input. Only reconfigure
-  it to an output when the pm_power_off function is called. If this optional
+  it to an output when the power-off handler is called. If this optional
   property is not specified, the GPIO is initialized as an output in its
   inactive state.
 
diff --git a/Documentation/devicetree/bindings/power/reset/qnap-poweroff.txt b/Documentation/devicetree/bindings/power/reset/qnap-poweroff.txt
index af25e77c0e0c..c363d7173129 100644
--- a/Documentation/devicetree/bindings/power/reset/qnap-poweroff.txt
+++ b/Documentation/devicetree/bindings/power/reset/qnap-poweroff.txt
@@ -3,8 +3,7 @@
 QNAP NAS devices have a microcontroller controlling the main power
 supply. This microcontroller is connected to UART1 of the Kirkwood and
 Orion5x SoCs. Sending the character 'A', at 19200 baud, tells the
-microcontroller to turn the power off. This driver adds a handler to
-pm_power_off which is called to turn the power off.
+microcontroller to turn the power off.
 
 Synology NAS devices use a similar scheme, but a different baud rate,
 9600, and a different character, '1'.
diff --git a/Documentation/devicetree/bindings/powerpc/4xx/emac.txt b/Documentation/devicetree/bindings/powerpc/4xx/emac.txt
index 712baf6c3e24..44b842b6ca15 100644
--- a/Documentation/devicetree/bindings/powerpc/4xx/emac.txt
+++ b/Documentation/devicetree/bindings/powerpc/4xx/emac.txt
@@ -71,6 +71,9 @@
                           For Axon it can be absent, though my current driver
                           doesn't handle phy-address yet so for now, keep
                           0x00ffffff in it.
+    - phy-handle        : Used to describe configurations where a external PHY
+                          is used. Please refer to:
+                          Documentation/devicetree/bindings/net/ethernet.txt
     - rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec
                           operations (if absent the value is the same as
                           rx-fifo-size).  For Axon, either absent or 2048.
@@ -81,8 +84,22 @@
                           offload, phandle of the TAH device node.
     - tah-channel       : 1 cell, optional. If appropriate, channel used on the
                           TAH engine.
+    - fixed-link        : Fixed-link subnode describing a link to a non-MDIO
+                          managed entity. See
+                          Documentation/devicetree/bindings/net/fixed-link.txt
+                          for details.
+    - mdio subnode      : When the EMAC has a phy connected to its local
+                          mdio, which us supported by the kernel's network
+                          PHY library in drivers/net/phy, there must be device
+                          tree subnode with the following required properties:
+                                - #address-cells: Must be <1>.
+                                - #size-cells: Must be <0>.
 
-    Example:
+                          For PHY definitions: Please refer to
+                          Documentation/devicetree/bindings/net/phy.txt and
+                          Documentation/devicetree/bindings/net/ethernet.txt
+
+    Examples:
 
         EMAC0: ethernet@40000800 {
                 device_type = "network";
@@ -104,6 +121,48 @@
                 zmii-channel = <0>;
         };
 
+        EMAC1: ethernet@ef600c00 {
+                device_type = "network";
+                compatible = "ibm,emac-apm821xx", "ibm,emac4sync";
+                interrupt-parent = <&EMAC1>;
+                interrupts = <0 1>;
+                #interrupt-cells = <1>;
+                #address-cells = <0>;
+                #size-cells = <0>;
+                interrupt-map = <0 &UIC2 0x10 IRQ_TYPE_LEVEL_HIGH /* Status */
+                                 1 &UIC2 0x14 IRQ_TYPE_LEVEL_HIGH /* Wake */>;
+                reg = <0xef600c00 0x000000c4>;
+                local-mac-address = [000000000000]; /* Filled in by U-Boot */
+                mal-device = <&MAL0>;
+                mal-tx-channel = <0>;
+                mal-rx-channel = <0>;
+                cell-index = <0>;
+                max-frame-size = <9000>;
+                rx-fifo-size = <16384>;
+                tx-fifo-size = <2048>;
+                fifo-entry-size = <10>;
+                phy-mode = "rgmii";
+                phy-handle = <&phy0>;
+                phy-map = <0x00000000>;
+                rgmii-device = <&RGMII0>;
+                rgmii-channel = <0>;
+                tah-device = <&TAH0>;
+                tah-channel = <0>;
+                has-inverted-stacr-oc;
+                has-new-stacr-staopc;
+
+                mdio {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        phy0: ethernet-phy@0 {
+                                compatible = "ethernet-phy-ieee802.3-c22";
+                                reg = <0>;
+                        };
+                };
+        };
+
+
       ii) McMAL node
 
     Required properties:
@@ -145,4 +204,3 @@
     - revision           : as provided by the RGMII new version register if
                            available.
                            For Axon: 0x0000012a
-
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt b/Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt
index c41b2187eaa8..dc9bb3182525 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt
@@ -5,8 +5,46 @@ The cache bindings explained below are ePAPR compliant
 
 Required Properties:
 
-- compatible    : Should include "fsl,chip-l2-cache-controller" and "cache"
-                  where chip is the processor (bsc9132, npc8572 etc.)
+- compatible    : Should include one of the following:
+                  "fsl,8540-l2-cache-controller"
+                  "fsl,8541-l2-cache-controller"
+                  "fsl,8544-l2-cache-controller"
+                  "fsl,8548-l2-cache-controller"
+                  "fsl,8555-l2-cache-controller"
+                  "fsl,8568-l2-cache-controller"
+                  "fsl,b4420-l2-cache-controller"
+                  "fsl,b4860-l2-cache-controller"
+                  "fsl,bsc9131-l2-cache-controller"
+                  "fsl,bsc9132-l2-cache-controller"
+                  "fsl,c293-l2-cache-controller"
+                  "fsl,mpc8536-l2-cache-controller"
+                  "fsl,mpc8540-l2-cache-controller"
+                  "fsl,mpc8541-l2-cache-controller"
+                  "fsl,mpc8544-l2-cache-controller"
+                  "fsl,mpc8548-l2-cache-controller"
+                  "fsl,mpc8555-l2-cache-controller"
+                  "fsl,mpc8560-l2-cache-controller"
+                  "fsl,mpc8568-l2-cache-controller"
+                  "fsl,mpc8569-l2-cache-controller"
+                  "fsl,mpc8572-l2-cache-controller"
+                  "fsl,p1010-l2-cache-controller"
+                  "fsl,p1011-l2-cache-controller"
+                  "fsl,p1012-l2-cache-controller"
+                  "fsl,p1013-l2-cache-controller"
+                  "fsl,p1014-l2-cache-controller"
+                  "fsl,p1015-l2-cache-controller"
+                  "fsl,p1016-l2-cache-controller"
+                  "fsl,p1020-l2-cache-controller"
+                  "fsl,p1021-l2-cache-controller"
+                  "fsl,p1022-l2-cache-controller"
+                  "fsl,p1023-l2-cache-controller"
+                  "fsl,p1024-l2-cache-controller"
+                  "fsl,p1025-l2-cache-controller"
+                  "fsl,p2010-l2-cache-controller"
+                  "fsl,p2020-l2-cache-controller"
+                  "fsl,t2080-l2-cache-controller"
+                  "fsl,t4240-l2-cache-controller"
+                  and "cache".
 - reg           : Address and size of L2 cache controller registers
 - cache-size    : Size of the entire L2 cache
 - interrupts    : Error interrupt of L2 controller
diff --git a/Documentation/devicetree/bindings/powerpc/opal/power-mgt.txt b/Documentation/devicetree/bindings/powerpc/opal/power-mgt.txt
new file mode 100644
index 000000000000..9d619e955576
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/opal/power-mgt.txt
@@ -0,0 +1,118 @@
+IBM Power-Management Bindings
+=============================
+
+Linux running on baremetal POWER machines has access to the processor
+idle states. The description of these idle states is exposed via the
+node @power-mgt in the device-tree by the firmware.
+
+Definitions:
+----------------
+Typically each idle state has the following associated properties:
+
+- name: The name of the idle state as defined by the firmware.
+
+- flags: indicating some aspects of this idle states such as the
+         extent of state-loss, whether timebase is stopped on this
+         idle states and so on. The flag bits are as follows:
+
+- exit-latency: The latency involved in transitioning the state of the
+                CPU from idle to running.
+
+- target-residency: The minimum time that the CPU needs to reside in
+                    this idle state in order to accrue power-savings
+                    benefit.
+
+Properties
+----------------
+The following properties provide details about the idle states. These
+properties are exposed as arrays. Each entry in the property array
+provides the value of that property for the idle state associated with
+the array index of that entry.
+
+If idle-states are defined, then the properties
+"ibm,cpu-idle-state-names" and "ibm,cpu-idle-state-flags" are
+required. The other properties are required unless mentioned
+otherwise. The length of all the property arrays must be the same.
+
+- ibm,cpu-idle-state-names:
+        Array of strings containing the names of the idle states.
+
+- ibm,cpu-idle-state-flags:
+        Array of unsigned 32-bit values containing the values of the
+        flags associated with the the aforementioned idle-states. The
+        flag bits are as follows:
+                0x00000001 /* Decrementer would stop */
+                0x00000002 /* Needs timebase restore */
+                0x00001000 /* Restore GPRs like nap */
+                0x00002000 /* Restore hypervisor resource from PACA pointer */
+                0x00004000 /* Program PORE to restore PACA pointer */
+                0x00010000 /* This is a nap state (POWER7,POWER8) */
+                0x00020000 /* This is a fast-sleep state (POWER8)*/
+                0x00040000 /* This is a winkle state (POWER8) */
+                0x00080000 /* This is a fast-sleep state which requires a */
+                           /* software workaround for restoring the */
+                           /* timebase (POWER8) */
+                0x00800000 /* This state uses SPR PMICR instruction */
+                           /* (POWER8)*/
+                0x00100000 /* This is a fast stop state (POWER9) */
+                0x00200000 /* This is a deep-stop state (POWER9) */
+
+- ibm,cpu-idle-state-latencies-ns:
+        Array of unsigned 32-bit values containing the values of the
+        exit-latencies (in ns) for the idle states in
+        ibm,cpu-idle-state-names.
+
+- ibm,cpu-idle-state-residency-ns:
+        Array of unsigned 32-bit values containing the values of the
+        target-residency (in ns) for the idle states in
+        ibm,cpu-idle-state-names. On POWER8 this is an optional
+        property. If the property is absent, the target residency for
+        the "Nap", "FastSleep" are defined to 10000 and 300000000
+        respectively by the kernel. On POWER9 this property is required.
+
+- ibm,cpu-idle-state-psscr:
+        Array of unsigned 64-bit values containing the values for the
+        PSSCR for each of the idle states in ibm,cpu-idle-state-names.
+        This property is required on POWER9 and absent on POWER8.
+
+- ibm,cpu-idle-state-psscr-mask:
+        Array of unsigned 64-bit values containing the masks
+        indicating which psscr fields are set in the corresponding
+        entries of ibm,cpu-idle-state-psscr. This property is
+        required on POWER9 and absent on POWER8.
+
+        Whenever the firmware sets an entry in
+        ibm,cpu-idle-state-psscr-mask value to 0xf, it implies that
+        only the Requested Level (RL) field of the corresponding entry
+        in ibm,cpu-idle-state-psscr should be considered by the
+        kernel. For such idle states, the kernel would set the
+        remaining fields of the psscr to the following sane-default
+        values.
+
+                - ESL and EC bits are to 1. So wakeup from any stop
+                  state will be at vector 0x100.
+
+                - MTL and PSLL are set to the maximum allowed value as
+                  per the ISA, i.e. 15.
+
+                - The Transition Rate, TR is set to the Maximum value
+                  3.
+
+        For all the other values of the entry in
+        ibm,cpu-idle-state-psscr-mask, the kernel expects all the
+        psscr fields of the corresponding entry in
+        ibm,cpu-idle-state-psscr to be correctly set by the firmware.
+
+- ibm,cpu-idle-state-pmicr:
+        Array of unsigned 64-bit values containing the pmicr values
+        for the idle states in ibm,cpu-idle-state-names. This 64-bit
+        register value is to be set in pmicr for the corresponding
+        state if the flag indicates that pmicr SPR should be set. This
+        is an optional property on POWER8 and is absent on
+        POWER9.
+
+- ibm,cpu-idle-state-pmicr-mask:
+        Array of unsigned 64-bit values containing the mask indicating
+        which of the fields of the PMICR are set in the corresponding
+        entries in ibm,cpu-idle-state-pmicr. This is an optional
+        property on POWER8 and is absent on POWER9.
diff --git a/Documentation/devicetree/bindings/pwm/imx-pwm.txt b/Documentation/devicetree/bindings/pwm/imx-pwm.txt
index e00c2e9f484d..c61bdf8cd41b 100644
--- a/Documentation/devicetree/bindings/pwm/imx-pwm.txt
+++ b/Documentation/devicetree/bindings/pwm/imx-pwm.txt
@@ -6,8 +6,8 @@ Required properties:
   - "fsl,imx1-pwm" for PWM compatible with the one integrated on i.MX1
   - "fsl,imx27-pwm" for PWM compatible with the one integrated on i.MX27
 - reg: physical base address and length of the controller's registers
-- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
-  the cells format.
+- #pwm-cells: 2 for i.MX1 and 3 for i.MX27 and newer SoCs. See pwm.txt
+  in this directory for a description of the cells format.
 - clocks : Clock specifiers for both ipg and per clocks.
 - clock-names : Clock names should include both "ipg" and "per"
 See the clock consumer binding,
@@ -17,7 +17,7 @@ See the clock consumer binding,
 Example:
 
 pwm1: pwm@53fb4000 {
-        #pwm-cells = <2>;
+        #pwm-cells = <3>;
         compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
         reg = <0x53fb4000 0x4000>;
         clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
diff --git a/Documentation/devicetree/bindings/pwm/pwm-stm32.txt b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt
new file mode 100644
index 000000000000..6dd040363e5e
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt
@@ -0,0 +1,35 @@
+STMicroelectronics STM32 Timers PWM bindings
+
+Must be a sub-node of an STM32 Timers device tree node.
+See ../mfd/stm32-timers.txt for details about the parent node.
+
+Required parameters:
+- compatible:           Must be "st,stm32-pwm".
+- pinctrl-names:        Set to "default".
+- pinctrl-0:            List of phandles pointing to pin configuration nodes for PWM module.
+                        For Pinctrl properties see ../pinctrl/pinctrl-bindings.txt
+
+Optional parameters:
+- st,breakinput:        One or two <index level filter> to describe break input configurations.
+                        "index" indicates on which break input (0 or 1) the configuration
+                        should be applied.
+                        "level" gives the active level (0=low or 1=high) of the input signal
+                        for this configuration.
+                        "filter" gives the filtering value to be applied.
+
+Example:
+        timers@40010000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "st,stm32-timers";
+                reg = <0x40010000 0x400>;
+                clocks = <&rcc 0 160>;
+                clock-names = "clk_int";
+
+                pwm {
+                        compatible = "st,stm32-pwm";
+                        pinctrl-0       = <&pwm1_pins>;
+                        pinctrl-names   = "default";
+                        st,breakinput = <0 1 5>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/regulator/ti-abb-regulator.txt b/Documentation/devicetree/bindings/regulator/ti-abb-regulator.txt
index c3f6546ebac7..6a23ad9ac53a 100644
--- a/Documentation/devicetree/bindings/regulator/ti-abb-regulator.txt
+++ b/Documentation/devicetree/bindings/regulator/ti-abb-regulator.txt
@@ -45,7 +45,7 @@ Required Properties:
 Optional Properties:
 - reg-names: In addition to the required properties, the following are optional
   - "efuse-address"     - Contains efuse base address used to pick up ABB info.
-  - "ldo-address"       - Contains address of ABB LDO overide register address.
+  - "ldo-address"       - Contains address of ABB LDO override register.
         "efuse-address" is required for this.
 - ti,ldovbb-vset-mask   - Required if ldo-address is set, mask for LDO override
         register to provide override vset value.
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
index b85885a298d8..75ad7b8df0b1 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
@@ -9,6 +9,7 @@ on the Qualcomm ADSP Hexagon core.
         Definition: must be one of:
                     "qcom,msm8974-adsp-pil"
                     "qcom,msm8996-adsp-pil"
+                    "qcom,msm8996-slpi-pil"
 
 - interrupts-extended:
         Usage: required
@@ -24,13 +25,13 @@ on the Qualcomm ADSP Hexagon core.
 - clocks:
         Usage: required
         Value type: <prop-encoded-array>
-        Definition: reference to the xo clock to be held on behalf of the
-                    booting Hexagon core
+        Definition: reference to the xo clock and optionally aggre2 clock to be
+                    held on behalf of the booting Hexagon core
 
 - clock-names:
         Usage: required
         Value type: <stringlist>
-        Definition: must be "xo"
+        Definition: must be "xo" and optionally include "aggre2"
 
 - cx-supply:
         Usage: required
@@ -38,6 +39,12 @@ on the Qualcomm ADSP Hexagon core.
         Definition: reference to the regulator to be held on behalf of the
                     booting Hexagon core
 
+- px-supply:
+        Usage: required
+        Value type: <phandle>
+        Definition: reference to the px regulator to be held on behalf of the
+                    booting Hexagon core
+
 - memory-region:
         Usage: required
         Value type: <phandle>
@@ -96,3 +103,31 @@ ADSP, as it is found on MSM8974 boards.
                         qcom,smd-edge = <1>;
                 };
         };
+
+The following example describes the resources needed to boot control the
+SLPI, as it is found on MSM8996 boards.
+
+        slpi {
+                compatible = "qcom,msm8996-slpi-pil";
+                interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>,
+                                      <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+                                      <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+                                      <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+                                      <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+                interrupt-names = "wdog",
+                                  "fatal",
+                                  "ready",
+                                  "handover",
+                                  "stop-ack";
+
+                clocks = <&rpmcc MSM8996_RPM_SMD_XO_CLK_SRC>,
+                         <&rpmcc MSM8996_RPM_SMD_AGGR2_NOC_CLK>;
+                clock-names = "xo", "aggre2";
+
+                cx-supply = <&pm8994_l26>;
+                px-supply = <&pm8994_lvs2>;
+
+                memory-region = <&slpi_region>;
+                qcom,smem-states = <&slpi_smp2p_out 0>;
+                qcom,smem-state-names = "stop";
+        };
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
index 57cb49ec55ca..92347fe6890e 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
@@ -7,7 +7,9 @@ on the Qualcomm Hexagon core.
         Usage: required
         Value type: <string>
         Definition: must be one of:
-                    "qcom,q6v5-pil"
+                    "qcom,q6v5-pil",
+                    "qcom,msm8916-mss-pil",
+                    "qcom,msm8974-mss-pil"
 
 - reg:
         Usage: required
diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt
new file mode 100644
index 000000000000..2bf3344b2a02
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt
@@ -0,0 +1,43 @@
+Hisilicon System Reset Controller
+======================================
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+The reset controller registers are part of the system-ctl block on
+hi3660 SoC.
+
+Required properties:
+- compatible: should be
+                 "hisilicon,hi3660-reset"
+- hisi,rst-syscon: phandle of the reset's syscon.
+- #reset-cells : Specifies the number of cells needed to encode a
+  reset source.  The type shall be a <u32> and the value shall be 2.
+
+         Cell #1 : offset of the reset assert control
+                   register from the syscon register base
+                   offset + 4: deassert control register
+                   offset + 8: status control register
+         Cell #2 : bit position of the reset in the reset control register
+
+Example:
+        iomcu: iomcu@ffd7e000 {
+                compatible = "hisilicon,hi3660-iomcu", "syscon";
+                reg = <0x0 0xffd7e000 0x0 0x1000>;
+        };
+
+        iomcu_rst: iomcu_rst_controller {
+                compatible = "hisilicon,hi3660-reset";
+                hisi,rst-syscon = <&iomcu>;
+                #reset-cells = <2>;
+        };
+
+Specifying reset lines connected to IP modules
+==============================================
+example:
+
+        i2c0: i2c@..... {
+                ...
+                resets = <&iomcu_rst 0x20 3>; /* offset: 0x20; bit: 3 */
+                ...
+        };
diff --git a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
index 164c7f34c451..c516d24959f2 100644
--- a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
+++ b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
@@ -63,7 +63,7 @@ Example:
 --------
 The following example demonstrates a syscon node, the reset controller node
 using the syscon node, and a consumer (a DSP device) on the TI Keystone 2
-Edison SoC.
+66AK2E SoC.
 
 / {
         soc {
@@ -71,13 +71,13 @@ Edison SoC.
                         compatible = "syscon", "simple-mfd";
                         reg = <0x02350000 0x1000>;
 
-                        pscrst: psc-reset {
+                        pscrst: reset-controller {
                                 compatible = "ti,k2e-pscrst", "ti,syscon-reset";
                                 #reset-cells = <1>;
 
                                 ti,reset-bits = <
-                                        0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_SET|DEASSERT_CLEAR|STATUS_SET)   /* 0: pcrst-dsp0 */
-                                        0xa40 5 0xa44 3 0     0 (ASSERT_SET|DEASSERT_CLEAR|STATUS_NONE)  /* 1: pcrst-example */
+                                        0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET   | STATUS_CLEAR) /* 0: dsp0 */
+                                        0xa40 5 0xa44 3 0     0 (ASSERT_SET   | DEASSERT_CLEAR | STATUS_NONE)  /* 1: example */
                                 >;
                         };
                 };
diff --git a/Documentation/devicetree/bindings/reset/uniphier-reset.txt b/Documentation/devicetree/bindings/reset/uniphier-reset.txt
index 5020524cddeb..83ab0f599c40 100644
--- a/Documentation/devicetree/bindings/reset/uniphier-reset.txt
+++ b/Documentation/devicetree/bindings/reset/uniphier-reset.txt
@@ -6,14 +6,14 @@ System reset
 
 Required properties:
 - compatible: should be one of the following:
-    "socionext,uniphier-sld3-reset" - for sLD3 SoC.
-    "socionext,uniphier-ld4-reset"  - for LD4 SoC.
-    "socionext,uniphier-pro4-reset" - for Pro4 SoC.
-    "socionext,uniphier-sld8-reset" - for sLD8 SoC.
-    "socionext,uniphier-pro5-reset" - for Pro5 SoC.
-    "socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC.
-    "socionext,uniphier-ld11-reset" - for LD11 SoC.
-    "socionext,uniphier-ld20-reset" - for LD20 SoC.
+    "socionext,uniphier-sld3-reset" - for sLD3 SoC
+    "socionext,uniphier-ld4-reset"  - for LD4 SoC
+    "socionext,uniphier-pro4-reset" - for Pro4 SoC
+    "socionext,uniphier-sld8-reset" - for sLD8 SoC
+    "socionext,uniphier-pro5-reset" - for Pro5 SoC
+    "socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC
+    "socionext,uniphier-ld11-reset" - for LD11 SoC
+    "socionext,uniphier-ld20-reset" - for LD20 SoC
 - #reset-cells: should be 1.
 
 Example:
@@ -37,14 +37,15 @@ Media I/O (MIO) reset, SD reset
 
 Required properties:
 - compatible: should be one of the following:
-    "socionext,uniphier-sld3-mio-reset" - for sLD3 SoC.
-    "socionext,uniphier-ld4-mio-reset"  - for LD4 SoC.
-    "socionext,uniphier-pro4-mio-reset" - for Pro4 SoC.
-    "socionext,uniphier-sld8-mio-reset" - for sLD8 SoC.
-    "socionext,uniphier-pro5-sd-reset"  - for Pro5 SoC.
-    "socionext,uniphier-pxs2-sd-reset"  - for PXs2/LD6b SoC.
-    "socionext,uniphier-ld11-mio-reset" - for LD11 SoC.
-    "socionext,uniphier-ld20-sd-reset"  - for LD20 SoC.
+    "socionext,uniphier-sld3-mio-reset" - for sLD3 SoC
+    "socionext,uniphier-ld4-mio-reset"  - for LD4 SoC
+    "socionext,uniphier-pro4-mio-reset" - for Pro4 SoC
+    "socionext,uniphier-sld8-mio-reset" - for sLD8 SoC
+    "socionext,uniphier-pro5-sd-reset"  - for Pro5 SoC
+    "socionext,uniphier-pxs2-sd-reset"  - for PXs2/LD6b SoC
+    "socionext,uniphier-ld11-mio-reset" - for LD11 SoC (MIO)
+    "socionext,uniphier-ld11-sd-reset"  - for LD11 SoC (SD)
+    "socionext,uniphier-ld20-sd-reset"  - for LD20 SoC
 - #reset-cells: should be 1.
 
 Example:
@@ -68,13 +69,13 @@ Peripheral reset
 
 Required properties:
 - compatible: should be one of the following:
-    "socionext,uniphier-ld4-peri-reset"  - for LD4 SoC.
-    "socionext,uniphier-pro4-peri-reset" - for Pro4 SoC.
-    "socionext,uniphier-sld8-peri-reset" - for sLD8 SoC.
-    "socionext,uniphier-pro5-peri-reset" - for Pro5 SoC.
-    "socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC.
-    "socionext,uniphier-ld11-peri-reset" - for LD11 SoC.
-    "socionext,uniphier-ld20-peri-reset" - for LD20 SoC.
+    "socionext,uniphier-ld4-peri-reset"  - for LD4 SoC
+    "socionext,uniphier-pro4-peri-reset" - for Pro4 SoC
+    "socionext,uniphier-sld8-peri-reset" - for sLD8 SoC
+    "socionext,uniphier-pro5-peri-reset" - for Pro5 SoC
+    "socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC
+    "socionext,uniphier-ld11-peri-reset" - for LD11 SoC
+    "socionext,uniphier-ld20-peri-reset" - for LD20 SoC
 - #reset-cells: should be 1.
 
 Example:
diff --git a/Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt b/Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt
new file mode 100644
index 000000000000..b015508f9780
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt
@@ -0,0 +1,20 @@
+ZTE zx2967 SoCs Reset Controller
+=======================================
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+Required properties:
+- compatible: should be one of the following.
+        * zte,zx296718-reset
+- reg: physical base address of the controller and length of memory mapped
+        region.
+- #reset-cells: must be 1.
+
+example:
+
+        reset: reset-controller@1461060 {
+                compatible = "zte,zx296718-reset";
+                reg = <0x01461060 0x8>;
+                #reset-cells = <1>;
+        };
diff --git a/Documentation/devicetree/bindings/rtc/armada-380-rtc.txt b/Documentation/devicetree/bindings/rtc/armada-380-rtc.txt
index 2eb9d4ee7dc0..c3c9a1226f9a 100644
--- a/Documentation/devicetree/bindings/rtc/armada-380-rtc.txt
+++ b/Documentation/devicetree/bindings/rtc/armada-380-rtc.txt
@@ -1,9 +1,11 @@
-* Real Time Clock of the Armada 38x SoCs
+* Real Time Clock of the Armada 38x/7K/8K SoCs
 
-RTC controller for the Armada 38x SoCs
+RTC controller for the Armada 38x, 7K and 8K SoCs
 
 Required properties:
-- compatible : Should be "marvell,armada-380-rtc"
+- compatible : Should be one of the following:
+        "marvell,armada-380-rtc" for Armada 38x SoC
+        "marvell,armada-8k-rtc" for Aramda 7K/8K SoCs
 - reg: a list of base address and size pairs, one for each entry in
   reg-names
 - reg names: should contain:
diff --git a/Documentation/devicetree/bindings/rtc/cortina,gemini.txt b/Documentation/devicetree/bindings/rtc/cortina,gemini.txt
new file mode 100644
index 000000000000..4ce4e794ddbb
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/cortina,gemini.txt
@@ -0,0 +1,14 @@
+* Cortina Systems Gemini RTC
+
+Gemini SoC real-time clock.
+
+Required properties:
+- compatible : Should be "cortina,gemini-rtc"
+
+Examples:
+
+rtc@45000000 {
+        compatible = "cortina,gemini-rtc";
+        reg = <0x45000000 0x100>;
+        interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
+};
diff --git a/Documentation/devicetree/bindings/rtc/imxdi-rtc.txt b/Documentation/devicetree/bindings/rtc/imxdi-rtc.txt
index c9d80d7da141..323cf26374cb 100644
--- a/Documentation/devicetree/bindings/rtc/imxdi-rtc.txt
+++ b/Documentation/devicetree/bindings/rtc/imxdi-rtc.txt
@@ -8,10 +8,13 @@ Required properties:
   region.
 - interrupts: rtc alarm interrupt
 
+Optional properties:
+- interrupts: dryice security violation interrupt
+
 Example:
 
 rtc@80056000 {
         compatible = "fsl,imx53-rtc", "fsl,imx25-rtc";
         reg = <0x80056000 2000>;
-        interrupts = <29>;
+        interrupts = <29 56>;
 };
diff --git a/Documentation/devicetree/bindings/rtc/maxim,ds3231.txt b/Documentation/devicetree/bindings/rtc/maxim,ds3231.txt
index 1ad4c1c2b3b3..85be53a42180 100644
--- a/Documentation/devicetree/bindings/rtc/maxim,ds3231.txt
+++ b/Documentation/devicetree/bindings/rtc/maxim,ds3231.txt
@@ -1,7 +1,8 @@
 * Maxim DS3231 Real Time Clock
 
 Required properties:
-see: Documentation/devicetree/bindings/i2c/trivial-admin-guide/devices.rst
+- compatible: Should contain "maxim,ds3231".
+- reg: I2C address for chip.
 
 Optional property:
 - #clock-cells: Should be 1.
diff --git a/Documentation/devicetree/bindings/rtc/pcf8563.txt b/Documentation/devicetree/bindings/rtc/pcf8563.txt
index 086c998c5561..36984acbb383 100644
--- a/Documentation/devicetree/bindings/rtc/pcf8563.txt
+++ b/Documentation/devicetree/bindings/rtc/pcf8563.txt
@@ -3,7 +3,8 @@
 Philips PCF8563/Epson RTC8564 Real Time Clock
 
 Required properties:
-see: Documentation/devicetree/bindings/i2c/trivial-admin-guide/devices.rst
+- compatible: Should contain "nxp,pcf8563".
+- reg: I2C address for chip.
 
 Optional property:
 - #clock-cells: Should be 0.
diff --git a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt
new file mode 100644
index 000000000000..e2837b951237
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt
@@ -0,0 +1,27 @@
+STM32 Real Time Clock
+
+Required properties:
+- compatible: "st,stm32-rtc".
+- reg: address range of rtc register set.
+- clocks: reference to the clock entry ck_rtc.
+- interrupt-parent: phandle for the interrupt controller.
+- interrupts: rtc alarm interrupt.
+- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain
+  (RTC registers) write protection.
+
+Optional properties (to override default ck_rtc parent clock):
+- assigned-clocks: reference to the ck_rtc clock entry.
+- assigned-clock-parents: phandle of the new parent clock of ck_rtc.
+
+Example:
+
+        rtc: rtc@40002800 {
+                compatible = "st,stm32-rtc";
+                reg = <0x40002800 0x400>;
+                clocks = <&rcc 1 CLK_RTC>;
+                assigned-clocks = <&rcc 1 CLK_RTC>;
+                assigned-clock-parents = <&rcc 1 CLK_LSE>;
+                interrupt-parent = <&exti>;
+                interrupts = <17 1>;
+                st,syscfg = <&pwrcfg>;
+        };
diff --git a/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt b/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt
index f007e428a1ab..945934918b71 100644
--- a/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt
+++ b/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt
@@ -8,10 +8,20 @@ Required properties:
                   memory mapped region.
 - interrupts    : IRQ lines for the RTC alarm 0 and alarm 1, in that order.
 
+Required properties for new device trees
+- clocks        : phandle to the 32kHz external oscillator
+- clock-output-names : name of the LOSC clock created
+- #clock-cells  : must be equals to 1. The RTC provides two clocks: the
+                  LOSC and its external output, with index 0 and 1
+                  respectively.
+
 Example:
 
 rtc: rtc@01f00000 {
         compatible = "allwinner,sun6i-a31-rtc";
         reg = <0x01f00000 0x54>;
         interrupts = <0 40 4>, <0 41 4>;
+        clock-output-names = "osc32k";
+        clocks = <&ext_osc32k>;
+        #clock-cells = <1>;
 };
diff --git a/Documentation/devicetree/bindings/serial/8250.txt b/Documentation/devicetree/bindings/serial/8250.txt
index f86bb06c39e9..10276a46ecef 100644
--- a/Documentation/devicetree/bindings/serial/8250.txt
+++ b/Documentation/devicetree/bindings/serial/8250.txt
@@ -19,6 +19,7 @@ Required properties:
         - "altr,16550-FIFO128"
         - "fsl,16550-FIFO64"
         - "fsl,ns16550"
+        - "ti,da830-uart"
         - "serial" if the port type is unknown.
 - reg : offset and length of the register set for the device.
 - interrupts : should contain uart interrupt.
diff --git a/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt b/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt
index 1e82802d8e32..574c3a2c77d5 100644
--- a/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt
+++ b/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt
@@ -6,11 +6,13 @@ Required properties:
 - interrupts : Should contain uart interrupt
 
 Optional properties:
-- uart-has-rtscts : Indicate the uart has rts and cts
 - fsl,irda-mode : Indicate the uart supports irda mode
 - fsl,dte-mode : Indicate the uart works in DTE mode. The uart works
                   in DCE mode by default.
 
+Please check Documentation/devicetree/bindings/serial/serial.txt
+for the complete list of generic properties.
+
 Note: Each uart controller should have an alias correctly numbered
 in "aliases" node.
 
diff --git a/Documentation/devicetree/bindings/serial/serial.txt b/Documentation/devicetree/bindings/serial/serial.txt
index fd970f76a7b8..b542a0ecf06e 100644
--- a/Documentation/devicetree/bindings/serial/serial.txt
+++ b/Documentation/devicetree/bindings/serial/serial.txt
@@ -23,7 +23,8 @@ Optional properties:
     they are available for use (wired and enabled by pinmux configuration).
     This depends on both the UART hardware and the board wiring.
     Note that this property is mutually-exclusive with "cts-gpios" and
-    "rts-gpios" above.
+    "rts-gpios" above, unless support is provided to switch between modes
+    dynamically.
 
 
 Examples:
diff --git a/Documentation/devicetree/bindings/serial/slave-device.txt b/Documentation/devicetree/bindings/serial/slave-device.txt
new file mode 100644
index 000000000000..f66037928f5f
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/slave-device.txt
@@ -0,0 +1,36 @@
+Serial Slave Device DT binding
+
+This documents the binding structure and common properties for serial
+attached devices. Common examples include Bluetooth, WiFi, NFC and GPS
+devices.
+
+Serial attached devices shall be a child node of the host UART device the
+slave device is attached to. It is expected that the attached device is
+the only child node of the UART device. The slave device node name shall
+reflect the generic type of device for the node.
+
+Required Properties:
+
+- compatible    : A string reflecting the vendor and specific device the node
+                  represents.
+
+Optional Properties:
+
+- max-speed     : The maximum baud rate the device operates at. This should
+                  only be present if the maximum is less than the slave device
+                  can support. For example, a particular board has some signal
+                  quality issue or the host processor can't support higher
+                  baud rates.
+
+Example:
+
+serial@1234 {
+        compatible = "ns16550a";
+        interrupts = <1>;
+
+        bluetooth {
+                compatible = "brcm,bcm43341-bt";
+                interrupt-parent = <&gpio>;
+                interrupts = <10>;
+        };
+};
diff --git a/Documentation/devicetree/bindings/soc/fsl/qman-portals.txt b/Documentation/devicetree/bindings/soc/fsl/qman-portals.txt
index 47e46ccbc170..5a34f3ab7bea 100644
--- a/Documentation/devicetree/bindings/soc/fsl/qman-portals.txt
+++ b/Documentation/devicetree/bindings/soc/fsl/qman-portals.txt
@@ -5,7 +5,6 @@ Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.
 CONTENTS
 
         - QMan Portal
-        - QMan Pool Channel
         - Example
 
 QMan Portal Node
@@ -82,25 +81,6 @@ These subnodes should have the following properties:
         Definition:     The phandle to the particular hardware device that this
                         portal is connected to.
 
-DPAA QMan Pool Channel Nodes
-
-Pool Channels are defined with the following properties.
-
-PROPERTIES
-
-- compatible
-        Usage:          Required
-        Value type:     <stringlist>
-        Definition:     Must include "fsl,qman-pool-channel"
-                        May include "fsl,<SoC>-qman-pool-channel"
-
-- fsl,qman-channel-id
-        Usage:          Required
-        Value type:     <u32>
-        Definition:     The hardware index of the channel. This can also be
-                        determined by dividing any of the channel's 8 work queue
-                        IDs by 8
-
 EXAMPLE
 
 The example below shows a (P4080) QMan portals container/bus node with two portals
diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.txt b/Documentation/devicetree/bindings/soc/rockchip/grf.txt
index 013e71a2cdc7..a0685c209218 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.txt
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.txt
@@ -5,20 +5,24 @@ is composed of many registers for system control.
 
 From RK3368 SoCs, the GRF is divided into two sections,
 - GRF, used for general non-secure system,
+- SGRF, used for general secure system,
 - PMUGRF, used for always on system
 
 Required Properties:
 
-- compatible: GRF should be one of the followings
+- compatible: GRF should be one of the following:
+   - "rockchip,rk3036-grf", "syscon": for rk3036
    - "rockchip,rk3066-grf", "syscon": for rk3066
    - "rockchip,rk3188-grf", "syscon": for rk3188
    - "rockchip,rk3228-grf", "syscon": for rk3228
    - "rockchip,rk3288-grf", "syscon": for rk3288
    - "rockchip,rk3368-grf", "syscon": for rk3368
    - "rockchip,rk3399-grf", "syscon": for rk3399
-- compatible: PMUGRF should be one of the followings
+- compatible: PMUGRF should be one of the following:
    - "rockchip,rk3368-pmugrf", "syscon": for rk3368
    - "rockchip,rk3399-pmugrf", "syscon": for rk3399
+- compatible: SGRF should be one of the following
+   - "rockchip,rk3288-sgrf", "syscon": for rk3288
 - reg: physical base address of the controller and length of memory mapped
   region.
 
diff --git a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
index f909ce06afc4..01bfb6745fbd 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
+++ b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
@@ -6,6 +6,7 @@ powered up/down by software based on different application scenes to save power.
 Required properties for power domain controller:
 - compatible: Should be one of the following.
         "rockchip,rk3288-power-controller" - for RK3288 SoCs.
+        "rockchip,rk3328-power-controller" - for RK3328 SoCs.
         "rockchip,rk3368-power-controller" - for RK3368 SoCs.
         "rockchip,rk3399-power-controller" - for RK3399 SoCs.
 - #power-domain-cells: Number of cells in a power-domain specifier.
@@ -16,6 +17,7 @@ Required properties for power domain controller:
 Required properties for power domain sub nodes:
 - reg: index of the power domain, should use macros in:
         "include/dt-bindings/power/rk3288-power.h" - for RK3288 type power domain.
+        "include/dt-bindings/power/rk3328-power.h" - for RK3328 type power domain.
         "include/dt-bindings/power/rk3368-power.h" - for RK3368 type power domain.
         "include/dt-bindings/power/rk3399-power.h" - for RK3399 type power domain.
 - clocks (optional): phandles to clocks which need to be enabled while power domain
@@ -90,6 +92,7 @@ containing a phandle to the power device node and an index specifying which
 power domain to use.
 The index should use macros in:
         "include/dt-bindings/power/rk3288-power.h" - for rk3288 type power domain.
+        "include/dt-bindings/power/rk3328-power.h" - for rk3328 type power domain.
         "include/dt-bindings/power/rk3368-power.h" - for rk3368 type power domain.
         "include/dt-bindings/power/rk3399-power.h" - for rk3399 type power domain.
 
diff --git a/Documentation/devicetree/bindings/soc/zte/pd-2967xx.txt b/Documentation/devicetree/bindings/soc/zte/pd-2967xx.txt
new file mode 100644
index 000000000000..7629de1c2c72
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/zte/pd-2967xx.txt
@@ -0,0 +1,19 @@
+* ZTE zx2967 family Power Domains
+
+zx2967 family includes support for multiple power domains which are used
+to gate power to one or more peripherals on the processor.
+
+Required Properties:
+  - compatible: should be one of the following.
+      * zte,zx296718-pcu - for zx296718 power domain.
+  - reg: physical base address of the controller and length of memory mapped
+      region.
+  - #power-domain-cells: Must be 1.
+
+Example:
+
+        pcu_domain: pcu@117000 {
+                compatible = "zte,zx296718-pcu";
+                reg = <0x00117000 0x1000>;
+                #power-domain-cells = <1>;
+        };
diff --git a/Documentation/devicetree/bindings/sound/axentia,tse850-pcm5142.txt b/Documentation/devicetree/bindings/sound/axentia,tse850-pcm5142.txt
index 5b9b38f578bb..fdb25b492514 100644
--- a/Documentation/devicetree/bindings/sound/axentia,tse850-pcm5142.txt
+++ b/Documentation/devicetree/bindings/sound/axentia,tse850-pcm5142.txt
@@ -2,8 +2,7 @@ Devicetree bindings for the Axentia TSE-850 audio complex
 
 Required properties:
   - compatible: "axentia,tse850-pcm5142"
-  - axentia,ssc-controller: The phandle of the atmel SSC controller used as
-    cpu dai.
+  - axentia,cpu-dai: The phandle of the cpu dai.
   - axentia,audio-codec: The phandle of the PCM5142 codec.
   - axentia,add-gpios: gpio specifier that controls the mixer.
   - axentia,loop1-gpios: gpio specifier that controls loop relays on channel 1.
@@ -43,6 +42,12 @@ the PCM5142 codec.
 
 Example:
 
+        &ssc0 {
+                #sound-dai-cells = <0>;
+
+                status = "okay";
+        };
+
         &i2c {
                 codec: pcm5142@4c {
                         compatible = "ti,pcm5142";
@@ -77,7 +82,7 @@ Example:
         sound {
                 compatible = "axentia,tse850-pcm5142";
 
-                axentia,ssc-controller = <&ssc0>;
+                axentia,cpu-dai = <&ssc0>;
                 axentia,audio-codec = <&codec>;
 
                 axentia,add-gpios = <&pioA 8 GPIO_ACTIVE_LOW>;
diff --git a/Documentation/devicetree/bindings/sound/es8328.txt b/Documentation/devicetree/bindings/sound/es8328.txt
index 30ea8a318ae9..33fbf058c997 100644
--- a/Documentation/devicetree/bindings/sound/es8328.txt
+++ b/Documentation/devicetree/bindings/sound/es8328.txt
@@ -4,7 +4,7 @@ This device supports both I2C and SPI.
 
 Required properties:
 
-  - compatible : "everest,es8328"
+  - compatible  : Should be "everest,es8328" or "everest,es8388"
   - DVDD-supply : Regulator providing digital core supply voltage 1.8 - 3.6V
   - AVDD-supply : Regulator providing analog supply voltage 3.3V
   - PVDD-supply : Regulator providing digital IO supply voltage 1.8 - 3.6V
diff --git a/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt b/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
index 3e623a724e55..9800a560e0c2 100644
--- a/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
+++ b/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
@@ -4,6 +4,7 @@ Required properties:
 - compatible = "mediatek,mt2701-audio";
 - reg: register location and size
 - interrupts: Should contain AFE interrupt
+- power-domains: should define the power domain
 - clock-names: should have these clock names:
                 "infra_sys_audio_clk",
                 "top_audio_mux1_sel",
@@ -58,6 +59,7 @@ Example:
                       <0 0x112A0000 0 0x20000>;
                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
                              <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
+                power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
                 clocks = <&infracfg CLK_INFRA_AUDIO>,
                          <&topckgen CLK_TOP_AUD_MUX1_SEL>,
                          <&topckgen CLK_TOP_AUD_MUX2_SEL>,
diff --git a/Documentation/devicetree/bindings/sound/nau8540.txt b/Documentation/devicetree/bindings/sound/nau8540.txt
new file mode 100644
index 000000000000..307a76528320
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/nau8540.txt
@@ -0,0 +1,16 @@
+NAU85L40 audio CODEC
+
+This device supports I2C only.
+
+Required properties:
+
+  - compatible : "nuvoton,nau8540"
+
+  - reg : the I2C address of the device.
+
+Example:
+
+codec: nau8540@1c {
+       compatible = "nuvoton,nau8540";
+       reg = <0x1c>;
+};
diff --git a/Documentation/devicetree/bindings/sound/rockchip,rk3288-hdmi-analog.txt b/Documentation/devicetree/bindings/sound/rockchip,rk3288-hdmi-analog.txt
new file mode 100644
index 000000000000..2539e1d68107
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/rockchip,rk3288-hdmi-analog.txt
@@ -0,0 +1,36 @@
+ROCKCHIP RK3288 with HDMI and analog audio
+
+Required properties:
+- compatible: "rockchip,rk3288-hdmi-analog"
+- rockchip,model: The user-visible name of this sound complex
+- rockchip,i2s-controller: The phandle of the Rockchip I2S controller that's
+  connected to the CODEC
+- rockchip,audio-codec: The phandle of the analog audio codec.
+- rockchip,routing: A list of the connections between audio components.
+                    Each entry is a pair of strings, the first being the
+                    connection's sink, the second being the connection's
+                    source. For this driver the first string should always be
+                    "Analog".
+
+Optionnal properties:
+- rockchip,hp-en-gpios = The phandle of the GPIO that power up/down the
+  headphone (when the analog output is an headphone).
+- rockchip,hp-det-gpios = The phandle of the GPIO that detects the headphone
+  (when the analog output is an headphone).
+- pinctrl-names, pinctrl-0: Please refer to pinctrl-bindings.txt
+
+Example:
+
+sound {
+        compatible = "rockchip,rockchip-audio-es8388";
+        rockchip,model = "Analog audio output";
+        rockchip,i2s-controller = <&i2s>;
+        rockchip,audio-codec = <&es8388>;
+        rockchip,routing = "Analog", "LOUT2",
+                           "Analog", "ROUT2";
+        rockchip,hp-en-gpios = <&gpio8 0 GPIO_ACTIVE_HIGH>;
+        rockchip,hp-det-gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&headphone>;
+};
+
diff --git a/Documentation/devicetree/bindings/sound/rockchip-i2s.txt b/Documentation/devicetree/bindings/sound/rockchip-i2s.txt
index 4ea29aa9af59..a6600f6dea64 100644
--- a/Documentation/devicetree/bindings/sound/rockchip-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/rockchip-i2s.txt
@@ -5,7 +5,7 @@ audio data transfer between devices in the system.
 
 Required properties:
 
-- compatible: should be one of the followings
+- compatible: should be one of the following:
    - "rockchip,rk3066-i2s": for rk3066
    - "rockchip,rk3188-i2s", "rockchip,rk3066-i2s": for rk3188
    - "rockchip,rk3288-i2s", "rockchip,rk3066-i2s": for rk3288
@@ -17,7 +17,7 @@ Required properties:
         Documentation/devicetree/bindings/dma/dma.txt
 - dma-names: should include "tx" and "rx".
 - clocks: a list of phandle + clock-specifer pairs, one for each entry in clock-names.
-- clock-names: should contain followings:
+- clock-names: should contain the following:
    - "i2s_hclk": clock for I2S BUS
    - "i2s_clk" : clock for I2S controller
 - rockchip,playback-channels: max playback channels, if not set, 8 channels default.
diff --git a/Documentation/devicetree/bindings/sound/rt5665.txt b/Documentation/devicetree/bindings/sound/rt5665.txt
index 419c89219681..419c89219681 100755..100644
--- a/Documentation/devicetree/bindings/sound/rt5665.txt
+++ b/Documentation/devicetree/bindings/sound/rt5665.txt
diff --git a/Documentation/devicetree/bindings/sound/sun4i-codec.txt b/Documentation/devicetree/bindings/sound/sun4i-codec.txt
index 3033bd8aab0f..3863531d1e6d 100644
--- a/Documentation/devicetree/bindings/sound/sun4i-codec.txt
+++ b/Documentation/devicetree/bindings/sound/sun4i-codec.txt
@@ -14,7 +14,7 @@ Required properties:
 - dma-names: should include "tx" and "rx".
 - clocks: a list of phandle + clock-specifer pairs, one for each entry
   in clock-names.
-- clock-names: should contain followings:
+- clock-names: should contain the following:
    - "apb": the parent APB clock for this controller
    - "codec": the parent module clock
 
diff --git a/Documentation/devicetree/bindings/sound/sun4i-i2s.txt b/Documentation/devicetree/bindings/sound/sun4i-i2s.txt
index 7b526ec64991..ee21da865771 100644
--- a/Documentation/devicetree/bindings/sound/sun4i-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/sun4i-i2s.txt
@@ -5,8 +5,9 @@ audio data transfer between devices in the system.
 
 Required properties:
 
-- compatible: should be one of the followings
+- compatible: should be one of the following:
    - "allwinner,sun4i-a10-i2s"
+   - "allwinner,sun6i-a31-i2s"
 - reg: physical base address of the controller and length of memory mapped
   region.
 - interrupts: should contain the I2S interrupt.
@@ -14,11 +15,15 @@ Required properties:
         Documentation/devicetree/bindings/dma/dma.txt
 - dma-names: should include "tx" and "rx".
 - clocks: a list of phandle + clock-specifer pairs, one for each entry in clock-names.
-- clock-names: should contain followings:
+- clock-names: should contain the following:
    - "apb" : clock for the I2S bus interface
    - "mod" : module clock for the I2S controller
 - #sound-dai-cells : Must be equal to 0
 
+Required properties for the following compatibles:
+        - "allwinner,sun6i-a31-i2s"
+- resets: phandle to the reset line for this codec
+
 Example:
 
 i2s0: i2s@01c22400 {
diff --git a/Documentation/devicetree/bindings/sound/sun8i-a33-codec.txt b/Documentation/devicetree/bindings/sound/sun8i-a33-codec.txt
new file mode 100644
index 000000000000..399b1b4bae22
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/sun8i-a33-codec.txt
@@ -0,0 +1,63 @@
+Allwinner SUN8I audio codec
+------------------------------------
+
+On Sun8i-A33 SoCs, the audio is separated in different parts:
+          - A DAI driver. It uses the "sun4i-i2s" driver which is
+          documented here:
+          Documentation/devicetree/bindings/sound/sun4i-i2s.txt
+          - An analog part of the codec which is handled as PRCM registers.
+          See Documentation/devicetree/bindings/sound/sun8i-codec-analog.txt
+          - An digital part of the codec which is documented in this current
+          binding documentation.
+          - And finally, an audio card which links all the above components.
+          The simple-audio card will be used.
+          See Documentation/devicetree/bindings/sound/simple-card.txt
+
+This bindings documentation exposes Sun8i codec (digital part).
+
+Required properties:
+- compatible: must be "allwinner,sun8i-a33-codec"
+- reg: must contain the registers location and length
+- interrupts: must contain the codec interrupt
+- clocks: a list of phandle + clock-specifer pairs, one for each entry
+  in clock-names.
+- clock-names: should contain followings:
+   - "bus": the parent APB clock for this controller
+   - "mod": the parent module clock
+
+Here is an example to add a sound card and the codec binding on sun8i SoCs that
+are similar to A33 using simple-card:
+
+        sound {
+                compatible = "simple-audio-card";
+                simple-audio-card,name = "sun8i-a33-audio";
+                simple-audio-card,format = "i2s";
+                simple-audio-card,frame-master = <&link_codec>;
+                simple-audio-card,bitclock-master = <&link_codec>;
+                simple-audio-card,mclk-fs = <512>;
+                simple-audio-card,aux-devs = <&codec_analog>;
+                simple-audio-card,routing =
+                                "Left DAC", "Digital Left DAC",
+                                "Right DAC", "Digital Right DAC";
+
+                simple-audio-card,cpu {
+                        sound-dai = <&dai>;
+                };
+
+                link_codec: simple-audio-card,codec {
+                        sound-dai = <&codec>;
+                };
+
+        soc@01c00000 {
+                [...]
+
+                audio-codec@1c22e00 {
+                        #sound-dai-cells = <0>;
+                        compatible = "allwinner,sun8i-a33-codec";
+                        reg = <0x01c22e00 0x400>;
+                        interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
+                        clock-names = "bus", "mod";
+                };
+        };
+
diff --git a/Documentation/devicetree/bindings/sound/sunxi,sun4i-spdif.txt b/Documentation/devicetree/bindings/sound/sunxi,sun4i-spdif.txt
index 0230c4d20506..fe0a65e6d629 100644
--- a/Documentation/devicetree/bindings/sound/sunxi,sun4i-spdif.txt
+++ b/Documentation/devicetree/bindings/sound/sunxi,sun4i-spdif.txt
@@ -10,6 +10,7 @@ Required properties:
   - compatible          : should be one of the following:
     - "allwinner,sun4i-a10-spdif": for the Allwinner A10 SoC
     - "allwinner,sun6i-a31-spdif": for the Allwinner A31 SoC
+    - "allwinner,sun8i-h3-spdif": for the Allwinner H3 SoC
 
   - reg                 : Offset and length of the register set for the device.
 
diff --git a/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt b/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt
index 7e5aa6f6b5a1..292ad5083704 100644
--- a/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt
@@ -1,10 +1,12 @@
 ZTE ZX296702 I2S controller
 
 Required properties:
- - compatible : Must be "zte,zx296702-i2s"
+ - compatible : Must be one of:
+        "zte,zx296718-i2s", "zte,zx296702-i2s"
+        "zte,zx296702-i2s"
  - reg : Must contain I2S core's registers location and length
  - clocks : Pairs of phandle and specifier referencing the controller's clocks.
- - clock-names: "tx" for the clock to the I2S interface.
+ - clock-names: "wclk" for the wclk, "pclk" for the pclk to the I2S interface.
  - dmas: Pairs of phandle and specifier for the DMA channel that is used by
    the core. The core expects two dma channels for transmit.
  - dma-names : Must be "tx" and "rx"
@@ -16,12 +18,12 @@ please check:
         * dma/dma.txt
 
 Example:
-        i2s0: i2s0@0b005000 {
+        i2s0: i2s@b005000 {
                 #sound-dai-cells = <0>;
-                compatible = "zte,zx296702-i2s";
+                compatible = "zte,zx296718-i2s", "zte,zx296702-i2s";
                 reg = <0x0b005000 0x1000>;
-                clocks = <&lsp0clk ZX296702_I2S0_DIV>;
-                clock-names = "tx";
+                clocks = <&audiocrm AUDIO_I2S0_WCLK>, <&audiocrm AUDIO_I2S0_PCLK>;
+                clock-names = "wclk", "pclk";
                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
                 dmas = <&dma 5>, <&dma 6>;
                 dma-names = "tx", "rx";
diff --git a/Documentation/devicetree/bindings/sram/sram.txt b/Documentation/devicetree/bindings/sram/sram.txt
index 068c2c03c38f..267da4410aef 100644
--- a/Documentation/devicetree/bindings/sram/sram.txt
+++ b/Documentation/devicetree/bindings/sram/sram.txt
@@ -42,6 +42,12 @@ Optional properties in the area nodes:
          and in use by another device or devices
 - export : indicates that the reserved SRAM area may be accessed outside
            of the kernel, e.g. by bootloader or userspace
+- protect-exec : Same as 'pool' above but with the additional
+                 constraint that code wil be run from the region and
+                 that the memory is maintained as read-only, executable
+                 during code execution. NOTE: This region must be page
+                 aligned on start and end in order to properly allow
+                 manipulation of the page attributes.
 - label : the name for the reserved partition, if omitted, the label
           is taken from the node name excluding the unit address.
 
diff --git a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
index 66223d561972..20ca4ef9d776 100644
--- a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
@@ -17,6 +17,12 @@ Required properties:
         calibration data, as specified by the SoC reference manual.
         The first cell of each pair is the value to be written to TTCFGR,
         and the second is the value to be written to TSCFGR.
+- #thermal-sensor-cells : Must be 1. The sensor specifier is the monitoring
+        site ID, and represents the "n" in TRITSRn and TRATSRn.
+
+Optional property:
+- little-endian : If present, the TMU registers are little endian. If absent,
+        the default is big endian.
 
 Example:
 
@@ -60,4 +66,5 @@ tmu@f0000 {
 
                                0x00030000 0x00000012
                                0x00030001 0x0000001d>;
+        #thermal-sensor-cells = <1>;
 };
diff --git a/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt b/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt
new file mode 100644
index 000000000000..07a9713ae6a7
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt
@@ -0,0 +1,56 @@
+* DT bindings for Renesas R-Car Gen3 Thermal Sensor driver
+
+On R-Car Gen3 SoCs, the thermal sensor controllers (TSC) control the thermal
+sensors (THS) which are the analog circuits for measuring temperature (Tj)
+inside the LSI.
+
+Required properties:
+- compatible            : "renesas,<soctype>-thermal",
+                          Examples with soctypes are:
+                            - "renesas,r8a7795-thermal" (R-Car H3)
+                            - "renesas,r8a7796-thermal" (R-Car M3-W)
+- reg                   : Address ranges of the thermal registers. Each sensor
+                          needs one address range. Sorting must be done in
+                          increasing order according to datasheet, i.e.
+                          TSC1, TSC2, ...
+- clocks                : Must contain a reference to the functional clock.
+- #thermal-sensor-cells : must be <1>.
+
+Optional properties:
+
+- interrupts           : interrupts routed to the TSC (3 for H3 and M3-W)
+- power-domain          : Must contain a reference to the power domain. This
+                          property is mandatory if the thermal sensor instance
+                          is part of a controllable power domain.
+
+Example:
+
+        tsc: thermal@e6198000 {
+                compatible = "renesas,r8a7795-thermal";
+                reg = <0 0xe6198000 0 0x68>,
+                      <0 0xe61a0000 0 0x5c>,
+                      <0 0xe61a8000 0 0x5c>;
+                interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cpg CPG_MOD 522>;
+                power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+                #thermal-sensor-cells = <1>;
+                status = "okay";
+        };
+
+        thermal-zones {
+                sensor_thermal1: sensor-thermal1 {
+                        polling-delay-passive = <250>;
+                        polling-delay = <1000>;
+                        thermal-sensors = <&tsc 0>;
+
+                        trips {
+                                sensor1_crit: sensor1-crit {
+                                        temperature = <90000>;
+                                        hysteresis = <2000>;
+                                        type = "critical";
+                                };
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/thermal/zx2967-thermal.txt b/Documentation/devicetree/bindings/thermal/zx2967-thermal.txt
new file mode 100644
index 000000000000..3dc1c6bf0478
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/zx2967-thermal.txt
@@ -0,0 +1,116 @@
+* ZTE zx2967 family Thermal
+
+Required Properties:
+- compatible: should be one of the following.
+    * zte,zx296718-thermal
+- reg: physical base address of the controller and length of memory mapped
+    region.
+- clocks : Pairs of phandle and specifier referencing the controller's clocks.
+- clock-names: "topcrm" for the topcrm clock.
+               "apb" for the apb clock.
+- #thermal-sensor-cells: must be 0.
+
+Please note: slope coefficient defined in thermal-zones section need to be
+multiplied by 1000.
+
+Example for tempsensor:
+
+        tempsensor: tempsensor@148a000 {
+                compatible = "zte,zx296718-thermal";
+                reg = <0x0148a000 0x20>;
+                clocks = <&topcrm TEMPSENSOR_GATE>, <&audiocrm AUDIO_TS_PCLK>;
+                clock-names = "topcrm", "apb";
+                #thermal-sensor-cells = <0>;
+        };
+
+Example for cooling device:
+
+        cooling_dev: cooling_dev {
+                cluster0_cooling_dev: cluster0-cooling-dev {
+                        #cooling-cells = <2>;
+                        cpumask = <0xf>;
+                        capacitance = <1500>;
+                };
+
+        cluster1_cooling_dev: cluster1-cooling-dev {
+                        #cooling-cells = <2>;
+                        cpumask = <0x30>;
+                        capacitance = <2000>;
+                };
+        };
+
+Example for thermal zones:
+
+        thermal-zones {
+                zx296718_thermal: zx296718_thermal {
+                        polling-delay-passive = <500>;
+                        polling-delay = <1000>;
+                        sustainable-power = <6500>;
+
+                        thermal-sensors = <&tempsensor 0>;
+                        /*
+                         * slope need to be multiplied by 1000.
+                         */
+                        coefficients = <1951 (-922)>;
+
+                        trips {
+                                trip0: switch_on_temperature {
+                                        temperature = <90000>;
+                                        hysteresis = <2000>;
+                                        type = "passive";
+                                };
+
+                                trip1: desired_temperature {
+                                        temperature = <100000>;
+                                        hysteresis = <2000>;
+                                        type = "passive";
+                                };
+
+                                crit: critical_temperature {
+                                        temperature = <110000>;
+                                        hysteresis = <2000>;
+                                        type = "critical";
+                                };
+                        };
+
+                        cooling-maps {
+                                map0 {
+                                        trip = <&trip0>;
+                                        cooling-device = <&gpu 2 5>;
+                                };
+
+                                map1 {
+                                        trip = <&trip0>;
+                                        cooling-device = <&cluster0_cooling_dev 1 2>;
+                                };
+
+                                map2 {
+                                        trip = <&trip1>;
+                                        cooling-device = <&cluster0_cooling_dev 1 2>;
+                                };
+
+                                map3 {
+                                        trip = <&crit>;
+                                        cooling-device = <&cluster0_cooling_dev 1 2>;
+                                };
+
+                                map4 {
+                                        trip = <&trip0>;
+                                        cooling-device = <&cluster1_cooling_dev 1 2>;
+                                        contribution = <9000>;
+                                };
+
+                                map5 {
+                                        trip = <&trip1>;
+                                        cooling-device = <&cluster1_cooling_dev 1 2>;
+                                        contribution = <4096>;
+                                };
+
+                                map6 {
+                                        trip = <&crit>;
+                                        cooling-device = <&cluster1_cooling_dev 1 2>;
+                                        contribution = <4096>;
+                                };
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/ufs/ufs-qcom.txt b/Documentation/devicetree/bindings/ufs/ufs-qcom.txt
index b6b5130e5f65..1f69ee1a61ea 100644
--- a/Documentation/devicetree/bindings/ufs/ufs-qcom.txt
+++ b/Documentation/devicetree/bindings/ufs/ufs-qcom.txt
@@ -29,7 +29,6 @@ Optional properties:
 - vdda-pll-max-microamp : specifies max. load that can be drawn from pll supply
 - vddp-ref-clk-supply   : phandle to UFS device ref_clk pad power supply
 - vddp-ref-clk-max-microamp : specifies max. load that can be drawn from this supply
-- vddp-ref-clk-always-on : specifies if this supply needs to be kept always on
 
 Example:
 
diff --git a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.txt b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.txt
index 862cd7c79805..d9b42da016f3 100644
--- a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.txt
+++ b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.txt
@@ -2,8 +2,8 @@ Allwinner sun4i A10 musb DRC/OTG controller
 -------------------------------------------
 
 Required properties:
- - compatible      : "allwinner,sun4i-a10-musb", "allwinner,sun6i-a31-musb"
-                     or "allwinner,sun8i-a33-musb"
+ - compatible      : "allwinner,sun4i-a10-musb", "allwinner,sun6i-a31-musb",
+                     "allwinner,sun8i-a33-musb" or "allwinner,sun8i-h3-musb"
  - reg             : mmio address range of the musb controller
  - clocks          : clock specifier for the musb controller ahb gate clock
  - reset           : reset specifier for the ahb reset (A31 and newer only)
diff --git a/Documentation/devicetree/bindings/usb/dwc3-st.txt b/Documentation/devicetree/bindings/usb/dwc3-st.txt
index 01c71b1258f4..50dee3b44665 100644
--- a/Documentation/devicetree/bindings/usb/dwc3-st.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3-st.txt
@@ -20,10 +20,10 @@ See: Documentation/devicetree/bindings/reset/reset.txt
    with 'reg' property
 
  - pinctl-names : A pinctrl state named "default" must be defined
-See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt
+See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
 
  - pinctrl-0    : Pin control group
-See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt
+See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
 
  - ranges       : allows valid 1:1 translation between child's address space and
                   parent's address space
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index e3e6983288e3..f658f394c2d3 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -56,6 +56,10 @@ Optional properties:
 
  - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be reallocated.
 
+ - in addition all properties from usb-xhci.txt from the current directory are
+   supported as well
+
+
 This is usually a subnode to DWC3 glue to which it is connected.
 
 dwc3@4a030000 {
diff --git a/Documentation/devicetree/bindings/usb/ehci-omap.txt b/Documentation/devicetree/bindings/usb/ehci-omap.txt
index 3dc231c832b0..d77e11a975a2 100644
--- a/Documentation/devicetree/bindings/usb/ehci-omap.txt
+++ b/Documentation/devicetree/bindings/usb/ehci-omap.txt
@@ -29,4 +29,3 @@ usbhsehci: ehci@4a064c00 {
 &usbhsehci {
         phys = <&hsusb1_phy 0 &hsusb3_phy>;
 };
-
diff --git a/Documentation/devicetree/bindings/usb/ehci-st.txt b/Documentation/devicetree/bindings/usb/ehci-st.txt
index fb45fa5770bb..410d922cfdd7 100644
--- a/Documentation/devicetree/bindings/usb/ehci-st.txt
+++ b/Documentation/devicetree/bindings/usb/ehci-st.txt
@@ -7,7 +7,7 @@ Required properties:
  - interrupts           : one EHCI interrupt should be described here
  - pinctrl-names        : a pinctrl state named "default" must be defined
  - pinctrl-0            : phandle referencing pin configuration of the USB controller
-See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt
+See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
  - clocks               : phandle list of usb clocks
  - clock-names          : should be "ic" for interconnect clock and "clk48"
 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
diff --git a/Documentation/devicetree/bindings/usb/mt8173-mtu3.txt b/Documentation/devicetree/bindings/usb/mt8173-mtu3.txt
index e049d199bf0d..1d7c3bc677f7 100644
--- a/Documentation/devicetree/bindings/usb/mt8173-mtu3.txt
+++ b/Documentation/devicetree/bindings/usb/mt8173-mtu3.txt
@@ -10,7 +10,7 @@ Required properties:
  - vusb33-supply : regulator of USB avdd3.3v
  - clocks : a list of phandle + clock-specifier pairs, one for each
         entry in clock-names
- - clock-names : must contain "sys_ck" for clock of controller;
+ - clock-names : must contain "sys_ck" and "ref_ck" for clock of controller;
         "wakeup_deb_p0" and "wakeup_deb_p1" are optional, they are
         depends on "mediatek,enable-wakeup"
  - phys : a list of phandle + phy specifier pairs
@@ -30,7 +30,7 @@ Optional properties:
         "id_float" and "id_ground" are optinal which depends on
         "mediatek,enable-manual-drd"
  - pinctrl-0 : pin control group
-        See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt
+        See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
 
  - maximum-speed : valid arguments are "super-speed", "high-speed" and
         "full-speed"; refer to usb/generic.txt
@@ -56,10 +56,10 @@ ssusb: usb@11271000 {
         phys = <&phy_port0 PHY_TYPE_USB3>,
                <&phy_port1 PHY_TYPE_USB2>;
         power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
-        clocks = <&topckgen CLK_TOP_USB30_SEL>,
+        clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>,
                  <&pericfg CLK_PERI_USB0>,
                  <&pericfg CLK_PERI_USB1>;
-        clock-names = "sys_ck",
+        clock-names = "sys_ck", "ref_ck",
                       "wakeup_deb_p0",
                       "wakeup_deb_p1";
         vusb33-supply = <&mt6397_vusb_reg>;
@@ -79,8 +79,8 @@ ssusb: usb@11271000 {
                 reg-names = "mac";
                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
                 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
-                clocks = <&topckgen CLK_TOP_USB30_SEL>;
-                clock-names = "sys_ck";
+                clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
+                clock-names = "sys_ck", "ref_ck";
                 vusb33-supply = <&mt6397_vusb_reg>;
                 status = "disabled";
         };
diff --git a/Documentation/devicetree/bindings/usb/mt8173-xhci.txt b/Documentation/devicetree/bindings/usb/mt8173-xhci.txt
index 2a930bd52b94..0acfc8acbea1 100644
--- a/Documentation/devicetree/bindings/usb/mt8173-xhci.txt
+++ b/Documentation/devicetree/bindings/usb/mt8173-xhci.txt
@@ -23,6 +23,7 @@ Required properties:
         entry in clock-names
  - clock-names : must contain
         "sys_ck": for clock of xHCI MAC
+        "ref_ck": for reference clock of xHCI MAC
         "wakeup_deb_p0": for USB wakeup debounce clock of port0
         "wakeup_deb_p1": for USB wakeup debounce clock of port1
 
@@ -37,7 +38,7 @@ Optional properties:
  - usb3-lpm-capable : supports USB3.0 LPM
  - pinctrl-names : a pinctrl state named "default" must be defined
  - pinctrl-0 : pin control group
-        See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt
+        See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
 
 Example:
 usb30: usb@11270000 {
@@ -47,10 +48,10 @@ usb30: usb@11270000 {
         reg-names = "mac", "ippc";
         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
         power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
-        clocks = <&topckgen CLK_TOP_USB30_SEL>,
+        clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>,
                  <&pericfg CLK_PERI_USB0>,
                  <&pericfg CLK_PERI_USB1>;
-        clock-names = "sys_ck",
+        clock-names = "sys_ck", "ref_ck",
                       "wakeup_deb_p0",
                       "wakeup_deb_p1";
         phys = <&phy_port0 PHY_TYPE_USB3>,
@@ -67,7 +68,7 @@ usb30: usb@11270000 {
 
 In the case, xhci is added as subnode to mtu3. An example and the DT binding
 details of mtu3 can be found in:
-Documentation/devicetree/bindings/usb/mtu3.txt
+Documentation/devicetree/bindings/usb/mt8173-mtu3.txt
 
 Required properties:
  - compatible : should contain "mediatek,mt8173-xhci"
@@ -82,6 +83,7 @@ Required properties:
         entry in clock-names
  - clock-names : must be
         "sys_ck": for clock of xHCI MAC
+        "ref_ck": for reference clock of xHCI MAC
 
 Optional properties:
  - vbus-supply : reference to the VBUS regulator;
@@ -94,8 +96,8 @@ usb30: usb@11270000 {
         reg-names = "mac";
         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
         power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
-        clocks = <&topckgen CLK_TOP_USB30_SEL>;
-        clock-names = "sys_ck";
+        clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
+        clock-names = "sys_ck", "ref_ck";
         vusb33-supply = <&mt6397_vusb_reg>;
         usb3-lpm-capable;
 };
diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
index 39acb084bce9..73cc0963e823 100644
--- a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
@@ -18,7 +18,7 @@ A child node must exist to represent the core DWC3 IP block. The name of
 the node is not important. The content of the node is defined in dwc3.txt.
 
 Phy documentation is provided in the following places:
-Documentation/devicetree/bindings/phy/qcom,dwc3-usb-phy.txt
+Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt
 
 Example device nodes:
 
diff --git a/Documentation/devicetree/bindings/usb/ulpi.txt b/Documentation/devicetree/bindings/usb/ulpi.txt
new file mode 100644
index 000000000000..ca179dc4bd50
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/ulpi.txt
@@ -0,0 +1,20 @@
+ULPI bus binding
+----------------
+
+Phys that are behind a ULPI connection can be described with the following
+binding. The host controller shall have a "ulpi" named node as a child, and
+that node shall have one enabled node underneath it representing the ulpi
+device on the bus.
+
+EXAMPLE
+-------
+
+usb {
+        compatible = "vendor,usb-controller";
+
+        ulpi {
+                phy {
+                        compatible = "vendor,phy";
+                };
+        };
+};
diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt
index 0b7d8576001c..2d80b60eeabe 100644
--- a/Documentation/devicetree/bindings/usb/usb-xhci.txt
+++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt
@@ -27,6 +27,7 @@ Required properties:
 Optional properties:
   - clocks: reference to a clock
   - usb3-lpm-capable: determines if platform is USB3 LPM capable
+  - quirk-broken-port-ped: set if the controller has broken port disable mechanism
 
 Example:
         usb@f0931000 {
diff --git a/Documentation/devicetree/bindings/usb/usb251xb.txt b/Documentation/devicetree/bindings/usb/usb251xb.txt
new file mode 100644
index 000000000000..3957d4edaa74
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/usb251xb.txt
@@ -0,0 +1,66 @@
+Microchip USB 2.0 Hi-Speed Hub Controller
+
+The device node for the configuration of a Microchip USB251xB/xBi USB 2.0
+Hi-Speed Controller.
+
+Required properties :
+ - compatible : Should be "microchip,usb251xb" or one of the specific types:
+        "microchip,usb2512b", "microchip,usb2512bi", "microchip,usb2513b",
+        "microchip,usb2513bi", "microchip,usb2514b", "microchip,usb2514bi"
+ - reset-gpios : Should specify the gpio for hub reset
+ - reg : I2C address on the selected bus (default is <0x2C>)
+
+Optional properties :
+ - skip-config : Skip Hub configuration, but only send the USB-Attach command
+ - vendor-id : Set USB Vendor ID of the hub (16 bit, default is 0x0424)
+ - product-id : Set USB Product ID of the hub (16 bit, default depends on type)
+ - device-id : Set USB Device ID of the hub (16 bit, default is 0x0bb3)
+ - language-id : Set USB Language ID (16 bit, default is 0x0000)
+ - manufacturer : Set USB Manufacturer string (max 31 characters long)
+ - product : Set USB Product string (max 31 characters long)
+ - serial : Set USB Serial string (max 31 characters long)
+ - {bus,self}-powered : selects between self- and bus-powered operation (default
+        is self-powered)
+ - disable-hi-speed : disable USB Hi-Speed support
+ - {multi,single}-tt : selects between multi- and single-transaction-translator
+        (default is multi-tt)
+ - disable-eop : disable End of Packet generation in full-speed mode
+ - {ganged,individual}-sensing : select over-current sense type in self-powered
+        mode (default is individual)
+ - {ganged,individual}-port-switching : select port power switching mode
+        (default is individual)
+ - dynamic-power-switching : enable auto-switching from self- to bus-powered
+        operation if the local power source is removed or unavailable
+ - oc-delay-us : Delay time (in microseconds) for filtering the over-current
+        sense inputs. Valid values are 100, 4000, 8000 (default) and 16000. If
+        an invalid value is given, the default is used instead.
+ - compound-device : indicate the hub is part of a compound device
+ - port-mapping-mode : enable port mapping mode
+ - string-support : enable string descriptor support (required for manufacturer,
+        product and serial string configuration)
+ - non-removable-ports : Should specify the ports which have a non-removable
+        device connected.
+ - sp-disabled-ports : Specifies the ports which will be self-power disabled
+ - bp-disabled-ports : Specifies the ports which will be bus-power disabled
+ - power-on-time-ms : Specifies the time it takes from the time the host
+        initiates the power-on sequence to a port until the port has adequate
+        power. The value is given in ms in a 0 - 510 range (default is 100ms).
+
+Examples:
+        usb2512b@2c {
+                compatible = "microchip,usb2512b";
+                reg = <0x2c>;
+                reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+        };
+
+        usb2514b@2c {
+                compatible = "microchip,usb2514b";
+                reg = <0x2c>;
+                reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+                vendor-id = /bits/ 16 <0x0000>;
+                product-id = /bits/ 16 <0x0000>;
+                string-support;
+                manufacturer = "Foo";
+                product = "Foo-Bar";
+                serial = "1234567890A";
+        };
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 16d3b5e7f5d1..ec0bfb9bbebd 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -40,6 +40,7 @@ atmel	Atmel Corporation
 auo     AU Optronics Corporation
 auvidea Auvidea GmbH
 avago   Avago Technologies
+avia    avia semiconductor
 avic    Shanghai AVIC Optoelectronics Co., Ltd.
 axentia Axentia Technologies AB
 axis    Axis Communications AB
@@ -75,6 +76,7 @@ dallas	Maxim Integrated Products (formerly Dallas Semiconductor)
 davicom DAVICOM Semiconductor, Inc.
 delta   Delta Electronics, Inc.
 denx    Denx Software Engineering
+devantech       Devantech, Ltd.
 digi    Digi International Inc.
 digilent        Diglent, Inc.
 dlg     Dialog Semiconductor
@@ -102,11 +104,13 @@ everest	Everest Semiconductor Co. Ltd.
 everspin        Everspin Technologies, Inc.
 excito  Excito
 ezchip  EZchip Semiconductor
+faraday Faraday Technology Corporation
 fcs     Fairchild Semiconductor
 firefly Firefly
 focaltech       FocalTech Systems Co.,Ltd
 friendlyarm     Guangzhou FriendlyARM Computer Tech Co., Ltd
 fsl     Freescale Semiconductor
+fujitsu Fujitsu Ltd.
 ge      General Electric Company
 geekbuying      GeekBuying
 gef     GE Fanuc Intelligent Platforms Embedded Systems, Inc.
@@ -118,6 +122,7 @@ gmt	Global Mixed-mode Technology, Inc.
 goodix  Shenzhen Huiding Technology Co., Ltd.
 google  Google, Inc.
 grinn   Grinn
+grmn    Garmin Limited
 gumstix Gumstix, Inc.
 gw      Gateworks Corporation
 hannstar        HannStar Display Corporation
@@ -159,11 +164,14 @@ kosagi	Sutajio Ko-Usagi PTE Ltd.
 kyo     Kyocera Corporation
 lacie   LaCie
 lantiq  Lantiq Semiconductor
+lego    LEGO Systems A/S
 lenovo  Lenovo Group Ltd.
 lg      LG Corporation
+licheepi        Lichee Pi
 linux   Linux-specific binding
 lltc    Linear Technology Corporation
 lsi     LSI Corp. (LSI Logic)
+lwn     Liebherr-Werk Nenzing GmbH
 macnica Macnica Americas
 marvell Marvell Technology Group Ltd.
 maxim   Maxim Integrated Products
@@ -187,6 +195,7 @@ mpl	MPL AG
 mqmaker mqmaker Inc.
 msi     Micro-Star International Co. Ltd.
 mti     Imagination Technologies Ltd. (formerly MIPS Technologies Inc.)
+multi-inno      Multi-Inno Technology Co.,Ltd
 mundoreader     Mundo Reader S.L.
 murata  Murata Manufacturing Co., Ltd.
 mxicy   Macronix International Co., Ltd.
@@ -196,6 +205,7 @@ nec	NEC LCD Technologies, Ltd.
 neonode         Neonode Inc.
 netgear NETGEAR
 netlogic        Broadcom Corporation (formerly NetLogic Microsystems)
+netron-dy       Netron DY
 netxeon         Shenzhen Netxeon Technology CO., LTD
 nexbox  Nexbox
 newhaven        Newhaven Display International
@@ -227,6 +237,7 @@ pine64	Pine64
 pixcir  PIXCIR MICROELECTRONICS Co., Ltd
 plathome        Plat'Home Co., Ltd.
 plda    PLDA
+poslab  Poslab Technology Co., Ltd.
 powervr PowerVR (deprecated, use img)
 pulsedlight     PulsedLight, Inc
 qca     Qualcomm Atheros, Inc.
@@ -296,6 +307,7 @@ technologic	Technologic Systems
 terasic Terasic Inc.
 thine   THine Electronics, Inc.
 ti      Texas Instruments
+tianma  Tianma Micro-electronics Co., Ltd.
 tlm     Trusted Logic Mobility
 topeet  Topeet
 toradex Toradex AG
@@ -320,6 +332,7 @@ virtio	Virtual I/O Device Specification, developed by the OASIS consortium
 vivante Vivante Corporation
 voipac  Voipac Technologies s.r.o.
 wd      Western Digital Corp.
+wetek   WeTek Electronics, limited.
 wexler  Wexler
 winbond Winbond Electronics corp.
 wlf     Wolfson Microelectronics
@@ -328,7 +341,9 @@ x-powers	X-Powers
 xes     Extreme Engineering Solutions (X-ES)
 xillybus        Xillybus Ltd.
 xlnx    Xilinx
+xunlong Shenzhen Xunlong Software CO.,Limited
 zarlink Zarlink Semiconductor
+zeitec  ZEITEC Semiconductor Co., LTD.
 zii     Zodiac Inflight Innovations
 zte     ZTE Corp.
 zyxel   ZyXEL Communications Corp.
diff --git a/Documentation/devicetree/bindings/watchdog/cortina,gemin-watchdog.txt b/Documentation/devicetree/bindings/watchdog/cortina,gemin-watchdog.txt
new file mode 100644
index 000000000000..bc4b865d178b
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/cortina,gemin-watchdog.txt
@@ -0,0 +1,17 @@
+Cortina Systems Gemini SoC Watchdog
+
+Required properties:
+- compatible : must be "cortina,gemini-watchdog"
+- reg : shall contain base register location and length
+- interrupts : shall contain the interrupt for the watchdog
+
+Optional properties:
+- timeout-sec : the default watchdog timeout in seconds.
+
+Example:
+
+watchdog@41000000 {
+        compatible = "cortina,gemini-watchdog";
+        reg = <0x41000000 0x1000>;
+        interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+};
diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt b/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt
index 8f3d96af81d7..1f6e101e299a 100644
--- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt
@@ -6,10 +6,11 @@ occurred.
 
 Required properties:
 - compatible : should be one among the following
-        (a) "samsung,s3c2410-wdt" for Exynos4 and previous SoCs
-        (b) "samsung,exynos5250-wdt" for Exynos5250
-        (c) "samsung,exynos5420-wdt" for Exynos5420
-        (c) "samsung,exynos7-wdt" for Exynos7
+        - "samsung,s3c2410-wdt" for S3C2410
+        - "samsung,s3c6410-wdt" for S3C6410, S5PV210 and Exynos4
+        - "samsung,exynos5250-wdt" for Exynos5250
+        - "samsung,exynos5420-wdt" for Exynos5420
+        - "samsung,exynos7-wdt" for Exynos7
 
 - reg : base physical address of the controller and length of memory mapped
         region.
diff --git a/Documentation/devicetree/bindings/watchdog/zte,zx2967-wdt.txt b/Documentation/devicetree/bindings/watchdog/zte,zx2967-wdt.txt
new file mode 100644
index 000000000000..06ce67766756
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/zte,zx2967-wdt.txt
@@ -0,0 +1,32 @@
+ZTE zx2967 Watchdog timer
+
+Required properties:
+
+- compatible : should be one of the following.
+       * zte,zx296718-wdt
+- reg : Specifies base physical address and size of the registers.
+- clocks : Pairs of phandle and specifier referencing the controller's clocks.
+- resets : Reference to the reset controller controlling the watchdog
+           controller.
+
+Optional properties:
+
+- timeout-sec : Contains the watchdog timeout in seconds.
+- zte,wdt-reset-sysctrl : Directs how to reset system by the watchdog.
+        if we don't want to restart system when watchdog been triggered,
+        it's not required, vice versa.
+        It should include following fields.
+          * phandle of aon-sysctrl.
+          * offset of register that be written, should be 0xb0.
+          * configure value that be written to aon-sysctrl.
+          * bit mask, corresponding bits will be affected.
+
+Example:
+
+wdt: watchdog@1465000 {
+        compatible = "zte,zx296718-wdt";
+        reg = <0x1465000 0x1000>;
+        clocks = <&topcrm WDT_WCLK>;
+        resets = <&toprst 35>;
+        zte,wdt-reset-sysctrl = <&aon_sysctrl 0xb0 1 0x115>;
+};