mailbox: add STMicroelectronics STM32 IPCC driver

The STMicroelectronics STM32 Inter-Processor Communication Controller
(IPCC) is used for communicating data between two processors.
It provides a non blocking signaling mechanism to post and retrieve
communication data in an atomic way.

Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>

3 files changed, 412 insertions, 0 deletions

diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 725dce5ba62d..fb3f250e587b 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -177,4 +177,12 @@ config BCM_FLEXRM_MBOX
           Mailbox implementation of the Broadcom FlexRM ring manager,
           which provides access to various offload engines on Broadcom
           SoCs. Say Y here if you want to use the Broadcom FlexRM.
+
+config STM32_IPCC
+        tristate "STM32 IPCC Mailbox"
+        depends on MACH_STM32MP157
+        help
+          Mailbox implementation for STMicroelectonics STM32 family chips
+          with hardware for Inter-Processor Communication Controller (IPCC)
+          between processors. Say Y here if you want to have this support.
 endif
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index cc23c3a43fcd..4d501bea7863 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -38,3 +38,5 @@ obj-$(CONFIG_BCM_FLEXRM_MBOX)	+= bcm-flexrm-mailbox.o
 obj-$(CONFIG_QCOM_APCS_IPC)     += qcom-apcs-ipc-mailbox.o
 
 obj-$(CONFIG_TEGRA_HSP_MBOX)    += tegra-hsp.o
+
+obj-$(CONFIG_STM32_IPCC)        += stm32-ipcc.o
diff --git a/drivers/mailbox/stm32-ipcc.c b/drivers/mailbox/stm32-ipcc.c
new file mode 100644
index 000000000000..533b0da5235d
--- /dev/null
+++ b/drivers/mailbox/stm32-ipcc.c
@@ -0,0 +1,402 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
+ * Authors: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
+ *          Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/interrupt.h>
+#include <linux/mailbox_controller.h>
+#include <linux/module.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/pm_wakeirq.h>
+
+#define IPCC_XCR                0x000
+#define XCR_RXOIE               BIT(0)
+#define XCR_TXOIE               BIT(16)
+
+#define IPCC_XMR                0x004
+#define IPCC_XSCR               0x008
+#define IPCC_XTOYSR             0x00c
+
+#define IPCC_PROC_OFFST         0x010
+
+#define IPCC_HWCFGR             0x3f0
+#define IPCFGR_CHAN_MASK        GENMASK(7, 0)
+
+#define IPCC_VER                0x3f4
+#define VER_MINREV_MASK         GENMASK(3, 0)
+#define VER_MAJREV_MASK         GENMASK(7, 4)
+
+#define RX_BIT_MASK             GENMASK(15, 0)
+#define RX_BIT_CHAN(chan)       BIT(chan)
+#define TX_BIT_SHIFT            16
+#define TX_BIT_MASK             GENMASK(31, 16)
+#define TX_BIT_CHAN(chan)       BIT(TX_BIT_SHIFT + (chan))
+
+#define STM32_MAX_PROCS         2
+
+enum {
+        IPCC_IRQ_RX,
+        IPCC_IRQ_TX,
+        IPCC_IRQ_NUM,
+};
+
+struct stm32_ipcc {
+        struct mbox_controller controller;
+        void __iomem *reg_base;
+        void __iomem *reg_proc;
+        struct clk *clk;
+        int irqs[IPCC_IRQ_NUM];
+        int wkp;
+        u32 proc_id;
+        u32 n_chans;
+        u32 xcr;
+        u32 xmr;
+};
+
+static inline void stm32_ipcc_set_bits(void __iomem *reg, u32 mask)
+{
+        writel_relaxed(readl_relaxed(reg) | mask, reg);
+}
+
+static inline void stm32_ipcc_clr_bits(void __iomem *reg, u32 mask)
+{
+        writel_relaxed(readl_relaxed(reg) & ~mask, reg);
+}
+
+static irqreturn_t stm32_ipcc_rx_irq(int irq, void *data)
+{
+        struct stm32_ipcc *ipcc = data;
+        struct device *dev = ipcc->controller.dev;
+        u32 status, mr, tosr, chan;
+        irqreturn_t ret = IRQ_NONE;
+        int proc_offset;
+
+        /* read 'channel occupied' status from other proc */
+        proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST;
+        tosr = readl_relaxed(ipcc->reg_proc + proc_offset + IPCC_XTOYSR);
+        mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
+
+        /* search for unmasked 'channel occupied' */
+        status = tosr & FIELD_GET(RX_BIT_MASK, ~mr);
+
+        for (chan = 0; chan < ipcc->n_chans; chan++) {
+                if (!(status & (1 << chan)))
+                        continue;
+
+                dev_dbg(dev, "%s: chan:%d rx\n", __func__, chan);
+
+                mbox_chan_received_data(&ipcc->controller.chans[chan], NULL);
+
+                stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XSCR,
+                                    RX_BIT_CHAN(chan));
+
+                ret = IRQ_HANDLED;
+        }
+
+        return ret;
+}
+
+static irqreturn_t stm32_ipcc_tx_irq(int irq, void *data)
+{
+        struct stm32_ipcc *ipcc = data;
+        struct device *dev = ipcc->controller.dev;
+        u32 status, mr, tosr, chan;
+        irqreturn_t ret = IRQ_NONE;
+
+        tosr = readl_relaxed(ipcc->reg_proc + IPCC_XTOYSR);
+        mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
+
+        /* search for unmasked 'channel free' */
+        status = ~tosr & FIELD_GET(TX_BIT_MASK, ~mr);
+
+        for (chan = 0; chan < ipcc->n_chans ; chan++) {
+                if (!(status & (1 << chan)))
+                        continue;
+
+                dev_dbg(dev, "%s: chan:%d tx\n", __func__, chan);
+
+                /* mask 'tx channel free' interrupt */
+                stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XMR,
+                                    TX_BIT_CHAN(chan));
+
+                mbox_chan_txdone(&ipcc->controller.chans[chan], 0);
+
+                ret = IRQ_HANDLED;
+        }
+
+        return ret;
+}
+
+static int stm32_ipcc_send_data(struct mbox_chan *link, void *data)
+{
+        unsigned int chan = (unsigned int)link->con_priv;
+        struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
+                                               controller);
+
+        dev_dbg(ipcc->controller.dev, "%s: chan:%d\n", __func__, chan);
+
+        /* set channel n occupied */
+        stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan));
+
+        /* unmask 'tx channel free' interrupt */
+        stm32_ipcc_clr_bits(ipcc->reg_proc + IPCC_XMR, TX_BIT_CHAN(chan));
+
+        return 0;
+}
+
+static int stm32_ipcc_startup(struct mbox_chan *link)
+{
+        unsigned int chan = (unsigned int)link->con_priv;
+        struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
+                                               controller);
+        int ret;
+
+        ret = clk_prepare_enable(ipcc->clk);
+        if (ret) {
+                dev_err(ipcc->controller.dev, "can not enable the clock\n");
+                return ret;
+        }
+
+        /* unmask 'rx channel occupied' interrupt */
+        stm32_ipcc_clr_bits(ipcc->reg_proc + IPCC_XMR, RX_BIT_CHAN(chan));
+
+        return 0;
+}
+
+static void stm32_ipcc_shutdown(struct mbox_chan *link)
+{
+        unsigned int chan = (unsigned int)link->con_priv;
+        struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
+                                               controller);
+
+        /* mask rx/tx interrupt */
+        stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XMR,
+                            RX_BIT_CHAN(chan) | TX_BIT_CHAN(chan));
+
+        clk_disable_unprepare(ipcc->clk);
+}