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authorBen Skeggs <bskeggs@redhat.com>2013-10-14 19:38:12 -0400
committerBen Skeggs <bskeggs@redhat.com>2013-11-08 00:40:04 -0500
commitff4b42c7532e6ed6a5ae3c9cb71395b41a0a4022 (patch)
treea2a8bfe60a5bbb89d5051b02467002ae079e7f66
parent682b1fc79399bad4d538a36bb3eb12b3ec356f03 (diff)
drm/nouveau/pwr: initial implementation
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat
-rw-r--r--drivers/gpu/drm/nouveau/Makefile6
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/base.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nv50.c5
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nvc0.c9
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nve0.c6
-rw-r--r--drivers/gpu/drm/nouveau/core/include/subdev/pwr.h80
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/mc/nv98.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/pwr/base.c247
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/host.fuc151
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/idle.fuc84
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc452
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/macros.fuc199
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc219
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc63
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h1165
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc63
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h1229
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc63
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h1229
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc63
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h1229
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h27
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/perf.fuc57
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/test.fuc64
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c121
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/pwr/nv108.c62
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/pwr/nva3.c71
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/pwr/nvc0.c62
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/pwr/nvd0.c62
30 files changed, 7091 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index 96492b426e28..fbe33ed5f6cf 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -129,6 +129,12 @@ nouveau-y += core/subdev/mc/nvc3.o
129nouveau-y += core/subdev/mxm/base.o 129nouveau-y += core/subdev/mxm/base.o
130nouveau-y += core/subdev/mxm/mxms.o 130nouveau-y += core/subdev/mxm/mxms.o
131nouveau-y += core/subdev/mxm/nv50.o 131nouveau-y += core/subdev/mxm/nv50.o
132nouveau-y += core/subdev/pwr/base.o
133nouveau-y += core/subdev/pwr/memx.o
134nouveau-y += core/subdev/pwr/nva3.o
135nouveau-y += core/subdev/pwr/nvc0.o
136nouveau-y += core/subdev/pwr/nvd0.o
137nouveau-y += core/subdev/pwr/nv108.o
132nouveau-y += core/subdev/therm/base.o 138nouveau-y += core/subdev/therm/base.o
133nouveau-y += core/subdev/therm/fan.o 139nouveau-y += core/subdev/therm/fan.o
134nouveau-y += core/subdev/therm/fannil.o 140nouveau-y += core/subdev/therm/fannil.o
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/base.c b/drivers/gpu/drm/nouveau/core/engine/device/base.c
index 85ed9fbf2f44..894985aa84f3 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/base.c
@@ -75,6 +75,7 @@ static const u64 disable_map[] = {
75 [NVDEV_SUBDEV_BAR] = NV_DEVICE_DISABLE_CORE, 75 [NVDEV_SUBDEV_BAR] = NV_DEVICE_DISABLE_CORE,
76 [NVDEV_SUBDEV_VOLT] = NV_DEVICE_DISABLE_CORE, 76 [NVDEV_SUBDEV_VOLT] = NV_DEVICE_DISABLE_CORE,
77 [NVDEV_SUBDEV_THERM] = NV_DEVICE_DISABLE_CORE, 77 [NVDEV_SUBDEV_THERM] = NV_DEVICE_DISABLE_CORE,
78 [NVDEV_SUBDEV_PWR] = NV_DEVICE_DISABLE_CORE,
78 [NVDEV_ENGINE_DMAOBJ] = NV_DEVICE_DISABLE_CORE, 79 [NVDEV_ENGINE_DMAOBJ] = NV_DEVICE_DISABLE_CORE,
79 [NVDEV_ENGINE_FIFO] = NV_DEVICE_DISABLE_FIFO, 80 [NVDEV_ENGINE_FIFO] = NV_DEVICE_DISABLE_FIFO,
80 [NVDEV_ENGINE_SW] = NV_DEVICE_DISABLE_FIFO, 81 [NVDEV_ENGINE_SW] = NV_DEVICE_DISABLE_FIFO,
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv50.c b/drivers/gpu/drm/nouveau/core/engine/device/nv50.c
index 3ac753a99297..536cacf9f5a6 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nv50.c
@@ -36,6 +36,7 @@
36#include <subdev/instmem.h> 36#include <subdev/instmem.h>
37#include <subdev/vm.h> 37#include <subdev/vm.h>
38#include <subdev/bar.h> 38#include <subdev/bar.h>
39#include <subdev/pwr.h>
39 40
40#include <engine/device.h> 41#include <engine/device.h>
41#include <engine/dmaobj.h> 42#include <engine/dmaobj.h>
@@ -327,6 +328,7 @@ nv50_identify(struct nouveau_device *device)
327 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; 328 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
328 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 329 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
329 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 330 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
331 device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass;
330 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; 332 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
331 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; 333 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
332 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 334 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
@@ -354,6 +356,7 @@ nv50_identify(struct nouveau_device *device)
354 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; 356 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
355 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 357 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
356 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 358 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
359 device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass;
357 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; 360 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
358 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; 361 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
359 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 362 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
@@ -380,6 +383,7 @@ nv50_identify(struct nouveau_device *device)
380 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; 383 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
381 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 384 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
382 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 385 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
386 device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass;
383 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; 387 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
384 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; 388 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
385 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 389 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
@@ -406,6 +410,7 @@ nv50_identify(struct nouveau_device *device)
406 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; 410 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
407 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; 411 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
408 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; 412 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
413 device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass;
409 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass; 414 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
410 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; 415 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
411 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 416 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
index 54c22e90ec45..e4947914f979 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
@@ -38,6 +38,7 @@
38#include <subdev/instmem.h> 38#include <subdev/instmem.h>
39#include <subdev/vm.h> 39#include <subdev/vm.h>
40#include <subdev/bar.h> 40#include <subdev/bar.h>
41#include <subdev/pwr.h>
41 42
42#include <engine/device.h> 43#include <engine/device.h>
43#include <engine/dmaobj.h> 44#include <engine/dmaobj.h>
@@ -72,6 +73,7 @@ nvc0_identify(struct nouveau_device *device)
72 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; 73 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
73 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 74 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
74 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 75 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
76 device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
75 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; 77 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
76 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; 78 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
77 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 79 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
@@ -101,6 +103,7 @@ nvc0_identify(struct nouveau_device *device)
101 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; 103 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
102 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 104 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
103 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 105 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
106 device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
104 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; 107 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
105 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; 108 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
106 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 109 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
@@ -130,6 +133,7 @@ nvc0_identify(struct nouveau_device *device)
130 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; 133 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
131 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 134 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
132 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 135 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
136 device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
133 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; 137 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
134 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; 138 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
135 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 139 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
@@ -158,6 +162,7 @@ nvc0_identify(struct nouveau_device *device)
158 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; 162 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
159 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 163 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
160 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 164 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
165 device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
161 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; 166 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
162 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; 167 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
163 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 168 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
@@ -187,6 +192,7 @@ nvc0_identify(struct nouveau_device *device)
187 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; 192 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
188 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 193 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
189 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 194 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
195 device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
190 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; 196 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
191 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; 197 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
192 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 198 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
@@ -216,6 +222,7 @@ nvc0_identify(struct nouveau_device *device)
216 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; 222 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
217 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 223 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
218 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 224 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
225 device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
219 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; 226 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
220 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; 227 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
221 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 228 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
@@ -244,6 +251,7 @@ nvc0_identify(struct nouveau_device *device)
244 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; 251 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
245 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 252 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
246 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 253 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
254 device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
247 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; 255 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
248 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; 256 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
249 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 257 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
@@ -273,6 +281,7 @@ nvc0_identify(struct nouveau_device *device)
273 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; 281 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
274 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 282 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
275 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 283 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
284 device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
276 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; 285 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
277 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; 286 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
278 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 287 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
index 9171f8d315ff..e6254a64e9fb 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
@@ -38,6 +38,7 @@
38#include <subdev/instmem.h> 38#include <subdev/instmem.h>
39#include <subdev/vm.h> 39#include <subdev/vm.h>
40#include <subdev/bar.h> 40#include <subdev/bar.h>
41#include <subdev/pwr.h>
41 42
42#include <engine/device.h> 43#include <engine/device.h>
43#include <engine/dmaobj.h> 44#include <engine/dmaobj.h>
@@ -72,6 +73,7 @@ nve0_identify(struct nouveau_device *device)
72 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; 73 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
73 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 74 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
74 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 75 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
76 device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
75 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; 77 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
76 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; 78 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
77 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 79 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
@@ -102,6 +104,7 @@ nve0_identify(struct nouveau_device *device)
102 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; 104 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
103 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 105 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
104 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 106 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
107 device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
105 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; 108 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
106 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; 109 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
107 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 110 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
@@ -132,6 +135,7 @@ nve0_identify(struct nouveau_device *device)
132 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; 135 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
133 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 136 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
134 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 137 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
138 device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
135 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; 139 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
136 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; 140 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
137 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 141 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
@@ -162,6 +166,7 @@ nve0_identify(struct nouveau_device *device)
162 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; 166 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
163 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 167 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
164 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 168 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
169 device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
165 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; 170 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
166 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; 171 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
167 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 172 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
@@ -194,6 +199,7 @@ nve0_identify(struct nouveau_device *device)
194 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; 199 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
195 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; 200 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
196 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 201 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
202 device->oclass[NVDEV_SUBDEV_PWR ] = &nv108_pwr_oclass;
197 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; 203 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
198#if 0 204#if 0
199 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; 205 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h b/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h
new file mode 100644
index 000000000000..c5c92cbed33f
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h
@@ -0,0 +1,80 @@
1#ifndef __NOUVEAU_PWR_H__
2#define __NOUVEAU_PWR_H__
3
4#include <core/subdev.h>
5#include <core/device.h>
6
7struct nouveau_pwr {
8 struct nouveau_subdev base;
9
10 struct {
11 u32 limit;
12 u32 *data;
13 u32 size;
14 } code;
15
16 struct {
17 u32 limit;
18 u32 *data;
19 u32 size;
20 } data;
21
22 struct {
23 u32 base;
24 u32 size;
25 } send;
26
27 struct {
28 u32 base;
29 u32 size;
30
31 struct work_struct work;
32 wait_queue_head_t wait;
33 u32 process;
34 u32 message;
35 u32 data[2];
36 } recv;
37
38 int (*message)(struct nouveau_pwr *, u32[2], u32, u32, u32, u32);
39};
40
41static inline struct nouveau_pwr *
42nouveau_pwr(void *obj)
43{
44 return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_PWR];
45}
46
47#define nouveau_pwr_create(p, e, o, d) \
48 nouveau_pwr_create_((p), (e), (o), sizeof(**d), (void **)d)
49#define nouveau_pwr_destroy(p) \
50 nouveau_subdev_destroy(&(p)->base)
51#define nouveau_pwr_init(p) ({ \
52 struct nouveau_pwr *ppwr = (p); \
53 _nouveau_pwr_init(nv_object(ppwr)); \
54})
55#define nouveau_pwr_fini(p,s) ({ \
56 struct nouveau_pwr *ppwr = (p); \
57 _nouveau_pwr_fini(nv_object(ppwr), (s)); \
58})
59
60int nouveau_pwr_create_(struct nouveau_object *, struct nouveau_object *,
61 struct nouveau_oclass *, int, void **);
62#define _nouveau_pwr_dtor _nouveau_subdev_dtor
63int _nouveau_pwr_init(struct nouveau_object *);
64int _nouveau_pwr_fini(struct nouveau_object *, bool);
65
66extern struct nouveau_oclass nva3_pwr_oclass;
67extern struct nouveau_oclass nvc0_pwr_oclass;
68extern struct nouveau_oclass nvd0_pwr_oclass;
69extern struct nouveau_oclass nv108_pwr_oclass;
70
71/* interface to MEMX process running on PPWR */
72struct nouveau_memx;
73int nouveau_memx_init(struct nouveau_pwr *, struct nouveau_memx **);
74int nouveau_memx_fini(struct nouveau_memx **, bool exec);
75void nouveau_memx_wr32(struct nouveau_memx *, u32 addr, u32 data);
76void nouveau_memx_wait(struct nouveau_memx *,
77 u32 addr, u32 mask, u32 data, u32 nsec);
78void nouveau_memx_nsec(struct nouveau_memx *, u32 nsec);
79
80#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv98.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nv98.c
index 0b2ee25a6629..f8a6f18e2d34 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv98.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/mc/nv98.c
@@ -32,6 +32,7 @@ nv98_mc_intr[] = {
32 { 0x00004000, NVDEV_ENGINE_CRYPT }, /* NV84:NVA3 */ 32 { 0x00004000, NVDEV_ENGINE_CRYPT }, /* NV84:NVA3 */
33 { 0x00008000, NVDEV_ENGINE_BSP }, 33 { 0x00008000, NVDEV_ENGINE_BSP },
34 { 0x00020000, NVDEV_ENGINE_VP }, 34 { 0x00020000, NVDEV_ENGINE_VP },
35 { 0x00040000, NVDEV_SUBDEV_PWR }, /* NVA3:NVC0 */
35 { 0x00080000, NVDEV_SUBDEV_THERM }, /* NVA3:NVC0 */ 36 { 0x00080000, NVDEV_SUBDEV_THERM }, /* NVA3:NVC0 */
36 { 0x00100000, NVDEV_SUBDEV_TIMER }, 37 { 0x00100000, NVDEV_SUBDEV_TIMER },
37 { 0x00200000, NVDEV_SUBDEV_GPIO }, 38 { 0x00200000, NVDEV_SUBDEV_GPIO },
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c
index 33c386736cf9..c02b4763a2d5 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c
@@ -37,6 +37,7 @@ nvc0_mc_intr[] = {
37 { 0x00020000, NVDEV_ENGINE_VP }, 37 { 0x00020000, NVDEV_ENGINE_VP },
38 { 0x00100000, NVDEV_SUBDEV_TIMER }, 38 { 0x00100000, NVDEV_SUBDEV_TIMER },
39 { 0x00200000, NVDEV_SUBDEV_GPIO }, 39 { 0x00200000, NVDEV_SUBDEV_GPIO },
40 { 0x01000000, NVDEV_SUBDEV_PWR },
40 { 0x02000000, NVDEV_SUBDEV_LTCG }, 41 { 0x02000000, NVDEV_SUBDEV_LTCG },
41 { 0x04000000, NVDEV_ENGINE_DISP }, 42 { 0x04000000, NVDEV_ENGINE_DISP },
42 { 0x10000000, NVDEV_SUBDEV_BUS }, 43 { 0x10000000, NVDEV_SUBDEV_BUS },
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/base.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/base.c
new file mode 100644
index 000000000000..9908f1f05a00
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/base.c
@@ -0,0 +1,247 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <subdev/pwr.h>
26#include <subdev/timer.h>
27
28static int
29nouveau_pwr_send(struct nouveau_pwr *ppwr, u32 reply[2],
30 u32 process, u32 message, u32 data0, u32 data1)
31{
32 struct nouveau_subdev *subdev = nv_subdev(ppwr);
33 u32 addr;
34
35 /* we currently only support a single process at a time waiting
36 * on a synchronous reply, take the PPWR mutex and tell the
37 * receive handler what we're waiting for
38 */
39 if (reply) {
40 mutex_lock(&subdev->mutex);
41 ppwr->recv.message = message;
42 ppwr->recv.process = process;
43 }
44
45 /* wait for a free slot in the fifo */
46 addr = nv_rd32(ppwr, 0x10a4a0);
47 if (!nv_wait_ne(ppwr, 0x10a4b0, 0xffffffff, addr ^ 8))
48 return -EBUSY;
49
50 /* acquire data segment access */
51 do {
52 nv_wr32(ppwr, 0x10a580, 0x00000001);
53 } while (nv_rd32(ppwr, 0x10a580) != 0x00000001);
54
55 /* write the packet */
56 nv_wr32(ppwr, 0x10a1c0, 0x01000000 | (((addr & 0x07) << 4) +
57 ppwr->send.base));
58 nv_wr32(ppwr, 0x10a1c4, process);
59 nv_wr32(ppwr, 0x10a1c4, message);
60 nv_wr32(ppwr, 0x10a1c4, data0);
61 nv_wr32(ppwr, 0x10a1c4, data1);
62 nv_wr32(ppwr, 0x10a4a0, (addr + 1) & 0x0f);
63
64 /* release data segment access */
65 nv_wr32(ppwr, 0x10a580, 0x00000000);
66
67 /* wait for reply, if requested */
68 if (reply) {
69 wait_event(ppwr->recv.wait, (ppwr->recv.process == 0));
70 reply[0] = ppwr->recv.data[0];
71 reply[1] = ppwr->recv.data[1];
72 mutex_unlock(&subdev->mutex);
73 }
74
75 return 0;
76}
77
78static void
79nouveau_pwr_recv(struct work_struct *work)
80{
81 struct nouveau_pwr *ppwr =
82 container_of(work, struct nouveau_pwr, recv.work);
83 u32 process, message, data0, data1;
84
85 /* nothing to do if GET == PUT */
86 u32 addr = nv_rd32(ppwr, 0x10a4cc);
87 if (addr == nv_rd32(ppwr, 0x10a4c8))
88 return;
89
90 /* acquire data segment access */
91 do {
92 nv_wr32(ppwr, 0x10a580, 0x00000002);
93 } while (nv_rd32(ppwr, 0x10a580) != 0x00000002);
94
95 /* read the packet */
96 nv_wr32(ppwr, 0x10a1c0, 0x02000000 | (((addr & 0x07) << 4) +
97 ppwr->recv.base));
98 process = nv_rd32(ppwr, 0x10a1c4);
99 message = nv_rd32(ppwr, 0x10a1c4);
100 data0 = nv_rd32(ppwr, 0x10a1c4);
101 data1 = nv_rd32(ppwr, 0x10a1c4);
102 nv_wr32(ppwr, 0x10a4cc, (addr + 1) & 0x0f);
103
104 /* release data segment access */
105 nv_wr32(ppwr, 0x10a580, 0x00000000);
106
107 /* wake process if it's waiting on a synchronous reply */
108 if (ppwr->recv.process) {
109 if (process == ppwr->recv.process &&
110 message == ppwr->recv.message) {
111 ppwr->recv.data[0] = data0;
112 ppwr->recv.data[1] = data1;
113 ppwr->recv.process = 0;
114 wake_up(&ppwr->recv.wait);
115 return;
116 }
117 }
118
119 /* right now there's no other expected responses from the engine,
120 * so assume that any unexpected message is an error.
121 */
122 nv_warn(ppwr, "%c%c%c%c 0x%08x 0x%08x 0x%08x 0x%08x\n",
123 (char)((process & 0x000000ff) >> 0),
124 (char)((process & 0x0000ff00) >> 8),
125 (char)((process & 0x00ff0000) >> 16),
126 (char)((process & 0xff000000) >> 24),
127 process, message, data0, data1);
128}
129
130static void
131nouveau_pwr_intr(struct nouveau_subdev *subdev)
132{
133 struct nouveau_pwr *ppwr = (void *)subdev;
134 u32 disp = nv_rd32(ppwr, 0x10a01c);
135 u32 intr = nv_rd32(ppwr, 0x10a008) & disp & ~(disp >> 16);
136
137 if (intr & 0x00000020) {
138 u32 stat = nv_rd32(ppwr, 0x10a16c);
139 if (stat & 0x80000000) {
140 nv_error(ppwr, "UAS fault at 0x%06x addr 0x%08x\n",
141 stat & 0x00ffffff, nv_rd32(ppwr, 0x10a168));
142 nv_wr32(ppwr, 0x10a16c, 0x00000000);
143 intr &= ~0x00000020;
144 }
145 }
146
147 if (intr & 0x00000040) {
148 schedule_work(&ppwr->recv.work);
149 nv_wr32(ppwr, 0x10a004, 0x00000040);
150 intr &= ~0x00000040;
151 }
152
153 if (intr & 0x00000080) {
154 nv_info(ppwr, "wr32 0x%06x 0x%08x\n", nv_rd32(ppwr, 0x10a7a0),
155 nv_rd32(ppwr, 0x10a7a4));
156 nv_wr32(ppwr, 0x10a004, 0x00000080);
157 intr &= ~0x00000080;
158 }
159
160 if (intr) {
161 nv_error(ppwr, "intr 0x%08x\n", intr);
162 nv_wr32(ppwr, 0x10a004, intr);
163 }
164}
165
166int
167_nouveau_pwr_fini(struct nouveau_object *object, bool suspend)
168{
169 struct nouveau_pwr *ppwr = (void *)object;
170
171 nv_wr32(ppwr, 0x10a014, 0x00000060);
172 flush_work(&ppwr->recv.work);
173
174 return nouveau_subdev_fini(&ppwr->base, suspend);
175}
176
177int
178_nouveau_pwr_init(struct nouveau_object *object)
179{
180 struct nouveau_pwr *ppwr = (void *)object;
181 int ret, i;
182
183 ret = nouveau_subdev_init(&ppwr->base);
184 if (ret)
185 return ret;
186
187 nv_subdev(ppwr)->intr = nouveau_pwr_intr;
188 ppwr->message = nouveau_pwr_send;
189
190 /* prevent previous ucode from running, wait for idle, reset */
191 nv_wr32(ppwr, 0x10a014, 0x0000ffff); /* INTR_EN_CLR = ALL */
192 nv_wait(ppwr, 0x10a04c, 0xffffffff, 0x00000000);
193 nv_mask(ppwr, 0x000200, 0x00002000, 0x00000000);
194 nv_mask(ppwr, 0x000200, 0x00002000, 0x00002000);
195
196 /* upload data segment */
197 nv_wr32(ppwr, 0x10a1c0, 0x01000000);
198 for (i = 0; i < ppwr->data.size / 4; i++)
199 nv_wr32(ppwr, 0x10a1c4, ppwr->data.data[i]);
200
201 /* upload code segment */
202 nv_wr32(ppwr, 0x10a180, 0x01000000);
203 for (i = 0; i < ppwr->code.size / 4; i++) {
204 if ((i & 0x3f) == 0)
205 nv_wr32(ppwr, 0x10a188, i >> 6);
206 nv_wr32(ppwr, 0x10a184, ppwr->code.data[i]);
207 }
208
209 /* start it running */
210 nv_wr32(ppwr, 0x10a10c, 0x00000000);
211 nv_wr32(ppwr, 0x10a104, 0x00000000);
212 nv_wr32(ppwr, 0x10a100, 0x00000002);
213
214 /* wait for valid host->pwr ring configuration */
215 if (!nv_wait_ne(ppwr, 0x10a4d0, 0xffffffff, 0x00000000))
216 return -EBUSY;
217 ppwr->send.base = nv_rd32(ppwr, 0x10a4d0) & 0x0000ffff;
218 ppwr->send.size = nv_rd32(ppwr, 0x10a4d0) >> 16;
219
220 /* wait for valid pwr->host ring configuration */
221 if (!nv_wait_ne(ppwr, 0x10a4dc, 0xffffffff, 0x00000000))
222 return -EBUSY;
223 ppwr->recv.base = nv_rd32(ppwr, 0x10a4dc) & 0x0000ffff;
224 ppwr->recv.size = nv_rd32(ppwr, 0x10a4dc) >> 16;
225
226 nv_wr32(ppwr, 0x10a010, 0x000000e0);
227 return 0;
228}
229
230int
231nouveau_pwr_create_(struct nouveau_object *parent,
232 struct nouveau_object *engine,
233 struct nouveau_oclass *oclass, int length, void **pobject)
234{
235 struct nouveau_pwr *ppwr;
236 int ret;
237
238 ret = nouveau_subdev_create_(parent, engine, oclass, 0, "PPWR",
239 "pwr", length, pobject);
240 ppwr = *pobject;
241 if (ret)
242 return ret;
243
244 INIT_WORK(&ppwr->recv.work, nouveau_pwr_recv);
245 init_waitqueue_head(&ppwr->recv.wait);
246 return 0;
247}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/host.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/host.fuc
new file mode 100644
index 000000000000..2284ecb1c9b8
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/host.fuc
@@ -0,0 +1,151 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#ifdef INCLUDE_PROC
26process(PROC_HOST, #host_init, #host_recv)
27#endif
28
29/******************************************************************************
30 * HOST data segment
31 *****************************************************************************/
32#ifdef INCLUDE_DATA
33// HOST (R)FIFO packet format
34.equ #fifo_process 0x00
35.equ #fifo_message 0x04
36.equ #fifo_data0 0x08
37.equ #fifo_data1 0x0c
38
39// HOST HOST->PWR queue description
40.equ #fifo_qlen 4 // log2(size of queue entry in bytes)
41.equ #fifo_qnum 3 // log2(max number of entries in queue)
42.equ #fifo_qmaskb (1 << #fifo_qnum) // max number of entries in queue
43.equ #fifo_qmaskp (#fifo_qmaskb - 1)
44.equ #fifo_qmaskf ((#fifo_qmaskb << 1) - 1)
45.equ #fifo_qsize (1 << (#fifo_qlen + #fifo_qnum))
46fifo_queue: .skip 128 // #fifo_qsize
47
48// HOST PWR->HOST queue description
49.equ #rfifo_qlen 4 // log2(size of queue entry in bytes)
50.equ #rfifo_qnum 3 // log2(max number of entries in queue)
51.equ #rfifo_qmaskb (1 << #rfifo_qnum) // max number of entries in queue
52.equ #rfifo_qmaskp (#rfifo_qmaskb - 1)
53.equ #rfifo_qmaskf ((#rfifo_qmaskb << 1) - 1)
54.equ #rfifo_qsize (1 << (#rfifo_qlen + #rfifo_qnum))
55rfifo_queue: .skip 128 // #rfifo_qsize
56#endif
57
58/******************************************************************************
59 * HOST code segment
60 *****************************************************************************/
61#ifdef INCLUDE_CODE
62// HOST->PWR comms - dequeue message(s) for process(es) from FIFO
63//
64// $r15 - current (host)
65// $r0 - zero
66host_send:
67 nv_iord($r1, NV_PPWR_FIFO_GET(0))
68 nv_iord($r2, NV_PPWR_FIFO_PUT(0))
69 cmp b32 $r1 $r2
70 bra e #host_send_done
71 // calculate address of message
72 and $r14 $r1 #fifo_qmaskp
73 shl b32 $r14 $r14 #fifo_qlen
74 add b32 $r14 #fifo_queue
75
76 // read message data, and pass to appropriate process
77 ld b32 $r11 D[$r14 + #fifo_data1]
78 ld b32 $r12 D[$r14 + #fifo_data0]
79 ld b32 $r13 D[$r14 + #fifo_message]
80 ld b32 $r14 D[$r14 + #fifo_process]
81 call(send)
82
83 // increment GET
84 add b32 $r1 0x1
85 and $r14 $r1 #fifo_qmaskf
86 nv_iowr(NV_PPWR_FIFO_GET(0), $r1)
87 bra #host_send
88 host_send_done:
89 ret
90
91// PWR->HOST comms - enqueue message for HOST to RFIFO
92//
93// $r15 - current (host)
94// $r14 - process
95// $r13 - message
96// $r12 - message data 0
97// $r11 - message data 1
98// $r0 - zero
99host_recv:
100 // message from intr handler == HOST->PWR comms pending
101 mov $r1 (PROC_KERN & 0x0000ffff)
102 sethi $r1 (PROC_KERN & 0xffff0000)
103 cmp b32 $r14 $r1
104 bra e #host_send
105
106 // wait for space in RFIFO
107 host_recv_wait:
108 nv_iord($r1, NV_PPWR_RFIFO_GET)
109 nv_iord($r2, NV_PPWR_RFIFO_PUT)
110 xor $r1 #rfifo_qmaskb
111 cmp b32 $r1 $r2
112 bra e #host_recv_wait
113
114 and $r3 $r2 #rfifo_qmaskp
115 shl b32 $r3 #rfifo_qlen
116 add b32 $r3 #rfifo_queue
117
118 // enqueue message
119 st b32 D[$r3 + #fifo_data1] $r11
120 st b32 D[$r3 + #fifo_data0] $r12
121 st b32 D[$r3 + #fifo_message] $r13
122 st b32 D[$r3 + #fifo_process] $r14
123
124 add b32 $r2 0x1
125 and $r2 #rfifo_qmaskf
126 nv_iowr(NV_PPWR_RFIFO_PUT, $r2)
127
128 // notify host of pending message
129 mov $r2 NV_PPWR_INTR_TRIGGER_USER0
130 nv_iowr(NV_PPWR_INTR_TRIGGER, $r2)
131 ret
132
133// $r15 - current (host)
134// $r0 - zero
135host_init:
136 // store each fifo's base/size in H2D/D2H scratch regs
137 mov $r1 #fifo_qsize
138 shl b32 $r1 16
139 or $r1 #fifo_queue
140 nv_iowr(NV_PPWR_H2D, $r1);
141
142 mov $r1 #rfifo_qsize
143 shl b32 $r1 16
144 or $r1 #rfifo_queue
145 nv_iowr(NV_PPWR_D2H, $r1);
146
147 // enable fifo subintr for first fifo
148 mov $r1 1
149 nv_iowr(NV_PPWR_FIFO_INTR_EN, $r1)
150 ret
151#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/idle.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/idle.fuc
new file mode 100644
index 000000000000..98f1c3738b42
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/idle.fuc
@@ -0,0 +1,84 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#ifdef INCLUDE_PROC
26process(PROC_IDLE, #idle, #idle_recv)
27#endif
28
29/******************************************************************************
30 * IDLE data segment
31 *****************************************************************************/
32#ifdef INCLUDE_DATA
33#endif
34
35/******************************************************************************
36 * IDLE code segment
37 *****************************************************************************/
38#ifdef INCLUDE_CODE
39// description
40//
41// $r15 - current (idle)
42// $r14 - message
43// $r0 - zero
44idle_recv:
45 ret
46
47// description
48//
49// $r15 - current (idle)
50// $r0 - zero
51idle:
52 // set our "no interrupt has occurred during our execution" flag
53 bset $flags $p0
54
55 // count IDLE invocations for debugging purposes
56 nv_iord($r1, NV_PPWR_DSCRATCH(1))
57 add b32 $r1 1
58 nv_iowr(NV_PPWR_DSCRATCH(1), $r1)
59
60 // keep looping while there's pending messages for any process
61 idle_loop:
62 mov $r1 #proc_list_head
63 bclr $flags $p2
64 idle_proc:
65 // process the process' messages until there's none left
66 idle_proc_exec:
67 push $r1
68 mov b32 $r14 $r1
69 call(recv)
70 pop $r1
71 bra not $p1 #idle_proc_next
72 bset $flags $p2
73 bra #idle_proc_exec
74 // next process!
75 idle_proc_next:
76 add b32 $r1 #proc_size
77 cmp b32 $r1 $r15
78 bra ne #idle_proc
79 bra $p2 #idle_loop
80
81 // sleep if no interrupts have occurred
82 sleep $p0
83 bra #idle
84#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc
new file mode 100644
index 000000000000..0a7b05fa5c11
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc
@@ -0,0 +1,452 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25/******************************************************************************
26 * kernel data segment
27 *****************************************************************************/
28#ifdef INCLUDE_PROC
29proc_kern:
30process(PROC_KERN, 0, 0)
31proc_list_head:
32#endif
33
34#ifdef INCLUDE_DATA
35proc_list_tail:
36time_prev: .b32 0
37time_next: .b32 0
38#endif
39
40/******************************************************************************
41 * kernel code segment
42 *****************************************************************************/
43#ifdef INCLUDE_CODE
44 bra #init
45
46// read nv register
47//
48// $r15 - current
49// $r14 - addr
50// $r13 - data (return)
51// $r0 - zero
52rd32:
53 nv_iowr(NV_PPWR_MMIO_ADDR, $r14)
54 mov $r14 NV_PPWR_MMIO_CTRL_OP_RD
55 sethi $r14 NV_PPWR_MMIO_CTRL_TRIGGER
56 nv_iowr(NV_PPWR_MMIO_CTRL, $r14)
57 rd32_wait:
58 nv_iord($r14, NV_PPWR_MMIO_CTRL)
59 and $r14 NV_PPWR_MMIO_CTRL_STATUS
60 bra nz #rd32_wait
61 nv_iord($r13, NV_PPWR_MMIO_DATA)
62 ret
63
64// write nv register
65//
66// $r15 - current
67// $r14 - addr
68// $r13 - data
69// $r0 - zero
70wr32:
71 nv_iowr(NV_PPWR_MMIO_ADDR, $r14)
72 nv_iowr(NV_PPWR_MMIO_DATA, $r13)
73 mov $r14 NV_PPWR_MMIO_CTRL_OP_WR
74 or $r14 NV_PPWR_MMIO_CTRL_MASK_B32_0
75 sethi $r14 NV_PPWR_MMIO_CTRL_TRIGGER
76
77#ifdef NVKM_FALCON_MMIO_TRAP
78 mov $r8 NV_PPWR_INTR_TRIGGER_USER1
79 nv_iowr(NV_PPWR_INTR_TRIGGER, $r8)
80 wr32_host:
81 nv_iord($r8, NV_PPWR_INTR)
82 and $r8 NV_PPWR_INTR_USER1
83 bra nz #wr32_host
84#endif
85
86 nv_iowr(NV_PPWR_MMIO_CTRL, $r14)
87 wr32_wait:
88 nv_iord($r14, NV_PPWR_MMIO_CTRL)
89 and $r14 NV_PPWR_MMIO_CTRL_STATUS
90 bra nz #wr32_wait
91 ret
92
93// busy-wait for a period of time
94//
95// $r15 - current
96// $r14 - ns
97// $r0 - zero
98nsec:
99 nv_iord($r8, NV_PPWR_TIMER_LOW)
100 nsec_loop:
101 nv_iord($r9, NV_PPWR_TIMER_LOW)
102 sub b32 $r9 $r8
103 cmp b32 $r9 $r14
104 bra l #nsec_loop
105 ret
106
107// busy-wait for a period of time
108//
109// $r15 - current
110// $r14 - addr
111// $r13 - mask
112// $r12 - data
113// $r11 - timeout (ns)
114// $r0 - zero
115wait:
116 nv_iord($r8, NV_PPWR_TIMER_LOW)
117 wait_loop:
118 nv_rd32($r10, $r14)
119 and $r10 $r13
120 cmp b32 $r10 $r12
121 bra e #wait_done
122 nv_iord($r9, NV_PPWR_TIMER_LOW)
123 sub b32 $r9 $r8
124 cmp b32 $r9 $r11
125 bra l #wait_loop
126 wait_done:
127 ret
128
129// $r15 - current (kern)
130// $r14 - process
131// $r8 - NV_PPWR_INTR
132intr_watchdog:
133 // read process' timer status, skip if not enabled
134 ld b32 $r9 D[$r14 + #proc_time]
135 cmp b32 $r9 0
136 bra z #intr_watchdog_next_proc
137
138 // subtract last timer's value from process' timer,
139 // if it's <= 0 then the timer has expired
140 ld b32 $r10 D[$r0 + #time_prev]
141 sub b32 $r9 $r10
142 bra g #intr_watchdog_next_time
143 mov $r13 KMSG_ALARM
144 call(send_proc)
145 clear b32 $r9
146 bra #intr_watchdog_next_proc
147
148 // otherwise, update the next timer's value if this
149 // process' timer is the soonest
150 intr_watchdog_next_time:
151 // ... or if there's no next timer yet
152 ld b32 $r10 D[$r0 + #time_next]
153 cmp b32 $r10 0
154 bra z #intr_watchdog_next_time_set
155
156 cmp b32 $r9 $r10
157 bra g #intr_watchdog_next_proc
158 intr_watchdog_next_time_set:
159 st b32 D[$r0 + #time_next] $r9
160
161 // update process' timer status, and advance
162 intr_watchdog_next_proc:
163 st b32 D[$r14 + #proc_time] $r9
164 add b32 $r14 #proc_size
165 cmp b32 $r14 #proc_list_tail
166 bra ne #intr_watchdog
167 ret
168
169intr:
170 push $r0
171 clear b32 $r0
172 push $r8
173 push $r9
174 push $r10
175 push $r11
176 push $r12
177 push $r13
178 push $r14
179 push $r15
180 mov $r15 #proc_kern
181 mov $r8 $flags
182 push $r8
183
184 nv_iord($r8, NV_PPWR_DSCRATCH(0))
185 add b32 $r8 1
186 nv_iowr(NV_PPWR_DSCRATCH(0), $r8)
187
188 nv_iord($r8, NV_PPWR_INTR)
189 and $r9 $r8 NV_PPWR_INTR_WATCHDOG
190 bra z #intr_skip_watchdog
191 st b32 D[$r0 + #time_next] $r0
192 mov $r14 #proc_list_head
193 call(intr_watchdog)
194 ld b32 $r9 D[$r0 + #time_next]
195 cmp b32 $r9 0
196 bra z #intr_skip_watchdog
197 nv_iowr(NV_PPWR_WATCHDOG_TIME, $r9)
198 st b32 D[$r0 + #time_prev] $r9
199
200 intr_skip_watchdog:
201 and $r9 $r8 NV_PPWR_INTR_SUBINTR
202 bra z #intr_skip_subintr
203 nv_iord($r9, NV_PPWR_SUBINTR)
204 and $r10 $r9 NV_PPWR_SUBINTR_FIFO
205 bra z #intr_subintr_skip_fifo
206 nv_iord($r12, NV_PPWR_FIFO_INTR)
207 push $r12
208 mov $r14 (PROC_HOST & 0x0000ffff)
209 sethi $r14 (PROC_HOST & 0xffff0000)
210 mov $r13 KMSG_FIFO
211 call(send)
212 pop $r12
213 nv_iowr(NV_PPWR_FIFO_INTR, $r12)
214 intr_subintr_skip_fifo:
215 nv_iowr(NV_PPWR_SUBINTR, $r9)
216
217 intr_skip_subintr:
218 and $r9 $r8 NV_PPWR_INTR_PAUSE
219 bra z #intr_skip_pause
220 and $r10 0xffbf
221
222 intr_skip_pause:
223 and $r9 $r8 NV_PPWR_INTR_USER0
224 bra z #intr_skip_user0
225 and $r10 0xffbf
226
227 intr_skip_user0:
228 nv_iowr(NV_PPWR_INTR_ACK, $r8)
229 pop $r8
230 mov $flags $r8
231 pop $r15
232 pop $r14
233 pop $r13
234 pop $r12
235 pop $r11
236 pop $r10
237 pop $r9
238 pop $r8
239 pop $r0
240 bclr $flags $p0
241 iret
242
243// request the current process be sent a message after a timeout expires
244//
245// $r15 - current
246// $r14 - ticks
247// $r0 - zero
248timer:
249 // interrupts off to prevent racing with timer isr
250 bclr $flags ie0
251
252 // if current process already has a timer set, bail
253 ld b32 $r8 D[$r15 + #proc_time]
254 cmp b32 $r8 0
255 bra g #timer_done
256 st b32 D[$r15 + #proc_time] $r14
257
258 // halt watchdog timer temporarily and check for a pending
259 // interrupt. if there's one already pending, we can just
260 // bail since the timer isr will queue the next soonest
261 // right after it's done
262 nv_iowr(NV_PPWR_WATCHDOG_ENABLE, $r8)
263 nv_iord($r8, NV_PPWR_INTR)
264 and $r8 NV_PPWR_INTR_WATCHDOG
265 bra nz #timer_enable
266
267 // update the watchdog if this timer should expire first,
268 // or if there's no timeout already set
269 nv_iord($r8, NV_PPWR_WATCHDOG_TIME)
270 cmp b32 $r14 $r0
271 bra e #timer_reset
272 cmp b32 $r14 $r8
273 bra l #timer_done
274 timer_reset:
275 nv_iowr(NV_PPWR_WATCHDOG_TIME, $r14)
276 st b32 D[$r0 + #time_prev] $r14
277
278 // re-enable the watchdog timer
279 timer_enable:
280 mov $r8 1
281 nv_iowr(NV_PPWR_WATCHDOG_ENABLE, $r8)
282
283 // interrupts back on
284 timer_done:
285 bset $flags ie0
286 ret
287
288// send message to another process
289//
290// $r15 - current
291// $r14 - process
292// $r13 - message
293// $r12 - message data 0
294// $r11 - message data 1
295// $r0 - zero
296send_proc:
297 push $r8
298 push $r9
299 // check for space in queue
300 ld b32 $r8 D[$r14 + #proc_qget]
301 ld b32 $r9 D[$r14 + #proc_qput]
302 xor $r8 #proc_qmaskb
303 cmp b32 $r8 $r9
304 bra e #send_done
305
306 // enqueue message
307 and $r8 $r9 #proc_qmaskp
308 shl b32 $r8 $r8 #proc_qlen
309 add b32 $r8 #proc_queue
310 add b32 $r8 $r14
311
312 ld b32 $r10 D[$r15 + #proc_id]
313 st b32 D[$r8 + #msg_process] $r10
314 st b32 D[$r8 + #msg_message] $r13
315 st b32 D[$r8 + #msg_data0] $r12
316 st b32 D[$r8 + #msg_data1] $r11
317
318 // increment PUT
319 add b32 $r9 1
320 and $r9 #proc_qmaskf
321 st b32 D[$r14 + #proc_qput] $r9
322 bset $flags $p2
323 send_done:
324 pop $r9
325 pop $r8
326 ret
327
328// lookup process structure by its name
329//
330// $r15 - current
331// $r14 - process name
332// $r0 - zero
333//
334// $r14 - process
335// $p1 - success
336find:
337 push $r8
338 mov $r8 #proc_list_head
339 bset $flags $p1
340 find_loop:
341 ld b32 $r10 D[$r8 + #proc_id]
342 cmp b32 $r10 $r14
343 bra e #find_done
344 add b32 $r8 #proc_size
345 cmp b32 $r8 #proc_list_tail
346 bra ne #find_loop
347 bclr $flags $p1
348 find_done:
349 mov b32 $r14 $r8
350 pop $r8
351 ret
352
353// send message to another process
354//
355// $r15 - current
356// $r14 - process id
357// $r13 - message
358// $r12 - message data 0
359// $r11 - message data 1
360// $r0 - zero
361send:
362 call(find)
363 bra $p1 #send_proc
364 ret
365
366// process single message for a given process
367//
368// $r15 - current
369// $r14 - process
370// $r0 - zero
371recv:
372 ld b32 $r8 D[$r14 + #proc_qget]
373 ld b32 $r9 D[$r14 + #proc_qput]
374 bclr $flags $p1
375 cmp b32 $r8 $r9
376 bra e #recv_done
377 // dequeue message
378 and $r9 $r8 #proc_qmaskp
379 add b32 $r8 1
380 and $r8 #proc_qmaskf
381 st b32 D[$r14 + #proc_qget] $r8
382 ld b32 $r10 D[$r14 + #proc_recv]
383
384 push $r15
385 mov $r15 $flags
386 push $r15
387 mov b32 $r15 $r14
388
389 shl b32 $r9 $r9 #proc_qlen
390 add b32 $r14 $r9
391 add b32 $r14 #proc_queue
392 ld b32 $r11 D[$r14 + #msg_data1]
393 ld b32 $r12 D[$r14 + #msg_data0]
394 ld b32 $r13 D[$r14 + #msg_message]
395 ld b32 $r14 D[$r14 + #msg_process]
396
397 // process it
398 call $r10
399 pop $r15
400 mov $flags $r15
401 bset $flags $p1
402 pop $r15
403 recv_done:
404 ret
405
406init:
407 // setup stack
408 nv_iord($r1, NV_PPWR_CAPS)
409 extr $r1 $r1 9:17
410 shl b32 $r1 8
411 mov $sp $r1
412
413#ifdef NVKM_FALCON_MMIO_UAS
414 // somehow allows the magic "access mmio via D[]" stuff that's
415 // used by the nv_rd32/nv_wr32 macros to work
416 mov $r1 0x0010
417 sethi $r1 NV_PPWR_UAS_CONFIG_ENABLE
418 nv_iowrs(NV_PPWR_UAS_CONFIG, $r1)
419#endif
420
421 // route all interrupts except user0/1 and pause to fuc
422 mov $r1 0x00e0
423 sethi $r1 0x00000000
424 nv_iowr(NV_PPWR_INTR_ROUTE, $r1)
425
426 // enable watchdog and subintr intrs
427 mov $r1 NV_PPWR_INTR_EN_CLR_MASK
428 nv_iowr(NV_PPWR_INTR_EN_CLR, $r1)
429 mov $r1 NV_PPWR_INTR_EN_SET_WATCHDOG
430 or $r1 NV_PPWR_INTR_EN_SET_SUBINTR
431 nv_iowr(NV_PPWR_INTR_EN_SET, $r1)
432
433 // enable interrupts globally
434 mov $r1 #intr
435 sethi $r1 0x00000000
436 mov $iv0 $r1
437 bset $flags ie0
438
439 // enable watchdog timer
440 mov $r1 1
441 nv_iowr(NV_PPWR_WATCHDOG_ENABLE, $r1)
442
443 // bootstrap processes, idle process will be last, and not return
444 mov $r15 #proc_list_head
445 init_proc:
446 ld b32 $r1 D[$r15 + #proc_init]
447 cmp b32 $r1 0
448 bra z #init_proc
449 call $r1
450 add b32 $r15 #proc_size
451 bra #init_proc
452#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/macros.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/macros.fuc
new file mode 100644
index 000000000000..2a74ea907604
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/macros.fuc
@@ -0,0 +1,199 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#define GT215 0xa3
26#define GF100 0xc0
27#define GF119 0xd9
28#define GK208 0x108
29
30#include "os.h"
31
32// IO addresses
33#define NV_PPWR_INTR_TRIGGER 0x0000
34#define NV_PPWR_INTR_TRIGGER_USER1 0x00000080
35#define NV_PPWR_INTR_TRIGGER_USER0 0x00000040
36#define NV_PPWR_INTR_ACK 0x0004
37#define NV_PPWR_INTR_ACK_SUBINTR 0x00000800
38#define NV_PPWR_INTR_ACK_WATCHDOG 0x00000002
39#define NV_PPWR_INTR 0x0008
40#define NV_PPWR_INTR_SUBINTR 0x00000800
41#define NV_PPWR_INTR_USER1 0x00000080
42#define NV_PPWR_INTR_USER0 0x00000040
43#define NV_PPWR_INTR_PAUSE 0x00000020
44#define NV_PPWR_INTR_WATCHDOG 0x00000002
45#define NV_PPWR_INTR_EN_SET 0x0010
46#define NV_PPWR_INTR_EN_SET_SUBINTR 0x00000800
47#define NV_PPWR_INTR_EN_SET_WATCHDOG 0x00000002
48#define NV_PPWR_INTR_EN_CLR 0x0014
49#define NV_PPWR_INTR_EN_CLR_MASK /* fuck i hate envyas */ -1
50#define NV_PPWR_INTR_ROUTE 0x001c
51#define NV_PPWR_TIMER_LOW 0x002c
52#define NV_PPWR_WATCHDOG_TIME 0x0034
53#define NV_PPWR_WATCHDOG_ENABLE 0x0038
54#define NV_PPWR_CAPS 0x0108
55#define NV_PPWR_UAS_CONFIG 0x0164
56#define NV_PPWR_UAS_CONFIG_ENABLE 0x00010000
57#if NVKM_PPWR_CHIPSET >= GK208
58#define NV_PPWR_DSCRATCH(i) (4 * (i) + 0x0450)
59#endif
60#define NV_PPWR_FIFO_PUT(i) (4 * (i) + 0x04a0)
61#define NV_PPWR_FIFO_GET(i) (4 * (i) + 0x04b0)
62#define NV_PPWR_FIFO_INTR 0x04c0
63#define NV_PPWR_FIFO_INTR_EN 0x04c4
64#define NV_PPWR_RFIFO_PUT 0x04c8
65#define NV_PPWR_RFIFO_GET 0x04cc
66#define NV_PPWR_H2D 0x04d0
67#define NV_PPWR_D2H 0x04dc
68#if NVKM_PPWR_CHIPSET < GK208
69#define NV_PPWR_DSCRATCH(i) (4 * (i) + 0x05d0)
70#endif
71#define NV_PPWR_SUBINTR 0x0688
72#define NV_PPWR_SUBINTR_FIFO 0x00000002
73#define NV_PPWR_MMIO_ADDR 0x07a0
74#define NV_PPWR_MMIO_DATA 0x07a4
75#define NV_PPWR_MMIO_CTRL 0x07ac
76#define NV_PPWR_MMIO_CTRL_TRIGGER 0x00010000
77#define NV_PPWR_MMIO_CTRL_STATUS 0x00007000
78#define NV_PPWR_MMIO_CTRL_STATUS_IDLE 0x00000000
79#define NV_PPWR_MMIO_CTRL_MASK 0x000000f0
80#define NV_PPWR_MMIO_CTRL_MASK_B32_0 0x000000f0
81#define NV_PPWR_MMIO_CTRL_OP 0x00000003
82#define NV_PPWR_MMIO_CTRL_OP_RD 0x00000001
83#define NV_PPWR_MMIO_CTRL_OP_WR 0x00000002
84#define NV_PPWR_OUTPUT 0x07c0
85#define NV_PPWR_OUTPUT_FB_PAUSE 0x00000004
86#define NV_PPWR_OUTPUT_SET 0x07e0
87#define NV_PPWR_OUTPUT_SET_FB_PAUSE 0x00000004
88#define NV_PPWR_OUTPUT_CLR 0x07e4
89#define NV_PPWR_OUTPUT_CLR_FB_PAUSE 0x00000004
90
91// Inter-process message format
92.equ #msg_process 0x00 /* send() target, recv() sender */
93.equ #msg_message 0x04
94.equ #msg_data0 0x08
95.equ #msg_data1 0x0c
96
97// Kernel message IDs
98#define KMSG_FIFO 0x00000000
99#define KMSG_ALARM 0x00000001
100
101// Process message queue description
102.equ #proc_qlen 4 // log2(size of queue entry in bytes)
103.equ #proc_qnum 2 // log2(max number of entries in queue)
104.equ #proc_qmaskb (1 << #proc_qnum) // max number of entries in queue
105.equ #proc_qmaskp (#proc_qmaskb - 1)
106.equ #proc_qmaskf ((#proc_qmaskb << 1) - 1)
107.equ #proc_qsize (1 << (#proc_qlen + #proc_qnum))
108
109// Process table entry
110.equ #proc_id 0x00
111.equ #proc_init 0x04
112.equ #proc_recv 0x08
113.equ #proc_time 0x0c
114.equ #proc_qput 0x10
115.equ #proc_qget 0x14
116.equ #proc_queue 0x18
117.equ #proc_size (0x18 + #proc_qsize)
118
119#define process(id,init,recv) /*
120*/ .b32 id /*
121*/ .b32 init /*
122*/ .b32 recv /*
123*/ .b32 0 /*
124*/ .b32 0 /*
125*/ .b32 0 /*
126*/ .skip 64
127
128#ifndef NVKM_FALCON_UNSHIFTED_IO
129#define nv_iord(reg,ior) /*
130*/ mov reg ior /*
131*/ shl b32 reg 6 /*
132*/ iord reg I[reg + 0x000]
133#else
134#define nv_iord(reg,ior) /*
135*/ mov reg ior /*
136*/ iord reg I[reg + 0x000]
137#endif
138
139#ifndef NVKM_FALCON_UNSHIFTED_IO
140#define nv_iowr(ior,reg) /*
141*/ mov $r0 ior /*
142*/ shl b32 $r0 6 /*
143*/ iowr I[$r0 + 0x000] reg /*
144*/ clear b32 $r0
145#else
146#define nv_iowr(ior,reg) /*
147*/ mov $r0 ior /*
148*/ iowr I[$r0 + 0x000] reg /*
149*/ clear b32 $r0
150#endif
151
152#ifndef NVKM_FALCON_UNSHIFTED_IO
153#define nv_iowrs(ior,reg) /*
154*/ mov $r0 ior /*
155*/ shl b32 $r0 6 /*
156*/ iowrs I[$r0 + 0x000] reg /*
157*/ clear b32 $r0
158#else
159#define nv_iowrs(ior,reg) /*
160*/ mov $r0 ior /*
161*/ iowrs I[$r0 + 0x000] reg /*
162*/ clear b32 $r0
163#endif
164
165#define hash #
166#define fn(a) a
167#ifndef NVKM_FALCON_PC24
168#define call(a) call fn(hash)a
169#else
170#define call(a) lcall fn(hash)a
171#endif
172
173#ifndef NVKM_FALCON_MMIO_UAS
174#define nv_rd32(reg,addr) /*
175*/ mov b32 $r14 addr /*
176*/ call(rd32) /*
177*/ mov b32 reg $r13
178#else
179#define nv_rd32(reg,addr) /*
180*/ sethi $r0 0x14000000 /*
181*/ or $r0 addr /*
182*/ ld b32 reg D[$r0] /*
183*/ clear b32 $r0
184#endif
185
186#if !defined(NVKM_FALCON_MMIO_UAS) || defined(NVKM_FALCON_MMIO_TRAP)
187#define nv_wr32(addr,reg) /*
188*/ push addr /*
189*/ push reg /*
190*/ pop $r13 /*
191*/ pop $r14 /*
192*/ call(wr32) /*
193#else
194#define nv_wr32(addr,reg) /*
195*/ sethi $r0 0x14000000 /*
196*/ or $r0 addr /*
197*/ st b32 D[$r0] reg /*
198*/ clear b32 $r0
199#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc
new file mode 100644
index 000000000000..d43741eccb11
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc
@@ -0,0 +1,219 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#ifdef INCLUDE_PROC
26process(PROC_MEMX, #memx_init, #memx_recv)
27#endif
28
29/******************************************************************************
30 * MEMX data segment
31 *****************************************************************************/
32#ifdef INCLUDE_DATA
33.equ #memx_opcode 0
34.equ #memx_header 2
35.equ #memx_length 4
36.equ #memx_func 8
37
38#define handler(cmd,hdr,len,func) /*
39*/ .b16 MEMX_##cmd /*
40*/ .b16 hdr /*
41*/ .b16 len /*
42*/ .b16 0 /*
43*/ .b32 func
44
45memx_func_head:
46handler(ENTER , 0x0001, 0x0000, #memx_func_enter)
47memx_func_next:
48handler(LEAVE , 0x0000, 0x0000, #memx_func_leave)
49handler(WR32 , 0x0000, 0x0002, #memx_func_wr32)
50handler(WAIT , 0x0004, 0x0000, #memx_func_wait)
51handler(DELAY , 0x0001, 0x0000, #memx_func_delay)
52memx_func_tail:
53
54.equ #memx_func_size #memx_func_next - #memx_func_head
55.equ #memx_func_num (#memx_func_tail - #memx_func_head) / #memx_func_size
56
57memx_data_head:
58.skip 0x0800
59memx_data_tail:
60#endif
61
62/******************************************************************************
63 * MEMX code segment
64 *****************************************************************************/
65#ifdef INCLUDE_CODE
66// description
67//
68// $r15 - current (memx)
69// $r4 - packet length
70// +00: bitmask of heads to wait for vblank on
71// $r3 - opcode desciption
72// $r0 - zero
73memx_func_enter:
74 mov $r6 NV_PPWR_OUTPUT_SET_FB_PAUSE
75 nv_iowr(NV_PPWR_OUTPUT_SET, $r6)
76 memx_func_enter_wait:
77 nv_iord($r6, NV_PPWR_OUTPUT)
78 and $r6 NV_PPWR_OUTPUT_FB_PAUSE
79 bra z #memx_func_enter_wait
80 //XXX: TODO
81 ld b32 $r6 D[$r1 + 0x00]
82 add b32 $r1 0x04
83 ret
84
85// description
86//
87// $r15 - current (memx)
88// $r4 - packet length
89// $r3 - opcode desciption
90// $r0 - zero
91memx_func_leave:
92 mov $r6 NV_PPWR_OUTPUT_CLR_FB_PAUSE
93 nv_iowr(NV_PPWR_OUTPUT_CLR, $r6)
94 memx_func_leave_wait:
95 nv_iord($r6, NV_PPWR_OUTPUT)
96 and $r6 NV_PPWR_OUTPUT_FB_PAUSE
97 bra nz #memx_func_leave_wait
98 ret
99
100// description
101//
102// $r15 - current (memx)
103// $r4 - packet length
104// +00*n: addr
105// +04*n: data
106// $r3 - opcode desciption
107// $r0 - zero
108memx_func_wr32:
109 ld b32 $r6 D[$r1 + 0x00]
110 ld b32 $r5 D[$r1 + 0x04]
111 add b32 $r1 0x08
112 nv_wr32($r6, $r5)
113 sub b32 $r4 0x02
114 bra nz #memx_func_wr32
115 ret
116
117// description
118//
119// $r15 - current (memx)
120// $r4 - packet length
121// +00: addr
122// +04: mask
123// +08: data
124// +0c: timeout (ns)
125// $r3 - opcode desciption
126// $r0 - zero
127memx_func_wait:
128 nv_iord($r8, NV_PPWR_TIMER_LOW)
129 ld b32 $r14 D[$r1 + 0x00]
130 ld b32 $r13 D[$r1 + 0x04]
131 ld b32 $r12 D[$r1 + 0x08]
132 ld b32 $r11 D[$r1 + 0x0c]
133 add b32 $r1 0x10
134 call(wait)
135 ret
136
137// description
138//
139// $r15 - current (memx)
140// $r4 - packet length
141// +00: time (ns)
142// $r3 - opcode desciption
143// $r0 - zero
144memx_func_delay:
145 ld b32 $r14 D[$r1 + 0x00]
146 add b32 $r1 0x04
147 call(nsec)
148 ret
149
150// description
151//
152// $r15 - current (memx)
153// $r14 - sender process name
154// $r13 - message (exec)
155// $r12 - head of script
156// $r11 - tail of script
157// $r0 - zero
158memx_exec:
159 push $r14
160 push $r13
161 mov b32 $r1 $r12
162 mov b32 $r2 $r11
163 memx_exec_next:
164 // fetch the packet header, and locate opcode info
165 ld b32 $r3 D[$r1]
166 add b32 $r1 4
167 shr b32 $r4 $r3 16
168 mulu $r3 #memx_func_size
169
170 // execute the opcode handler
171 ld b32 $r5 D[$r3 + #memx_func_head + #memx_func]
172 call $r5
173
174 // keep going, if we haven't reached the end
175 cmp b32 $r1 $r2
176 bra l #memx_exec_next
177
178 // send completion reply
179 pop $r13
180 pop $r14
181 call(send)
182 ret
183
184// description
185//
186// $r15 - current (memx)
187// $r14 - sender process name
188// $r13 - message
189// $r12 - data0
190// $r11 - data1
191// $r0 - zero
192memx_info:
193 mov $r12 #memx_data_head
194 mov $r11 #memx_data_tail - #memx_data_head
195 call(send)
196 ret
197
198// description
199//
200// $r15 - current (memx)
201// $r14 - sender process name
202// $r13 - message
203// $r12 - data0
204// $r11 - data1
205// $r0 - zero
206memx_recv:
207 cmp b32 $r13 MEMX_MSG_EXEC
208 bra e #memx_exec
209 cmp b32 $r13 MEMX_MSG_INFO
210 bra e #memx_info
211 ret
212
213// description
214//
215// $r15 - current (memx)
216// $r0 - zero
217memx_init:
218 ret
219#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc
new file mode 100644
index 000000000000..947be536daef
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc
@@ -0,0 +1,63 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#define NVKM_PPWR_CHIPSET GK208
26
27#define NVKM_FALCON_PC24
28#define NVKM_FALCON_UNSHIFTED_IO
29//#define NVKM_FALCON_MMIO_UAS
30//#define NVKM_FALCON_MMIO_TRAP
31
32#include "macros.fuc"
33
34.section #nv108_pwr_data
35#define INCLUDE_PROC
36#include "kernel.fuc"
37#include "host.fuc"
38#include "memx.fuc"
39#include "perf.fuc"
40#include "test.fuc"
41#include "idle.fuc"
42#undef INCLUDE_PROC
43
44#define INCLUDE_DATA
45#include "kernel.fuc"
46#include "host.fuc"
47#include "memx.fuc"
48#include "perf.fuc"
49#include "test.fuc"
50#include "idle.fuc"
51#undef INCLUDE_DATA
52.align 256
53
54.section #nv108_pwr_code
55#define INCLUDE_CODE
56#include "kernel.fuc"
57#include "host.fuc"
58#include "memx.fuc"
59#include "perf.fuc"
60#include "test.fuc"
61#include "idle.fuc"
62#undef INCLUDE_CODE
63.align 256
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h
new file mode 100644
index 000000000000..9342e2d7d3b7
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h
@@ -0,0 +1,1165 @@
1uint32_t nv108_pwr_data[] = {
2/* 0x0000: proc_kern */
3 0x52544e49,
4 0x00000000,
5 0x00000000,
6 0x00000000,
7 0x00000000,
8 0x00000000,
9 0x00000000,
10 0x00000000,
11 0x00000000,
12 0x00000000,
13 0x00000000,
14 0x00000000,
15 0x00000000,
16 0x00000000,
17 0x00000000,
18 0x00000000,
19 0x00000000,
20 0x00000000,
21 0x00000000,
22 0x00000000,
23 0x00000000,
24 0x00000000,
25/* 0x0058: proc_list_head */
26 0x54534f48,
27 0x00000379,
28 0x0000032a,
29 0x00000000,
30 0x00000000,
31 0x00000000,
32 0x00000000,
33 0x00000000,
34 0x00000000,
35 0x00000000,
36 0x00000000,
37 0x00000000,
38 0x00000000,
39 0x00000000,
40 0x00000000,
41 0x00000000,
42 0x00000000,
43 0x00000000,
44 0x00000000,
45 0x00000000,
46 0x00000000,
47 0x00000000,
48 0x584d454d,
49 0x0000046f,
50 0x00000461,
51 0x00000000,
52 0x00000000,
53 0x00000000,
54 0x00000000,
55 0x00000000,
56 0x00000000,
57 0x00000000,
58 0x00000000,
59 0x00000000,
60 0x00000000,
61 0x00000000,
62 0x00000000,
63 0x00000000,
64 0x00000000,
65 0x00000000,
66 0x00000000,
67 0x00000000,
68 0x00000000,
69 0x00000000,
70 0x46524550,
71 0x00000473,
72 0x00000471,
73 0x00000000,
74 0x00000000,
75 0x00000000,
76 0x00000000,
77 0x00000000,
78 0x00000000,
79 0x00000000,
80 0x00000000,
81 0x00000000,
82 0x00000000,
83 0x00000000,
84 0x00000000,
85 0x00000000,
86 0x00000000,
87 0x00000000,
88 0x00000000,
89 0x00000000,
90 0x00000000,
91 0x00000000,
92 0x54534554,
93 0x00000494,
94 0x00000475,
95 0x00000000,
96 0x00000000,
97 0x00000000,
98 0x00000000,
99 0x00000000,
100 0x00000000,
101 0x00000000,
102 0x00000000,
103 0x00000000,
104 0x00000000,
105 0x00000000,
106 0x00000000,
107 0x00000000,
108 0x00000000,
109 0x00000000,
110 0x00000000,
111 0x00000000,
112 0x00000000,
113 0x00000000,
114 0x454c4449,
115 0x0000049f,
116 0x0000049d,
117 0x00000000,
118 0x00000000,
119 0x00000000,
120 0x00000000,
121 0x00000000,
122 0x00000000,
123 0x00000000,
124 0x00000000,
125 0x00000000,
126 0x00000000,
127 0x00000000,
128 0x00000000,
129 0x00000000,
130 0x00000000,
131 0x00000000,
132 0x00000000,
133 0x00000000,
134 0x00000000,
135 0x00000000,
136/* 0x0210: proc_list_tail */
137/* 0x0210: time_prev */
138 0x00000000,
139/* 0x0214: time_next */
140 0x00000000,
141/* 0x0218: fifo_queue */
142 0x00000000,
143 0x00000000,
144 0x00000000,
145 0x00000000,
146 0x00000000,
147 0x00000000,
148 0x00000000,
149 0x00000000,
150 0x00000000,
151 0x00000000,
152 0x00000000,
153 0x00000000,
154 0x00000000,
155 0x00000000,
156 0x00000000,
157 0x00000000,
158 0x00000000,
159 0x00000000,
160 0x00000000,
161 0x00000000,
162 0x00000000,
163 0x00000000,
164 0x00000000,
165 0x00000000,
166 0x00000000,
167 0x00000000,
168 0x00000000,
169 0x00000000,
170 0x00000000,
171 0x00000000,
172 0x00000000,
173 0x00000000,
174/* 0x0298: rfifo_queue */
175 0x00000000,
176 0x00000000,
177 0x00000000,
178 0x00000000,
179 0x00000000,
180 0x00000000,
181 0x00000000,
182 0x00000000,
183 0x00000000,
184 0x00000000,
185 0x00000000,
186 0x00000000,
187 0x00000000,
188 0x00000000,
189 0x00000000,
190 0x00000000,
191 0x00000000,
192 0x00000000,
193 0x00000000,
194 0x00000000,
195 0x00000000,
196 0x00000000,
197 0x00000000,
198 0x00000000,
199 0x00000000,
200 0x00000000,
201 0x00000000,
202 0x00000000,
203 0x00000000,
204 0x00000000,
205 0x00000000,
206 0x00000000,
207/* 0x0318: memx_func_head */
208 0x00010000,
209 0x00000000,
210 0x000003a9,
211/* 0x0324: memx_func_next */
212 0x00000001,
213 0x00000000,
214 0x000003c7,
215 0x00000002,
216 0x00000002,
217 0x000003df,
218 0x00040003,
219 0x00000000,
220 0x00000407,
221 0x00010004,
222 0x00000000,
223 0x00000421,
224/* 0x0354: memx_func_tail */
225/* 0x0354: memx_data_head */
226 0x00000000,
227 0x00000000,
228 0x00000000,
229 0x00000000,
230 0x00000000,
231 0x00000000,
232 0x00000000,
233 0x00000000,
234 0x00000000,
235 0x00000000,
236 0x00000000,
237 0x00000000,
238 0x00000000,
239 0x00000000,
240 0x00000000,
241 0x00000000,
242 0x00000000,
243 0x00000000,
244 0x00000000,
245 0x00000000,
246 0x00000000,
247 0x00000000,
248 0x00000000,
249 0x00000000,
250 0x00000000,
251 0x00000000,
252 0x00000000,
253 0x00000000,
254 0x00000000,
255 0x00000000,
256 0x00000000,
257 0x00000000,
258 0x00000000,
259 0x00000000,
260 0x00000000,
261 0x00000000,
262 0x00000000,
263 0x00000000,
264 0x00000000,
265 0x00000000,
266 0x00000000,
267 0x00000000,
268 0x00000000,
269 0x00000000,
270 0x00000000,
271 0x00000000,
272 0x00000000,
273 0x00000000,
274 0x00000000,
275 0x00000000,
276 0x00000000,
277 0x00000000,
278 0x00000000,
279 0x00000000,
280 0x00000000,
281 0x00000000,
282 0x00000000,
283 0x00000000,
284 0x00000000,
285 0x00000000,
286 0x00000000,
287 0x00000000,
288 0x00000000,
289 0x00000000,
290 0x00000000,
291 0x00000000,
292 0x00000000,
293 0x00000000,
294 0x00000000,
295 0x00000000,
296 0x00000000,
297 0x00000000,
298 0x00000000,
299 0x00000000,
300 0x00000000,
301 0x00000000,
302 0x00000000,
303 0x00000000,
304 0x00000000,
305 0x00000000,
306 0x00000000,
307 0x00000000,
308 0x00000000,
309 0x00000000,
310 0x00000000,
311 0x00000000,
312 0x00000000,
313 0x00000000,
314 0x00000000,
315 0x00000000,
316 0x00000000,
317 0x00000000,
318 0x00000000,
319 0x00000000,
320 0x00000000,
321 0x00000000,
322 0x00000000,
323 0x00000000,
324 0x00000000,
325 0x00000000,
326 0x00000000,
327 0x00000000,
328 0x00000000,
329 0x00000000,
330 0x00000000,
331 0x00000000,
332 0x00000000,
333 0x00000000,
334 0x00000000,
335 0x00000000,
336 0x00000000,
337 0x00000000,
338 0x00000000,
339 0x00000000,
340 0x00000000,
341 0x00000000,
342 0x00000000,
343 0x00000000,
344 0x00000000,
345 0x00000000,
346 0x00000000,
347 0x00000000,
348 0x00000000,
349 0x00000000,
350 0x00000000,
351 0x00000000,
352 0x00000000,
353 0x00000000,
354 0x00000000,
355 0x00000000,
356 0x00000000,
357 0x00000000,
358 0x00000000,
359 0x00000000,
360 0x00000000,
361 0x00000000,
362 0x00000000,
363 0x00000000,
364 0x00000000,
365 0x00000000,
366 0x00000000,
367 0x00000000,
368 0x00000000,
369 0x00000000,
370 0x00000000,
371 0x00000000,
372 0x00000000,
373 0x00000000,
374 0x00000000,
375 0x00000000,
376 0x00000000,
377 0x00000000,
378 0x00000000,
379 0x00000000,
380 0x00000000,
381 0x00000000,
382 0x00000000,
383 0x00000000,
384 0x00000000,
385 0x00000000,
386 0x00000000,
387 0x00000000,
388 0x00000000,
389 0x00000000,
390 0x00000000,
391 0x00000000,
392 0x00000000,
393 0x00000000,
394 0x00000000,
395 0x00000000,
396 0x00000000,
397 0x00000000,
398 0x00000000,
399 0x00000000,
400 0x00000000,
401 0x00000000,
402 0x00000000,
403 0x00000000,
404 0x00000000,
405 0x00000000,
406 0x00000000,
407 0x00000000,
408 0x00000000,
409 0x00000000,
410 0x00000000,
411 0x00000000,
412 0x00000000,
413 0x00000000,
414 0x00000000,
415 0x00000000,
416 0x00000000,
417 0x00000000,
418 0x00000000,
419 0x00000000,
420 0x00000000,
421 0x00000000,
422 0x00000000,
423 0x00000000,
424 0x00000000,
425 0x00000000,
426 0x00000000,
427 0x00000000,
428 0x00000000,
429 0x00000000,
430 0x00000000,
431 0x00000000,
432 0x00000000,
433 0x00000000,
434 0x00000000,
435 0x00000000,
436 0x00000000,
437 0x00000000,
438 0x00000000,
439 0x00000000,
440 0x00000000,
441 0x00000000,
442 0x00000000,
443 0x00000000,
444 0x00000000,
445 0x00000000,
446 0x00000000,
447 0x00000000,
448 0x00000000,
449 0x00000000,
450 0x00000000,
451 0x00000000,
452 0x00000000,
453 0x00000000,
454 0x00000000,
455 0x00000000,
456 0x00000000,
457 0x00000000,
458 0x00000000,
459 0x00000000,
460 0x00000000,
461 0x00000000,
462 0x00000000,
463 0x00000000,
464 0x00000000,
465 0x00000000,
466 0x00000000,
467 0x00000000,
468 0x00000000,
469 0x00000000,
470 0x00000000,
471 0x00000000,
472 0x00000000,
473 0x00000000,
474 0x00000000,
475 0x00000000,
476 0x00000000,
477 0x00000000,
478 0x00000000,
479 0x00000000,
480 0x00000000,
481 0x00000000,
482 0x00000000,
483 0x00000000,
484 0x00000000,
485 0x00000000,
486 0x00000000,
487 0x00000000,
488 0x00000000,
489 0x00000000,
490 0x00000000,
491 0x00000000,
492 0x00000000,
493 0x00000000,
494 0x00000000,
495 0x00000000,
496 0x00000000,
497 0x00000000,
498 0x00000000,
499 0x00000000,
500 0x00000000,
501 0x00000000,
502 0x00000000,
503 0x00000000,
504 0x00000000,
505 0x00000000,
506 0x00000000,
507 0x00000000,
508 0x00000000,
509 0x00000000,
510 0x00000000,
511 0x00000000,
512 0x00000000,
513 0x00000000,
514 0x00000000,
515 0x00000000,
516 0x00000000,
517 0x00000000,
518 0x00000000,
519 0x00000000,
520 0x00000000,
521 0x00000000,
522 0x00000000,
523 0x00000000,
524 0x00000000,
525 0x00000000,
526 0x00000000,
527 0x00000000,
528 0x00000000,
529 0x00000000,
530 0x00000000,
531 0x00000000,
532 0x00000000,
533 0x00000000,
534 0x00000000,
535 0x00000000,
536 0x00000000,
537 0x00000000,
538 0x00000000,
539 0x00000000,
540 0x00000000,
541 0x00000000,
542 0x00000000,
543 0x00000000,
544 0x00000000,
545 0x00000000,
546 0x00000000,
547 0x00000000,
548 0x00000000,
549 0x00000000,
550 0x00000000,
551 0x00000000,
552 0x00000000,
553 0x00000000,
554 0x00000000,
555 0x00000000,
556 0x00000000,
557 0x00000000,
558 0x00000000,
559 0x00000000,
560 0x00000000,
561 0x00000000,
562 0x00000000,
563 0x00000000,
564 0x00000000,
565 0x00000000,
566 0x00000000,
567 0x00000000,
568 0x00000000,
569 0x00000000,
570 0x00000000,
571 0x00000000,
572 0x00000000,
573 0x00000000,
574 0x00000000,
575 0x00000000,
576 0x00000000,
577 0x00000000,
578 0x00000000,
579 0x00000000,
580 0x00000000,
581 0x00000000,
582 0x00000000,
583 0x00000000,
584 0x00000000,
585 0x00000000,
586 0x00000000,
587 0x00000000,
588 0x00000000,
589 0x00000000,
590 0x00000000,
591 0x00000000,
592 0x00000000,
593 0x00000000,
594 0x00000000,
595 0x00000000,
596 0x00000000,
597 0x00000000,
598 0x00000000,
599 0x00000000,
600 0x00000000,
601 0x00000000,
602 0x00000000,
603 0x00000000,
604 0x00000000,
605 0x00000000,
606 0x00000000,
607 0x00000000,
608 0x00000000,
609 0x00000000,
610 0x00000000,
611 0x00000000,
612 0x00000000,
613 0x00000000,
614 0x00000000,
615 0x00000000,
616 0x00000000,
617 0x00000000,
618 0x00000000,
619 0x00000000,
620 0x00000000,
621 0x00000000,
622 0x00000000,
623 0x00000000,
624 0x00000000,
625 0x00000000,
626 0x00000000,
627 0x00000000,
628 0x00000000,
629 0x00000000,
630 0x00000000,
631 0x00000000,
632 0x00000000,
633 0x00000000,
634 0x00000000,
635 0x00000000,
636 0x00000000,
637 0x00000000,
638 0x00000000,
639 0x00000000,
640 0x00000000,
641 0x00000000,
642 0x00000000,
643 0x00000000,
644 0x00000000,
645 0x00000000,
646 0x00000000,
647 0x00000000,
648 0x00000000,
649 0x00000000,
650 0x00000000,
651 0x00000000,
652 0x00000000,
653 0x00000000,
654 0x00000000,
655 0x00000000,
656 0x00000000,
657 0x00000000,
658 0x00000000,
659 0x00000000,
660 0x00000000,
661 0x00000000,
662 0x00000000,
663 0x00000000,
664 0x00000000,
665 0x00000000,
666 0x00000000,
667 0x00000000,
668 0x00000000,
669 0x00000000,
670 0x00000000,
671 0x00000000,
672 0x00000000,
673 0x00000000,
674 0x00000000,
675 0x00000000,
676 0x00000000,
677 0x00000000,
678 0x00000000,
679 0x00000000,
680 0x00000000,
681 0x00000000,
682 0x00000000,
683 0x00000000,
684 0x00000000,
685 0x00000000,
686 0x00000000,
687 0x00000000,
688 0x00000000,
689 0x00000000,
690 0x00000000,
691 0x00000000,
692 0x00000000,
693 0x00000000,
694 0x00000000,
695 0x00000000,
696 0x00000000,
697 0x00000000,
698 0x00000000,
699 0x00000000,
700 0x00000000,
701 0x00000000,
702 0x00000000,
703 0x00000000,
704 0x00000000,
705 0x00000000,
706 0x00000000,
707 0x00000000,
708 0x00000000,
709 0x00000000,
710 0x00000000,
711 0x00000000,
712 0x00000000,
713 0x00000000,
714 0x00000000,
715 0x00000000,
716 0x00000000,
717 0x00000000,
718 0x00000000,
719 0x00000000,
720 0x00000000,
721 0x00000000,
722 0x00000000,
723 0x00000000,
724 0x00000000,
725 0x00000000,
726 0x00000000,
727 0x00000000,
728 0x00000000,
729 0x00000000,
730 0x00000000,
731 0x00000000,
732 0x00000000,
733 0x00000000,
734 0x00000000,
735 0x00000000,
736 0x00000000,
737 0x00000000,
738/* 0x0b54: memx_data_tail */
739 0x00000000,
740 0x00000000,
741 0x00000000,
742 0x00000000,
743 0x00000000,
744 0x00000000,
745 0x00000000,
746 0x00000000,
747 0x00000000,
748 0x00000000,
749 0x00000000,
750 0x00000000,
751 0x00000000,
752 0x00000000,
753 0x00000000,
754 0x00000000,
755 0x00000000,
756 0x00000000,
757 0x00000000,
758 0x00000000,
759 0x00000000,
760 0x00000000,
761 0x00000000,
762 0x00000000,
763 0x00000000,
764 0x00000000,
765 0x00000000,
766 0x00000000,
767 0x00000000,
768 0x00000000,
769 0x00000000,
770 0x00000000,
771 0x00000000,
772 0x00000000,
773 0x00000000,
774 0x00000000,
775 0x00000000,
776 0x00000000,
777 0x00000000,
778 0x00000000,
779 0x00000000,
780 0x00000000,
781 0x00000000,
782};
783
784uint32_t nv108_pwr_code[] = {
785 0x02910ef5,
786/* 0x0004: rd32 */
787 0xf607a040,
788 0x04bd000e,
789 0xe3f0010e,
790 0x07ac4001,
791 0xbd000ef6,
792/* 0x0019: rd32_wait */
793 0x07ac4e04,
794 0xf100eecf,
795 0xf47000e4,
796 0xa44df61b,
797 0x00ddcf07,
798/* 0x002e: wr32 */
799 0xa04000f8,
800 0x000ef607,
801 0xa44004bd,
802 0x000df607,
803 0x020e04bd,
804 0xf0f0e5f0,
805 0xac4001e3,
806 0x000ef607,
807/* 0x004e: wr32_wait */
808 0xac4e04bd,
809 0x00eecf07,
810 0x7000e4f1,
811 0xf8f61bf4,
812/* 0x005d: nsec */
813 0xcf2c0800,
814/* 0x0062: nsec_loop */
815 0x2c090088,
816 0xbb0099cf,
817 0x9ea60298,
818 0xf8f61ef4,
819/* 0x0071: wait */
820 0xcf2c0800,
821/* 0x0076: wait_loop */
822 0xeeb20088,
823 0x0000047e,
824 0xadfddab2,
825 0xf4aca604,
826 0x2c09100b,
827 0xbb0099cf,
828 0x9ba60298,
829/* 0x0093: wait_done */
830 0xf8e61ef4,
831/* 0x0095: intr_watchdog */
832 0x03e99800,
833 0xf40096b0,
834 0x0a98280b,
835 0x029abb84,
836 0x0d0e1cf4,
837 0x01de7e01,
838 0xf494bd00,
839/* 0x00b2: intr_watchdog_next_time */
840 0x0a98140e,
841 0x00a6b085,
842 0xa6080bf4,
843 0x061cf49a,
844/* 0x00c0: intr_watchdog_next_time_set */
845/* 0x00c3: intr_watchdog_next_proc */
846 0xb58509b5,
847 0xe0b603e9,
848 0x10e6b158,
849 0xc81bf402,
850/* 0x00d2: intr */
851 0x00f900f8,
852 0x80f904bd,
853 0xa0f990f9,
854 0xc0f9b0f9,
855 0xe0f9d0f9,
856 0x000ff0f9,
857 0xf90188fe,
858 0x04504880,
859 0xb60088cf,
860 0x50400180,
861 0x0008f604,
862 0x080804bd,
863 0xc40088cf,
864 0x0bf40289,
865 0x8500b51f,
866 0x957e580e,
867 0x09980000,
868 0x0096b085,
869 0x000d0bf4,
870 0x0009f634,
871 0x09b504bd,
872/* 0x0125: intr_skip_watchdog */
873 0x0089e484,
874 0x360bf408,
875 0xcf068849,
876 0x9ac40099,
877 0x220bf402,
878 0xcf04c04c,
879 0xc0f900cc,
880 0xf14f484e,
881 0x0d5453e3,
882 0x023f7e00,
883 0x40c0fc00,
884 0x0cf604c0,
885/* 0x0157: intr_subintr_skip_fifo */
886 0x4004bd00,
887 0x09f60688,
888/* 0x015f: intr_skip_subintr */
889 0xc404bd00,
890 0x0bf42089,
891 0xbfa4f107,
892/* 0x0169: intr_skip_pause */
893 0x4089c4ff,
894 0xf1070bf4,
895/* 0x0173: intr_skip_user0 */
896 0x00ffbfa4,
897 0x0008f604,
898 0x80fc04bd,
899 0xfc0088fe,
900 0xfce0fcf0,
901 0xfcc0fcd0,
902 0xfca0fcb0,
903 0xfc80fc90,
904 0x0032f400,
905/* 0x0196: timer */
906 0x32f401f8,
907 0x03f89810,
908 0xf40086b0,
909 0xfeb53a1c,
910 0xf6380003,
911 0x04bd0008,
912 0x88cf0808,
913 0x0284f000,
914 0x081c1bf4,
915 0x0088cf34,
916 0x0bf4e0a6,
917 0xf4e8a608,
918/* 0x01c6: timer_reset */
919 0x3400161e,
920 0xbd000ef6,
921 0x840eb504,
922/* 0x01d0: timer_enable */
923 0x38000108,
924 0xbd0008f6,
925/* 0x01d9: timer_done */
926 0x1031f404,
927/* 0x01de: send_proc */
928 0x80f900f8,
929 0xe89890f9,
930 0x04e99805,
931 0xa60486f0,
932 0x2a0bf489,
933 0x940398c4,
934 0x80b60488,
935 0x008ebb18,
936 0xb500fa98,
937 0x8db5008a,
938 0x028cb501,
939 0xb6038bb5,
940 0x94f00190,
941 0x04e9b507,
942/* 0x0217: send_done */
943 0xfc0231f4,
944 0xf880fc90,
945/* 0x021d: find */
946 0x0880f900,
947 0x0131f458,
948/* 0x0224: find_loop */
949 0xa6008a98,
950 0x100bf4ae,
951 0xb15880b6,
952 0xf4021086,
953 0x32f4f11b,
954/* 0x0239: find_done */
955 0xfc8eb201,
956/* 0x023f: send */
957 0x7e00f880,
958 0xf400021d,
959 0x00f89b01,
960/* 0x0248: recv */
961 0x9805e898,
962 0x32f404e9,
963 0xf489a601,
964 0x89c43c0b,
965 0x0180b603,
966 0xb50784f0,
967 0xea9805e8,
968 0xfef0f902,
969 0xf0f9018f,
970 0x9994efb2,
971 0x00e9bb04,
972 0x9818e0b6,
973 0xec9803eb,
974 0x01ed9802,
975 0xf900ee98,
976 0xfef0fca5,
977 0x31f400f8,
978/* 0x028f: recv_done */
979 0xf8f0fc01,
980/* 0x0291: init */
981 0x01084100,
982 0xe70011cf,
983 0xb6010911,
984 0x14fe0814,
985 0x00e04100,
986 0x000013f0,
987 0x0001f61c,
988 0xff0104bd,
989 0x01f61400,
990 0x0104bd00,
991 0x0015f102,
992 0xf6100008,
993 0x04bd0001,
994 0xf000d241,
995 0x10fe0013,
996 0x1031f400,
997 0x38000101,
998 0xbd0001f6,
999/* 0x02db: init_proc */
1000 0x98580f04,
1001 0x16b001f1,
1002 0xfa0bf400,
1003 0xf0b615f9,
1004 0xf20ef458,
1005/* 0x02ec: host_send */
1006 0xcf04b041,
1007 0xa0420011,
1008 0x0022cf04,
1009 0x0bf412a6,
1010 0x071ec42e,
1011 0xb704ee94,
1012 0x980218e0,
1013 0xec9803eb,
1014 0x01ed9802,
1015 0x7e00ee98,
1016 0xb600023f,
1017 0x1ec40110,
1018 0x04b0400f,
1019 0xbd0001f6,
1020 0xc70ef404,
1021/* 0x0328: host_send_done */
1022/* 0x032a: host_recv */
1023 0x494100f8,
1024 0x5413f14e,
1025 0xf4e1a652,
1026/* 0x0336: host_recv_wait */
1027 0xcc41b90b,
1028 0x0011cf04,
1029 0xcf04c842,
1030 0x16f00022,
1031 0xf412a608,
1032 0x23c4ef0b,
1033 0x0434b607,
1034 0x029830b7,
1035 0xb5033bb5,
1036 0x3db5023c,
1037 0x003eb501,
1038 0xf00120b6,
1039 0xc8400f24,
1040 0x0002f604,
1041 0x400204bd,
1042 0x02f60000,
1043 0xf804bd00,
1044/* 0x0379: host_init */
1045 0x00804100,
1046 0xf11014b6,
1047 0x40021815,
1048 0x01f604d0,
1049 0x4104bd00,
1050 0x14b60080,
1051 0x9815f110,
1052 0x04dc4002,
1053 0xbd0001f6,
1054 0x40010104,
1055 0x01f604c4,
1056 0xf804bd00,
1057/* 0x03a9: memx_func_enter */
1058 0x40040600,
1059 0x06f607e0,
1060/* 0x03b3: memx_func_enter_wait */
1061 0x4604bd00,
1062 0x66cf07c0,
1063 0x0464f000,
1064 0x98f70bf4,
1065 0x10b60016,
1066/* 0x03c7: memx_func_leave */
1067 0x0600f804,
1068 0x07e44004,
1069 0xbd0006f6,
1070/* 0x03d1: memx_func_leave_wait */
1071 0x07c04604,
1072 0xf00066cf,
1073 0x1bf40464,
1074/* 0x03df: memx_func_wr32 */
1075 0x9800f8f7,
1076 0x15980016,
1077 0x0810b601,
1078 0x50f960f9,
1079 0xe0fcd0fc,
1080 0x00002e7e,
1081 0x140003f1,
1082 0xa00506fd,
1083 0xb604bd05,
1084 0x1bf40242,
1085/* 0x0407: memx_func_wait */
1086 0x0800f8dd,
1087 0x0088cf2c,
1088 0x98001e98,
1089 0x1c98011d,
1090 0x031b9802,
1091 0x7e1010b6,
1092 0xf8000071,
1093/* 0x0421: memx_func_delay */
1094 0x001e9800,
1095 0x7e0410b6,
1096 0xf800005d,
1097/* 0x042d: memx_exec */
1098 0xf9e0f900,
1099 0xb2c1b2d0,
1100/* 0x0435: memx_exec_next */
1101 0x001398b2,
1102 0x950410b6,
1103 0x30f01034,
1104 0xc835980c,
1105 0x12a655f9,
1106 0xfced1ef4,
1107 0x7ee0fcd0,
1108 0xf800023f,
1109/* 0x0455: memx_info */
1110 0x03544c00,
1111 0x7e08004b,
1112 0xf800023f,
1113/* 0x0461: memx_recv */
1114 0x01d6b000,
1115 0xb0c90bf4,
1116 0x0bf400d6,
1117/* 0x046f: memx_init */
1118 0xf800f8eb,
1119/* 0x0471: perf_recv */
1120/* 0x0473: perf_init */
1121 0xf800f800,
1122/* 0x0475: test_recv */
1123 0x04584100,
1124 0xb60011cf,
1125 0x58400110,
1126 0x0001f604,
1127 0xe7f104bd,
1128 0xe3f1d900,
1129 0x967e134f,
1130 0x00f80001,
1131/* 0x0494: test_init */
1132 0x7e08004e,
1133 0xf8000196,
1134/* 0x049d: idle_recv */
1135/* 0x049f: idle */
1136 0xf400f800,
1137 0x54410031,
1138 0x0011cf04,
1139 0x400110b6,
1140 0x01f60454,
1141/* 0x04b3: idle_loop */
1142 0x0104bd00,
1143 0x0232f458,
1144/* 0x04b8: idle_proc */
1145/* 0x04b8: idle_proc_exec */
1146 0x1eb210f9,
1147 0x0002487e,
1148 0x11f410fc,
1149 0x0231f409,
1150/* 0x04cb: idle_proc_next */
1151 0xb6f00ef4,
1152 0x1fa65810,
1153 0xf4e81bf4,
1154 0x28f4e002,
1155 0xc60ef400,
1156 0x00000000,
1157 0x00000000,
1158 0x00000000,
1159 0x00000000,
1160 0x00000000,
1161 0x00000000,
1162 0x00000000,
1163 0x00000000,
1164 0x00000000,
1165};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc
new file mode 100644
index 000000000000..6fde0b89e5aa
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc
@@ -0,0 +1,63 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#define NVKM_PPWR_CHIPSET GT215
26
27//#define NVKM_FALCON_PC24
28//#define NVKM_FALCON_UNSHIFTED_IO
29//#define NVKM_FALCON_MMIO_UAS
30//#define NVKM_FALCON_MMIO_TRAP
31
32#include "macros.fuc"
33
34.section #nva3_pwr_data
35#define INCLUDE_PROC
36#include "kernel.fuc"
37#include "host.fuc"
38#include "memx.fuc"
39#include "perf.fuc"
40#include "test.fuc"
41#include "idle.fuc"
42#undef INCLUDE_PROC
43
44#define INCLUDE_DATA
45#include "kernel.fuc"
46#include "host.fuc"
47#include "memx.fuc"
48#include "perf.fuc"
49#include "test.fuc"
50#include "idle.fuc"
51#undef INCLUDE_DATA
52.align 256
53
54.section #nva3_pwr_code
55#define INCLUDE_CODE
56#include "kernel.fuc"
57#include "host.fuc"
58#include "memx.fuc"
59#include "perf.fuc"
60#include "test.fuc"
61#include "idle.fuc"
62#undef INCLUDE_CODE
63.align 256
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h
new file mode 100644
index 000000000000..0fa4d7dcd407
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h
@@ -0,0 +1,1229 @@
1uint32_t nva3_pwr_data[] = {
2/* 0x0000: proc_kern */
3 0x52544e49,
4 0x00000000,
5 0x00000000,
6 0x00000000,
7 0x00000000,
8 0x00000000,
9 0x00000000,
10 0x00000000,
11 0x00000000,
12 0x00000000,
13 0x00000000,
14 0x00000000,
15 0x00000000,
16 0x00000000,
17 0x00000000,
18 0x00000000,
19 0x00000000,
20 0x00000000,
21 0x00000000,
22 0x00000000,
23 0x00000000,
24 0x00000000,
25/* 0x0058: proc_list_head */
26 0x54534f48,
27 0x00000430,
28 0x000003cd,
29 0x00000000,
30 0x00000000,
31 0x00000000,
32 0x00000000,
33 0x00000000,
34 0x00000000,
35 0x00000000,
36 0x00000000,
37 0x00000000,
38 0x00000000,
39 0x00000000,
40 0x00000000,
41 0x00000000,
42 0x00000000,
43 0x00000000,
44 0x00000000,
45 0x00000000,
46 0x00000000,
47 0x00000000,
48 0x584d454d,
49 0x0000054e,
50 0x00000540,
51 0x00000000,
52 0x00000000,
53 0x00000000,
54 0x00000000,
55 0x00000000,
56 0x00000000,
57 0x00000000,
58 0x00000000,
59 0x00000000,
60 0x00000000,
61 0x00000000,
62 0x00000000,
63 0x00000000,
64 0x00000000,
65 0x00000000,
66 0x00000000,
67 0x00000000,
68 0x00000000,
69 0x00000000,
70 0x46524550,
71 0x00000552,
72 0x00000550,
73 0x00000000,
74 0x00000000,
75 0x00000000,
76 0x00000000,
77 0x00000000,
78 0x00000000,
79 0x00000000,
80 0x00000000,
81 0x00000000,
82 0x00000000,
83 0x00000000,
84 0x00000000,
85 0x00000000,
86 0x00000000,
87 0x00000000,
88 0x00000000,
89 0x00000000,
90 0x00000000,
91 0x00000000,
92 0x54534554,
93 0x0000057b,
94 0x00000554,
95 0x00000000,
96 0x00000000,
97 0x00000000,
98 0x00000000,
99 0x00000000,
100 0x00000000,
101 0x00000000,
102 0x00000000,
103 0x00000000,
104 0x00000000,
105 0x00000000,
106 0x00000000,
107 0x00000000,
108 0x00000000,
109 0x00000000,
110 0x00000000,
111 0x00000000,
112 0x00000000,
113 0x00000000,
114 0x454c4449,
115 0x00000587,
116 0x00000585,
117 0x00000000,
118 0x00000000,
119 0x00000000,
120 0x00000000,
121 0x00000000,
122 0x00000000,
123 0x00000000,
124 0x00000000,
125 0x00000000,
126 0x00000000,
127 0x00000000,
128 0x00000000,
129 0x00000000,
130 0x00000000,
131 0x00000000,
132 0x00000000,
133 0x00000000,
134 0x00000000,
135 0x00000000,
136/* 0x0210: proc_list_tail */
137/* 0x0210: time_prev */
138 0x00000000,
139/* 0x0214: time_next */
140 0x00000000,
141/* 0x0218: fifo_queue */
142 0x00000000,
143 0x00000000,
144 0x00000000,
145 0x00000000,
146 0x00000000,
147 0x00000000,
148 0x00000000,
149 0x00000000,
150 0x00000000,
151 0x00000000,
152 0x00000000,
153 0x00000000,
154 0x00000000,
155 0x00000000,
156 0x00000000,
157 0x00000000,
158 0x00000000,
159 0x00000000,
160 0x00000000,
161 0x00000000,
162 0x00000000,
163 0x00000000,
164 0x00000000,
165 0x00000000,
166 0x00000000,
167 0x00000000,
168 0x00000000,
169 0x00000000,
170 0x00000000,
171 0x00000000,
172 0x00000000,
173 0x00000000,
174/* 0x0298: rfifo_queue */
175 0x00000000,
176 0x00000000,
177 0x00000000,
178 0x00000000,
179 0x00000000,
180 0x00000000,
181 0x00000000,
182 0x00000000,
183 0x00000000,
184 0x00000000,
185 0x00000000,
186 0x00000000,
187 0x00000000,
188 0x00000000,
189 0x00000000,
190 0x00000000,
191 0x00000000,
192 0x00000000,
193 0x00000000,
194 0x00000000,
195 0x00000000,
196 0x00000000,
197 0x00000000,
198 0x00000000,
199 0x00000000,
200 0x00000000,
201 0x00000000,
202 0x00000000,
203 0x00000000,
204 0x00000000,
205 0x00000000,
206 0x00000000,
207/* 0x0318: memx_func_head */
208 0x00010000,
209 0x00000000,
210 0x0000046f,
211/* 0x0324: memx_func_next */
212 0x00000001,
213 0x00000000,
214 0x00000496,
215 0x00000002,
216 0x00000002,
217 0x000004b7,
218 0x00040003,
219 0x00000000,
220 0x000004df,
221 0x00010004,
222 0x00000000,
223 0x000004fc,
224/* 0x0354: memx_func_tail */
225/* 0x0354: memx_data_head */
226 0x00000000,
227 0x00000000,
228 0x00000000,
229 0x00000000,
230 0x00000000,
231 0x00000000,
232 0x00000000,
233 0x00000000,
234 0x00000000,
235 0x00000000,
236 0x00000000,
237 0x00000000,
238 0x00000000,
239 0x00000000,
240 0x00000000,
241 0x00000000,
242 0x00000000,
243 0x00000000,
244 0x00000000,
245 0x00000000,
246 0x00000000,
247 0x00000000,
248 0x00000000,
249 0x00000000,
250 0x00000000,
251 0x00000000,
252 0x00000000,
253 0x00000000,
254 0x00000000,
255 0x00000000,
256 0x00000000,
257 0x00000000,
258 0x00000000,
259 0x00000000,
260 0x00000000,
261 0x00000000,
262 0x00000000,
263 0x00000000,
264 0x00000000,
265 0x00000000,
266 0x00000000,
267 0x00000000,
268 0x00000000,
269 0x00000000,
270 0x00000000,
271 0x00000000,
272 0x00000000,
273 0x00000000,
274 0x00000000,
275 0x00000000,
276 0x00000000,
277 0x00000000,
278 0x00000000,
279 0x00000000,
280 0x00000000,
281 0x00000000,
282 0x00000000,
283 0x00000000,
284 0x00000000,
285 0x00000000,
286 0x00000000,
287 0x00000000,
288 0x00000000,
289 0x00000000,
290 0x00000000,
291 0x00000000,
292 0x00000000,
293 0x00000000,
294 0x00000000,
295 0x00000000,
296 0x00000000,
297 0x00000000,
298 0x00000000,
299 0x00000000,
300 0x00000000,
301 0x00000000,
302 0x00000000,
303 0x00000000,
304 0x00000000,
305 0x00000000,
306 0x00000000,
307 0x00000000,
308 0x00000000,
309 0x00000000,
310 0x00000000,
311 0x00000000,
312 0x00000000,
313 0x00000000,
314 0x00000000,
315 0x00000000,
316 0x00000000,
317 0x00000000,
318 0x00000000,
319 0x00000000,
320 0x00000000,
321 0x00000000,
322 0x00000000,
323 0x00000000,
324 0x00000000,
325 0x00000000,
326 0x00000000,
327 0x00000000,
328 0x00000000,
329 0x00000000,
330 0x00000000,
331 0x00000000,
332 0x00000000,
333 0x00000000,
334 0x00000000,
335 0x00000000,
336 0x00000000,
337 0x00000000,
338 0x00000000,
339 0x00000000,
340 0x00000000,
341 0x00000000,
342 0x00000000,
343 0x00000000,
344 0x00000000,
345 0x00000000,
346 0x00000000,
347 0x00000000,
348 0x00000000,
349 0x00000000,
350 0x00000000,
351 0x00000000,
352 0x00000000,
353 0x00000000,
354 0x00000000,
355 0x00000000,
356 0x00000000,
357 0x00000000,
358 0x00000000,
359 0x00000000,
360 0x00000000,
361 0x00000000,
362 0x00000000,
363 0x00000000,
364 0x00000000,
365 0x00000000,
366 0x00000000,
367 0x00000000,
368 0x00000000,
369 0x00000000,
370 0x00000000,
371 0x00000000,
372 0x00000000,
373 0x00000000,
374 0x00000000,
375 0x00000000,
376 0x00000000,
377 0x00000000,
378 0x00000000,
379 0x00000000,
380 0x00000000,
381 0x00000000,
382 0x00000000,
383 0x00000000,
384 0x00000000,
385 0x00000000,
386 0x00000000,
387 0x00000000,
388 0x00000000,
389 0x00000000,
390 0x00000000,
391 0x00000000,
392 0x00000000,
393 0x00000000,
394 0x00000000,
395 0x00000000,
396 0x00000000,
397 0x00000000,
398 0x00000000,
399 0x00000000,
400 0x00000000,
401 0x00000000,
402 0x00000000,
403 0x00000000,
404 0x00000000,
405 0x00000000,
406 0x00000000,
407 0x00000000,
408 0x00000000,
409 0x00000000,
410 0x00000000,
411 0x00000000,
412 0x00000000,
413 0x00000000,
414 0x00000000,
415 0x00000000,
416 0x00000000,
417 0x00000000,
418 0x00000000,
419 0x00000000,
420 0x00000000,
421 0x00000000,
422 0x00000000,
423 0x00000000,
424 0x00000000,
425 0x00000000,
426 0x00000000,
427 0x00000000,
428 0x00000000,
429 0x00000000,
430 0x00000000,
431 0x00000000,
432 0x00000000,
433 0x00000000,
434 0x00000000,
435 0x00000000,
436 0x00000000,
437 0x00000000,
438 0x00000000,
439 0x00000000,
440 0x00000000,
441 0x00000000,
442 0x00000000,
443 0x00000000,
444 0x00000000,
445 0x00000000,
446 0x00000000,
447 0x00000000,
448 0x00000000,
449 0x00000000,
450 0x00000000,
451 0x00000000,
452 0x00000000,
453 0x00000000,
454 0x00000000,
455 0x00000000,
456 0x00000000,
457 0x00000000,
458 0x00000000,
459 0x00000000,
460 0x00000000,
461 0x00000000,
462 0x00000000,
463 0x00000000,
464 0x00000000,
465 0x00000000,
466 0x00000000,
467 0x00000000,
468 0x00000000,
469 0x00000000,
470 0x00000000,
471 0x00000000,
472 0x00000000,
473 0x00000000,
474 0x00000000,
475 0x00000000,
476 0x00000000,
477 0x00000000,
478 0x00000000,
479 0x00000000,
480 0x00000000,
481 0x00000000,
482 0x00000000,
483 0x00000000,
484 0x00000000,
485 0x00000000,
486 0x00000000,
487 0x00000000,
488 0x00000000,
489 0x00000000,
490 0x00000000,
491 0x00000000,
492 0x00000000,
493 0x00000000,
494 0x00000000,
495 0x00000000,
496 0x00000000,
497 0x00000000,
498 0x00000000,
499 0x00000000,
500 0x00000000,
501 0x00000000,
502 0x00000000,
503 0x00000000,
504 0x00000000,
505 0x00000000,
506 0x00000000,
507 0x00000000,
508 0x00000000,
509 0x00000000,
510 0x00000000,
511 0x00000000,
512 0x00000000,
513 0x00000000,
514 0x00000000,
515 0x00000000,
516 0x00000000,
517 0x00000000,
518 0x00000000,
519 0x00000000,
520 0x00000000,
521 0x00000000,
522 0x00000000,
523 0x00000000,
524 0x00000000,
525 0x00000000,
526 0x00000000,
527 0x00000000,
528 0x00000000,
529 0x00000000,
530 0x00000000,
531 0x00000000,
532 0x00000000,
533 0x00000000,
534 0x00000000,
535 0x00000000,
536 0x00000000,
537 0x00000000,
538 0x00000000,
539 0x00000000,
540 0x00000000,
541 0x00000000,
542 0x00000000,
543 0x00000000,
544 0x00000000,
545 0x00000000,
546 0x00000000,
547 0x00000000,
548 0x00000000,
549 0x00000000,
550 0x00000000,
551 0x00000000,
552 0x00000000,
553 0x00000000,
554 0x00000000,
555 0x00000000,
556 0x00000000,
557 0x00000000,
558 0x00000000,
559 0x00000000,
560 0x00000000,
561 0x00000000,
562 0x00000000,
563 0x00000000,
564 0x00000000,
565 0x00000000,
566 0x00000000,
567 0x00000000,
568 0x00000000,
569 0x00000000,
570 0x00000000,
571 0x00000000,
572 0x00000000,
573 0x00000000,
574 0x00000000,
575 0x00000000,
576 0x00000000,
577 0x00000000,
578 0x00000000,
579 0x00000000,
580 0x00000000,
581 0x00000000,
582 0x00000000,
583 0x00000000,
584 0x00000000,
585 0x00000000,
586 0x00000000,
587 0x00000000,
588 0x00000000,
589 0x00000000,
590 0x00000000,
591 0x00000000,
592 0x00000000,
593 0x00000000,
594 0x00000000,
595 0x00000000,
596 0x00000000,
597 0x00000000,
598 0x00000000,
599 0x00000000,
600 0x00000000,
601 0x00000000,
602 0x00000000,
603 0x00000000,
604 0x00000000,
605 0x00000000,
606 0x00000000,
607 0x00000000,
608 0x00000000,
609 0x00000000,
610 0x00000000,
611 0x00000000,
612 0x00000000,
613 0x00000000,
614 0x00000000,
615 0x00000000,
616 0x00000000,
617 0x00000000,
618 0x00000000,
619 0x00000000,
620 0x00000000,
621 0x00000000,
622 0x00000000,
623 0x00000000,
624 0x00000000,
625 0x00000000,
626 0x00000000,
627 0x00000000,
628 0x00000000,
629 0x00000000,
630 0x00000000,
631 0x00000000,
632 0x00000000,
633 0x00000000,
634 0x00000000,
635 0x00000000,
636 0x00000000,
637 0x00000000,
638 0x00000000,
639 0x00000000,
640 0x00000000,
641 0x00000000,
642 0x00000000,
643 0x00000000,
644 0x00000000,
645 0x00000000,
646 0x00000000,
647 0x00000000,
648 0x00000000,
649 0x00000000,
650 0x00000000,
651 0x00000000,
652 0x00000000,
653 0x00000000,
654 0x00000000,
655 0x00000000,
656 0x00000000,
657 0x00000000,
658 0x00000000,
659 0x00000000,
660 0x00000000,
661 0x00000000,
662 0x00000000,
663 0x00000000,
664 0x00000000,
665 0x00000000,
666 0x00000000,
667 0x00000000,
668 0x00000000,
669 0x00000000,
670 0x00000000,
671 0x00000000,
672 0x00000000,
673 0x00000000,
674 0x00000000,
675 0x00000000,
676 0x00000000,
677 0x00000000,
678 0x00000000,
679 0x00000000,
680 0x00000000,
681 0x00000000,
682 0x00000000,
683 0x00000000,
684 0x00000000,
685 0x00000000,
686 0x00000000,
687 0x00000000,
688 0x00000000,
689 0x00000000,
690 0x00000000,
691 0x00000000,
692 0x00000000,
693 0x00000000,
694 0x00000000,
695 0x00000000,
696 0x00000000,
697 0x00000000,
698 0x00000000,
699 0x00000000,
700 0x00000000,
701 0x00000000,
702 0x00000000,
703 0x00000000,
704 0x00000000,
705 0x00000000,
706 0x00000000,
707 0x00000000,
708 0x00000000,
709 0x00000000,
710 0x00000000,
711 0x00000000,
712 0x00000000,
713 0x00000000,
714 0x00000000,
715 0x00000000,
716 0x00000000,
717 0x00000000,
718 0x00000000,
719 0x00000000,
720 0x00000000,
721 0x00000000,
722 0x00000000,
723 0x00000000,
724 0x00000000,
725 0x00000000,
726 0x00000000,
727 0x00000000,
728 0x00000000,
729 0x00000000,
730 0x00000000,
731 0x00000000,
732 0x00000000,
733 0x00000000,
734 0x00000000,
735 0x00000000,
736 0x00000000,
737 0x00000000,
738/* 0x0b54: memx_data_tail */
739 0x00000000,
740 0x00000000,
741 0x00000000,
742 0x00000000,
743 0x00000000,
744 0x00000000,
745 0x00000000,
746 0x00000000,
747 0x00000000,
748 0x00000000,
749 0x00000000,
750 0x00000000,
751 0x00000000,
752 0x00000000,
753 0x00000000,
754 0x00000000,
755 0x00000000,
756 0x00000000,
757 0x00000000,
758 0x00000000,
759 0x00000000,
760 0x00000000,
761 0x00000000,
762 0x00000000,
763 0x00000000,
764 0x00000000,
765 0x00000000,
766 0x00000000,
767 0x00000000,
768 0x00000000,
769 0x00000000,
770 0x00000000,
771 0x00000000,
772 0x00000000,
773 0x00000000,
774 0x00000000,
775 0x00000000,
776 0x00000000,
777 0x00000000,
778 0x00000000,
779 0x00000000,
780 0x00000000,
781 0x00000000,
782};
783
784uint32_t nva3_pwr_code[] = {
785 0x030d0ef5,
786/* 0x0004: rd32 */
787 0x07a007f1,
788 0xd00604b6,
789 0x04bd000e,
790 0xf001e7f0,
791 0x07f101e3,
792 0x04b607ac,
793 0x000ed006,
794/* 0x0022: rd32_wait */
795 0xe7f104bd,
796 0xe4b607ac,
797 0x00eecf06,
798 0x7000e4f1,
799 0xf1f21bf4,
800 0xb607a4d7,
801 0xddcf06d4,
802/* 0x003f: wr32 */
803 0xf100f800,
804 0xb607a007,
805 0x0ed00604,
806 0xf104bd00,
807 0xb607a407,
808 0x0dd00604,
809 0xf004bd00,
810 0xe5f002e7,
811 0x01e3f0f0,
812 0x07ac07f1,
813 0xd00604b6,
814 0x04bd000e,
815/* 0x006c: wr32_wait */
816 0x07ace7f1,
817 0xcf06e4b6,
818 0xe4f100ee,
819 0x1bf47000,
820/* 0x007f: nsec */
821 0xf000f8f2,
822 0x84b62c87,
823 0x0088cf06,
824/* 0x0088: nsec_loop */
825 0xb62c97f0,
826 0x99cf0694,
827 0x0298bb00,
828 0xf4069eb8,
829 0x00f8f11e,
830/* 0x009c: wait */
831 0xb62c87f0,
832 0x88cf0684,
833/* 0x00a5: wait_loop */
834 0x02eeb900,
835 0xb90421f4,
836 0xadfd02da,
837 0x06acb804,
838 0xf0150bf4,
839 0x94b62c97,
840 0x0099cf06,
841 0xb80298bb,
842 0x1ef4069b,
843/* 0x00c9: wait_done */
844/* 0x00cb: intr_watchdog */
845 0x9800f8df,
846 0x96b003e9,
847 0x2a0bf400,
848 0xbb840a98,
849 0x1cf4029a,
850 0x01d7f00f,
851 0x025421f5,
852 0x0ef494bd,
853/* 0x00e9: intr_watchdog_next_time */
854 0x850a9815,
855 0xf400a6b0,
856 0x9ab8090b,
857 0x061cf406,
858/* 0x00f8: intr_watchdog_next_time_set */
859/* 0x00fb: intr_watchdog_next_proc */
860 0x80850980,
861 0xe0b603e9,
862 0x10e6b158,
863 0xc61bf402,
864/* 0x010a: intr */
865 0x00f900f8,
866 0x80f904bd,
867 0xa0f990f9,
868 0xc0f9b0f9,
869 0xe0f9d0f9,
870 0xf7f0f0f9,
871 0x0188fe00,
872 0x87f180f9,
873 0x84b605d0,
874 0x0088cf06,
875 0xf10180b6,
876 0xb605d007,
877 0x08d00604,
878 0xf004bd00,
879 0x84b60887,
880 0x0088cf06,
881 0xf40289c4,
882 0x0080230b,
883 0x58e7f085,
884 0x98cb21f4,
885 0x96b08509,
886 0x110bf400,
887 0xb63407f0,
888 0x09d00604,
889 0x8004bd00,
890/* 0x016e: intr_skip_watchdog */
891 0x89e48409,
892 0x0bf40800,
893 0x8897f148,
894 0x0694b606,
895 0xc40099cf,
896 0x0bf4029a,
897 0xc0c7f12c,
898 0x06c4b604,
899 0xf900cccf,
900 0x48e7f1c0,
901 0x53e3f14f,
902 0x00d7f054,
903 0x02b921f5,
904 0x07f1c0fc,
905 0x04b604c0,
906 0x000cd006,
907/* 0x01ae: intr_subintr_skip_fifo */
908 0x07f104bd,
909 0x04b60688,
910 0x0009d006,
911/* 0x01ba: intr_skip_subintr */
912 0x89c404bd,
913 0x070bf420,
914 0xffbfa4f1,
915/* 0x01c4: intr_skip_pause */
916 0xf44089c4,
917 0xa4f1070b,
918/* 0x01ce: intr_skip_user0 */
919 0x07f0ffbf,
920 0x0604b604,
921 0xbd0008d0,
922 0xfe80fc04,
923 0xf0fc0088,
924 0xd0fce0fc,
925 0xb0fcc0fc,
926 0x90fca0fc,
927 0x00fc80fc,
928 0xf80032f4,
929/* 0x01f5: timer */
930 0x1032f401,
931 0xb003f898,
932 0x1cf40086,
933 0x03fe8051,
934 0xb63807f0,
935 0x08d00604,
936 0xf004bd00,
937 0x84b60887,
938 0x0088cf06,
939 0xf40284f0,
940 0x87f0261b,
941 0x0684b634,
942 0xb80088cf,
943 0x0bf406e0,
944 0x06e8b809,
945/* 0x0233: timer_reset */
946 0xf01f1ef4,
947 0x04b63407,
948 0x000ed006,
949 0x0e8004bd,
950/* 0x0241: timer_enable */
951 0x0187f084,
952 0xb63807f0,
953 0x08d00604,
954/* 0x024f: timer_done */
955 0xf404bd00,
956 0x00f81031,
957/* 0x0254: send_proc */
958 0x90f980f9,
959 0x9805e898,
960 0x86f004e9,
961 0x0689b804,
962 0xc42a0bf4,
963 0x88940398,
964 0x1880b604,
965 0x98008ebb,
966 0x8a8000fa,
967 0x018d8000,
968 0x80028c80,
969 0x90b6038b,
970 0x0794f001,
971 0xf404e980,
972/* 0x028e: send_done */
973 0x90fc0231,
974 0x00f880fc,
975/* 0x0294: find */
976 0x87f080f9,
977 0x0131f458,
978/* 0x029c: find_loop */
979 0xb8008a98,
980 0x0bf406ae,
981 0x5880b610,
982 0x021086b1,
983 0xf4f01bf4,
984/* 0x02b2: find_done */
985 0x8eb90132,
986 0xf880fc02,
987/* 0x02b9: send */
988 0x9421f500,
989 0x9701f402,
990/* 0x02c2: recv */
991 0xe89800f8,
992 0x04e99805,
993 0xb80132f4,
994 0x0bf40689,
995 0x0389c43d,
996 0xf00180b6,
997 0xe8800784,
998 0x02ea9805,
999 0x8ffef0f9,
1000 0xb9f0f901,
1001 0x999402ef,
1002 0x00e9bb04,
1003 0x9818e0b6,
1004 0xec9803eb,
1005 0x01ed9802,
1006 0xf900ee98,
1007 0xfef0fca5,
1008 0x31f400f8,
1009/* 0x030b: recv_done */
1010 0xf8f0fc01,
1011/* 0x030d: init */
1012 0x0817f100,
1013 0x0614b601,
1014 0xe70011cf,
1015 0xb6010911,
1016 0x14fe0814,
1017 0xe017f100,
1018 0x0013f000,
1019 0xb61c07f0,
1020 0x01d00604,
1021 0xf004bd00,
1022 0x07f0ff17,
1023 0x0604b614,
1024 0xbd0001d0,
1025 0x0217f004,
1026 0x080015f1,
1027 0xb61007f0,
1028 0x01d00604,
1029 0xf104bd00,
1030 0xf0010a17,
1031 0x10fe0013,
1032 0x1031f400,
1033 0xf00117f0,
1034 0x04b63807,
1035 0x0001d006,
1036 0xf7f004bd,
1037/* 0x0371: init_proc */
1038 0x01f19858,
1039 0xf40016b0,
1040 0x15f9fa0b,
1041 0xf458f0b6,
1042/* 0x0382: host_send */
1043 0x17f1f20e,
1044 0x14b604b0,
1045 0x0011cf06,
1046 0x04a027f1,
1047 0xcf0624b6,
1048 0x12b80022,
1049 0x320bf406,
1050 0x94071ec4,
1051 0xe0b704ee,
1052 0xeb980218,
1053 0x02ec9803,
1054 0x9801ed98,
1055 0x21f500ee,
1056 0x10b602b9,
1057 0x0f1ec401,
1058 0x04b007f1,
1059 0xd00604b6,
1060 0x04bd0001,
1061/* 0x03cb: host_send_done */
1062 0xf8ba0ef4,
1063/* 0x03cd: host_recv */
1064 0x4917f100,
1065 0x5413f14e,
1066 0x06e1b852,
1067/* 0x03db: host_recv_wait */
1068 0xf1aa0bf4,
1069 0xb604cc17,
1070 0x11cf0614,
1071 0xc827f100,
1072 0x0624b604,
1073 0xf00022cf,
1074 0x12b80816,
1075 0xe60bf406,
1076 0xb60723c4,
1077 0x30b70434,
1078 0x3b800298,
1079 0x023c8003,
1080 0x80013d80,
1081 0x20b6003e,
1082 0x0f24f001,
1083 0x04c807f1,
1084 0xd00604b6,
1085 0x04bd0002,
1086 0xf04027f0,
1087 0x04b60007,
1088 0x0002d006,
1089 0x00f804bd,
1090/* 0x0430: host_init */
1091 0x008017f1,
1092 0xf11014b6,
1093 0xf1021815,
1094 0xb604d007,
1095 0x01d00604,
1096 0xf104bd00,
1097 0xb6008017,
1098 0x15f11014,
1099 0x07f10298,
1100 0x04b604dc,
1101 0x0001d006,
1102 0x17f004bd,
1103 0xc407f101,
1104 0x0604b604,
1105 0xbd0001d0,
1106/* 0x046f: memx_func_enter */
1107 0xf000f804,
1108 0x07f10467,
1109 0x04b607e0,
1110 0x0006d006,
1111/* 0x047e: memx_func_enter_wait */
1112 0x67f104bd,
1113 0x64b607c0,
1114 0x0066cf06,
1115 0xf40464f0,
1116 0x1698f30b,
1117 0x0410b600,
1118/* 0x0496: memx_func_leave */
1119 0x67f000f8,
1120 0xe407f104,
1121 0x0604b607,
1122 0xbd0006d0,
1123/* 0x04a5: memx_func_leave_wait */
1124 0xc067f104,
1125 0x0664b607,
1126 0xf00066cf,
1127 0x1bf40464,
1128/* 0x04b7: memx_func_wr32 */
1129 0x9800f8f3,
1130 0x15980016,
1131 0x0810b601,
1132 0x50f960f9,
1133 0xe0fcd0fc,
1134 0xf13f21f4,
1135 0xfd140003,
1136 0x05800506,
1137 0xb604bd00,
1138 0x1bf40242,
1139/* 0x04df: memx_func_wait */
1140 0xf000f8dd,
1141 0x84b62c87,
1142 0x0088cf06,
1143 0x98001e98,
1144 0x1c98011d,
1145 0x031b9802,
1146 0xf41010b6,
1147 0x00f89c21,
1148/* 0x04fc: memx_func_delay */
1149 0xb6001e98,
1150 0x21f40410,
1151/* 0x0507: memx_exec */
1152 0xf900f87f,
1153 0xb9d0f9e0,
1154 0xb2b902c1,
1155/* 0x0511: memx_exec_next */
1156 0x00139802,
1157 0x950410b6,
1158 0x30f01034,
1159 0xc835980c,
1160 0x12b855f9,
1161 0xec1ef406,
1162 0xe0fcd0fc,
1163 0x02b921f5,
1164/* 0x0532: memx_info */
1165 0xc7f100f8,
1166 0xb7f10354,
1167 0x21f50800,
1168 0x00f802b9,
1169/* 0x0540: memx_recv */
1170 0xf401d6b0,
1171 0xd6b0c40b,
1172 0xe90bf400,
1173/* 0x054e: memx_init */
1174 0x00f800f8,
1175/* 0x0550: perf_recv */
1176/* 0x0552: perf_init */
1177 0x00f800f8,
1178/* 0x0554: test_recv */
1179 0x05d817f1,
1180 0xcf0614b6,
1181 0x10b60011,
1182 0xd807f101,
1183 0x0604b605,
1184 0xbd0001d0,
1185 0x00e7f104,
1186 0x4fe3f1d9,
1187 0xf521f513,
1188/* 0x057b: test_init */
1189 0xf100f801,
1190 0xf50800e7,
1191 0xf801f521,
1192/* 0x0585: idle_recv */
1193/* 0x0587: idle */
1194 0xf400f800,
1195 0x17f10031,
1196 0x14b605d4,
1197 0x0011cf06,
1198 0xf10110b6,
1199 0xb605d407,
1200 0x01d00604,
1201/* 0x05a3: idle_loop */
1202 0xf004bd00,
1203 0x32f45817,
1204/* 0x05a9: idle_proc */
1205/* 0x05a9: idle_proc_exec */
1206 0xb910f902,
1207 0x21f5021e,
1208 0x10fc02c2,
1209 0xf40911f4,
1210 0x0ef40231,
1211/* 0x05bd: idle_proc_next */
1212 0x5810b6ef,
1213 0xf4061fb8,
1214 0x02f4e61b,
1215 0x0028f4dd,
1216 0x00bb0ef4,
1217 0x00000000,
1218 0x00000000,
1219 0x00000000,
1220 0x00000000,
1221 0x00000000,
1222 0x00000000,
1223 0x00000000,
1224 0x00000000,
1225 0x00000000,
1226 0x00000000,
1227 0x00000000,
1228 0x00000000,
1229};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc
new file mode 100644
index 000000000000..eaa64da68e36
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc
@@ -0,0 +1,63 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#define NVKM_PPWR_CHIPSET GF100
26
27//#define NVKM_FALCON_PC24
28//#define NVKM_FALCON_UNSHIFTED_IO
29//#define NVKM_FALCON_MMIO_UAS
30//#define NVKM_FALCON_MMIO_TRAP
31
32#include "macros.fuc"
33
34.section #nvc0_pwr_data
35#define INCLUDE_PROC
36#include "kernel.fuc"
37#include "host.fuc"
38#include "memx.fuc"
39#include "perf.fuc"
40#include "test.fuc"
41#include "idle.fuc"
42#undef INCLUDE_PROC
43
44#define INCLUDE_DATA
45#include "kernel.fuc"
46#include "host.fuc"
47#include "memx.fuc"
48#include "perf.fuc"
49#include "test.fuc"
50#include "idle.fuc"
51#undef INCLUDE_DATA
52.align 256
53
54.section #nvc0_pwr_code
55#define INCLUDE_CODE
56#include "kernel.fuc"
57#include "host.fuc"
58#include "memx.fuc"
59#include "perf.fuc"
60#include "test.fuc"
61#include "idle.fuc"
62#undef INCLUDE_CODE
63.align 256
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h
new file mode 100644
index 000000000000..82c8e8b88917
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h
@@ -0,0 +1,1229 @@
1uint32_t nvc0_pwr_data[] = {
2/* 0x0000: proc_kern */
3 0x52544e49,
4 0x00000000,
5 0x00000000,
6 0x00000000,
7 0x00000000,
8 0x00000000,
9 0x00000000,
10 0x00000000,
11 0x00000000,
12 0x00000000,
13 0x00000000,
14 0x00000000,
15 0x00000000,
16 0x00000000,
17 0x00000000,
18 0x00000000,
19 0x00000000,
20 0x00000000,
21 0x00000000,
22 0x00000000,
23 0x00000000,
24 0x00000000,
25/* 0x0058: proc_list_head */
26 0x54534f48,
27 0x00000430,
28 0x000003cd,
29 0x00000000,
30 0x00000000,
31 0x00000000,
32 0x00000000,
33 0x00000000,
34 0x00000000,
35 0x00000000,
36 0x00000000,
37 0x00000000,
38 0x00000000,
39 0x00000000,
40 0x00000000,
41 0x00000000,
42 0x00000000,
43 0x00000000,
44 0x00000000,
45 0x00000000,
46 0x00000000,
47 0x00000000,
48 0x584d454d,
49 0x0000054e,
50 0x00000540,
51 0x00000000,
52 0x00000000,
53 0x00000000,
54 0x00000000,
55 0x00000000,
56 0x00000000,
57 0x00000000,
58 0x00000000,
59 0x00000000,
60 0x00000000,
61 0x00000000,
62 0x00000000,
63 0x00000000,
64 0x00000000,
65 0x00000000,
66 0x00000000,
67 0x00000000,
68 0x00000000,
69 0x00000000,
70 0x46524550,
71 0x00000552,
72 0x00000550,
73 0x00000000,
74 0x00000000,
75 0x00000000,
76 0x00000000,
77 0x00000000,
78 0x00000000,
79 0x00000000,
80 0x00000000,
81 0x00000000,
82 0x00000000,
83 0x00000000,
84 0x00000000,
85 0x00000000,
86 0x00000000,
87 0x00000000,
88 0x00000000,
89 0x00000000,
90 0x00000000,
91 0x00000000,
92 0x54534554,
93 0x0000057b,
94 0x00000554,
95 0x00000000,
96 0x00000000,
97 0x00000000,
98 0x00000000,
99 0x00000000,
100 0x00000000,
101 0x00000000,
102 0x00000000,
103 0x00000000,
104 0x00000000,
105 0x00000000,
106 0x00000000,
107 0x00000000,
108 0x00000000,
109 0x00000000,
110 0x00000000,
111 0x00000000,
112 0x00000000,
113 0x00000000,
114 0x454c4449,
115 0x00000587,
116 0x00000585,
117 0x00000000,
118 0x00000000,
119 0x00000000,
120 0x00000000,
121 0x00000000,
122 0x00000000,
123 0x00000000,
124 0x00000000,
125 0x00000000,
126 0x00000000,
127 0x00000000,
128 0x00000000,
129 0x00000000,
130 0x00000000,
131 0x00000000,
132 0x00000000,
133 0x00000000,
134 0x00000000,
135 0x00000000,
136/* 0x0210: proc_list_tail */
137/* 0x0210: time_prev */
138 0x00000000,
139/* 0x0214: time_next */
140 0x00000000,
141/* 0x0218: fifo_queue */
142 0x00000000,
143 0x00000000,
144 0x00000000,
145 0x00000000,
146 0x00000000,
147 0x00000000,
148 0x00000000,
149 0x00000000,
150 0x00000000,
151 0x00000000,
152 0x00000000,
153 0x00000000,
154 0x00000000,
155 0x00000000,
156 0x00000000,
157 0x00000000,
158 0x00000000,
159 0x00000000,
160 0x00000000,
161 0x00000000,
162 0x00000000,
163 0x00000000,
164 0x00000000,
165 0x00000000,
166 0x00000000,
167 0x00000000,
168 0x00000000,
169 0x00000000,
170 0x00000000,
171 0x00000000,
172 0x00000000,
173 0x00000000,
174/* 0x0298: rfifo_queue */
175 0x00000000,
176 0x00000000,
177 0x00000000,
178 0x00000000,
179 0x00000000,
180 0x00000000,
181 0x00000000,
182 0x00000000,
183 0x00000000,
184 0x00000000,
185 0x00000000,
186 0x00000000,
187 0x00000000,
188 0x00000000,
189 0x00000000,
190 0x00000000,
191 0x00000000,
192 0x00000000,
193 0x00000000,
194 0x00000000,
195 0x00000000,
196 0x00000000,
197 0x00000000,
198 0x00000000,
199 0x00000000,
200 0x00000000,
201 0x00000000,
202 0x00000000,
203 0x00000000,
204 0x00000000,
205 0x00000000,
206 0x00000000,
207/* 0x0318: memx_func_head */
208 0x00010000,
209 0x00000000,
210 0x0000046f,
211/* 0x0324: memx_func_next */
212 0x00000001,
213 0x00000000,
214 0x00000496,
215 0x00000002,
216 0x00000002,
217 0x000004b7,
218 0x00040003,
219 0x00000000,
220 0x000004df,
221 0x00010004,
222 0x00000000,
223 0x000004fc,
224/* 0x0354: memx_func_tail */
225/* 0x0354: memx_data_head */
226 0x00000000,
227 0x00000000,
228 0x00000000,
229 0x00000000,
230 0x00000000,
231 0x00000000,
232 0x00000000,
233 0x00000000,
234 0x00000000,
235 0x00000000,
236 0x00000000,
237 0x00000000,
238 0x00000000,
239 0x00000000,
240 0x00000000,
241 0x00000000,
242 0x00000000,
243 0x00000000,
244 0x00000000,
245 0x00000000,
246 0x00000000,
247 0x00000000,
248 0x00000000,
249 0x00000000,
250 0x00000000,
251 0x00000000,
252 0x00000000,
253 0x00000000,
254 0x00000000,
255 0x00000000,
256 0x00000000,
257 0x00000000,
258 0x00000000,
259 0x00000000,
260 0x00000000,
261 0x00000000,
262 0x00000000,
263 0x00000000,
264 0x00000000,
265 0x00000000,
266 0x00000000,
267 0x00000000,
268 0x00000000,
269 0x00000000,
270 0x00000000,
271 0x00000000,
272 0x00000000,
273 0x00000000,
274 0x00000000,
275 0x00000000,
276 0x00000000,
277 0x00000000,
278 0x00000000,
279 0x00000000,
280 0x00000000,
281 0x00000000,
282 0x00000000,
283 0x00000000,
284 0x00000000,
285 0x00000000,
286 0x00000000,
287 0x00000000,
288 0x00000000,
289 0x00000000,
290 0x00000000,
291 0x00000000,
292 0x00000000,
293 0x00000000,
294 0x00000000,
295 0x00000000,
296 0x00000000,
297 0x00000000,
298 0x00000000,
299 0x00000000,
300 0x00000000,
301 0x00000000,
302 0x00000000,
303 0x00000000,
304 0x00000000,
305 0x00000000,
306 0x00000000,
307 0x00000000,
308 0x00000000,
309 0x00000000,
310 0x00000000,
311 0x00000000,
312 0x00000000,
313 0x00000000,
314 0x00000000,
315 0x00000000,
316 0x00000000,
317 0x00000000,
318 0x00000000,
319 0x00000000,
320 0x00000000,
321 0x00000000,
322 0x00000000,
323 0x00000000,
324 0x00000000,
325 0x00000000,
326 0x00000000,
327 0x00000000,
328 0x00000000,
329 0x00000000,
330 0x00000000,
331 0x00000000,
332 0x00000000,
333 0x00000000,
334 0x00000000,
335 0x00000000,
336 0x00000000,
337 0x00000000,
338 0x00000000,
339 0x00000000,
340 0x00000000,
341 0x00000000,
342 0x00000000,
343 0x00000000,
344 0x00000000,
345 0x00000000,
346 0x00000000,
347 0x00000000,
348 0x00000000,
349 0x00000000,
350 0x00000000,
351 0x00000000,
352 0x00000000,
353 0x00000000,
354 0x00000000,
355 0x00000000,
356 0x00000000,
357 0x00000000,
358 0x00000000,
359 0x00000000,
360 0x00000000,
361 0x00000000,
362 0x00000000,
363 0x00000000,
364 0x00000000,
365 0x00000000,
366 0x00000000,
367 0x00000000,
368 0x00000000,
369 0x00000000,
370 0x00000000,
371 0x00000000,
372 0x00000000,
373 0x00000000,
374 0x00000000,
375 0x00000000,
376 0x00000000,
377 0x00000000,
378 0x00000000,
379 0x00000000,
380 0x00000000,
381 0x00000000,
382 0x00000000,
383 0x00000000,
384 0x00000000,
385 0x00000000,
386 0x00000000,
387 0x00000000,
388 0x00000000,
389 0x00000000,
390 0x00000000,
391 0x00000000,
392 0x00000000,
393 0x00000000,
394 0x00000000,
395 0x00000000,
396 0x00000000,
397 0x00000000,
398 0x00000000,
399 0x00000000,
400 0x00000000,
401 0x00000000,
402 0x00000000,
403 0x00000000,
404 0x00000000,
405 0x00000000,
406 0x00000000,
407 0x00000000,
408 0x00000000,
409 0x00000000,
410 0x00000000,
411 0x00000000,
412 0x00000000,
413 0x00000000,
414 0x00000000,
415 0x00000000,
416 0x00000000,
417 0x00000000,
418 0x00000000,
419 0x00000000,
420 0x00000000,
421 0x00000000,
422 0x00000000,
423 0x00000000,
424 0x00000000,
425 0x00000000,
426 0x00000000,
427 0x00000000,
428 0x00000000,
429 0x00000000,
430 0x00000000,
431 0x00000000,
432 0x00000000,
433 0x00000000,
434 0x00000000,
435 0x00000000,
436 0x00000000,
437 0x00000000,
438 0x00000000,
439 0x00000000,
440 0x00000000,
441 0x00000000,
442 0x00000000,
443 0x00000000,
444 0x00000000,
445 0x00000000,
446 0x00000000,
447 0x00000000,
448 0x00000000,
449 0x00000000,
450 0x00000000,
451 0x00000000,
452 0x00000000,
453 0x00000000,
454 0x00000000,
455 0x00000000,
456 0x00000000,
457 0x00000000,
458 0x00000000,
459 0x00000000,
460 0x00000000,
461 0x00000000,
462 0x00000000,
463 0x00000000,
464 0x00000000,
465 0x00000000,
466 0x00000000,
467 0x00000000,
468 0x00000000,
469 0x00000000,
470 0x00000000,
471 0x00000000,
472 0x00000000,
473 0x00000000,
474 0x00000000,
475 0x00000000,
476 0x00000000,
477 0x00000000,
478 0x00000000,
479 0x00000000,
480 0x00000000,
481 0x00000000,
482 0x00000000,
483 0x00000000,
484 0x00000000,
485 0x00000000,
486 0x00000000,
487 0x00000000,
488 0x00000000,
489 0x00000000,
490 0x00000000,
491 0x00000000,
492 0x00000000,
493 0x00000000,
494 0x00000000,
495 0x00000000,
496 0x00000000,
497 0x00000000,
498 0x00000000,
499 0x00000000,
500 0x00000000,
501 0x00000000,
502 0x00000000,
503 0x00000000,
504 0x00000000,
505 0x00000000,
506 0x00000000,
507 0x00000000,
508 0x00000000,
509 0x00000000,
510 0x00000000,
511 0x00000000,
512 0x00000000,
513 0x00000000,
514 0x00000000,
515 0x00000000,
516 0x00000000,
517 0x00000000,
518 0x00000000,
519 0x00000000,
520 0x00000000,
521 0x00000000,
522 0x00000000,
523 0x00000000,
524 0x00000000,
525 0x00000000,
526 0x00000000,
527 0x00000000,
528 0x00000000,
529 0x00000000,
530 0x00000000,
531 0x00000000,
532 0x00000000,
533 0x00000000,
534 0x00000000,
535 0x00000000,
536 0x00000000,
537 0x00000000,
538 0x00000000,
539 0x00000000,
540 0x00000000,
541 0x00000000,
542 0x00000000,
543 0x00000000,
544 0x00000000,
545 0x00000000,
546 0x00000000,
547 0x00000000,
548 0x00000000,
549 0x00000000,
550 0x00000000,
551 0x00000000,
552 0x00000000,
553 0x00000000,
554 0x00000000,
555 0x00000000,
556 0x00000000,
557 0x00000000,
558 0x00000000,
559 0x00000000,
560 0x00000000,
561 0x00000000,
562 0x00000000,
563 0x00000000,
564 0x00000000,
565 0x00000000,
566 0x00000000,
567 0x00000000,
568 0x00000000,
569 0x00000000,
570 0x00000000,
571 0x00000000,
572 0x00000000,
573 0x00000000,
574 0x00000000,
575 0x00000000,
576 0x00000000,
577 0x00000000,
578 0x00000000,
579 0x00000000,
580 0x00000000,
581 0x00000000,
582 0x00000000,
583 0x00000000,
584 0x00000000,
585 0x00000000,
586 0x00000000,
587 0x00000000,
588 0x00000000,
589 0x00000000,
590 0x00000000,
591 0x00000000,
592 0x00000000,
593 0x00000000,
594 0x00000000,
595 0x00000000,
596 0x00000000,
597 0x00000000,
598 0x00000000,
599 0x00000000,
600 0x00000000,
601 0x00000000,
602 0x00000000,
603 0x00000000,
604 0x00000000,
605 0x00000000,
606 0x00000000,
607 0x00000000,
608 0x00000000,
609 0x00000000,
610 0x00000000,
611 0x00000000,
612 0x00000000,
613 0x00000000,
614 0x00000000,
615 0x00000000,
616 0x00000000,
617 0x00000000,
618 0x00000000,
619 0x00000000,
620 0x00000000,
621 0x00000000,
622 0x00000000,
623 0x00000000,
624 0x00000000,
625 0x00000000,
626 0x00000000,
627 0x00000000,
628 0x00000000,
629 0x00000000,
630 0x00000000,
631 0x00000000,
632 0x00000000,
633 0x00000000,
634 0x00000000,
635 0x00000000,
636 0x00000000,
637 0x00000000,
638 0x00000000,
639 0x00000000,
640 0x00000000,
641 0x00000000,
642 0x00000000,
643 0x00000000,
644 0x00000000,
645 0x00000000,
646 0x00000000,
647 0x00000000,
648 0x00000000,
649 0x00000000,
650 0x00000000,
651 0x00000000,
652 0x00000000,
653 0x00000000,
654 0x00000000,
655 0x00000000,
656 0x00000000,
657 0x00000000,
658 0x00000000,
659 0x00000000,
660 0x00000000,
661 0x00000000,
662 0x00000000,
663 0x00000000,
664 0x00000000,
665 0x00000000,
666 0x00000000,
667 0x00000000,
668 0x00000000,
669 0x00000000,
670 0x00000000,
671 0x00000000,
672 0x00000000,
673 0x00000000,
674 0x00000000,
675 0x00000000,
676 0x00000000,
677 0x00000000,
678 0x00000000,
679 0x00000000,
680 0x00000000,
681 0x00000000,
682 0x00000000,
683 0x00000000,
684 0x00000000,
685 0x00000000,
686 0x00000000,
687 0x00000000,
688 0x00000000,
689 0x00000000,
690 0x00000000,
691 0x00000000,
692 0x00000000,
693 0x00000000,
694 0x00000000,
695 0x00000000,
696 0x00000000,
697 0x00000000,
698 0x00000000,
699 0x00000000,
700 0x00000000,
701 0x00000000,
702 0x00000000,
703 0x00000000,
704 0x00000000,
705 0x00000000,
706 0x00000000,
707 0x00000000,
708 0x00000000,
709 0x00000000,
710 0x00000000,
711 0x00000000,
712 0x00000000,
713 0x00000000,
714 0x00000000,
715 0x00000000,
716 0x00000000,
717 0x00000000,
718 0x00000000,
719 0x00000000,
720 0x00000000,
721 0x00000000,
722 0x00000000,
723 0x00000000,
724 0x00000000,
725 0x00000000,
726 0x00000000,
727 0x00000000,
728 0x00000000,
729 0x00000000,
730 0x00000000,
731 0x00000000,
732 0x00000000,
733 0x00000000,
734 0x00000000,
735 0x00000000,
736 0x00000000,
737 0x00000000,
738/* 0x0b54: memx_data_tail */
739 0x00000000,
740 0x00000000,
741 0x00000000,
742 0x00000000,
743 0x00000000,
744 0x00000000,
745 0x00000000,
746 0x00000000,
747 0x00000000,
748 0x00000000,
749 0x00000000,
750 0x00000000,
751 0x00000000,
752 0x00000000,
753 0x00000000,
754 0x00000000,
755 0x00000000,
756 0x00000000,
757 0x00000000,
758 0x00000000,
759 0x00000000,
760 0x00000000,
761 0x00000000,
762 0x00000000,
763 0x00000000,
764 0x00000000,
765 0x00000000,
766 0x00000000,
767 0x00000000,
768 0x00000000,
769 0x00000000,
770 0x00000000,
771 0x00000000,
772 0x00000000,
773 0x00000000,
774 0x00000000,
775 0x00000000,
776 0x00000000,
777 0x00000000,
778 0x00000000,
779 0x00000000,
780 0x00000000,
781 0x00000000,
782};
783
784uint32_t nvc0_pwr_code[] = {
785 0x030d0ef5,
786/* 0x0004: rd32 */
787 0x07a007f1,
788 0xd00604b6,
789 0x04bd000e,
790 0xf001e7f0,
791 0x07f101e3,
792 0x04b607ac,
793 0x000ed006,
794/* 0x0022: rd32_wait */
795 0xe7f104bd,
796 0xe4b607ac,
797 0x00eecf06,
798 0x7000e4f1,
799 0xf1f21bf4,
800 0xb607a4d7,
801 0xddcf06d4,
802/* 0x003f: wr32 */
803 0xf100f800,
804 0xb607a007,
805 0x0ed00604,
806 0xf104bd00,
807 0xb607a407,
808 0x0dd00604,
809 0xf004bd00,
810 0xe5f002e7,
811 0x01e3f0f0,
812 0x07ac07f1,
813 0xd00604b6,
814 0x04bd000e,
815/* 0x006c: wr32_wait */
816 0x07ace7f1,
817 0xcf06e4b6,
818 0xe4f100ee,
819 0x1bf47000,
820/* 0x007f: nsec */
821 0xf000f8f2,
822 0x84b62c87,
823 0x0088cf06,
824/* 0x0088: nsec_loop */
825 0xb62c97f0,
826 0x99cf0694,
827 0x0298bb00,
828 0xf4069eb8,
829 0x00f8f11e,
830/* 0x009c: wait */
831 0xb62c87f0,
832 0x88cf0684,
833/* 0x00a5: wait_loop */
834 0x02eeb900,
835 0xb90421f4,
836 0xadfd02da,
837 0x06acb804,
838 0xf0150bf4,
839 0x94b62c97,
840 0x0099cf06,
841 0xb80298bb,
842 0x1ef4069b,
843/* 0x00c9: wait_done */
844/* 0x00cb: intr_watchdog */
845 0x9800f8df,
846 0x96b003e9,
847 0x2a0bf400,
848 0xbb840a98,
849 0x1cf4029a,
850 0x01d7f00f,
851 0x025421f5,
852 0x0ef494bd,
853/* 0x00e9: intr_watchdog_next_time */
854 0x850a9815,
855 0xf400a6b0,
856 0x9ab8090b,
857 0x061cf406,
858/* 0x00f8: intr_watchdog_next_time_set */
859/* 0x00fb: intr_watchdog_next_proc */
860 0x80850980,
861 0xe0b603e9,
862 0x10e6b158,
863 0xc61bf402,
864/* 0x010a: intr */
865 0x00f900f8,
866 0x80f904bd,
867 0xa0f990f9,
868 0xc0f9b0f9,
869 0xe0f9d0f9,
870 0xf7f0f0f9,
871 0x0188fe00,
872 0x87f180f9,
873 0x84b605d0,
874 0x0088cf06,
875 0xf10180b6,
876 0xb605d007,
877 0x08d00604,
878 0xf004bd00,
879 0x84b60887,
880 0x0088cf06,
881 0xf40289c4,
882 0x0080230b,
883 0x58e7f085,
884 0x98cb21f4,
885 0x96b08509,
886 0x110bf400,
887 0xb63407f0,
888 0x09d00604,
889 0x8004bd00,
890/* 0x016e: intr_skip_watchdog */
891 0x89e48409,
892 0x0bf40800,
893 0x8897f148,
894 0x0694b606,
895 0xc40099cf,
896 0x0bf4029a,
897 0xc0c7f12c,
898 0x06c4b604,
899 0xf900cccf,
900 0x48e7f1c0,
901 0x53e3f14f,
902 0x00d7f054,
903 0x02b921f5,
904 0x07f1c0fc,
905 0x04b604c0,
906 0x000cd006,
907/* 0x01ae: intr_subintr_skip_fifo */
908 0x07f104bd,
909 0x04b60688,
910 0x0009d006,
911/* 0x01ba: intr_skip_subintr */
912 0x89c404bd,
913 0x070bf420,
914 0xffbfa4f1,
915/* 0x01c4: intr_skip_pause */
916 0xf44089c4,
917 0xa4f1070b,
918/* 0x01ce: intr_skip_user0 */
919 0x07f0ffbf,
920 0x0604b604,
921 0xbd0008d0,
922 0xfe80fc04,
923 0xf0fc0088,
924 0xd0fce0fc,
925 0xb0fcc0fc,
926 0x90fca0fc,
927 0x00fc80fc,
928 0xf80032f4,
929/* 0x01f5: timer */
930 0x1032f401,
931 0xb003f898,
932 0x1cf40086,
933 0x03fe8051,
934 0xb63807f0,
935 0x08d00604,
936 0xf004bd00,
937 0x84b60887,
938 0x0088cf06,
939 0xf40284f0,
940 0x87f0261b,
941 0x0684b634,
942 0xb80088cf,
943 0x0bf406e0,
944 0x06e8b809,
945/* 0x0233: timer_reset */
946 0xf01f1ef4,
947 0x04b63407,
948 0x000ed006,
949 0x0e8004bd,
950/* 0x0241: timer_enable */
951 0x0187f084,
952 0xb63807f0,
953 0x08d00604,
954/* 0x024f: timer_done */
955 0xf404bd00,
956 0x00f81031,
957/* 0x0254: send_proc */
958 0x90f980f9,
959 0x9805e898,
960 0x86f004e9,
961 0x0689b804,
962 0xc42a0bf4,
963 0x88940398,
964 0x1880b604,
965 0x98008ebb,
966 0x8a8000fa,
967 0x018d8000,
968 0x80028c80,
969 0x90b6038b,
970 0x0794f001,
971 0xf404e980,
972/* 0x028e: send_done */
973 0x90fc0231,
974 0x00f880fc,
975/* 0x0294: find */
976 0x87f080f9,
977 0x0131f458,
978/* 0x029c: find_loop */
979 0xb8008a98,
980 0x0bf406ae,
981 0x5880b610,
982 0x021086b1,
983 0xf4f01bf4,
984/* 0x02b2: find_done */
985 0x8eb90132,
986 0xf880fc02,
987/* 0x02b9: send */
988 0x9421f500,
989 0x9701f402,
990/* 0x02c2: recv */
991 0xe89800f8,
992 0x04e99805,
993 0xb80132f4,
994 0x0bf40689,
995 0x0389c43d,
996 0xf00180b6,
997 0xe8800784,
998 0x02ea9805,
999 0x8ffef0f9,
1000 0xb9f0f901,
1001 0x999402ef,
1002 0x00e9bb04,
1003 0x9818e0b6,
1004 0xec9803eb,
1005 0x01ed9802,
1006 0xf900ee98,
1007 0xfef0fca5,
1008 0x31f400f8,
1009/* 0x030b: recv_done */
1010 0xf8f0fc01,
1011/* 0x030d: init */
1012 0x0817f100,
1013 0x0614b601,
1014 0xe70011cf,
1015 0xb6010911,
1016 0x14fe0814,
1017 0xe017f100,
1018 0x0013f000,
1019 0xb61c07f0,
1020 0x01d00604,
1021 0xf004bd00,
1022 0x07f0ff17,
1023 0x0604b614,
1024 0xbd0001d0,
1025 0x0217f004,
1026 0x080015f1,
1027 0xb61007f0,
1028 0x01d00604,
1029 0xf104bd00,
1030 0xf0010a17,
1031 0x10fe0013,
1032 0x1031f400,
1033 0xf00117f0,
1034 0x04b63807,
1035 0x0001d006,
1036 0xf7f004bd,
1037/* 0x0371: init_proc */
1038 0x01f19858,
1039 0xf40016b0,
1040 0x15f9fa0b,
1041 0xf458f0b6,
1042/* 0x0382: host_send */
1043 0x17f1f20e,
1044 0x14b604b0,
1045 0x0011cf06,
1046 0x04a027f1,
1047 0xcf0624b6,
1048 0x12b80022,
1049 0x320bf406,
1050 0x94071ec4,
1051 0xe0b704ee,
1052 0xeb980218,
1053 0x02ec9803,
1054 0x9801ed98,
1055 0x21f500ee,
1056 0x10b602b9,
1057 0x0f1ec401,
1058 0x04b007f1,
1059 0xd00604b6,
1060 0x04bd0001,
1061/* 0x03cb: host_send_done */
1062 0xf8ba0ef4,
1063/* 0x03cd: host_recv */
1064 0x4917f100,
1065 0x5413f14e,
1066 0x06e1b852,
1067/* 0x03db: host_recv_wait */
1068 0xf1aa0bf4,
1069 0xb604cc17,
1070 0x11cf0614,
1071 0xc827f100,
1072 0x0624b604,
1073 0xf00022cf,
1074 0x12b80816,
1075 0xe60bf406,
1076 0xb60723c4,
1077 0x30b70434,
1078 0x3b800298,
1079 0x023c8003,
1080 0x80013d80,
1081 0x20b6003e,
1082 0x0f24f001,
1083 0x04c807f1,
1084 0xd00604b6,
1085 0x04bd0002,
1086 0xf04027f0,
1087 0x04b60007,
1088 0x0002d006,
1089 0x00f804bd,
1090/* 0x0430: host_init */
1091 0x008017f1,
1092 0xf11014b6,
1093 0xf1021815,
1094 0xb604d007,
1095 0x01d00604,
1096 0xf104bd00,
1097 0xb6008017,
1098 0x15f11014,
1099 0x07f10298,
1100 0x04b604dc,
1101 0x0001d006,
1102 0x17f004bd,
1103 0xc407f101,
1104 0x0604b604,
1105 0xbd0001d0,
1106/* 0x046f: memx_func_enter */
1107 0xf000f804,
1108 0x07f10467,
1109 0x04b607e0,
1110 0x0006d006,
1111/* 0x047e: memx_func_enter_wait */
1112 0x67f104bd,
1113 0x64b607c0,
1114 0x0066cf06,
1115 0xf40464f0,
1116 0x1698f30b,
1117 0x0410b600,
1118/* 0x0496: memx_func_leave */
1119 0x67f000f8,
1120 0xe407f104,
1121 0x0604b607,
1122 0xbd0006d0,
1123/* 0x04a5: memx_func_leave_wait */
1124 0xc067f104,
1125 0x0664b607,
1126 0xf00066cf,
1127 0x1bf40464,
1128/* 0x04b7: memx_func_wr32 */
1129 0x9800f8f3,
1130 0x15980016,
1131 0x0810b601,
1132 0x50f960f9,
1133 0xe0fcd0fc,
1134 0xf13f21f4,
1135 0xfd140003,
1136 0x05800506,
1137 0xb604bd00,
1138 0x1bf40242,
1139/* 0x04df: memx_func_wait */
1140 0xf000f8dd,
1141 0x84b62c87,
1142 0x0088cf06,
1143 0x98001e98,
1144 0x1c98011d,
1145 0x031b9802,
1146 0xf41010b6,
1147 0x00f89c21,
1148/* 0x04fc: memx_func_delay */
1149 0xb6001e98,
1150 0x21f40410,
1151/* 0x0507: memx_exec */
1152 0xf900f87f,
1153 0xb9d0f9e0,
1154 0xb2b902c1,
1155/* 0x0511: memx_exec_next */
1156 0x00139802,
1157 0x950410b6,
1158 0x30f01034,
1159 0xc835980c,
1160 0x12b855f9,
1161 0xec1ef406,
1162 0xe0fcd0fc,
1163 0x02b921f5,
1164/* 0x0532: memx_info */
1165 0xc7f100f8,
1166 0xb7f10354,
1167 0x21f50800,
1168 0x00f802b9,
1169/* 0x0540: memx_recv */
1170 0xf401d6b0,
1171 0xd6b0c40b,
1172 0xe90bf400,
1173/* 0x054e: memx_init */
1174 0x00f800f8,
1175/* 0x0550: perf_recv */
1176/* 0x0552: perf_init */
1177 0x00f800f8,
1178/* 0x0554: test_recv */
1179 0x05d817f1,
1180 0xcf0614b6,
1181 0x10b60011,
1182 0xd807f101,
1183 0x0604b605,
1184 0xbd0001d0,
1185 0x00e7f104,
1186 0x4fe3f1d9,
1187 0xf521f513,
1188/* 0x057b: test_init */
1189 0xf100f801,
1190 0xf50800e7,
1191 0xf801f521,
1192/* 0x0585: idle_recv */
1193/* 0x0587: idle */
1194 0xf400f800,
1195 0x17f10031,
1196 0x14b605d4,
1197 0x0011cf06,
1198 0xf10110b6,
1199 0xb605d407,
1200 0x01d00604,
1201/* 0x05a3: idle_loop */
1202 0xf004bd00,
1203 0x32f45817,
1204/* 0x05a9: idle_proc */
1205/* 0x05a9: idle_proc_exec */
1206 0xb910f902,
1207 0x21f5021e,
1208 0x10fc02c2,
1209 0xf40911f4,
1210 0x0ef40231,
1211/* 0x05bd: idle_proc_next */
1212 0x5810b6ef,
1213 0xf4061fb8,
1214 0x02f4e61b,
1215 0x0028f4dd,
1216 0x00bb0ef4,
1217 0x00000000,
1218 0x00000000,
1219 0x00000000,
1220 0x00000000,
1221 0x00000000,
1222 0x00000000,
1223 0x00000000,
1224 0x00000000,
1225 0x00000000,
1226 0x00000000,
1227 0x00000000,
1228 0x00000000,
1229};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc
new file mode 100644
index 000000000000..32d65ea254dd
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc
@@ -0,0 +1,63 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#define NVKM_PPWR_CHIPSET GF119
26
27//#define NVKM_FALCON_PC24
28#define NVKM_FALCON_UNSHIFTED_IO
29//#define NVKM_FALCON_MMIO_UAS
30//#define NVKM_FALCON_MMIO_TRAP
31
32#include "macros.fuc"
33
34.section #nvd0_pwr_data
35#define INCLUDE_PROC
36#include "kernel.fuc"
37#include "host.fuc"
38#include "memx.fuc"
39#include "perf.fuc"
40#include "test.fuc"
41#include "idle.fuc"
42#undef INCLUDE_PROC
43
44#define INCLUDE_DATA
45#include "kernel.fuc"
46#include "host.fuc"
47#include "memx.fuc"
48#include "perf.fuc"
49#include "test.fuc"
50#include "idle.fuc"
51#undef INCLUDE_DATA
52.align 256
53
54.section #nvd0_pwr_code
55#define INCLUDE_CODE
56#include "kernel.fuc"
57#include "host.fuc"
58#include "memx.fuc"
59#include "perf.fuc"
60#include "test.fuc"
61#include "idle.fuc"
62#undef INCLUDE_CODE
63.align 256
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h
new file mode 100644
index 000000000000..ce65e2a4b789
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h
@@ -0,0 +1,1229 @@
1uint32_t nvd0_pwr_data[] = {
2/* 0x0000: proc_kern */
3 0x52544e49,
4 0x00000000,
5 0x00000000,
6 0x00000000,
7 0x00000000,
8 0x00000000,
9 0x00000000,
10 0x00000000,
11 0x00000000,
12 0x00000000,
13 0x00000000,
14 0x00000000,
15 0x00000000,
16 0x00000000,
17 0x00000000,
18 0x00000000,
19 0x00000000,
20 0x00000000,
21 0x00000000,
22 0x00000000,
23 0x00000000,
24 0x00000000,
25/* 0x0058: proc_list_head */
26 0x54534f48,
27 0x000003be,
28 0x00000367,
29 0x00000000,
30 0x00000000,
31 0x00000000,
32 0x00000000,
33 0x00000000,
34 0x00000000,
35 0x00000000,
36 0x00000000,
37 0x00000000,
38 0x00000000,
39 0x00000000,
40 0x00000000,
41 0x00000000,
42 0x00000000,
43 0x00000000,
44 0x00000000,
45 0x00000000,
46 0x00000000,
47 0x00000000,
48 0x584d454d,
49 0x000004c4,
50 0x000004b6,
51 0x00000000,
52 0x00000000,
53 0x00000000,
54 0x00000000,
55 0x00000000,
56 0x00000000,
57 0x00000000,
58 0x00000000,
59 0x00000000,
60 0x00000000,
61 0x00000000,
62 0x00000000,
63 0x00000000,
64 0x00000000,
65 0x00000000,
66 0x00000000,
67 0x00000000,
68 0x00000000,
69 0x00000000,
70 0x46524550,
71 0x000004c8,
72 0x000004c6,
73 0x00000000,
74 0x00000000,
75 0x00000000,
76 0x00000000,
77 0x00000000,
78 0x00000000,
79 0x00000000,
80 0x00000000,
81 0x00000000,
82 0x00000000,
83 0x00000000,
84 0x00000000,
85 0x00000000,
86 0x00000000,
87 0x00000000,
88 0x00000000,
89 0x00000000,
90 0x00000000,
91 0x00000000,
92 0x54534554,
93 0x000004eb,
94 0x000004ca,
95 0x00000000,
96 0x00000000,
97 0x00000000,
98 0x00000000,
99 0x00000000,
100 0x00000000,
101 0x00000000,
102 0x00000000,
103 0x00000000,
104 0x00000000,
105 0x00000000,
106 0x00000000,
107 0x00000000,
108 0x00000000,
109 0x00000000,
110 0x00000000,
111 0x00000000,
112 0x00000000,
113 0x00000000,
114 0x454c4449,
115 0x000004f7,
116 0x000004f5,
117 0x00000000,
118 0x00000000,
119 0x00000000,
120 0x00000000,
121 0x00000000,
122 0x00000000,
123 0x00000000,
124 0x00000000,
125 0x00000000,
126 0x00000000,
127 0x00000000,
128 0x00000000,
129 0x00000000,
130 0x00000000,
131 0x00000000,
132 0x00000000,
133 0x00000000,
134 0x00000000,
135 0x00000000,
136/* 0x0210: proc_list_tail */
137/* 0x0210: time_prev */
138 0x00000000,
139/* 0x0214: time_next */
140 0x00000000,
141/* 0x0218: fifo_queue */
142 0x00000000,
143 0x00000000,
144 0x00000000,
145 0x00000000,
146 0x00000000,
147 0x00000000,
148 0x00000000,
149 0x00000000,
150 0x00000000,
151 0x00000000,
152 0x00000000,
153 0x00000000,
154 0x00000000,
155 0x00000000,
156 0x00000000,
157 0x00000000,
158 0x00000000,
159 0x00000000,
160 0x00000000,
161 0x00000000,
162 0x00000000,
163 0x00000000,
164 0x00000000,
165 0x00000000,
166 0x00000000,
167 0x00000000,
168 0x00000000,
169 0x00000000,
170 0x00000000,
171 0x00000000,
172 0x00000000,
173 0x00000000,
174/* 0x0298: rfifo_queue */
175 0x00000000,
176 0x00000000,
177 0x00000000,
178 0x00000000,
179 0x00000000,
180 0x00000000,
181 0x00000000,
182 0x00000000,
183 0x00000000,
184 0x00000000,
185 0x00000000,
186 0x00000000,
187 0x00000000,
188 0x00000000,
189 0x00000000,
190 0x00000000,
191 0x00000000,
192 0x00000000,
193 0x00000000,
194 0x00000000,
195 0x00000000,
196 0x00000000,
197 0x00000000,
198 0x00000000,
199 0x00000000,
200 0x00000000,
201 0x00000000,
202 0x00000000,
203 0x00000000,
204 0x00000000,
205 0x00000000,
206 0x00000000,
207/* 0x0318: memx_func_head */
208 0x00010000,
209 0x00000000,
210 0x000003f4,
211/* 0x0324: memx_func_next */
212 0x00000001,
213 0x00000000,
214 0x00000415,
215 0x00000002,
216 0x00000002,
217 0x00000430,
218 0x00040003,
219 0x00000000,
220 0x00000458,
221 0x00010004,
222 0x00000000,
223 0x00000472,
224/* 0x0354: memx_func_tail */
225/* 0x0354: memx_data_head */
226 0x00000000,
227 0x00000000,
228 0x00000000,
229 0x00000000,
230 0x00000000,
231 0x00000000,
232 0x00000000,
233 0x00000000,
234 0x00000000,
235 0x00000000,
236 0x00000000,
237 0x00000000,
238 0x00000000,
239 0x00000000,
240 0x00000000,
241 0x00000000,
242 0x00000000,
243 0x00000000,
244 0x00000000,
245 0x00000000,
246 0x00000000,
247 0x00000000,
248 0x00000000,
249 0x00000000,
250 0x00000000,
251 0x00000000,
252 0x00000000,
253 0x00000000,
254 0x00000000,
255 0x00000000,
256 0x00000000,
257 0x00000000,
258 0x00000000,
259 0x00000000,
260 0x00000000,
261 0x00000000,
262 0x00000000,
263 0x00000000,
264 0x00000000,
265 0x00000000,
266 0x00000000,
267 0x00000000,
268 0x00000000,
269 0x00000000,
270 0x00000000,
271 0x00000000,
272 0x00000000,
273 0x00000000,
274 0x00000000,
275 0x00000000,
276 0x00000000,
277 0x00000000,
278 0x00000000,
279 0x00000000,
280 0x00000000,
281 0x00000000,
282 0x00000000,
283 0x00000000,
284 0x00000000,
285 0x00000000,
286 0x00000000,
287 0x00000000,
288 0x00000000,
289 0x00000000,
290 0x00000000,
291 0x00000000,
292 0x00000000,
293 0x00000000,
294 0x00000000,
295 0x00000000,
296 0x00000000,
297 0x00000000,
298 0x00000000,
299 0x00000000,
300 0x00000000,
301 0x00000000,
302 0x00000000,
303 0x00000000,
304 0x00000000,
305 0x00000000,
306 0x00000000,
307 0x00000000,
308 0x00000000,
309 0x00000000,
310 0x00000000,
311 0x00000000,
312 0x00000000,
313 0x00000000,
314 0x00000000,
315 0x00000000,
316 0x00000000,
317 0x00000000,
318 0x00000000,
319 0x00000000,
320 0x00000000,
321 0x00000000,
322 0x00000000,
323 0x00000000,
324 0x00000000,
325 0x00000000,
326 0x00000000,
327 0x00000000,
328 0x00000000,
329 0x00000000,
330 0x00000000,
331 0x00000000,
332 0x00000000,
333 0x00000000,
334 0x00000000,
335 0x00000000,
336 0x00000000,
337 0x00000000,
338 0x00000000,
339 0x00000000,
340 0x00000000,
341 0x00000000,
342 0x00000000,
343 0x00000000,
344 0x00000000,
345 0x00000000,
346 0x00000000,
347 0x00000000,
348 0x00000000,
349 0x00000000,
350 0x00000000,
351 0x00000000,
352 0x00000000,
353 0x00000000,
354 0x00000000,
355 0x00000000,
356 0x00000000,
357 0x00000000,
358 0x00000000,
359 0x00000000,
360 0x00000000,
361 0x00000000,
362 0x00000000,
363 0x00000000,
364 0x00000000,
365 0x00000000,
366 0x00000000,
367 0x00000000,
368 0x00000000,
369 0x00000000,
370 0x00000000,
371 0x00000000,
372 0x00000000,
373 0x00000000,
374 0x00000000,
375 0x00000000,
376 0x00000000,
377 0x00000000,
378 0x00000000,
379 0x00000000,
380 0x00000000,
381 0x00000000,
382 0x00000000,
383 0x00000000,
384 0x00000000,
385 0x00000000,
386 0x00000000,
387 0x00000000,
388 0x00000000,
389 0x00000000,
390 0x00000000,
391 0x00000000,
392 0x00000000,
393 0x00000000,
394 0x00000000,
395 0x00000000,
396 0x00000000,
397 0x00000000,
398 0x00000000,
399 0x00000000,
400 0x00000000,
401 0x00000000,
402 0x00000000,
403 0x00000000,
404 0x00000000,
405 0x00000000,
406 0x00000000,
407 0x00000000,
408 0x00000000,
409 0x00000000,
410 0x00000000,
411 0x00000000,
412 0x00000000,
413 0x00000000,
414 0x00000000,
415 0x00000000,
416 0x00000000,
417 0x00000000,
418 0x00000000,
419 0x00000000,
420 0x00000000,
421 0x00000000,
422 0x00000000,
423 0x00000000,
424 0x00000000,
425 0x00000000,
426 0x00000000,
427 0x00000000,
428 0x00000000,
429 0x00000000,
430 0x00000000,
431 0x00000000,
432 0x00000000,
433 0x00000000,
434 0x00000000,
435 0x00000000,
436 0x00000000,
437 0x00000000,
438 0x00000000,
439 0x00000000,
440 0x00000000,
441 0x00000000,
442 0x00000000,
443 0x00000000,
444 0x00000000,
445 0x00000000,
446 0x00000000,
447 0x00000000,
448 0x00000000,
449 0x00000000,
450 0x00000000,
451 0x00000000,
452 0x00000000,
453 0x00000000,
454 0x00000000,
455 0x00000000,
456 0x00000000,
457 0x00000000,
458 0x00000000,
459 0x00000000,
460 0x00000000,
461 0x00000000,
462 0x00000000,
463 0x00000000,
464 0x00000000,
465 0x00000000,
466 0x00000000,
467 0x00000000,
468 0x00000000,
469 0x00000000,
470 0x00000000,
471 0x00000000,
472 0x00000000,
473 0x00000000,
474 0x00000000,
475 0x00000000,
476 0x00000000,
477 0x00000000,
478 0x00000000,
479 0x00000000,
480 0x00000000,
481 0x00000000,
482 0x00000000,
483 0x00000000,
484 0x00000000,
485 0x00000000,
486 0x00000000,
487 0x00000000,
488 0x00000000,
489 0x00000000,
490 0x00000000,
491 0x00000000,
492 0x00000000,
493 0x00000000,
494 0x00000000,
495 0x00000000,
496 0x00000000,
497 0x00000000,
498 0x00000000,
499 0x00000000,
500 0x00000000,
501 0x00000000,
502 0x00000000,
503 0x00000000,
504 0x00000000,
505 0x00000000,
506 0x00000000,
507 0x00000000,
508 0x00000000,
509 0x00000000,
510 0x00000000,
511 0x00000000,
512 0x00000000,
513 0x00000000,
514 0x00000000,
515 0x00000000,
516 0x00000000,
517 0x00000000,
518 0x00000000,
519 0x00000000,
520 0x00000000,
521 0x00000000,
522 0x00000000,
523 0x00000000,
524 0x00000000,
525 0x00000000,
526 0x00000000,
527 0x00000000,
528 0x00000000,
529 0x00000000,
530 0x00000000,
531 0x00000000,
532 0x00000000,
533 0x00000000,
534 0x00000000,
535 0x00000000,
536 0x00000000,
537 0x00000000,
538 0x00000000,
539 0x00000000,
540 0x00000000,
541 0x00000000,
542 0x00000000,
543 0x00000000,
544 0x00000000,
545 0x00000000,
546 0x00000000,
547 0x00000000,
548 0x00000000,
549 0x00000000,
550 0x00000000,
551 0x00000000,
552 0x00000000,
553 0x00000000,
554 0x00000000,
555 0x00000000,
556 0x00000000,
557 0x00000000,
558 0x00000000,
559 0x00000000,
560 0x00000000,
561 0x00000000,
562 0x00000000,
563 0x00000000,
564 0x00000000,
565 0x00000000,
566 0x00000000,
567 0x00000000,
568 0x00000000,
569 0x00000000,
570 0x00000000,
571 0x00000000,
572 0x00000000,
573 0x00000000,
574 0x00000000,
575 0x00000000,
576 0x00000000,
577 0x00000000,
578 0x00000000,
579 0x00000000,
580 0x00000000,
581 0x00000000,
582 0x00000000,
583 0x00000000,
584 0x00000000,
585 0x00000000,
586 0x00000000,
587 0x00000000,
588 0x00000000,
589 0x00000000,
590 0x00000000,
591 0x00000000,
592 0x00000000,
593 0x00000000,
594 0x00000000,
595 0x00000000,
596 0x00000000,
597 0x00000000,
598 0x00000000,
599 0x00000000,
600 0x00000000,
601 0x00000000,
602 0x00000000,
603 0x00000000,
604 0x00000000,
605 0x00000000,
606 0x00000000,
607 0x00000000,
608 0x00000000,
609 0x00000000,
610 0x00000000,
611 0x00000000,
612 0x00000000,
613 0x00000000,
614 0x00000000,
615 0x00000000,
616 0x00000000,
617 0x00000000,
618 0x00000000,
619 0x00000000,
620 0x00000000,
621 0x00000000,
622 0x00000000,
623 0x00000000,
624 0x00000000,
625 0x00000000,
626 0x00000000,
627 0x00000000,
628 0x00000000,
629 0x00000000,
630 0x00000000,
631 0x00000000,
632 0x00000000,
633 0x00000000,
634 0x00000000,
635 0x00000000,
636 0x00000000,
637 0x00000000,
638 0x00000000,
639 0x00000000,
640 0x00000000,
641 0x00000000,
642 0x00000000,
643 0x00000000,
644 0x00000000,
645 0x00000000,
646 0x00000000,
647 0x00000000,
648 0x00000000,
649 0x00000000,
650 0x00000000,
651 0x00000000,
652 0x00000000,
653 0x00000000,
654 0x00000000,
655 0x00000000,
656 0x00000000,
657 0x00000000,
658 0x00000000,
659 0x00000000,
660 0x00000000,
661 0x00000000,
662 0x00000000,
663 0x00000000,
664 0x00000000,
665 0x00000000,
666 0x00000000,
667 0x00000000,
668 0x00000000,
669 0x00000000,
670 0x00000000,
671 0x00000000,
672 0x00000000,
673 0x00000000,
674 0x00000000,
675 0x00000000,
676 0x00000000,
677 0x00000000,
678 0x00000000,
679 0x00000000,
680 0x00000000,
681 0x00000000,
682 0x00000000,
683 0x00000000,
684 0x00000000,
685 0x00000000,
686 0x00000000,
687 0x00000000,
688 0x00000000,
689 0x00000000,
690 0x00000000,
691 0x00000000,
692 0x00000000,
693 0x00000000,
694 0x00000000,
695 0x00000000,
696 0x00000000,
697 0x00000000,
698 0x00000000,
699 0x00000000,
700 0x00000000,
701 0x00000000,
702 0x00000000,
703 0x00000000,
704 0x00000000,
705 0x00000000,
706 0x00000000,
707 0x00000000,
708 0x00000000,
709 0x00000000,
710 0x00000000,
711 0x00000000,
712 0x00000000,
713 0x00000000,
714 0x00000000,
715 0x00000000,
716 0x00000000,
717 0x00000000,
718 0x00000000,
719 0x00000000,
720 0x00000000,
721 0x00000000,
722 0x00000000,
723 0x00000000,
724 0x00000000,
725 0x00000000,
726 0x00000000,
727 0x00000000,
728 0x00000000,
729 0x00000000,
730 0x00000000,
731 0x00000000,
732 0x00000000,
733 0x00000000,
734 0x00000000,
735 0x00000000,
736 0x00000000,
737 0x00000000,
738/* 0x0b54: memx_data_tail */
739 0x00000000,
740 0x00000000,
741 0x00000000,
742 0x00000000,
743 0x00000000,
744 0x00000000,
745 0x00000000,
746 0x00000000,
747 0x00000000,
748 0x00000000,
749 0x00000000,
750 0x00000000,
751 0x00000000,
752 0x00000000,
753 0x00000000,
754 0x00000000,
755 0x00000000,
756 0x00000000,
757 0x00000000,
758 0x00000000,
759 0x00000000,
760 0x00000000,
761 0x00000000,
762 0x00000000,
763 0x00000000,
764 0x00000000,
765 0x00000000,
766 0x00000000,
767 0x00000000,
768 0x00000000,
769 0x00000000,
770 0x00000000,
771 0x00000000,
772 0x00000000,
773 0x00000000,
774 0x00000000,
775 0x00000000,
776 0x00000000,
777 0x00000000,
778 0x00000000,
779 0x00000000,
780 0x00000000,
781 0x00000000,
782};
783
784uint32_t nvd0_pwr_code[] = {
785 0x02bf0ef5,
786/* 0x0004: rd32 */
787 0x07a007f1,
788 0xbd000ed0,
789 0x01e7f004,
790 0xf101e3f0,
791 0xd007ac07,
792 0x04bd000e,
793/* 0x001c: rd32_wait */
794 0x07ace7f1,
795 0xf100eecf,
796 0xf47000e4,
797 0xd7f1f51b,
798 0xddcf07a4,
799/* 0x0033: wr32 */
800 0xf100f800,
801 0xd007a007,
802 0x04bd000e,
803 0x07a407f1,
804 0xbd000dd0,
805 0x02e7f004,
806 0xf0f0e5f0,
807 0x07f101e3,
808 0x0ed007ac,
809/* 0x0057: wr32_wait */
810 0xf104bd00,
811 0xcf07ace7,
812 0xe4f100ee,
813 0x1bf47000,
814/* 0x0067: nsec */
815 0xf000f8f5,
816 0x88cf2c87,
817/* 0x006d: nsec_loop */
818 0x2c97f000,
819 0xbb0099cf,
820 0x9eb80298,
821 0xf41ef406,
822/* 0x007e: wait */
823 0x87f000f8,
824 0x0088cf2c,
825/* 0x0084: wait_loop */
826 0xf402eeb9,
827 0xdab90421,
828 0x04adfd02,
829 0xf406acb8,
830 0x97f0120b,
831 0x0099cf2c,
832 0xb80298bb,
833 0x1ef4069b,
834/* 0x00a5: wait_done */
835/* 0x00a7: intr_watchdog */
836 0x9800f8e2,
837 0x96b003e9,
838 0x2a0bf400,
839 0xbb840a98,
840 0x1cf4029a,
841 0x01d7f00f,
842 0x020621f5,
843 0x0ef494bd,
844/* 0x00c5: intr_watchdog_next_time */
845 0x850a9815,
846 0xf400a6b0,
847 0x9ab8090b,
848 0x061cf406,
849/* 0x00d4: intr_watchdog_next_time_set */
850/* 0x00d7: intr_watchdog_next_proc */
851 0x80850980,
852 0xe0b603e9,
853 0x10e6b158,
854 0xc61bf402,
855/* 0x00e6: intr */
856 0x00f900f8,
857 0x80f904bd,
858 0xa0f990f9,
859 0xc0f9b0f9,
860 0xe0f9d0f9,
861 0xf7f0f0f9,
862 0x0188fe00,
863 0x87f180f9,
864 0x88cf05d0,
865 0x0180b600,
866 0x05d007f1,
867 0xbd0008d0,
868 0x0887f004,
869 0xc40088cf,
870 0x0bf40289,
871 0x85008020,
872 0xf458e7f0,
873 0x0998a721,
874 0x0096b085,
875 0xf00e0bf4,
876 0x09d03407,
877 0x8004bd00,
878/* 0x013e: intr_skip_watchdog */
879 0x89e48409,
880 0x0bf40800,
881 0x8897f13c,
882 0x0099cf06,
883 0xf4029ac4,
884 0xc7f1260b,
885 0xcccf04c0,
886 0xf1c0f900,
887 0xf14f48e7,
888 0xf05453e3,
889 0x21f500d7,
890 0xc0fc026b,
891 0x04c007f1,
892 0xbd000cd0,
893/* 0x0175: intr_subintr_skip_fifo */
894 0x8807f104,
895 0x0009d006,
896/* 0x017e: intr_skip_subintr */
897 0x89c404bd,
898 0x070bf420,
899 0xffbfa4f1,
900/* 0x0188: intr_skip_pause */
901 0xf44089c4,
902 0xa4f1070b,
903/* 0x0192: intr_skip_user0 */
904 0x07f0ffbf,
905 0x0008d004,
906 0x80fc04bd,
907 0xfc0088fe,
908 0xfce0fcf0,
909 0xfcc0fcd0,
910 0xfca0fcb0,
911 0xfc80fc90,
912 0x0032f400,
913/* 0x01b6: timer */
914 0x32f401f8,
915 0x03f89810,
916 0xf40086b0,
917 0xfe80421c,
918 0x3807f003,
919 0xbd0008d0,
920 0x0887f004,
921 0xf00088cf,
922 0x1bf40284,
923 0x3487f020,
924 0xb80088cf,
925 0x0bf406e0,
926 0x06e8b809,
927/* 0x01eb: timer_reset */
928 0xf0191ef4,
929 0x0ed03407,
930 0x8004bd00,
931/* 0x01f6: timer_enable */
932 0x87f0840e,
933 0x3807f001,
934 0xbd0008d0,
935/* 0x0201: timer_done */
936 0x1031f404,
937/* 0x0206: send_proc */
938 0x80f900f8,
939 0xe89890f9,
940 0x04e99805,
941 0xb80486f0,
942 0x0bf40689,
943 0x0398c42a,
944 0xb6048894,
945 0x8ebb1880,
946 0x00fa9800,
947 0x80008a80,
948 0x8c80018d,
949 0x038b8002,
950 0xf00190b6,
951 0xe9800794,
952 0x0231f404,
953/* 0x0240: send_done */
954 0x80fc90fc,
955/* 0x0246: find */
956 0x80f900f8,
957 0xf45887f0,
958/* 0x024e: find_loop */
959 0x8a980131,
960 0x06aeb800,
961 0xb6100bf4,
962 0x86b15880,
963 0x1bf40210,
964 0x0132f4f0,
965/* 0x0264: find_done */
966 0xfc028eb9,
967/* 0x026b: send */
968 0xf500f880,
969 0xf4024621,
970 0x00f89701,
971/* 0x0274: recv */
972 0x9805e898,
973 0x32f404e9,
974 0x0689b801,
975 0xc43d0bf4,
976 0x80b60389,
977 0x0784f001,
978 0x9805e880,
979 0xf0f902ea,
980 0xf9018ffe,
981 0x02efb9f0,
982 0xbb049994,
983 0xe0b600e9,
984 0x03eb9818,
985 0x9802ec98,
986 0xee9801ed,
987 0xfca5f900,
988 0x00f8fef0,
989 0xfc0131f4,
990/* 0x02bd: recv_done */
991/* 0x02bf: init */
992 0xf100f8f0,
993 0xcf010817,
994 0x11e70011,
995 0x14b60109,
996 0x0014fe08,
997 0x00e017f1,
998 0xf00013f0,
999 0x01d01c07,
1000 0xf004bd00,
1001 0x07f0ff17,
1002 0x0001d014,
1003 0x17f004bd,
1004 0x0015f102,
1005 0x1007f008,
1006 0xbd0001d0,
1007 0xe617f104,
1008 0x0013f000,
1009 0xf40010fe,
1010 0x17f01031,
1011 0x3807f001,
1012 0xbd0001d0,
1013 0x58f7f004,
1014/* 0x0314: init_proc */
1015 0xb001f198,
1016 0x0bf40016,
1017 0xb615f9fa,
1018 0x0ef458f0,
1019/* 0x0325: host_send */
1020 0xb017f1f2,
1021 0x0011cf04,
1022 0x04a027f1,
1023 0xb80022cf,
1024 0x0bf40612,
1025 0x071ec42f,
1026 0xb704ee94,
1027 0x980218e0,
1028 0xec9803eb,
1029 0x01ed9802,
1030 0xf500ee98,
1031 0xb6026b21,
1032 0x1ec40110,
1033 0xb007f10f,
1034 0x0001d004,
1035 0x0ef404bd,
1036/* 0x0365: host_send_done */
1037/* 0x0367: host_recv */
1038 0xf100f8c3,
1039 0xf14e4917,
1040 0xb8525413,
1041 0x0bf406e1,
1042/* 0x0375: host_recv_wait */
1043 0xcc17f1b3,
1044 0x0011cf04,
1045 0x04c827f1,
1046 0xf00022cf,
1047 0x12b80816,
1048 0xec0bf406,
1049 0xb60723c4,
1050 0x30b70434,
1051 0x3b800298,
1052 0x023c8003,
1053 0x80013d80,
1054 0x20b6003e,
1055 0x0f24f001,
1056 0x04c807f1,
1057 0xbd0002d0,
1058 0x4027f004,
1059 0xd00007f0,
1060 0x04bd0002,
1061/* 0x03be: host_init */
1062 0x17f100f8,
1063 0x14b60080,
1064 0x1815f110,
1065 0xd007f102,
1066 0x0001d004,
1067 0x17f104bd,
1068 0x14b60080,
1069 0x9815f110,
1070 0xdc07f102,
1071 0x0001d004,
1072 0x17f004bd,
1073 0xc407f101,
1074 0x0001d004,
1075 0x00f804bd,
1076/* 0x03f4: memx_func_enter */
1077 0xf10467f0,
1078 0xd007e007,
1079 0x04bd0006,
1080/* 0x0400: memx_func_enter_wait */
1081 0x07c067f1,
1082 0xf00066cf,
1083 0x0bf40464,
1084 0x001698f6,
1085 0xf80410b6,
1086/* 0x0415: memx_func_leave */
1087 0x0467f000,
1088 0x07e407f1,
1089 0xbd0006d0,
1090/* 0x0421: memx_func_leave_wait */
1091 0xc067f104,
1092 0x0066cf07,
1093 0xf40464f0,
1094 0x00f8f61b,
1095/* 0x0430: memx_func_wr32 */
1096 0x98001698,
1097 0x10b60115,
1098 0xf960f908,
1099 0xfcd0fc50,
1100 0x3321f4e0,
1101 0x140003f1,
1102 0x800506fd,
1103 0x04bd0005,
1104 0xf40242b6,
1105 0x00f8dd1b,
1106/* 0x0458: memx_func_wait */
1107 0xcf2c87f0,
1108 0x1e980088,
1109 0x011d9800,
1110 0x98021c98,
1111 0x10b6031b,
1112 0x7e21f410,
1113/* 0x0472: memx_func_delay */
1114 0x1e9800f8,
1115 0x0410b600,
1116 0xf86721f4,
1117/* 0x047d: memx_exec */
1118 0xf9e0f900,
1119 0x02c1b9d0,
1120/* 0x0487: memx_exec_next */
1121 0x9802b2b9,
1122 0x10b60013,
1123 0x10349504,
1124 0x980c30f0,
1125 0x55f9c835,
1126 0xf40612b8,
1127 0xd0fcec1e,
1128 0x21f5e0fc,
1129 0x00f8026b,
1130/* 0x04a8: memx_info */
1131 0x0354c7f1,
1132 0x0800b7f1,
1133 0x026b21f5,
1134/* 0x04b6: memx_recv */
1135 0xd6b000f8,
1136 0xc40bf401,
1137 0xf400d6b0,
1138 0x00f8e90b,
1139/* 0x04c4: memx_init */
1140/* 0x04c6: perf_recv */
1141 0x00f800f8,
1142/* 0x04c8: perf_init */
1143/* 0x04ca: test_recv */
1144 0x17f100f8,
1145 0x11cf05d8,
1146 0x0110b600,
1147 0x05d807f1,
1148 0xbd0001d0,
1149 0x00e7f104,
1150 0x4fe3f1d9,
1151 0xb621f513,
1152/* 0x04eb: test_init */
1153 0xf100f801,
1154 0xf50800e7,
1155 0xf801b621,
1156/* 0x04f5: idle_recv */
1157/* 0x04f7: idle */
1158 0xf400f800,
1159 0x17f10031,
1160 0x11cf05d4,
1161 0x0110b600,
1162 0x05d407f1,
1163 0xbd0001d0,
1164/* 0x050d: idle_loop */
1165 0x5817f004,
1166/* 0x0513: idle_proc */
1167/* 0x0513: idle_proc_exec */
1168 0xf90232f4,
1169 0x021eb910,
1170 0x027421f5,
1171 0x11f410fc,
1172 0x0231f409,
1173/* 0x0527: idle_proc_next */
1174 0xb6ef0ef4,
1175 0x1fb85810,
1176 0xe61bf406,
1177 0xf4dd02f4,
1178 0x0ef40028,
1179 0x000000c1,
1180 0x00000000,
1181 0x00000000,
1182 0x00000000,
1183 0x00000000,
1184 0x00000000,
1185 0x00000000,
1186 0x00000000,
1187 0x00000000,
1188 0x00000000,
1189 0x00000000,
1190 0x00000000,
1191 0x00000000,
1192 0x00000000,
1193 0x00000000,
1194 0x00000000,
1195 0x00000000,
1196 0x00000000,
1197 0x00000000,
1198 0x00000000,
1199 0x00000000,
1200 0x00000000,
1201 0x00000000,
1202 0x00000000,
1203 0x00000000,
1204 0x00000000,
1205 0x00000000,
1206 0x00000000,
1207 0x00000000,
1208 0x00000000,
1209 0x00000000,
1210 0x00000000,
1211 0x00000000,
1212 0x00000000,
1213 0x00000000,
1214 0x00000000,
1215 0x00000000,
1216 0x00000000,
1217 0x00000000,
1218 0x00000000,
1219 0x00000000,
1220 0x00000000,
1221 0x00000000,
1222 0x00000000,
1223 0x00000000,
1224 0x00000000,
1225 0x00000000,
1226 0x00000000,
1227 0x00000000,
1228 0x00000000,
1229};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h
new file mode 100644
index 000000000000..5fb0cccc6c64
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h
@@ -0,0 +1,27 @@
1#ifndef __NVKM_PWR_OS_H__
2#define __NVKM_PWR_OS_H__
3
4/* Process names */
5#define PROC_KERN 0x52544e49
6#define PROC_IDLE 0x454c4449
7#define PROC_HOST 0x54534f48
8#define PROC_MEMX 0x584d454d
9#define PROC_PERF 0x46524550
10#define PROC_TEST 0x54534554
11
12/* KERN: message identifiers */
13#define KMSG_FIFO 0x00000000
14#define KMSG_ALARM 0x00000001
15
16/* MEMX: message identifiers */
17#define MEMX_MSG_INFO 0
18#define MEMX_MSG_EXEC 1
19
20/* MEMX: script opcode definitions */
21#define MEMX_ENTER 0
22#define MEMX_LEAVE 1
23#define MEMX_WR32 2
24#define MEMX_WAIT 3
25#define MEMX_DELAY 4
26
27#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/perf.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/perf.fuc
new file mode 100644
index 000000000000..38eadf705cbf
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/perf.fuc
@@ -0,0 +1,57 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#ifdef INCLUDE_PROC
26process(PROC_PERF, #perf_init, #perf_recv)
27#endif
28
29/******************************************************************************
30 * PERF data segment
31 *****************************************************************************/
32#ifdef INCLUDE_DATA
33#endif
34
35/******************************************************************************
36 * PERF code segment
37 *****************************************************************************/
38#ifdef INCLUDE_CODE
39
40// description
41//
42// $r15 - current (perf)
43// $r14 - sender process name
44// $r13 - message
45// $r12 - data0
46// $r11 - data1
47// $r0 - zero
48perf_recv:
49 ret
50
51// description
52//
53// $r15 - current (perf)
54// $r0 - zero
55perf_init:
56 ret
57#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/test.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/test.fuc
new file mode 100644
index 000000000000..0c3a71bf5459
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/test.fuc
@@ -0,0 +1,64 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#ifdef INCLUDE_PROC
26process(PROC_TEST, #test_init, #test_recv)
27#endif
28
29/******************************************************************************
30 * TEST data segment
31 *****************************************************************************/
32#ifdef INCLUDE_DATA
33#endif
34
35/******************************************************************************
36 * TEST code segment
37 *****************************************************************************/
38#ifdef INCLUDE_CODE
39// description
40//
41// $r15 - current (test)
42// $r14 - sender process name
43// $r13 - message
44// $r12 - data0
45// $r11 - data1
46// $r0 - zero
47test_recv:
48 nv_iord($r1, NV_PPWR_DSCRATCH(2))
49 add b32 $r1 1
50 nv_iowr(NV_PPWR_DSCRATCH(2), $r1)
51 mov $r14 -0x2700 /* 0xd900, envyas grrr! */
52 sethi $r14 0x134f0000
53 call(timer)
54 ret
55
56// description
57//
58// $r15 - current (test)
59// $r0 - zero
60test_init:
61 mov $r14 0x800
62 call(timer)
63 ret
64#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c
new file mode 100644
index 000000000000..03de3107d29f
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c
@@ -0,0 +1,121 @@
1#ifndef __NVKM_PWR_MEMX_H__
2#define __NVKM_PWR_MEMX_H__
3
4#include <subdev/pwr.h>
5#include <subdev/pwr/fuc/os.h>
6
7struct nouveau_memx {
8 struct nouveau_pwr *ppwr;
9 u32 base;
10 u32 size;
11 struct {
12 u32 mthd;
13 u32 size;
14 u32 data[64];
15 } c;
16};
17
18static void
19memx_out(struct nouveau_memx *memx)
20{
21 struct nouveau_pwr *ppwr = memx->ppwr;
22 int i;
23
24 if (memx->c.size) {
25 nv_wr32(ppwr, 0x10a1c4, (memx->c.size << 16) | memx->c.mthd);
26 for (i = 0; i < memx->c.size; i++)
27 nv_wr32(ppwr, 0x10a1c4, memx->c.data[i]);
28 memx->c.size = 0;
29 }
30}
31
32static void
33memx_cmd(struct nouveau_memx *memx, u32 mthd, u32 size, u32 data[])
34{
35 if ((memx->c.size + size >= ARRAY_SIZE(memx->c.data)) ||
36 (memx->c.size && memx->c.mthd != mthd))
37 memx_out(memx);
38 memcpy(&memx->c.data[memx->c.size], data, size * sizeof(data[0]));
39 memx->c.size += size;
40 memx->c.mthd = mthd;
41}
42
43int
44nouveau_memx_init(struct nouveau_pwr *ppwr, struct nouveau_memx **pmemx)
45{
46 struct nouveau_memx *memx;
47 u32 reply[2];
48 int ret;
49
50 ret = ppwr->message(ppwr, reply, PROC_MEMX, MEMX_MSG_INFO, 0, 0);
51 if (ret)
52 return ret;
53
54 memx = *pmemx = kzalloc(sizeof(*memx), GFP_KERNEL);
55 if (!memx)
56 return -ENOMEM;
57 memx->ppwr = ppwr;
58 memx->base = reply[0];
59 memx->size = reply[1];
60
61 /* acquire data segment access */
62 do {
63 nv_wr32(ppwr, 0x10a580, 0x00000003);
64 } while (nv_rd32(ppwr, 0x10a580) != 0x00000003);
65 nv_wr32(ppwr, 0x10a1c0, 0x01000000 | memx->base);
66 nv_wr32(ppwr, 0x10a1c4, 0x00010000 | MEMX_ENTER);
67 nv_wr32(ppwr, 0x10a1c4, 0x00000000);
68 return 0;
69}
70
71int
72nouveau_memx_fini(struct nouveau_memx **pmemx, bool exec)
73{
74 struct nouveau_memx *memx = *pmemx;
75 struct nouveau_pwr *ppwr = memx->ppwr;
76 u32 finish, reply[2];
77
78 /* flush the cache... */
79 memx_out(memx);
80
81 /* release data segment access */
82 nv_wr32(ppwr, 0x10a1c4, 0x00000000 | MEMX_LEAVE);
83 finish = nv_rd32(ppwr, 0x10a1c0) & 0x00ffffff;
84 nv_wr32(ppwr, 0x10a580, 0x00000000);
85
86 /* call MEMX process to execute the script, and wait for reply */
87 if (exec) {
88 ppwr->message(ppwr, reply, PROC_MEMX, MEMX_MSG_EXEC,
89 memx->base, finish);
90 }
91
92 kfree(memx);
93 return 0;
94}
95
96void
97nouveau_memx_wr32(struct nouveau_memx *memx, u32 addr, u32 data)
98{
99 nv_debug(memx->ppwr, "R[%06x] = 0x%08x\n", addr, data);
100 memx_cmd(memx, MEMX_WR32, 2, (u32[]){ addr, data });
101}
102
103void
104nouveau_memx_wait(struct nouveau_memx *memx,
105 u32 addr, u32 mask, u32 data, u32 nsec)
106{
107 nv_debug(memx->ppwr, "R[%06x] & 0x%08x == 0x%08x, %d us\n",
108 addr, mask, data, nsec);
109 memx_cmd(memx, MEMX_WAIT, 4, (u32[]){ addr, ~mask, data, nsec });
110 memx_out(memx); /* fuc can't handle multiple */
111}
112
113void
114nouveau_memx_nsec(struct nouveau_memx *memx, u32 nsec)
115{
116 nv_debug(memx->ppwr, " DELAY = %d ns\n", nsec);
117 memx_cmd(memx, MEMX_DELAY, 1, (u32[]){ nsec });
118 memx_out(memx); /* fuc can't handle multiple */
119}
120
121#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/nv108.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/nv108.c
new file mode 100644
index 000000000000..52c85414866a
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/nv108.c
@@ -0,0 +1,62 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <subdev/pwr.h>
26
27#include "fuc/nv108.fuc.h"
28
29struct nv108_pwr_priv {
30 struct nouveau_pwr base;
31};
32
33static int
34nv108_pwr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
35 struct nouveau_oclass *oclass, void *data, u32 size,
36 struct nouveau_object **pobject)
37{
38 struct nv108_pwr_priv *priv;
39 int ret;
40
41 ret = nouveau_pwr_create(parent, engine, oclass, &priv);
42 *pobject = nv_object(priv);
43 if (ret)
44 return ret;
45
46 priv->base.code.data = nv108_pwr_code;
47 priv->base.code.size = sizeof(nv108_pwr_code);
48 priv->base.data.data = nv108_pwr_data;
49 priv->base.data.size = sizeof(nv108_pwr_data);
50 return 0;
51}
52
53struct nouveau_oclass
54nv108_pwr_oclass = {
55 .handle = NV_SUBDEV(PWR, 0x00),
56 .ofuncs = &(struct nouveau_ofuncs) {
57 .ctor = nv108_pwr_ctor,
58 .dtor = _nouveau_pwr_dtor,
59 .init = _nouveau_pwr_init,
60 .fini = _nouveau_pwr_fini,
61 },
62};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/nva3.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/nva3.c
new file mode 100644
index 000000000000..c132b7ca9747
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/nva3.c
@@ -0,0 +1,71 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <subdev/pwr.h>
26
27#include "fuc/nva3.fuc.h"
28
29struct nva3_pwr_priv {
30 struct nouveau_pwr base;
31};
32
33static int
34nva3_pwr_init(struct nouveau_object *object)
35{
36 struct nva3_pwr_priv *priv = (void *)object;
37 nv_mask(priv, 0x022210, 0x00000001, 0x00000000);
38 nv_mask(priv, 0x022210, 0x00000001, 0x00000001);
39 return nouveau_pwr_init(&priv->base);
40}
41
42static int
43nva3_pwr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
44 struct nouveau_oclass *oclass, void *data, u32 size,
45 struct nouveau_object **pobject)
46{
47 struct nva3_pwr_priv *priv;
48 int ret;
49
50 ret = nouveau_pwr_create(parent, engine, oclass, &priv);
51 *pobject = nv_object(priv);
52 if (ret)
53 return ret;
54
55 priv->base.code.data = nva3_pwr_code;
56 priv->base.code.size = sizeof(nva3_pwr_code);
57 priv->base.data.data = nva3_pwr_data;
58 priv->base.data.size = sizeof(nva3_pwr_data);
59 return 0;
60}
61
62struct nouveau_oclass
63nva3_pwr_oclass = {
64 .handle = NV_SUBDEV(PWR, 0xa3),
65 .ofuncs = &(struct nouveau_ofuncs) {
66 .ctor = nva3_pwr_ctor,
67 .dtor = _nouveau_pwr_dtor,
68 .init = nva3_pwr_init,
69 .fini = _nouveau_pwr_fini,
70 },
71};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/nvc0.c
new file mode 100644
index 000000000000..495f6857428d
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/nvc0.c
@@ -0,0 +1,62 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <subdev/pwr.h>
26
27#include "fuc/nvc0.fuc.h"
28
29struct nvc0_pwr_priv {
30 struct nouveau_pwr base;
31};
32
33static int
34nvc0_pwr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
35 struct nouveau_oclass *oclass, void *data, u32 size,
36 struct nouveau_object **pobject)
37{
38 struct nvc0_pwr_priv *priv;
39 int ret;
40
41 ret = nouveau_pwr_create(parent, engine, oclass, &priv);
42 *pobject = nv_object(priv);
43 if (ret)
44 return ret;
45
46 priv->base.code.data = nvc0_pwr_code;
47 priv->base.code.size = sizeof(nvc0_pwr_code);
48 priv->base.data.data = nvc0_pwr_data;
49 priv->base.data.size = sizeof(nvc0_pwr_data);
50 return 0;
51}
52
53struct nouveau_oclass
54nvc0_pwr_oclass = {
55 .handle = NV_SUBDEV(PWR, 0xc0),
56 .ofuncs = &(struct nouveau_ofuncs) {
57 .ctor = nvc0_pwr_ctor,
58 .dtor = _nouveau_pwr_dtor,
59 .init = _nouveau_pwr_init,
60 .fini = _nouveau_pwr_fini,
61 },
62};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/nvd0.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/nvd0.c
new file mode 100644
index 000000000000..043aa142fe82
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/nvd0.c
@@ -0,0 +1,62 @@
1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <subdev/pwr.h>
26
27#include "fuc/nvd0.fuc.h"
28
29struct nvd0_pwr_priv {
30 struct nouveau_pwr base;
31};
32
33static int
34nvd0_pwr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
35 struct nouveau_oclass *oclass, void *data, u32 size,
36 struct nouveau_object **pobject)
37{
38 struct nvd0_pwr_priv *priv;
39 int ret;
40
41 ret = nouveau_pwr_create(parent, engine, oclass, &priv);
42 *pobject = nv_object(priv);
43 if (ret)
44 return ret;
45
46 priv->base.code.data = nvd0_pwr_code;
47 priv->base.code.size = sizeof(nvd0_pwr_code);
48 priv->base.data.data = nvd0_pwr_data;
49 priv->base.data.size = sizeof(nvd0_pwr_data);
50 return 0;
51}
52
53struct nouveau_oclass
54nvd0_pwr_oclass = {
55 .handle = NV_SUBDEV(PWR, 0xd0),
56 .ofuncs = &(struct nouveau_ofuncs) {
57 .ctor = nvd0_pwr_ctor,
58 .dtor = _nouveau_pwr_dtor,
59 .init = _nouveau_pwr_init,
60 .fini = _nouveau_pwr_fini,
61 },
62};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-22 07:05:28 -0400