aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorYuval Mintz <Yuval.Mintz@qlogic.com>2016-02-28 05:26:54 -0500
committerDavid S. Miller <davem@davemloft.net>2016-03-01 17:39:50 -0500
commitff38577aa9534fed1434d2ff8a0d1666a7f11fe4 (patch)
tree429490ac532379a9283289241c3864ed9af61b10
parent0d956e8a65d53e0d1a71d28975c821cf0f6ba676 (diff)
qed: Print HW attention reasons
Each HW block contains common information about attention reasons, raising a bit for each one of the different sub-reasons that caused it to raise an attention. This patch extends the infrastructure by allowing logging of the various reasons causing the HW blocks to generate an attention. Signed-off-by: Yuval Mintz <Yuval.Mintz@qlogic.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/ethernet/qlogic/qed/qed_int.c1543
1 files changed, 1436 insertions, 107 deletions
diff --git a/drivers/net/ethernet/qlogic/qed/qed_int.c b/drivers/net/ethernet/qlogic/qed/qed_int.c
index c914ac5940eb..c8bca7776b43 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_int.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_int.c
@@ -39,6 +39,11 @@ struct qed_sb_sp_info {
39 struct qed_pi_info pi_info_arr[PIS_PER_SB]; 39 struct qed_pi_info pi_info_arr[PIS_PER_SB];
40}; 40};
41 41
42enum qed_attention_type {
43 QED_ATTN_TYPE_ATTN,
44 QED_ATTN_TYPE_PARITY,
45};
46
42#define SB_ATTN_ALIGNED_SIZE(p_hwfn) \ 47#define SB_ATTN_ALIGNED_SIZE(p_hwfn) \
43 ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn) 48 ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn)
44 49
@@ -60,6 +65,8 @@ struct aeu_invert_reg_bit {
60#define ATTENTION_OFFSET_MASK (0x000ff000) 65#define ATTENTION_OFFSET_MASK (0x000ff000)
61#define ATTENTION_OFFSET_SHIFT (12) 66#define ATTENTION_OFFSET_SHIFT (12)
62 unsigned int flags; 67 unsigned int flags;
68
69 enum block_id block_index;
63}; 70};
64 71
65struct aeu_invert_reg { 72struct aeu_invert_reg {
@@ -69,158 +76,1379 @@ struct aeu_invert_reg {
69#define MAX_ATTN_GRPS (8) 76#define MAX_ATTN_GRPS (8)
70#define NUM_ATTN_REGS (9) 77#define NUM_ATTN_REGS (9)
71 78
79/* HW Attention register */
80struct attn_hw_reg {
81 u16 reg_idx; /* Index of this register in its block */
82 u16 num_of_bits; /* number of valid attention bits */
83 u32 sts_addr; /* Address of the STS register */
84 u32 sts_clr_addr; /* Address of the STS_CLR register */
85 u32 sts_wr_addr; /* Address of the STS_WR register */
86 u32 mask_addr; /* Address of the MASK register */
87};
88
89/* HW block attention registers */
90struct attn_hw_regs {
91 u16 num_of_int_regs; /* Number of interrupt regs */
92 u16 num_of_prty_regs; /* Number of parity regs */
93 struct attn_hw_reg **int_regs; /* interrupt regs */
94 struct attn_hw_reg **prty_regs; /* parity regs */
95};
96
97/* HW block attention registers */
98struct attn_hw_block {
99 const char *name; /* Block name */
100 struct attn_hw_regs chip_regs[1];
101};
102
103static struct attn_hw_reg grc_int0_bb_b0 = {
104 0, 4, 0x50180, 0x5018c, 0x50188, 0x50184};
105
106static struct attn_hw_reg *grc_int_bb_b0_regs[1] = {
107 &grc_int0_bb_b0};
108
109static struct attn_hw_reg grc_prty1_bb_b0 = {
110 0, 2, 0x50200, 0x5020c, 0x50208, 0x50204};
111
112static struct attn_hw_reg *grc_prty_bb_b0_regs[1] = {
113 &grc_prty1_bb_b0};
114
115static struct attn_hw_reg miscs_int0_bb_b0 = {
116 0, 3, 0x9180, 0x918c, 0x9188, 0x9184};
117
118static struct attn_hw_reg miscs_int1_bb_b0 = {
119 1, 11, 0x9190, 0x919c, 0x9198, 0x9194};
120
121static struct attn_hw_reg *miscs_int_bb_b0_regs[2] = {
122 &miscs_int0_bb_b0, &miscs_int1_bb_b0};
123
124static struct attn_hw_reg miscs_prty0_bb_b0 = {
125 0, 1, 0x91a0, 0x91ac, 0x91a8, 0x91a4};
126
127static struct attn_hw_reg *miscs_prty_bb_b0_regs[1] = {
128 &miscs_prty0_bb_b0};
129
130static struct attn_hw_reg misc_int0_bb_b0 = {
131 0, 1, 0x8180, 0x818c, 0x8188, 0x8184};
132
133static struct attn_hw_reg *misc_int_bb_b0_regs[1] = {
134 &misc_int0_bb_b0};
135
136static struct attn_hw_reg pglue_b_int0_bb_b0 = {
137 0, 23, 0x2a8180, 0x2a818c, 0x2a8188, 0x2a8184};
138
139static struct attn_hw_reg *pglue_b_int_bb_b0_regs[1] = {
140 &pglue_b_int0_bb_b0};
141
142static struct attn_hw_reg pglue_b_prty0_bb_b0 = {
143 0, 1, 0x2a8190, 0x2a819c, 0x2a8198, 0x2a8194};
144
145static struct attn_hw_reg pglue_b_prty1_bb_b0 = {
146 1, 22, 0x2a8200, 0x2a820c, 0x2a8208, 0x2a8204};
147
148static struct attn_hw_reg *pglue_b_prty_bb_b0_regs[2] = {
149 &pglue_b_prty0_bb_b0, &pglue_b_prty1_bb_b0};
150
151static struct attn_hw_reg cnig_int0_bb_b0 = {
152 0, 6, 0x2182e8, 0x2182f4, 0x2182f0, 0x2182ec};
153
154static struct attn_hw_reg *cnig_int_bb_b0_regs[1] = {
155 &cnig_int0_bb_b0};
156
157static struct attn_hw_reg cnig_prty0_bb_b0 = {
158 0, 2, 0x218348, 0x218354, 0x218350, 0x21834c};
159
160static struct attn_hw_reg *cnig_prty_bb_b0_regs[1] = {
161 &cnig_prty0_bb_b0};
162
163static struct attn_hw_reg cpmu_int0_bb_b0 = {
164 0, 1, 0x303e0, 0x303ec, 0x303e8, 0x303e4};
165
166static struct attn_hw_reg *cpmu_int_bb_b0_regs[1] = {
167 &cpmu_int0_bb_b0};
168
169static struct attn_hw_reg ncsi_int0_bb_b0 = {
170 0, 1, 0x404cc, 0x404d8, 0x404d4, 0x404d0};
171
172static struct attn_hw_reg *ncsi_int_bb_b0_regs[1] = {
173 &ncsi_int0_bb_b0};
174
175static struct attn_hw_reg ncsi_prty1_bb_b0 = {
176 0, 1, 0x40000, 0x4000c, 0x40008, 0x40004};
177
178static struct attn_hw_reg *ncsi_prty_bb_b0_regs[1] = {
179 &ncsi_prty1_bb_b0};
180
181static struct attn_hw_reg opte_prty1_bb_b0 = {
182 0, 11, 0x53000, 0x5300c, 0x53008, 0x53004};
183
184static struct attn_hw_reg opte_prty0_bb_b0 = {
185 1, 1, 0x53208, 0x53214, 0x53210, 0x5320c};
186
187static struct attn_hw_reg *opte_prty_bb_b0_regs[2] = {
188 &opte_prty1_bb_b0, &opte_prty0_bb_b0};
189
190static struct attn_hw_reg bmb_int0_bb_b0 = {
191 0, 16, 0x5400c0, 0x5400cc, 0x5400c8, 0x5400c4};
192
193static struct attn_hw_reg bmb_int1_bb_b0 = {
194 1, 28, 0x5400d8, 0x5400e4, 0x5400e0, 0x5400dc};
195
196static struct attn_hw_reg bmb_int2_bb_b0 = {
197 2, 26, 0x5400f0, 0x5400fc, 0x5400f8, 0x5400f4};
198
199static struct attn_hw_reg bmb_int3_bb_b0 = {
200 3, 31, 0x540108, 0x540114, 0x540110, 0x54010c};
201
202static struct attn_hw_reg bmb_int4_bb_b0 = {
203 4, 27, 0x540120, 0x54012c, 0x540128, 0x540124};
204
205static struct attn_hw_reg bmb_int5_bb_b0 = {
206 5, 29, 0x540138, 0x540144, 0x540140, 0x54013c};
207
208static struct attn_hw_reg bmb_int6_bb_b0 = {
209 6, 30, 0x540150, 0x54015c, 0x540158, 0x540154};
210
211static struct attn_hw_reg bmb_int7_bb_b0 = {
212 7, 32, 0x540168, 0x540174, 0x540170, 0x54016c};
213
214static struct attn_hw_reg bmb_int8_bb_b0 = {
215 8, 32, 0x540184, 0x540190, 0x54018c, 0x540188};
216
217static struct attn_hw_reg bmb_int9_bb_b0 = {
218 9, 32, 0x54019c, 0x5401a8, 0x5401a4, 0x5401a0};
219
220static struct attn_hw_reg bmb_int10_bb_b0 = {
221 10, 3, 0x5401b4, 0x5401c0, 0x5401bc, 0x5401b8};
222
223static struct attn_hw_reg bmb_int11_bb_b0 = {
224 11, 4, 0x5401cc, 0x5401d8, 0x5401d4, 0x5401d0};
225
226static struct attn_hw_reg *bmb_int_bb_b0_regs[12] = {
227 &bmb_int0_bb_b0, &bmb_int1_bb_b0, &bmb_int2_bb_b0, &bmb_int3_bb_b0,
228 &bmb_int4_bb_b0, &bmb_int5_bb_b0, &bmb_int6_bb_b0, &bmb_int7_bb_b0,
229 &bmb_int8_bb_b0, &bmb_int9_bb_b0, &bmb_int10_bb_b0, &bmb_int11_bb_b0};
230
231static struct attn_hw_reg bmb_prty0_bb_b0 = {
232 0, 5, 0x5401dc, 0x5401e8, 0x5401e4, 0x5401e0};
233
234static struct attn_hw_reg bmb_prty1_bb_b0 = {
235 1, 31, 0x540400, 0x54040c, 0x540408, 0x540404};
236
237static struct attn_hw_reg bmb_prty2_bb_b0 = {
238 2, 15, 0x540410, 0x54041c, 0x540418, 0x540414};
239
240static struct attn_hw_reg *bmb_prty_bb_b0_regs[3] = {
241 &bmb_prty0_bb_b0, &bmb_prty1_bb_b0, &bmb_prty2_bb_b0};
242
243static struct attn_hw_reg pcie_prty1_bb_b0 = {
244 0, 17, 0x54000, 0x5400c, 0x54008, 0x54004};
245
246static struct attn_hw_reg *pcie_prty_bb_b0_regs[1] = {
247 &pcie_prty1_bb_b0};
248
249static struct attn_hw_reg mcp2_prty0_bb_b0 = {
250 0, 1, 0x52040, 0x5204c, 0x52048, 0x52044};
251
252static struct attn_hw_reg mcp2_prty1_bb_b0 = {
253 1, 12, 0x52204, 0x52210, 0x5220c, 0x52208};
254
255static struct attn_hw_reg *mcp2_prty_bb_b0_regs[2] = {
256 &mcp2_prty0_bb_b0, &mcp2_prty1_bb_b0};
257
258static struct attn_hw_reg pswhst_int0_bb_b0 = {
259 0, 18, 0x2a0180, 0x2a018c, 0x2a0188, 0x2a0184};
260
261static struct attn_hw_reg *pswhst_int_bb_b0_regs[1] = {
262 &pswhst_int0_bb_b0};
263
264static struct attn_hw_reg pswhst_prty0_bb_b0 = {
265 0, 1, 0x2a0190, 0x2a019c, 0x2a0198, 0x2a0194};
266
267static struct attn_hw_reg pswhst_prty1_bb_b0 = {
268 1, 17, 0x2a0200, 0x2a020c, 0x2a0208, 0x2a0204};
269
270static struct attn_hw_reg *pswhst_prty_bb_b0_regs[2] = {
271 &pswhst_prty0_bb_b0, &pswhst_prty1_bb_b0};
272
273static struct attn_hw_reg pswhst2_int0_bb_b0 = {
274 0, 5, 0x29e180, 0x29e18c, 0x29e188, 0x29e184};
275
276static struct attn_hw_reg *pswhst2_int_bb_b0_regs[1] = {
277 &pswhst2_int0_bb_b0};
278
279static struct attn_hw_reg pswhst2_prty0_bb_b0 = {
280 0, 1, 0x29e190, 0x29e19c, 0x29e198, 0x29e194};
281
282static struct attn_hw_reg *pswhst2_prty_bb_b0_regs[1] = {
283 &pswhst2_prty0_bb_b0};
284
285static struct attn_hw_reg pswrd_int0_bb_b0 = {
286 0, 3, 0x29c180, 0x29c18c, 0x29c188, 0x29c184};
287
288static struct attn_hw_reg *pswrd_int_bb_b0_regs[1] = {
289 &pswrd_int0_bb_b0};
290
291static struct attn_hw_reg pswrd_prty0_bb_b0 = {
292 0, 1, 0x29c190, 0x29c19c, 0x29c198, 0x29c194};
293
294static struct attn_hw_reg *pswrd_prty_bb_b0_regs[1] = {
295 &pswrd_prty0_bb_b0};
296
297static struct attn_hw_reg pswrd2_int0_bb_b0 = {
298 0, 5, 0x29d180, 0x29d18c, 0x29d188, 0x29d184};
299
300static struct attn_hw_reg *pswrd2_int_bb_b0_regs[1] = {
301 &pswrd2_int0_bb_b0};
302
303static struct attn_hw_reg pswrd2_prty0_bb_b0 = {
304 0, 1, 0x29d190, 0x29d19c, 0x29d198, 0x29d194};
305
306static struct attn_hw_reg pswrd2_prty1_bb_b0 = {
307 1, 31, 0x29d200, 0x29d20c, 0x29d208, 0x29d204};
308
309static struct attn_hw_reg pswrd2_prty2_bb_b0 = {
310 2, 3, 0x29d210, 0x29d21c, 0x29d218, 0x29d214};
311
312static struct attn_hw_reg *pswrd2_prty_bb_b0_regs[3] = {
313 &pswrd2_prty0_bb_b0, &pswrd2_prty1_bb_b0, &pswrd2_prty2_bb_b0};
314
315static struct attn_hw_reg pswwr_int0_bb_b0 = {
316 0, 16, 0x29a180, 0x29a18c, 0x29a188, 0x29a184};
317
318static struct attn_hw_reg *pswwr_int_bb_b0_regs[1] = {
319 &pswwr_int0_bb_b0};
320
321static struct attn_hw_reg pswwr_prty0_bb_b0 = {
322 0, 1, 0x29a190, 0x29a19c, 0x29a198, 0x29a194};
323
324static struct attn_hw_reg *pswwr_prty_bb_b0_regs[1] = {
325 &pswwr_prty0_bb_b0};
326
327static struct attn_hw_reg pswwr2_int0_bb_b0 = {
328 0, 19, 0x29b180, 0x29b18c, 0x29b188, 0x29b184};
329
330static struct attn_hw_reg *pswwr2_int_bb_b0_regs[1] = {
331 &pswwr2_int0_bb_b0};
332
333static struct attn_hw_reg pswwr2_prty0_bb_b0 = {
334 0, 1, 0x29b190, 0x29b19c, 0x29b198, 0x29b194};
335
336static struct attn_hw_reg pswwr2_prty1_bb_b0 = {
337 1, 31, 0x29b200, 0x29b20c, 0x29b208, 0x29b204};
338
339static struct attn_hw_reg pswwr2_prty2_bb_b0 = {
340 2, 31, 0x29b210, 0x29b21c, 0x29b218, 0x29b214};
341
342static struct attn_hw_reg pswwr2_prty3_bb_b0 = {
343 3, 31, 0x29b220, 0x29b22c, 0x29b228, 0x29b224};
344
345static struct attn_hw_reg pswwr2_prty4_bb_b0 = {
346 4, 20, 0x29b230, 0x29b23c, 0x29b238, 0x29b234};
347
348static struct attn_hw_reg *pswwr2_prty_bb_b0_regs[5] = {
349 &pswwr2_prty0_bb_b0, &pswwr2_prty1_bb_b0, &pswwr2_prty2_bb_b0,
350 &pswwr2_prty3_bb_b0, &pswwr2_prty4_bb_b0};
351
352static struct attn_hw_reg pswrq_int0_bb_b0 = {
353 0, 21, 0x280180, 0x28018c, 0x280188, 0x280184};
354
355static struct attn_hw_reg *pswrq_int_bb_b0_regs[1] = {
356 &pswrq_int0_bb_b0};
357
358static struct attn_hw_reg pswrq_prty0_bb_b0 = {
359 0, 1, 0x280190, 0x28019c, 0x280198, 0x280194};
360
361static struct attn_hw_reg *pswrq_prty_bb_b0_regs[1] = {
362 &pswrq_prty0_bb_b0};
363
364static struct attn_hw_reg pswrq2_int0_bb_b0 = {
365 0, 15, 0x240180, 0x24018c, 0x240188, 0x240184};
366
367static struct attn_hw_reg *pswrq2_int_bb_b0_regs[1] = {
368 &pswrq2_int0_bb_b0};
369
370static struct attn_hw_reg pswrq2_prty1_bb_b0 = {
371 0, 9, 0x240200, 0x24020c, 0x240208, 0x240204};
372
373static struct attn_hw_reg *pswrq2_prty_bb_b0_regs[1] = {
374 &pswrq2_prty1_bb_b0};
375
376static struct attn_hw_reg pglcs_int0_bb_b0 = {
377 0, 1, 0x1d00, 0x1d0c, 0x1d08, 0x1d04};
378
379static struct attn_hw_reg *pglcs_int_bb_b0_regs[1] = {
380 &pglcs_int0_bb_b0};
381
382static struct attn_hw_reg dmae_int0_bb_b0 = {
383 0, 2, 0xc180, 0xc18c, 0xc188, 0xc184};
384
385static struct attn_hw_reg *dmae_int_bb_b0_regs[1] = {
386 &dmae_int0_bb_b0};
387
388static struct attn_hw_reg dmae_prty1_bb_b0 = {
389 0, 3, 0xc200, 0xc20c, 0xc208, 0xc204};
390
391static struct attn_hw_reg *dmae_prty_bb_b0_regs[1] = {
392 &dmae_prty1_bb_b0};
393
394static struct attn_hw_reg ptu_int0_bb_b0 = {
395 0, 8, 0x560180, 0x56018c, 0x560188, 0x560184};
396
397static struct attn_hw_reg *ptu_int_bb_b0_regs[1] = {
398 &ptu_int0_bb_b0};
399
400static struct attn_hw_reg ptu_prty1_bb_b0 = {
401 0, 18, 0x560200, 0x56020c, 0x560208, 0x560204};
402
403static struct attn_hw_reg *ptu_prty_bb_b0_regs[1] = {
404 &ptu_prty1_bb_b0};
405
406static struct attn_hw_reg tcm_int0_bb_b0 = {
407 0, 8, 0x1180180, 0x118018c, 0x1180188, 0x1180184};
408
409static struct attn_hw_reg tcm_int1_bb_b0 = {
410 1, 32, 0x1180190, 0x118019c, 0x1180198, 0x1180194};
411
412static struct attn_hw_reg tcm_int2_bb_b0 = {
413 2, 1, 0x11801a0, 0x11801ac, 0x11801a8, 0x11801a4};
414
415static struct attn_hw_reg *tcm_int_bb_b0_regs[3] = {
416 &tcm_int0_bb_b0, &tcm_int1_bb_b0, &tcm_int2_bb_b0};
417
418static struct attn_hw_reg tcm_prty1_bb_b0 = {
419 0, 31, 0x1180200, 0x118020c, 0x1180208, 0x1180204};
420
421static struct attn_hw_reg tcm_prty2_bb_b0 = {
422 1, 2, 0x1180210, 0x118021c, 0x1180218, 0x1180214};
423
424static struct attn_hw_reg *tcm_prty_bb_b0_regs[2] = {
425 &tcm_prty1_bb_b0, &tcm_prty2_bb_b0};
426
427static struct attn_hw_reg mcm_int0_bb_b0 = {
428 0, 14, 0x1200180, 0x120018c, 0x1200188, 0x1200184};
429
430static struct attn_hw_reg mcm_int1_bb_b0 = {
431 1, 26, 0x1200190, 0x120019c, 0x1200198, 0x1200194};
432
433static struct attn_hw_reg mcm_int2_bb_b0 = {
434 2, 1, 0x12001a0, 0x12001ac, 0x12001a8, 0x12001a4};
435
436static struct attn_hw_reg *mcm_int_bb_b0_regs[3] = {
437 &mcm_int0_bb_b0, &mcm_int1_bb_b0, &mcm_int2_bb_b0};
438
439static struct attn_hw_reg mcm_prty1_bb_b0 = {
440 0, 31, 0x1200200, 0x120020c, 0x1200208, 0x1200204};
441
442static struct attn_hw_reg mcm_prty2_bb_b0 = {
443 1, 4, 0x1200210, 0x120021c, 0x1200218, 0x1200214};
444
445static struct attn_hw_reg *mcm_prty_bb_b0_regs[2] = {
446 &mcm_prty1_bb_b0, &mcm_prty2_bb_b0};
447
448static struct attn_hw_reg ucm_int0_bb_b0 = {
449 0, 17, 0x1280180, 0x128018c, 0x1280188, 0x1280184};
450
451static struct attn_hw_reg ucm_int1_bb_b0 = {
452 1, 29, 0x1280190, 0x128019c, 0x1280198, 0x1280194};
453
454static struct attn_hw_reg ucm_int2_bb_b0 = {
455 2, 1, 0x12801a0, 0x12801ac, 0x12801a8, 0x12801a4};
456
457static struct attn_hw_reg *ucm_int_bb_b0_regs[3] = {
458 &ucm_int0_bb_b0, &ucm_int1_bb_b0, &ucm_int2_bb_b0};
459
460static struct attn_hw_reg ucm_prty1_bb_b0 = {
461 0, 31, 0x1280200, 0x128020c, 0x1280208, 0x1280204};
462
463static struct attn_hw_reg ucm_prty2_bb_b0 = {
464 1, 7, 0x1280210, 0x128021c, 0x1280218, 0x1280214};
465
466static struct attn_hw_reg *ucm_prty_bb_b0_regs[2] = {
467 &ucm_prty1_bb_b0, &ucm_prty2_bb_b0};
468
469static struct attn_hw_reg xcm_int0_bb_b0 = {
470 0, 16, 0x1000180, 0x100018c, 0x1000188, 0x1000184};
471
472static struct attn_hw_reg xcm_int1_bb_b0 = {
473 1, 25, 0x1000190, 0x100019c, 0x1000198, 0x1000194};
474
475static struct attn_hw_reg xcm_int2_bb_b0 = {
476 2, 8, 0x10001a0, 0x10001ac, 0x10001a8, 0x10001a4};
477
478static struct attn_hw_reg *xcm_int_bb_b0_regs[3] = {
479 &xcm_int0_bb_b0, &xcm_int1_bb_b0, &xcm_int2_bb_b0};
480
481static struct attn_hw_reg xcm_prty1_bb_b0 = {
482 0, 31, 0x1000200, 0x100020c, 0x1000208, 0x1000204};
483
484static struct attn_hw_reg xcm_prty2_bb_b0 = {
485 1, 11, 0x1000210, 0x100021c, 0x1000218, 0x1000214};
486
487static struct attn_hw_reg *xcm_prty_bb_b0_regs[2] = {
488 &xcm_prty1_bb_b0, &xcm_prty2_bb_b0};
489
490static struct attn_hw_reg ycm_int0_bb_b0 = {
491 0, 13, 0x1080180, 0x108018c, 0x1080188, 0x1080184};
492
493static struct attn_hw_reg ycm_int1_bb_b0 = {
494 1, 23, 0x1080190, 0x108019c, 0x1080198, 0x1080194};
495
496static struct attn_hw_reg ycm_int2_bb_b0 = {
497 2, 1, 0x10801a0, 0x10801ac, 0x10801a8, 0x10801a4};
498
499static struct attn_hw_reg *ycm_int_bb_b0_regs[3] = {
500 &ycm_int0_bb_b0, &ycm_int1_bb_b0, &ycm_int2_bb_b0};
501
502static struct attn_hw_reg ycm_prty1_bb_b0 = {
503 0, 31, 0x1080200, 0x108020c, 0x1080208, 0x1080204};
504
505static struct attn_hw_reg ycm_prty2_bb_b0 = {
506 1, 3, 0x1080210, 0x108021c, 0x1080218, 0x1080214};
507
508static struct attn_hw_reg *ycm_prty_bb_b0_regs[2] = {
509 &ycm_prty1_bb_b0, &ycm_prty2_bb_b0};
510
511static struct attn_hw_reg pcm_int0_bb_b0 = {
512 0, 5, 0x1100180, 0x110018c, 0x1100188, 0x1100184};
513
514static struct attn_hw_reg pcm_int1_bb_b0 = {
515 1, 14, 0x1100190, 0x110019c, 0x1100198, 0x1100194};
516
517static struct attn_hw_reg pcm_int2_bb_b0 = {
518 2, 1, 0x11001a0, 0x11001ac, 0x11001a8, 0x11001a4};
519
520static struct attn_hw_reg *pcm_int_bb_b0_regs[3] = {
521 &pcm_int0_bb_b0, &pcm_int1_bb_b0, &pcm_int2_bb_b0};
522
523static struct attn_hw_reg pcm_prty1_bb_b0 = {
524 0, 11, 0x1100200, 0x110020c, 0x1100208, 0x1100204};
525
526static struct attn_hw_reg *pcm_prty_bb_b0_regs[1] = {
527 &pcm_prty1_bb_b0};
528
529static struct attn_hw_reg qm_int0_bb_b0 = {
530 0, 22, 0x2f0180, 0x2f018c, 0x2f0188, 0x2f0184};
531
532static struct attn_hw_reg *qm_int_bb_b0_regs[1] = {
533 &qm_int0_bb_b0};
534
535static struct attn_hw_reg qm_prty0_bb_b0 = {
536 0, 11, 0x2f0190, 0x2f019c, 0x2f0198, 0x2f0194};
537
538static struct attn_hw_reg qm_prty1_bb_b0 = {
539 1, 31, 0x2f0200, 0x2f020c, 0x2f0208, 0x2f0204};
540
541static struct attn_hw_reg qm_prty2_bb_b0 = {
542 2, 31, 0x2f0210, 0x2f021c, 0x2f0218, 0x2f0214};
543
544static struct attn_hw_reg qm_prty3_bb_b0 = {
545 3, 11, 0x2f0220, 0x2f022c, 0x2f0228, 0x2f0224};
546
547static struct attn_hw_reg *qm_prty_bb_b0_regs[4] = {
548 &qm_prty0_bb_b0, &qm_prty1_bb_b0, &qm_prty2_bb_b0, &qm_prty3_bb_b0};
549
550static struct attn_hw_reg tm_int0_bb_b0 = {
551 0, 32, 0x2c0180, 0x2c018c, 0x2c0188, 0x2c0184};
552
553static struct attn_hw_reg tm_int1_bb_b0 = {
554 1, 11, 0x2c0190, 0x2c019c, 0x2c0198, 0x2c0194};
555
556static struct attn_hw_reg *tm_int_bb_b0_regs[2] = {
557 &tm_int0_bb_b0, &tm_int1_bb_b0};
558
559static struct attn_hw_reg tm_prty1_bb_b0 = {
560 0, 17, 0x2c0200, 0x2c020c, 0x2c0208, 0x2c0204};
561
562static struct attn_hw_reg *tm_prty_bb_b0_regs[1] = {
563 &tm_prty1_bb_b0};
564
565static struct attn_hw_reg dorq_int0_bb_b0 = {
566 0, 9, 0x100180, 0x10018c, 0x100188, 0x100184};
567
568static struct attn_hw_reg *dorq_int_bb_b0_regs[1] = {
569 &dorq_int0_bb_b0};
570
571static struct attn_hw_reg dorq_prty0_bb_b0 = {
572 0, 1, 0x100190, 0x10019c, 0x100198, 0x100194};
573
574static struct attn_hw_reg dorq_prty1_bb_b0 = {
575 1, 6, 0x100200, 0x10020c, 0x100208, 0x100204};
576
577static struct attn_hw_reg *dorq_prty_bb_b0_regs[2] = {
578 &dorq_prty0_bb_b0, &dorq_prty1_bb_b0};
579
580static struct attn_hw_reg brb_int0_bb_b0 = {
581 0, 32, 0x3400c0, 0x3400cc, 0x3400c8, 0x3400c4};
582
583static struct attn_hw_reg brb_int1_bb_b0 = {
584 1, 30, 0x3400d8, 0x3400e4, 0x3400e0, 0x3400dc};
585
586static struct attn_hw_reg brb_int2_bb_b0 = {
587 2, 28, 0x3400f0, 0x3400fc, 0x3400f8, 0x3400f4};
588
589static struct attn_hw_reg brb_int3_bb_b0 = {
590 3, 31, 0x340108, 0x340114, 0x340110, 0x34010c};
591
592static struct attn_hw_reg brb_int4_bb_b0 = {
593 4, 27, 0x340120, 0x34012c, 0x340128, 0x340124};
594
595static struct attn_hw_reg brb_int5_bb_b0 = {
596 5, 1, 0x340138, 0x340144, 0x340140, 0x34013c};
597
598static struct attn_hw_reg brb_int6_bb_b0 = {
599 6, 8, 0x340150, 0x34015c, 0x340158, 0x340154};
600
601static struct attn_hw_reg brb_int7_bb_b0 = {
602 7, 32, 0x340168, 0x340174, 0x340170, 0x34016c};
603
604static struct attn_hw_reg brb_int8_bb_b0 = {
605 8, 17, 0x340184, 0x340190, 0x34018c, 0x340188};
606
607static struct attn_hw_reg brb_int9_bb_b0 = {
608 9, 1, 0x34019c, 0x3401a8, 0x3401a4, 0x3401a0};
609
610static struct attn_hw_reg brb_int10_bb_b0 = {
611 10, 14, 0x3401b4, 0x3401c0, 0x3401bc, 0x3401b8};
612
613static struct attn_hw_reg brb_int11_bb_b0 = {
614 11, 8, 0x3401cc, 0x3401d8, 0x3401d4, 0x3401d0};
615
616static struct attn_hw_reg *brb_int_bb_b0_regs[12] = {
617 &brb_int0_bb_b0, &brb_int1_bb_b0, &brb_int2_bb_b0, &brb_int3_bb_b0,
618 &brb_int4_bb_b0, &brb_int5_bb_b0, &brb_int6_bb_b0, &brb_int7_bb_b0,
619 &brb_int8_bb_b0, &brb_int9_bb_b0, &brb_int10_bb_b0, &brb_int11_bb_b0};
620
621static struct attn_hw_reg brb_prty0_bb_b0 = {
622 0, 5, 0x3401dc, 0x3401e8, 0x3401e4, 0x3401e0};
623
624static struct attn_hw_reg brb_prty1_bb_b0 = {
625 1, 31, 0x340400, 0x34040c, 0x340408, 0x340404};
626
627static struct attn_hw_reg brb_prty2_bb_b0 = {
628 2, 14, 0x340410, 0x34041c, 0x340418, 0x340414};
629
630static struct attn_hw_reg *brb_prty_bb_b0_regs[3] = {
631 &brb_prty0_bb_b0, &brb_prty1_bb_b0, &brb_prty2_bb_b0};
632
633static struct attn_hw_reg src_int0_bb_b0 = {
634 0, 1, 0x2381d8, 0x2381dc, 0x2381e0, 0x2381e4};
635
636static struct attn_hw_reg *src_int_bb_b0_regs[1] = {
637 &src_int0_bb_b0};
638
639static struct attn_hw_reg prs_int0_bb_b0 = {
640 0, 2, 0x1f0040, 0x1f004c, 0x1f0048, 0x1f0044};
641
642static struct attn_hw_reg *prs_int_bb_b0_regs[1] = {
643 &prs_int0_bb_b0};
644
645static struct attn_hw_reg prs_prty0_bb_b0 = {
646 0, 2, 0x1f0050, 0x1f005c, 0x1f0058, 0x1f0054};
647
648static struct attn_hw_reg prs_prty1_bb_b0 = {
649 1, 31, 0x1f0204, 0x1f0210, 0x1f020c, 0x1f0208};
650
651static struct attn_hw_reg prs_prty2_bb_b0 = {
652 2, 5, 0x1f0214, 0x1f0220, 0x1f021c, 0x1f0218};
653
654static struct attn_hw_reg *prs_prty_bb_b0_regs[3] = {
655 &prs_prty0_bb_b0, &prs_prty1_bb_b0, &prs_prty2_bb_b0};
656
657static struct attn_hw_reg tsdm_int0_bb_b0 = {
658 0, 26, 0xfb0040, 0xfb004c, 0xfb0048, 0xfb0044};
659
660static struct attn_hw_reg *tsdm_int_bb_b0_regs[1] = {
661 &tsdm_int0_bb_b0};
662
663static struct attn_hw_reg tsdm_prty1_bb_b0 = {
664 0, 10, 0xfb0200, 0xfb020c, 0xfb0208, 0xfb0204};
665
666static struct attn_hw_reg *tsdm_prty_bb_b0_regs[1] = {
667 &tsdm_prty1_bb_b0};
668
669static struct attn_hw_reg msdm_int0_bb_b0 = {
670 0, 26, 0xfc0040, 0xfc004c, 0xfc0048, 0xfc0044};
671
672static struct attn_hw_reg *msdm_int_bb_b0_regs[1] = {
673 &msdm_int0_bb_b0};
674
675static struct attn_hw_reg msdm_prty1_bb_b0 = {
676 0, 11, 0xfc0200, 0xfc020c, 0xfc0208, 0xfc0204};
677
678static struct attn_hw_reg *msdm_prty_bb_b0_regs[1] = {
679 &msdm_prty1_bb_b0};
680
681static struct attn_hw_reg usdm_int0_bb_b0 = {
682 0, 26, 0xfd0040, 0xfd004c, 0xfd0048, 0xfd0044};
683
684static struct attn_hw_reg *usdm_int_bb_b0_regs[1] = {
685 &usdm_int0_bb_b0};
686
687static struct attn_hw_reg usdm_prty1_bb_b0 = {
688 0, 10, 0xfd0200, 0xfd020c, 0xfd0208, 0xfd0204};
689
690static struct attn_hw_reg *usdm_prty_bb_b0_regs[1] = {
691 &usdm_prty1_bb_b0};
692
693static struct attn_hw_reg xsdm_int0_bb_b0 = {
694 0, 26, 0xf80040, 0xf8004c, 0xf80048, 0xf80044};
695
696static struct attn_hw_reg *xsdm_int_bb_b0_regs[1] = {
697 &xsdm_int0_bb_b0};
698
699static struct attn_hw_reg xsdm_prty1_bb_b0 = {
700 0, 10, 0xf80200, 0xf8020c, 0xf80208, 0xf80204};
701
702static struct attn_hw_reg *xsdm_prty_bb_b0_regs[1] = {
703 &xsdm_prty1_bb_b0};
704
705static struct attn_hw_reg ysdm_int0_bb_b0 = {
706 0, 26, 0xf90040, 0xf9004c, 0xf90048, 0xf90044};
707
708static struct attn_hw_reg *ysdm_int_bb_b0_regs[1] = {
709 &ysdm_int0_bb_b0};
710
711static struct attn_hw_reg ysdm_prty1_bb_b0 = {
712 0, 9, 0xf90200, 0xf9020c, 0xf90208, 0xf90204};
713
714static struct attn_hw_reg *ysdm_prty_bb_b0_regs[1] = {
715 &ysdm_prty1_bb_b0};
716
717static struct attn_hw_reg psdm_int0_bb_b0 = {
718 0, 26, 0xfa0040, 0xfa004c, 0xfa0048, 0xfa0044};
719
720static struct attn_hw_reg *psdm_int_bb_b0_regs[1] = {
721 &psdm_int0_bb_b0};
722
723static struct attn_hw_reg psdm_prty1_bb_b0 = {
724 0, 9, 0xfa0200, 0xfa020c, 0xfa0208, 0xfa0204};
725
726static struct attn_hw_reg *psdm_prty_bb_b0_regs[1] = {
727 &psdm_prty1_bb_b0};
728
729static struct attn_hw_reg tsem_int0_bb_b0 = {
730 0, 32, 0x1700040, 0x170004c, 0x1700048, 0x1700044};
731
732static struct attn_hw_reg tsem_int1_bb_b0 = {
733 1, 13, 0x1700050, 0x170005c, 0x1700058, 0x1700054};
734
735static struct attn_hw_reg tsem_fast_memory_int0_bb_b0 = {
736 2, 1, 0x1740040, 0x174004c, 0x1740048, 0x1740044};
737
738static struct attn_hw_reg *tsem_int_bb_b0_regs[3] = {
739 &tsem_int0_bb_b0, &tsem_int1_bb_b0, &tsem_fast_memory_int0_bb_b0};
740
741static struct attn_hw_reg tsem_prty0_bb_b0 = {
742 0, 3, 0x17000c8, 0x17000d4, 0x17000d0, 0x17000cc};
743
744static struct attn_hw_reg tsem_prty1_bb_b0 = {
745 1, 6, 0x1700200, 0x170020c, 0x1700208, 0x1700204};
746
747static struct attn_hw_reg tsem_fast_memory_vfc_config_prty1_bb_b0 = {
748 2, 6, 0x174a200, 0x174a20c, 0x174a208, 0x174a204};
749
750static struct attn_hw_reg *tsem_prty_bb_b0_regs[3] = {
751 &tsem_prty0_bb_b0, &tsem_prty1_bb_b0,
752 &tsem_fast_memory_vfc_config_prty1_bb_b0};
753
754static struct attn_hw_reg msem_int0_bb_b0 = {
755 0, 32, 0x1800040, 0x180004c, 0x1800048, 0x1800044};
756
757static struct attn_hw_reg msem_int1_bb_b0 = {
758 1, 13, 0x1800050, 0x180005c, 0x1800058, 0x1800054};
759
760static struct attn_hw_reg msem_fast_memory_int0_bb_b0 = {
761 2, 1, 0x1840040, 0x184004c, 0x1840048, 0x1840044};
762
763static struct attn_hw_reg *msem_int_bb_b0_regs[3] = {
764 &msem_int0_bb_b0, &msem_int1_bb_b0, &msem_fast_memory_int0_bb_b0};
765
766static struct attn_hw_reg msem_prty0_bb_b0 = {
767 0, 3, 0x18000c8, 0x18000d4, 0x18000d0, 0x18000cc};
768
769static struct attn_hw_reg msem_prty1_bb_b0 = {
770 1, 6, 0x1800200, 0x180020c, 0x1800208, 0x1800204};
771
772static struct attn_hw_reg *msem_prty_bb_b0_regs[2] = {
773 &msem_prty0_bb_b0, &msem_prty1_bb_b0};
774
775static struct attn_hw_reg usem_int0_bb_b0 = {
776 0, 32, 0x1900040, 0x190004c, 0x1900048, 0x1900044};
777
778static struct attn_hw_reg usem_int1_bb_b0 = {
779 1, 13, 0x1900050, 0x190005c, 0x1900058, 0x1900054};
780
781static struct attn_hw_reg usem_fast_memory_int0_bb_b0 = {
782 2, 1, 0x1940040, 0x194004c, 0x1940048, 0x1940044};
783
784static struct attn_hw_reg *usem_int_bb_b0_regs[3] = {
785 &usem_int0_bb_b0, &usem_int1_bb_b0, &usem_fast_memory_int0_bb_b0};
786
787static struct attn_hw_reg usem_prty0_bb_b0 = {
788 0, 3, 0x19000c8, 0x19000d4, 0x19000d0, 0x19000cc};
789
790static struct attn_hw_reg usem_prty1_bb_b0 = {
791 1, 6, 0x1900200, 0x190020c, 0x1900208, 0x1900204};
792
793static struct attn_hw_reg *usem_prty_bb_b0_regs[2] = {
794 &usem_prty0_bb_b0, &usem_prty1_bb_b0};
795
796static struct attn_hw_reg xsem_int0_bb_b0 = {
797 0, 32, 0x1400040, 0x140004c, 0x1400048, 0x1400044};
798
799static struct attn_hw_reg xsem_int1_bb_b0 = {
800 1, 13, 0x1400050, 0x140005c, 0x1400058, 0x1400054};
801
802static struct attn_hw_reg xsem_fast_memory_int0_bb_b0 = {
803 2, 1, 0x1440040, 0x144004c, 0x1440048, 0x1440044};
804
805static struct attn_hw_reg *xsem_int_bb_b0_regs[3] = {
806 &xsem_int0_bb_b0, &xsem_int1_bb_b0, &xsem_fast_memory_int0_bb_b0};
807
808static struct attn_hw_reg xsem_prty0_bb_b0 = {
809 0, 3, 0x14000c8, 0x14000d4, 0x14000d0, 0x14000cc};
810
811static struct attn_hw_reg xsem_prty1_bb_b0 = {
812 1, 7, 0x1400200, 0x140020c, 0x1400208, 0x1400204};
813
814static struct attn_hw_reg *xsem_prty_bb_b0_regs[2] = {
815 &xsem_prty0_bb_b0, &xsem_prty1_bb_b0};
816
817static struct attn_hw_reg ysem_int0_bb_b0 = {
818 0, 32, 0x1500040, 0x150004c, 0x1500048, 0x1500044};
819
820static struct attn_hw_reg ysem_int1_bb_b0 = {
821 1, 13, 0x1500050, 0x150005c, 0x1500058, 0x1500054};
822
823static struct attn_hw_reg ysem_fast_memory_int0_bb_b0 = {
824 2, 1, 0x1540040, 0x154004c, 0x1540048, 0x1540044};
825
826static struct attn_hw_reg *ysem_int_bb_b0_regs[3] = {
827 &ysem_int0_bb_b0, &ysem_int1_bb_b0, &ysem_fast_memory_int0_bb_b0};
828
829static struct attn_hw_reg ysem_prty0_bb_b0 = {
830 0, 3, 0x15000c8, 0x15000d4, 0x15000d0, 0x15000cc};
831
832static struct attn_hw_reg ysem_prty1_bb_b0 = {
833 1, 7, 0x1500200, 0x150020c, 0x1500208, 0x1500204};
834
835static struct attn_hw_reg *ysem_prty_bb_b0_regs[2] = {
836 &ysem_prty0_bb_b0, &ysem_prty1_bb_b0};
837
838static struct attn_hw_reg psem_int0_bb_b0 = {
839 0, 32, 0x1600040, 0x160004c, 0x1600048, 0x1600044};
840
841static struct attn_hw_reg psem_int1_bb_b0 = {
842 1, 13, 0x1600050, 0x160005c, 0x1600058, 0x1600054};
843
844static struct attn_hw_reg psem_fast_memory_int0_bb_b0 = {
845 2, 1, 0x1640040, 0x164004c, 0x1640048, 0x1640044};
846
847static struct attn_hw_reg *psem_int_bb_b0_regs[3] = {
848 &psem_int0_bb_b0, &psem_int1_bb_b0, &psem_fast_memory_int0_bb_b0};
849
850static struct attn_hw_reg psem_prty0_bb_b0 = {
851 0, 3, 0x16000c8, 0x16000d4, 0x16000d0, 0x16000cc};
852
853static struct attn_hw_reg psem_prty1_bb_b0 = {
854 1, 6, 0x1600200, 0x160020c, 0x1600208, 0x1600204};
855
856static struct attn_hw_reg psem_fast_memory_vfc_config_prty1_bb_b0 = {
857 2, 6, 0x164a200, 0x164a20c, 0x164a208, 0x164a204};
858
859static struct attn_hw_reg *psem_prty_bb_b0_regs[3] = {
860 &psem_prty0_bb_b0, &psem_prty1_bb_b0,
861 &psem_fast_memory_vfc_config_prty1_bb_b0};
862
863static struct attn_hw_reg rss_int0_bb_b0 = {
864 0, 12, 0x238980, 0x23898c, 0x238988, 0x238984};
865
866static struct attn_hw_reg *rss_int_bb_b0_regs[1] = {
867 &rss_int0_bb_b0};
868
869static struct attn_hw_reg rss_prty1_bb_b0 = {
870 0, 4, 0x238a00, 0x238a0c, 0x238a08, 0x238a04};
871
872static struct attn_hw_reg *rss_prty_bb_b0_regs[1] = {
873 &rss_prty1_bb_b0};
874
875static struct attn_hw_reg tmld_int0_bb_b0 = {
876 0, 6, 0x4d0180, 0x4d018c, 0x4d0188, 0x4d0184};
877
878static struct attn_hw_reg *tmld_int_bb_b0_regs[1] = {
879 &tmld_int0_bb_b0};
880
881static struct attn_hw_reg tmld_prty1_bb_b0 = {
882 0, 8, 0x4d0200, 0x4d020c, 0x4d0208, 0x4d0204};
883
884static struct attn_hw_reg *tmld_prty_bb_b0_regs[1] = {
885 &tmld_prty1_bb_b0};
886
887static struct attn_hw_reg muld_int0_bb_b0 = {
888 0, 6, 0x4e0180, 0x4e018c, 0x4e0188, 0x4e0184};
889
890static struct attn_hw_reg *muld_int_bb_b0_regs[1] = {
891 &muld_int0_bb_b0};
892
893static struct attn_hw_reg muld_prty1_bb_b0 = {
894 0, 10, 0x4e0200, 0x4e020c, 0x4e0208, 0x4e0204};
895
896static struct attn_hw_reg *muld_prty_bb_b0_regs[1] = {
897 &muld_prty1_bb_b0};
898
899static struct attn_hw_reg yuld_int0_bb_b0 = {
900 0, 6, 0x4c8180, 0x4c818c, 0x4c8188, 0x4c8184};
901
902static struct attn_hw_reg *yuld_int_bb_b0_regs[1] = {
903 &yuld_int0_bb_b0};
904
905static struct attn_hw_reg yuld_prty1_bb_b0 = {
906 0, 6, 0x4c8200, 0x4c820c, 0x4c8208, 0x4c8204};
907
908static struct attn_hw_reg *yuld_prty_bb_b0_regs[1] = {
909 &yuld_prty1_bb_b0};
910
911static struct attn_hw_reg xyld_int0_bb_b0 = {
912 0, 6, 0x4c0180, 0x4c018c, 0x4c0188, 0x4c0184};
913
914static struct attn_hw_reg *xyld_int_bb_b0_regs[1] = {
915 &xyld_int0_bb_b0};
916
917static struct attn_hw_reg xyld_prty1_bb_b0 = {
918 0, 9, 0x4c0200, 0x4c020c, 0x4c0208, 0x4c0204};
919
920static struct attn_hw_reg *xyld_prty_bb_b0_regs[1] = {
921 &xyld_prty1_bb_b0};
922
923static struct attn_hw_reg prm_int0_bb_b0 = {
924 0, 11, 0x230040, 0x23004c, 0x230048, 0x230044};
925
926static struct attn_hw_reg *prm_int_bb_b0_regs[1] = {
927 &prm_int0_bb_b0};
928
929static struct attn_hw_reg prm_prty0_bb_b0 = {
930 0, 1, 0x230050, 0x23005c, 0x230058, 0x230054};
931
932static struct attn_hw_reg prm_prty1_bb_b0 = {
933 1, 24, 0x230200, 0x23020c, 0x230208, 0x230204};
934
935static struct attn_hw_reg *prm_prty_bb_b0_regs[2] = {
936 &prm_prty0_bb_b0, &prm_prty1_bb_b0};
937
938static struct attn_hw_reg pbf_pb1_int0_bb_b0 = {
939 0, 9, 0xda0040, 0xda004c, 0xda0048, 0xda0044};
940
941static struct attn_hw_reg *pbf_pb1_int_bb_b0_regs[1] = {
942 &pbf_pb1_int0_bb_b0};
943
944static struct attn_hw_reg pbf_pb1_prty0_bb_b0 = {
945 0, 1, 0xda0050, 0xda005c, 0xda0058, 0xda0054};
946
947static struct attn_hw_reg *pbf_pb1_prty_bb_b0_regs[1] = {
948 &pbf_pb1_prty0_bb_b0};
949
950static struct attn_hw_reg pbf_pb2_int0_bb_b0 = {
951 0, 9, 0xda4040, 0xda404c, 0xda4048, 0xda4044};
952
953static struct attn_hw_reg *pbf_pb2_int_bb_b0_regs[1] = {
954 &pbf_pb2_int0_bb_b0};
955
956static struct attn_hw_reg pbf_pb2_prty0_bb_b0 = {
957 0, 1, 0xda4050, 0xda405c, 0xda4058, 0xda4054};
958
959static struct attn_hw_reg *pbf_pb2_prty_bb_b0_regs[1] = {
960 &pbf_pb2_prty0_bb_b0};
961
962static struct attn_hw_reg rpb_int0_bb_b0 = {
963 0, 9, 0x23c040, 0x23c04c, 0x23c048, 0x23c044};
964
965static struct attn_hw_reg *rpb_int_bb_b0_regs[1] = {
966 &rpb_int0_bb_b0};
967
968static struct attn_hw_reg rpb_prty0_bb_b0 = {
969 0, 1, 0x23c050, 0x23c05c, 0x23c058, 0x23c054};
970
971static struct attn_hw_reg *rpb_prty_bb_b0_regs[1] = {
972 &rpb_prty0_bb_b0};
973
974static struct attn_hw_reg btb_int0_bb_b0 = {
975 0, 16, 0xdb00c0, 0xdb00cc, 0xdb00c8, 0xdb00c4};
976
977static struct attn_hw_reg btb_int1_bb_b0 = {
978 1, 16, 0xdb00d8, 0xdb00e4, 0xdb00e0, 0xdb00dc};
979
980static struct attn_hw_reg btb_int2_bb_b0 = {
981 2, 4, 0xdb00f0, 0xdb00fc, 0xdb00f8, 0xdb00f4};
982
983static struct attn_hw_reg btb_int3_bb_b0 = {
984 3, 32, 0xdb0108, 0xdb0114, 0xdb0110, 0xdb010c};
985
986static struct attn_hw_reg btb_int4_bb_b0 = {
987 4, 23, 0xdb0120, 0xdb012c, 0xdb0128, 0xdb0124};
988
989static struct attn_hw_reg btb_int5_bb_b0 = {
990 5, 32, 0xdb0138, 0xdb0144, 0xdb0140, 0xdb013c};
991
992static struct attn_hw_reg btb_int6_bb_b0 = {
993 6, 1, 0xdb0150, 0xdb015c, 0xdb0158, 0xdb0154};
994
995static struct attn_hw_reg btb_int8_bb_b0 = {
996 7, 1, 0xdb0184, 0xdb0190, 0xdb018c, 0xdb0188};
997
998static struct attn_hw_reg btb_int9_bb_b0 = {
999 8, 1, 0xdb019c, 0xdb01a8, 0xdb01a4, 0xdb01a0};
1000
1001static struct attn_hw_reg btb_int10_bb_b0 = {
1002 9, 1, 0xdb01b4, 0xdb01c0, 0xdb01bc, 0xdb01b8};
1003
1004static struct attn_hw_reg btb_int11_bb_b0 = {
1005 10, 2, 0xdb01cc, 0xdb01d8, 0xdb01d4, 0xdb01d0};
1006
1007static struct attn_hw_reg *btb_int_bb_b0_regs[11] = {
1008 &btb_int0_bb_b0, &btb_int1_bb_b0, &btb_int2_bb_b0, &btb_int3_bb_b0,
1009 &btb_int4_bb_b0, &btb_int5_bb_b0, &btb_int6_bb_b0, &btb_int8_bb_b0,
1010 &btb_int9_bb_b0, &btb_int10_bb_b0, &btb_int11_bb_b0};
1011
1012static struct attn_hw_reg btb_prty0_bb_b0 = {
1013 0, 5, 0xdb01dc, 0xdb01e8, 0xdb01e4, 0xdb01e0};
1014
1015static struct attn_hw_reg btb_prty1_bb_b0 = {
1016 1, 23, 0xdb0400, 0xdb040c, 0xdb0408, 0xdb0404};
1017
1018static struct attn_hw_reg *btb_prty_bb_b0_regs[2] = {
1019 &btb_prty0_bb_b0, &btb_prty1_bb_b0};
1020
1021static struct attn_hw_reg pbf_int0_bb_b0 = {
1022 0, 1, 0xd80180, 0xd8018c, 0xd80188, 0xd80184};
1023
1024static struct attn_hw_reg *pbf_int_bb_b0_regs[1] = {
1025 &pbf_int0_bb_b0};
1026
1027static struct attn_hw_reg pbf_prty0_bb_b0 = {
1028 0, 1, 0xd80190, 0xd8019c, 0xd80198, 0xd80194};
1029
1030static struct attn_hw_reg pbf_prty1_bb_b0 = {
1031 1, 31, 0xd80200, 0xd8020c, 0xd80208, 0xd80204};
1032
1033static struct attn_hw_reg pbf_prty2_bb_b0 = {
1034 2, 27, 0xd80210, 0xd8021c, 0xd80218, 0xd80214};
1035
1036static struct attn_hw_reg *pbf_prty_bb_b0_regs[3] = {
1037 &pbf_prty0_bb_b0, &pbf_prty1_bb_b0, &pbf_prty2_bb_b0};
1038
1039static struct attn_hw_reg rdif_int0_bb_b0 = {
1040 0, 8, 0x300180, 0x30018c, 0x300188, 0x300184};
1041
1042static struct attn_hw_reg *rdif_int_bb_b0_regs[1] = {
1043 &rdif_int0_bb_b0};
1044
1045static struct attn_hw_reg rdif_prty0_bb_b0 = {
1046 0, 1, 0x300190, 0x30019c, 0x300198, 0x300194};
1047
1048static struct attn_hw_reg *rdif_prty_bb_b0_regs[1] = {
1049 &rdif_prty0_bb_b0};
1050
1051static struct attn_hw_reg tdif_int0_bb_b0 = {
1052 0, 8, 0x310180, 0x31018c, 0x310188, 0x310184};
1053
1054static struct attn_hw_reg *tdif_int_bb_b0_regs[1] = {
1055 &tdif_int0_bb_b0};
1056
1057static struct attn_hw_reg tdif_prty0_bb_b0 = {
1058 0, 1, 0x310190, 0x31019c, 0x310198, 0x310194};
1059
1060static struct attn_hw_reg tdif_prty1_bb_b0 = {
1061 1, 11, 0x310200, 0x31020c, 0x310208, 0x310204};
1062
1063static struct attn_hw_reg *tdif_prty_bb_b0_regs[2] = {
1064 &tdif_prty0_bb_b0, &tdif_prty1_bb_b0};
1065
1066static struct attn_hw_reg cdu_int0_bb_b0 = {
1067 0, 8, 0x5801c0, 0x5801c4, 0x5801c8, 0x5801cc};
1068
1069static struct attn_hw_reg *cdu_int_bb_b0_regs[1] = {
1070 &cdu_int0_bb_b0};
1071
1072static struct attn_hw_reg cdu_prty1_bb_b0 = {
1073 0, 5, 0x580200, 0x58020c, 0x580208, 0x580204};
1074
1075static struct attn_hw_reg *cdu_prty_bb_b0_regs[1] = {
1076 &cdu_prty1_bb_b0};
1077
1078static struct attn_hw_reg ccfc_int0_bb_b0 = {
1079 0, 2, 0x2e0180, 0x2e018c, 0x2e0188, 0x2e0184};
1080
1081static struct attn_hw_reg *ccfc_int_bb_b0_regs[1] = {
1082 &ccfc_int0_bb_b0};
1083
1084static struct attn_hw_reg ccfc_prty1_bb_b0 = {
1085 0, 2, 0x2e0200, 0x2e020c, 0x2e0208, 0x2e0204};
1086
1087static struct attn_hw_reg ccfc_prty0_bb_b0 = {
1088 1, 6, 0x2e05e4, 0x2e05f0, 0x2e05ec, 0x2e05e8};
1089
1090static struct attn_hw_reg *ccfc_prty_bb_b0_regs[2] = {
1091 &ccfc_prty1_bb_b0, &ccfc_prty0_bb_b0};
1092
1093static struct attn_hw_reg tcfc_int0_bb_b0 = {
1094 0, 2, 0x2d0180, 0x2d018c, 0x2d0188, 0x2d0184};
1095
1096static struct attn_hw_reg *tcfc_int_bb_b0_regs[1] = {
1097 &tcfc_int0_bb_b0};
1098
1099static struct attn_hw_reg tcfc_prty1_bb_b0 = {
1100 0, 2, 0x2d0200, 0x2d020c, 0x2d0208, 0x2d0204};
1101
1102static struct attn_hw_reg tcfc_prty0_bb_b0 = {
1103 1, 6, 0x2d05e4, 0x2d05f0, 0x2d05ec, 0x2d05e8};
1104
1105static struct attn_hw_reg *tcfc_prty_bb_b0_regs[2] = {
1106 &tcfc_prty1_bb_b0, &tcfc_prty0_bb_b0};
1107
1108static struct attn_hw_reg igu_int0_bb_b0 = {
1109 0, 11, 0x180180, 0x18018c, 0x180188, 0x180184};
1110
1111static struct attn_hw_reg *igu_int_bb_b0_regs[1] = {
1112 &igu_int0_bb_b0};
1113
1114static struct attn_hw_reg igu_prty0_bb_b0 = {
1115 0, 1, 0x180190, 0x18019c, 0x180198, 0x180194};
1116
1117static struct attn_hw_reg igu_prty1_bb_b0 = {
1118 1, 31, 0x180200, 0x18020c, 0x180208, 0x180204};
1119
1120static struct attn_hw_reg igu_prty2_bb_b0 = {
1121 2, 1, 0x180210, 0x18021c, 0x180218, 0x180214};
1122
1123static struct attn_hw_reg *igu_prty_bb_b0_regs[3] = {
1124 &igu_prty0_bb_b0, &igu_prty1_bb_b0, &igu_prty2_bb_b0};
1125
1126static struct attn_hw_reg cau_int0_bb_b0 = {
1127 0, 11, 0x1c00d4, 0x1c00d8, 0x1c00dc, 0x1c00e0};
1128
1129static struct attn_hw_reg *cau_int_bb_b0_regs[1] = {
1130 &cau_int0_bb_b0};
1131
1132static struct attn_hw_reg cau_prty1_bb_b0 = {
1133 0, 13, 0x1c0200, 0x1c020c, 0x1c0208, 0x1c0204};
1134
1135static struct attn_hw_reg *cau_prty_bb_b0_regs[1] = {
1136 &cau_prty1_bb_b0};
1137
1138static struct attn_hw_reg dbg_int0_bb_b0 = {
1139 0, 1, 0x10180, 0x1018c, 0x10188, 0x10184};
1140
1141static struct attn_hw_reg *dbg_int_bb_b0_regs[1] = {
1142 &dbg_int0_bb_b0};
1143
1144static struct attn_hw_reg dbg_prty1_bb_b0 = {
1145 0, 1, 0x10200, 0x1020c, 0x10208, 0x10204};
1146
1147static struct attn_hw_reg *dbg_prty_bb_b0_regs[1] = {
1148 &dbg_prty1_bb_b0};
1149
1150static struct attn_hw_reg nig_int0_bb_b0 = {
1151 0, 12, 0x500040, 0x50004c, 0x500048, 0x500044};
1152
1153static struct attn_hw_reg nig_int1_bb_b0 = {
1154 1, 32, 0x500050, 0x50005c, 0x500058, 0x500054};
1155
1156static struct attn_hw_reg nig_int2_bb_b0 = {
1157 2, 20, 0x500060, 0x50006c, 0x500068, 0x500064};
1158
1159static struct attn_hw_reg nig_int3_bb_b0 = {
1160 3, 18, 0x500070, 0x50007c, 0x500078, 0x500074};
1161
1162static struct attn_hw_reg nig_int4_bb_b0 = {
1163 4, 20, 0x500080, 0x50008c, 0x500088, 0x500084};
1164
1165static struct attn_hw_reg nig_int5_bb_b0 = {
1166 5, 18, 0x500090, 0x50009c, 0x500098, 0x500094};
1167
1168static struct attn_hw_reg *nig_int_bb_b0_regs[6] = {
1169 &nig_int0_bb_b0, &nig_int1_bb_b0, &nig_int2_bb_b0, &nig_int3_bb_b0,
1170 &nig_int4_bb_b0, &nig_int5_bb_b0};
1171
1172static struct attn_hw_reg nig_prty0_bb_b0 = {
1173 0, 1, 0x5000a0, 0x5000ac, 0x5000a8, 0x5000a4};
1174
1175static struct attn_hw_reg nig_prty1_bb_b0 = {
1176 1, 31, 0x500200, 0x50020c, 0x500208, 0x500204};
1177
1178static struct attn_hw_reg nig_prty2_bb_b0 = {
1179 2, 31, 0x500210, 0x50021c, 0x500218, 0x500214};
1180
1181static struct attn_hw_reg nig_prty3_bb_b0 = {
1182 3, 31, 0x500220, 0x50022c, 0x500228, 0x500224};
1183
1184static struct attn_hw_reg nig_prty4_bb_b0 = {
1185 4, 17, 0x500230, 0x50023c, 0x500238, 0x500234};
1186
1187static struct attn_hw_reg *nig_prty_bb_b0_regs[5] = {
1188 &nig_prty0_bb_b0, &nig_prty1_bb_b0, &nig_prty2_bb_b0,
1189 &nig_prty3_bb_b0, &nig_prty4_bb_b0};
1190
1191static struct attn_hw_reg ipc_int0_bb_b0 = {
1192 0, 13, 0x2050c, 0x20518, 0x20514, 0x20510};
1193
1194static struct attn_hw_reg *ipc_int_bb_b0_regs[1] = {
1195 &ipc_int0_bb_b0};
1196
1197static struct attn_hw_reg ipc_prty0_bb_b0 = {
1198 0, 1, 0x2051c, 0x20528, 0x20524, 0x20520};
1199
1200static struct attn_hw_reg *ipc_prty_bb_b0_regs[1] = {
1201 &ipc_prty0_bb_b0};
1202
1203static struct attn_hw_block attn_blocks[] = {
1204 {"grc", {{1, 1, grc_int_bb_b0_regs, grc_prty_bb_b0_regs} } },
1205 {"miscs", {{2, 1, miscs_int_bb_b0_regs, miscs_prty_bb_b0_regs} } },
1206 {"misc", {{1, 0, misc_int_bb_b0_regs, NULL} } },
1207 {"dbu", {{0, 0, NULL, NULL} } },
1208 {"pglue_b", {{1, 2, pglue_b_int_bb_b0_regs,
1209 pglue_b_prty_bb_b0_regs} } },
1210 {"cnig", {{1, 1, cnig_int_bb_b0_regs, cnig_prty_bb_b0_regs} } },
1211 {"cpmu", {{1, 0, cpmu_int_bb_b0_regs, NULL} } },
1212 {"ncsi", {{1, 1, ncsi_int_bb_b0_regs, ncsi_prty_bb_b0_regs} } },
1213 {"opte", {{0, 2, NULL, opte_prty_bb_b0_regs} } },
1214 {"bmb", {{12, 3, bmb_int_bb_b0_regs, bmb_prty_bb_b0_regs} } },
1215 {"pcie", {{0, 1, NULL, pcie_prty_bb_b0_regs} } },
1216 {"mcp", {{0, 0, NULL, NULL} } },
1217 {"mcp2", {{0, 2, NULL, mcp2_prty_bb_b0_regs} } },
1218 {"pswhst", {{1, 2, pswhst_int_bb_b0_regs, pswhst_prty_bb_b0_regs} } },
1219 {"pswhst2", {{1, 1, pswhst2_int_bb_b0_regs,
1220 pswhst2_prty_bb_b0_regs} } },
1221 {"pswrd", {{1, 1, pswrd_int_bb_b0_regs, pswrd_prty_bb_b0_regs} } },
1222 {"pswrd2", {{1, 3, pswrd2_int_bb_b0_regs, pswrd2_prty_bb_b0_regs} } },
1223 {"pswwr", {{1, 1, pswwr_int_bb_b0_regs, pswwr_prty_bb_b0_regs} } },
1224 {"pswwr2", {{1, 5, pswwr2_int_bb_b0_regs, pswwr2_prty_bb_b0_regs} } },
1225 {"pswrq", {{1, 1, pswrq_int_bb_b0_regs, pswrq_prty_bb_b0_regs} } },
1226 {"pswrq2", {{1, 1, pswrq2_int_bb_b0_regs, pswrq2_prty_bb_b0_regs} } },
1227 {"pglcs", {{1, 0, pglcs_int_bb_b0_regs, NULL} } },
1228 {"dmae", {{1, 1, dmae_int_bb_b0_regs, dmae_prty_bb_b0_regs} } },
1229 {"ptu", {{1, 1, ptu_int_bb_b0_regs, ptu_prty_bb_b0_regs} } },
1230 {"tcm", {{3, 2, tcm_int_bb_b0_regs, tcm_prty_bb_b0_regs} } },
1231 {"mcm", {{3, 2, mcm_int_bb_b0_regs, mcm_prty_bb_b0_regs} } },
1232 {"ucm", {{3, 2, ucm_int_bb_b0_regs, ucm_prty_bb_b0_regs} } },
1233 {"xcm", {{3, 2, xcm_int_bb_b0_regs, xcm_prty_bb_b0_regs} } },
1234 {"ycm", {{3, 2, ycm_int_bb_b0_regs, ycm_prty_bb_b0_regs} } },
1235 {"pcm", {{3, 1, pcm_int_bb_b0_regs, pcm_prty_bb_b0_regs} } },
1236 {"qm", {{1, 4, qm_int_bb_b0_regs, qm_prty_bb_b0_regs} } },
1237 {"tm", {{2, 1, tm_int_bb_b0_regs, tm_prty_bb_b0_regs} } },
1238 {"dorq", {{1, 2, dorq_int_bb_b0_regs, dorq_prty_bb_b0_regs} } },
1239 {"brb", {{12, 3, brb_int_bb_b0_regs, brb_prty_bb_b0_regs} } },
1240 {"src", {{1, 0, src_int_bb_b0_regs, NULL} } },
1241 {"prs", {{1, 3, prs_int_bb_b0_regs, prs_prty_bb_b0_regs} } },
1242 {"tsdm", {{1, 1, tsdm_int_bb_b0_regs, tsdm_prty_bb_b0_regs} } },
1243 {"msdm", {{1, 1, msdm_int_bb_b0_regs, msdm_prty_bb_b0_regs} } },
1244 {"usdm", {{1, 1, usdm_int_bb_b0_regs, usdm_prty_bb_b0_regs} } },
1245 {"xsdm", {{1, 1, xsdm_int_bb_b0_regs, xsdm_prty_bb_b0_regs} } },
1246 {"ysdm", {{1, 1, ysdm_int_bb_b0_regs, ysdm_prty_bb_b0_regs} } },
1247 {"psdm", {{1, 1, psdm_int_bb_b0_regs, psdm_prty_bb_b0_regs} } },
1248 {"tsem", {{3, 3, tsem_int_bb_b0_regs, tsem_prty_bb_b0_regs} } },
1249 {"msem", {{3, 2, msem_int_bb_b0_regs, msem_prty_bb_b0_regs} } },
1250 {"usem", {{3, 2, usem_int_bb_b0_regs, usem_prty_bb_b0_regs} } },
1251 {"xsem", {{3, 2, xsem_int_bb_b0_regs, xsem_prty_bb_b0_regs} } },
1252 {"ysem", {{3, 2, ysem_int_bb_b0_regs, ysem_prty_bb_b0_regs} } },
1253 {"psem", {{3, 3, psem_int_bb_b0_regs, psem_prty_bb_b0_regs} } },
1254 {"rss", {{1, 1, rss_int_bb_b0_regs, rss_prty_bb_b0_regs} } },
1255 {"tmld", {{1, 1, tmld_int_bb_b0_regs, tmld_prty_bb_b0_regs} } },
1256 {"muld", {{1, 1, muld_int_bb_b0_regs, muld_prty_bb_b0_regs} } },
1257 {"yuld", {{1, 1, yuld_int_bb_b0_regs, yuld_prty_bb_b0_regs} } },
1258 {"xyld", {{1, 1, xyld_int_bb_b0_regs, xyld_prty_bb_b0_regs} } },
1259 {"prm", {{1, 2, prm_int_bb_b0_regs, prm_prty_bb_b0_regs} } },
1260 {"pbf_pb1", {{1, 1, pbf_pb1_int_bb_b0_regs,
1261 pbf_pb1_prty_bb_b0_regs} } },
1262 {"pbf_pb2", {{1, 1, pbf_pb2_int_bb_b0_regs,
1263 pbf_pb2_prty_bb_b0_regs} } },
1264 {"rpb", { {1, 1, rpb_int_bb_b0_regs, rpb_prty_bb_b0_regs} } },
1265 {"btb", { {11, 2, btb_int_bb_b0_regs, btb_prty_bb_b0_regs} } },
1266 {"pbf", { {1, 3, pbf_int_bb_b0_regs, pbf_prty_bb_b0_regs} } },
1267 {"rdif", { {1, 1, rdif_int_bb_b0_regs, rdif_prty_bb_b0_regs} } },
1268 {"tdif", { {1, 2, tdif_int_bb_b0_regs, tdif_prty_bb_b0_regs} } },
1269 {"cdu", { {1, 1, cdu_int_bb_b0_regs, cdu_prty_bb_b0_regs} } },
1270 {"ccfc", { {1, 2, ccfc_int_bb_b0_regs, ccfc_prty_bb_b0_regs} } },
1271 {"tcfc", { {1, 2, tcfc_int_bb_b0_regs, tcfc_prty_bb_b0_regs} } },
1272 {"igu", { {1, 3, igu_int_bb_b0_regs, igu_prty_bb_b0_regs} } },
1273 {"cau", { {1, 1, cau_int_bb_b0_regs, cau_prty_bb_b0_regs} } },
1274 {"umac", { {0, 0, NULL, NULL} } },
1275 {"xmac", { {0, 0, NULL, NULL} } },
1276 {"dbg", { {1, 1, dbg_int_bb_b0_regs, dbg_prty_bb_b0_regs} } },
1277 {"nig", { {6, 5, nig_int_bb_b0_regs, nig_prty_bb_b0_regs} } },
1278 {"wol", { {0, 0, NULL, NULL} } },
1279 {"bmbn", { {0, 0, NULL, NULL} } },
1280 {"ipc", { {1, 1, ipc_int_bb_b0_regs, ipc_prty_bb_b0_regs} } },
1281 {"nwm", { {0, 0, NULL, NULL} } },
1282 {"nws", { {0, 0, NULL, NULL} } },
1283 {"ms", { {0, 0, NULL, NULL} } },
1284 {"phy_pcie", { {0, 0, NULL, NULL} } },
1285 {"misc_aeu", { {0, 0, NULL, NULL} } },
1286 {"bar0_map", { {0, 0, NULL, NULL} } },};
1287
72/* Notice aeu_invert_reg must be defined in the same order of bits as HW; */ 1288/* Notice aeu_invert_reg must be defined in the same order of bits as HW; */
73static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = { 1289static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = {
74 { 1290 {
75 { /* After Invert 1 */ 1291 { /* After Invert 1 */
76 {"GPIO0 function%d", 1292 {"GPIO0 function%d",
77 (32 << ATTENTION_LENGTH_SHIFT)}, 1293 (32 << ATTENTION_LENGTH_SHIFT), MAX_BLOCK_ID},
78 } 1294 }
79 }, 1295 },
80 1296
81 { 1297 {
82 { /* After Invert 2 */ 1298 { /* After Invert 2 */
83 {"PGLUE config_space", ATTENTION_SINGLE}, 1299 {"PGLUE config_space", ATTENTION_SINGLE, MAX_BLOCK_ID},
84 {"PGLUE misc_flr", ATTENTION_SINGLE}, 1300 {"PGLUE misc_flr", ATTENTION_SINGLE, MAX_BLOCK_ID},
85 {"PGLUE B RBC", ATTENTION_PAR_INT}, 1301 {"PGLUE B RBC", ATTENTION_PAR_INT, BLOCK_PGLUE_B},
86 {"PGLUE misc_mctp", ATTENTION_SINGLE}, 1302 {"PGLUE misc_mctp", ATTENTION_SINGLE, MAX_BLOCK_ID},
87 {"Flash event", ATTENTION_SINGLE}, 1303 {"Flash event", ATTENTION_SINGLE, MAX_BLOCK_ID},
88 {"SMB event", ATTENTION_SINGLE}, 1304 {"SMB event", ATTENTION_SINGLE, MAX_BLOCK_ID},
89 {"Main Power", ATTENTION_SINGLE}, 1305 {"Main Power", ATTENTION_SINGLE, MAX_BLOCK_ID},
90 {"SW timers #%d", (8 << ATTENTION_LENGTH_SHIFT) | 1306 {"SW timers #%d", (8 << ATTENTION_LENGTH_SHIFT) |
91 (1 << ATTENTION_OFFSET_SHIFT)}, 1307 (1 << ATTENTION_OFFSET_SHIFT),
1308 MAX_BLOCK_ID},
92 {"PCIE glue/PXP VPD %d", 1309 {"PCIE glue/PXP VPD %d",
93 (16 << ATTENTION_LENGTH_SHIFT)}, 1310 (16 << ATTENTION_LENGTH_SHIFT), BLOCK_PGLCS},
94 } 1311 }
95 }, 1312 },
96 1313
97 { 1314 {
98 { /* After Invert 3 */ 1315 { /* After Invert 3 */
99 {"General Attention %d", 1316 {"General Attention %d",
100 (32 << ATTENTION_LENGTH_SHIFT)}, 1317 (32 << ATTENTION_LENGTH_SHIFT), MAX_BLOCK_ID},
101 } 1318 }
102 }, 1319 },
103 1320
104 { 1321 {
105 { /* After Invert 4 */ 1322 { /* After Invert 4 */
106 {"General Attention 32", ATTENTION_SINGLE}, 1323 {"General Attention 32", ATTENTION_SINGLE,
1324 MAX_BLOCK_ID},
107 {"General Attention %d", 1325 {"General Attention %d",
108 (2 << ATTENTION_LENGTH_SHIFT) | 1326 (2 << ATTENTION_LENGTH_SHIFT) |
109 (33 << ATTENTION_OFFSET_SHIFT)}, 1327 (33 << ATTENTION_OFFSET_SHIFT), MAX_BLOCK_ID},
110 {"General Attention 35", ATTENTION_SINGLE}, 1328 {"General Attention 35", ATTENTION_SINGLE,
111 {"CNIG port %d", (4 << ATTENTION_LENGTH_SHIFT)}, 1329 MAX_BLOCK_ID},
112 {"MCP CPU", ATTENTION_SINGLE}, 1330 {"CNIG port %d", (4 << ATTENTION_LENGTH_SHIFT),
113 {"MCP Watchdog timer", ATTENTION_SINGLE}, 1331 BLOCK_CNIG},
114 {"MCP M2P", ATTENTION_SINGLE}, 1332 {"MCP CPU", ATTENTION_SINGLE, MAX_BLOCK_ID},
115 {"AVS stop status ready", ATTENTION_SINGLE}, 1333 {"MCP Watchdog timer", ATTENTION_SINGLE, MAX_BLOCK_ID},
116 {"MSTAT", ATTENTION_PAR_INT}, 1334 {"MCP M2P", ATTENTION_SINGLE, MAX_BLOCK_ID},
117 {"MSTAT per-path", ATTENTION_PAR_INT}, 1335 {"AVS stop status ready", ATTENTION_SINGLE,
118 {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT)}, 1336 MAX_BLOCK_ID},
119 {"NIG", ATTENTION_PAR_INT}, 1337 {"MSTAT", ATTENTION_PAR_INT, MAX_BLOCK_ID},
120 {"BMB/OPTE/MCP", ATTENTION_PAR_INT}, 1338 {"MSTAT per-path", ATTENTION_PAR_INT, MAX_BLOCK_ID},
121 {"BTB", ATTENTION_PAR_INT}, 1339 {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT),
122 {"BRB", ATTENTION_PAR_INT}, 1340 MAX_BLOCK_ID},
123 {"PRS", ATTENTION_PAR_INT}, 1341 {"NIG", ATTENTION_PAR_INT, BLOCK_NIG},
1342 {"BMB/OPTE/MCP", ATTENTION_PAR_INT, BLOCK_BMB},
1343 {"BTB", ATTENTION_PAR_INT, BLOCK_BTB},
1344 {"BRB", ATTENTION_PAR_INT, BLOCK_BRB},
1345 {"PRS", ATTENTION_PAR_INT, BLOCK_PRS},
124 } 1346 }
125 }, 1347 },
126 1348
127 { 1349 {
128 { /* After Invert 5 */ 1350 { /* After Invert 5 */
129 {"SRC", ATTENTION_PAR_INT}, 1351 {"SRC", ATTENTION_PAR_INT, BLOCK_SRC},
130 {"PB Client1", ATTENTION_PAR_INT}, 1352 {"PB Client1", ATTENTION_PAR_INT, BLOCK_PBF_PB1},
131 {"PB Client2", ATTENTION_PAR_INT}, 1353 {"PB Client2", ATTENTION_PAR_INT, BLOCK_PBF_PB2},
132 {"RPB", ATTENTION_PAR_INT}, 1354 {"RPB", ATTENTION_PAR_INT, BLOCK_RPB},
133 {"PBF", ATTENTION_PAR_INT}, 1355 {"PBF", ATTENTION_PAR_INT, BLOCK_PBF},
134 {"QM", ATTENTION_PAR_INT}, 1356 {"QM", ATTENTION_PAR_INT, BLOCK_QM},
135 {"TM", ATTENTION_PAR_INT}, 1357 {"TM", ATTENTION_PAR_INT, BLOCK_TM},
136 {"MCM", ATTENTION_PAR_INT}, 1358 {"MCM", ATTENTION_PAR_INT, BLOCK_MCM},
137 {"MSDM", ATTENTION_PAR_INT}, 1359 {"MSDM", ATTENTION_PAR_INT, BLOCK_MSDM},
138 {"MSEM", ATTENTION_PAR_INT}, 1360 {"MSEM", ATTENTION_PAR_INT, BLOCK_MSEM},
139 {"PCM", ATTENTION_PAR_INT}, 1361 {"PCM", ATTENTION_PAR_INT, BLOCK_PCM},
140 {"PSDM", ATTENTION_PAR_INT}, 1362 {"PSDM", ATTENTION_PAR_INT, BLOCK_PSDM},
141 {"PSEM", ATTENTION_PAR_INT}, 1363 {"PSEM", ATTENTION_PAR_INT, BLOCK_PSEM},
142 {"TCM", ATTENTION_PAR_INT}, 1364 {"TCM", ATTENTION_PAR_INT, BLOCK_TCM},
143 {"TSDM", ATTENTION_PAR_INT}, 1365 {"TSDM", ATTENTION_PAR_INT, BLOCK_TSDM},
144 {"TSEM", ATTENTION_PAR_INT}, 1366 {"TSEM", ATTENTION_PAR_INT, BLOCK_TSEM},
145 } 1367 }
146 }, 1368 },
147 1369
148 { 1370 {
149 { /* After Invert 6 */ 1371 { /* After Invert 6 */
150 {"UCM", ATTENTION_PAR_INT}, 1372 {"UCM", ATTENTION_PAR_INT, BLOCK_UCM},
151 {"USDM", ATTENTION_PAR_INT}, 1373 {"USDM", ATTENTION_PAR_INT, BLOCK_USDM},
152 {"USEM", ATTENTION_PAR_INT}, 1374 {"USEM", ATTENTION_PAR_INT, BLOCK_USEM},
153 {"XCM", ATTENTION_PAR_INT}, 1375 {"XCM", ATTENTION_PAR_INT, BLOCK_XCM},
154 {"XSDM", ATTENTION_PAR_INT}, 1376 {"XSDM", ATTENTION_PAR_INT, BLOCK_XSDM},
155 {"XSEM", ATTENTION_PAR_INT}, 1377 {"XSEM", ATTENTION_PAR_INT, BLOCK_XSEM},
156 {"YCM", ATTENTION_PAR_INT}, 1378 {"YCM", ATTENTION_PAR_INT, BLOCK_YCM},
157 {"YSDM", ATTENTION_PAR_INT}, 1379 {"YSDM", ATTENTION_PAR_INT, BLOCK_YSDM},
158 {"YSEM", ATTENTION_PAR_INT}, 1380 {"YSEM", ATTENTION_PAR_INT, BLOCK_YSEM},
159 {"XYLD", ATTENTION_PAR_INT}, 1381 {"XYLD", ATTENTION_PAR_INT, BLOCK_XYLD},
160 {"TMLD", ATTENTION_PAR_INT}, 1382 {"TMLD", ATTENTION_PAR_INT, BLOCK_TMLD},
161 {"MYLD", ATTENTION_PAR_INT}, 1383 {"MYLD", ATTENTION_PAR_INT, BLOCK_MULD},
162 {"YULD", ATTENTION_PAR_INT}, 1384 {"YULD", ATTENTION_PAR_INT, BLOCK_YULD},
163 {"DORQ", ATTENTION_PAR_INT}, 1385 {"DORQ", ATTENTION_PAR_INT, BLOCK_DORQ},
164 {"DBG", ATTENTION_PAR_INT}, 1386 {"DBG", ATTENTION_PAR_INT, BLOCK_DBG},
165 {"IPC", ATTENTION_PAR_INT}, 1387 {"IPC", ATTENTION_PAR_INT, BLOCK_IPC},
166 } 1388 }
167 }, 1389 },
168 1390
169 { 1391 {
170 { /* After Invert 7 */ 1392 { /* After Invert 7 */
171 {"CCFC", ATTENTION_PAR_INT}, 1393 {"CCFC", ATTENTION_PAR_INT, BLOCK_CCFC},
172 {"CDU", ATTENTION_PAR_INT}, 1394 {"CDU", ATTENTION_PAR_INT, BLOCK_CDU},
173 {"DMAE", ATTENTION_PAR_INT}, 1395 {"DMAE", ATTENTION_PAR_INT, BLOCK_DMAE},
174 {"IGU", ATTENTION_PAR_INT}, 1396 {"IGU", ATTENTION_PAR_INT, BLOCK_IGU},
175 {"ATC", ATTENTION_PAR_INT}, 1397 {"ATC", ATTENTION_PAR_INT, MAX_BLOCK_ID},
176 {"CAU", ATTENTION_PAR_INT}, 1398 {"CAU", ATTENTION_PAR_INT, BLOCK_CAU},
177 {"PTU", ATTENTION_PAR_INT}, 1399 {"PTU", ATTENTION_PAR_INT, BLOCK_PTU},
178 {"PRM", ATTENTION_PAR_INT}, 1400 {"PRM", ATTENTION_PAR_INT, BLOCK_PRM},
179 {"TCFC", ATTENTION_PAR_INT}, 1401 {"TCFC", ATTENTION_PAR_INT, BLOCK_TCFC},
180 {"RDIF", ATTENTION_PAR_INT}, 1402 {"RDIF", ATTENTION_PAR_INT, BLOCK_RDIF},
181 {"TDIF", ATTENTION_PAR_INT}, 1403 {"TDIF", ATTENTION_PAR_INT, BLOCK_TDIF},
182 {"RSS", ATTENTION_PAR_INT}, 1404 {"RSS", ATTENTION_PAR_INT, BLOCK_RSS},
183 {"MISC", ATTENTION_PAR_INT}, 1405 {"MISC", ATTENTION_PAR_INT, BLOCK_MISC},
184 {"MISCS", ATTENTION_PAR_INT}, 1406 {"MISCS", ATTENTION_PAR_INT, BLOCK_MISCS},
185 {"PCIE", ATTENTION_PAR}, 1407 {"PCIE", ATTENTION_PAR, BLOCK_PCIE},
186 {"Vaux PCI core", ATTENTION_SINGLE}, 1408 {"Vaux PCI core", ATTENTION_SINGLE, BLOCK_PGLCS},
187 {"PSWRQ", ATTENTION_PAR_INT}, 1409 {"PSWRQ", ATTENTION_PAR_INT, BLOCK_PSWRQ},
188 } 1410 }
189 }, 1411 },
190 1412
191 { 1413 {
192 { /* After Invert 8 */ 1414 { /* After Invert 8 */
193 {"PSWRQ (pci_clk)", ATTENTION_PAR_INT}, 1415 {"PSWRQ (pci_clk)", ATTENTION_PAR_INT, BLOCK_PSWRQ2},
194 {"PSWWR", ATTENTION_PAR_INT}, 1416 {"PSWWR", ATTENTION_PAR_INT, BLOCK_PSWWR},
195 {"PSWWR (pci_clk)", ATTENTION_PAR_INT}, 1417 {"PSWWR (pci_clk)", ATTENTION_PAR_INT, BLOCK_PSWWR2},
196 {"PSWRD", ATTENTION_PAR_INT}, 1418 {"PSWRD", ATTENTION_PAR_INT, BLOCK_PSWRD},
197 {"PSWRD (pci_clk)", ATTENTION_PAR_INT}, 1419 {"PSWRD (pci_clk)", ATTENTION_PAR_INT, BLOCK_PSWRD2},
198 {"PSWHST", ATTENTION_PAR_INT}, 1420 {"PSWHST", ATTENTION_PAR_INT, BLOCK_PSWHST},
199 {"PSWHST (pci_clk)", ATTENTION_PAR_INT}, 1421 {"PSWHST (pci_clk)", ATTENTION_PAR_INT, BLOCK_PSWHST2},
200 {"GRC", ATTENTION_PAR_INT}, 1422 {"GRC", ATTENTION_PAR_INT, BLOCK_GRC},
201 {"CPMU", ATTENTION_PAR_INT}, 1423 {"CPMU", ATTENTION_PAR_INT, BLOCK_CPMU},
202 {"NCSI", ATTENTION_PAR_INT}, 1424 {"NCSI", ATTENTION_PAR_INT, BLOCK_NCSI},
203 {"MSEM PRAM", ATTENTION_PAR}, 1425 {"MSEM PRAM", ATTENTION_PAR, MAX_BLOCK_ID},
204 {"PSEM PRAM", ATTENTION_PAR}, 1426 {"PSEM PRAM", ATTENTION_PAR, MAX_BLOCK_ID},
205 {"TSEM PRAM", ATTENTION_PAR}, 1427 {"TSEM PRAM", ATTENTION_PAR, MAX_BLOCK_ID},
206 {"USEM PRAM", ATTENTION_PAR}, 1428 {"USEM PRAM", ATTENTION_PAR, MAX_BLOCK_ID},
207 {"XSEM PRAM", ATTENTION_PAR}, 1429 {"XSEM PRAM", ATTENTION_PAR, MAX_BLOCK_ID},
208 {"YSEM PRAM", ATTENTION_PAR}, 1430 {"YSEM PRAM", ATTENTION_PAR, MAX_BLOCK_ID},
209 {"pxp_misc_mps", ATTENTION_PAR}, 1431 {"pxp_misc_mps", ATTENTION_PAR, BLOCK_PGLCS},
210 {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE}, 1432 {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE,
211 {"PERST_B assertion", ATTENTION_SINGLE}, 1433 BLOCK_PGLCS},
212 {"PERST_B deassertion", ATTENTION_SINGLE}, 1434 {"PERST_B assertion", ATTENTION_SINGLE, MAX_BLOCK_ID},
213 {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT)}, 1435 {"PERST_B deassertion", ATTENTION_SINGLE,
1436 MAX_BLOCK_ID},
1437 {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT),
1438 MAX_BLOCK_ID},
214 } 1439 }
215 }, 1440 },
216 1441
217 { 1442 {
218 { /* After Invert 9 */ 1443 { /* After Invert 9 */
219 {"MCP Latched memory", ATTENTION_PAR}, 1444 {"MCP Latched memory", ATTENTION_PAR, MAX_BLOCK_ID},
220 {"MCP Latched scratchpad cache", ATTENTION_SINGLE}, 1445 {"MCP Latched scratchpad cache", ATTENTION_SINGLE,
221 {"MCP Latched ump_tx", ATTENTION_PAR}, 1446 MAX_BLOCK_ID},
222 {"MCP Latched scratchpad", ATTENTION_PAR}, 1447 {"MCP Latched ump_tx", ATTENTION_PAR, MAX_BLOCK_ID},
223 {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT)}, 1448 {"MCP Latched scratchpad", ATTENTION_PAR,
1449 MAX_BLOCK_ID},
1450 {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT),
1451 MAX_BLOCK_ID},
224 } 1452 }
225 }, 1453 },
226}; 1454};
@@ -316,6 +1544,28 @@ static int qed_int_assertion(struct qed_hwfn *p_hwfn,
316 return 0; 1544 return 0;
317} 1545}
318 1546
1547static void qed_int_deassertion_print_bit(struct qed_hwfn *p_hwfn,
1548 struct attn_hw_reg *p_reg_desc,
1549 struct attn_hw_block *p_block,
1550 enum qed_attention_type type,
1551 u32 val, u32 mask)
1552{
1553 int j;
1554
1555 for (j = 0; j < p_reg_desc->num_of_bits; j++) {
1556 if (!(val & (1 << j)))
1557 continue;
1558
1559 DP_NOTICE(p_hwfn,
1560 "%s (%s): reg %d [0x%08x], bit %d [%s]\n",
1561 p_block->name,
1562 type == QED_ATTN_TYPE_ATTN ? "Interrupt" :
1563 "Parity",
1564 p_reg_desc->reg_idx, p_reg_desc->sts_addr,
1565 j, (mask & (1 << j)) ? " [MASKED]" : "");
1566 }
1567}
1568
319/** 1569/**
320 * @brief qed_int_deassertion_aeu_bit - handles the effects of a single 1570 * @brief qed_int_deassertion_aeu_bit - handles the effects of a single
321 * cause of the attention 1571 * cause of the attention
@@ -340,6 +1590,31 @@ qed_int_deassertion_aeu_bit(struct qed_hwfn *p_hwfn,
340 DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n", 1590 DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n",
341 p_aeu->bit_name, bitmask); 1591 p_aeu->bit_name, bitmask);
342 1592
1593 /* Handle HW block interrupt registers */
1594 if (p_aeu->block_index != MAX_BLOCK_ID) {
1595 struct attn_hw_block *p_block;
1596 int i;
1597
1598 p_block = &attn_blocks[p_aeu->block_index];
1599
1600 /* Handle each interrupt register */
1601 for (i = 0; i < p_block->chip_regs[0].num_of_int_regs; i++) {
1602 struct attn_hw_reg *p_reg_desc;
1603 u32 sts_addr;
1604
1605 p_reg_desc = p_block->chip_regs[0].int_regs[i];
1606 sts_addr = p_reg_desc->sts_addr;
1607
1608 val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, sts_addr);
1609 mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1610 p_reg_desc->mask_addr);
1611 qed_int_deassertion_print_bit(p_hwfn, p_reg_desc,
1612 p_block,
1613 QED_ATTN_TYPE_ATTN,
1614 val, mask);
1615 }
1616 }
1617
343 /* Prevent this Attention from being asserted in the future */ 1618 /* Prevent this Attention from being asserted in the future */
344 val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); 1619 val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
345 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & mask)); 1620 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & mask));
@@ -349,6 +1624,62 @@ qed_int_deassertion_aeu_bit(struct qed_hwfn *p_hwfn,
349 return rc; 1624 return rc;
350} 1625}
351 1626
1627static void qed_int_parity_print(struct qed_hwfn *p_hwfn,
1628 struct aeu_invert_reg_bit *p_aeu,
1629 struct attn_hw_block *p_block,
1630 u8 bit_index)
1631{
1632 int i;
1633
1634 for (i = 0; i < p_block->chip_regs[0].num_of_prty_regs; i++) {
1635 struct attn_hw_reg *p_reg_desc;
1636 u32 val, mask;
1637
1638 p_reg_desc = p_block->chip_regs[0].prty_regs[i];
1639
1640 val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1641 p_reg_desc->sts_clr_addr);
1642 mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1643 p_reg_desc->mask_addr);
1644 qed_int_deassertion_print_bit(p_hwfn, p_reg_desc,
1645 p_block,
1646 QED_ATTN_TYPE_PARITY,
1647 val, mask);
1648 }
1649}
1650
1651/**
1652 * @brief qed_int_deassertion_parity - handle a single parity AEU source
1653 *
1654 * @param p_hwfn
1655 * @param p_aeu - descriptor of an AEU bit which caused the parity
1656 * @param bit_index
1657 */
1658static void qed_int_deassertion_parity(struct qed_hwfn *p_hwfn,
1659 struct aeu_invert_reg_bit *p_aeu,
1660 u8 bit_index)
1661{
1662 u32 block_id = p_aeu->block_index;
1663
1664 DP_INFO(p_hwfn->cdev, "%s[%d] parity attention is set\n",
1665 p_aeu->bit_name, bit_index);
1666
1667 if (block_id != MAX_BLOCK_ID) {
1668 qed_int_parity_print(p_hwfn, p_aeu, &attn_blocks[block_id],
1669 bit_index);
1670
1671 /* In BB, there's a single parity bit for several blocks */
1672 if (block_id == BLOCK_BTB) {
1673 qed_int_parity_print(p_hwfn, p_aeu,
1674 &attn_blocks[BLOCK_OPTE],
1675 bit_index);
1676 qed_int_parity_print(p_hwfn, p_aeu,
1677 &attn_blocks[BLOCK_MCP],
1678 bit_index);
1679 }
1680 }
1681}
1682
352/** 1683/**
353 * @brief - handles deassertion of previously asserted attentions. 1684 * @brief - handles deassertion of previously asserted attentions.
354 * 1685 *
@@ -392,11 +1723,9 @@ static int qed_int_deassertion(struct qed_hwfn *p_hwfn,
392 struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j]; 1723 struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j];
393 1724
394 if ((p_bit->flags & ATTENTION_PARITY) && 1725 if ((p_bit->flags & ATTENTION_PARITY) &&
395 !!(parities & (1 << bit_idx))) { 1726 !!(parities & (1 << bit_idx)))
396 DP_INFO(p_hwfn, 1727 qed_int_deassertion_parity(p_hwfn, p_bit,
397 "%s[%d] parity attention is set\n", 1728 bit_idx);
398 p_bit->bit_name, bit_idx);
399 }
400 1729
401 bit_idx += ATTENTION_LENGTH(p_bit->flags); 1730 bit_idx += ATTENTION_LENGTH(p_bit->flags);
402 } 1731 }
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-30 09:47:17 -0400