diff options
| author | Rodrigo Vivi <vivijim@rdvivi-cozumel.jf.intel.com> | 2019-01-24 17:50:02 -0500 |
|---|---|---|
| committer | Rodrigo Vivi <vivijim@rdvivi-cozumel.jf.intel.com> | 2019-01-24 17:50:04 -0500 |
| commit | ff00d85b4df97bf9cc7082b3d0dc2c317b946aa2 (patch) | |
| tree | 7dae9d0338e0d894dd0cb80c16fff18d28918f58 | |
| parent | 0cdc1d07b4616f164978e8f1b3a5fe8b0a3ac835 (diff) | |
| parent | 2e679d48f38c378650db403b4ba2248adf0691b2 (diff) | |
Merge tag 'gvt-next-2019-01-24' of https://github.com/intel/gvt-linux into drm-intel-next-queued
gvt-next-2019-01-24
- split kvmgt as seperate module (Zhenyu)
- Coffeelake GVT support (Fred)
- const treatment and change for kernel type (Jani)
Signed-off-by: Rodrigo Vivi <vivijim@rdvivi-cozumel.jf.intel.com>
From: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190124054048.GO7203@zhen-hp.sh.intel.com
22 files changed, 204 insertions, 213 deletions
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index f050759686ca..8300efe60fe1 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile | |||
| @@ -200,3 +200,4 @@ endif | |||
| 200 | i915-y += intel_lpe_audio.o | 200 | i915-y += intel_lpe_audio.o |
| 201 | 201 | ||
| 202 | obj-$(CONFIG_DRM_I915) += i915.o | 202 | obj-$(CONFIG_DRM_I915) += i915.o |
| 203 | obj-$(CONFIG_DRM_I915_GVT_KVMGT) += gvt/kvmgt.o | ||
diff --git a/drivers/gpu/drm/i915/gvt/Makefile b/drivers/gpu/drm/i915/gvt/Makefile index b016dc753db9..271fb46d4dd0 100644 --- a/drivers/gpu/drm/i915/gvt/Makefile +++ b/drivers/gpu/drm/i915/gvt/Makefile | |||
| @@ -7,4 +7,3 @@ GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o firmware.o \ | |||
| 7 | 7 | ||
| 8 | ccflags-y += -I$(src) -I$(src)/$(GVT_DIR) | 8 | ccflags-y += -I$(src) -I$(src)/$(GVT_DIR) |
| 9 | i915-y += $(addprefix $(GVT_DIR)/, $(GVT_SOURCE)) | 9 | i915-y += $(addprefix $(GVT_DIR)/, $(GVT_SOURCE)) |
| 10 | obj-$(CONFIG_DRM_I915_GVT_KVMGT) += $(GVT_DIR)/kvmgt.o | ||
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index 77ae634eb11c..35b4ec3f7618 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c | |||
| @@ -55,10 +55,10 @@ struct sub_op_bits { | |||
| 55 | int low; | 55 | int low; |
| 56 | }; | 56 | }; |
| 57 | struct decode_info { | 57 | struct decode_info { |
| 58 | char *name; | 58 | const char *name; |
| 59 | int op_len; | 59 | int op_len; |
| 60 | int nr_sub_op; | 60 | int nr_sub_op; |
| 61 | struct sub_op_bits *sub_op; | 61 | const struct sub_op_bits *sub_op; |
| 62 | }; | 62 | }; |
| 63 | 63 | ||
| 64 | #define MAX_CMD_BUDGET 0x7fffffff | 64 | #define MAX_CMD_BUDGET 0x7fffffff |
| @@ -375,7 +375,7 @@ typedef int (*parser_cmd_handler)(struct parser_exec_state *s); | |||
| 375 | #define ADDR_FIX_5(x1, x2, x3, x4, x5) (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5)) | 375 | #define ADDR_FIX_5(x1, x2, x3, x4, x5) (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5)) |
| 376 | 376 | ||
| 377 | struct cmd_info { | 377 | struct cmd_info { |
| 378 | char *name; | 378 | const char *name; |
| 379 | u32 opcode; | 379 | u32 opcode; |
| 380 | 380 | ||
| 381 | #define F_LEN_MASK (1U<<0) | 381 | #define F_LEN_MASK (1U<<0) |
| @@ -399,10 +399,10 @@ struct cmd_info { | |||
| 399 | #define R_VECS (1 << VECS) | 399 | #define R_VECS (1 << VECS) |
| 400 | #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS) | 400 | #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS) |
| 401 | /* rings that support this cmd: BLT/RCS/VCS/VECS */ | 401 | /* rings that support this cmd: BLT/RCS/VCS/VECS */ |
| 402 | uint16_t rings; | 402 | u16 rings; |
| 403 | 403 | ||
| 404 | /* devices that support this cmd: SNB/IVB/HSW/... */ | 404 | /* devices that support this cmd: SNB/IVB/HSW/... */ |
| 405 | uint16_t devices; | 405 | u16 devices; |
| 406 | 406 | ||
| 407 | /* which DWords are address that need fix up. | 407 | /* which DWords are address that need fix up. |
| 408 | * bit 0 means a 32-bit non address operand in command | 408 | * bit 0 means a 32-bit non address operand in command |
| @@ -412,20 +412,20 @@ struct cmd_info { | |||
| 412 | * No matter the address length, each address only takes | 412 | * No matter the address length, each address only takes |
| 413 | * one bit in the bitmap. | 413 | * one bit in the bitmap. |
| 414 | */ | 414 | */ |
| 415 | uint16_t addr_bitmap; | 415 | u16 addr_bitmap; |
| 416 | 416 | ||
| 417 | /* flag == F_LEN_CONST : command length | 417 | /* flag == F_LEN_CONST : command length |
| 418 | * flag == F_LEN_VAR : length bias bits | 418 | * flag == F_LEN_VAR : length bias bits |
| 419 | * Note: length is in DWord | 419 | * Note: length is in DWord |
| 420 | */ | 420 | */ |
| 421 | uint8_t len; | 421 | u8 len; |
| 422 | 422 | ||
| 423 | parser_cmd_handler handler; | 423 | parser_cmd_handler handler; |
| 424 | }; | 424 | }; |
| 425 | 425 | ||
| 426 | struct cmd_entry { | 426 | struct cmd_entry { |
| 427 | struct hlist_node hlist; | 427 | struct hlist_node hlist; |
| 428 | struct cmd_info *info; | 428 | const struct cmd_info *info; |
| 429 | }; | 429 | }; |
| 430 | 430 | ||
| 431 | enum { | 431 | enum { |
| @@ -474,7 +474,7 @@ struct parser_exec_state { | |||
| 474 | int saved_buf_addr_type; | 474 | int saved_buf_addr_type; |
| 475 | bool is_ctx_wa; | 475 | bool is_ctx_wa; |
| 476 | 476 | ||
| 477 | struct cmd_info *info; | 477 | const struct cmd_info *info; |
| 478 | 478 | ||
| 479 | struct intel_vgpu_workload *workload; | 479 | struct intel_vgpu_workload *workload; |
| 480 | }; | 480 | }; |
| @@ -485,12 +485,12 @@ struct parser_exec_state { | |||
| 485 | static unsigned long bypass_scan_mask = 0; | 485 | static unsigned long bypass_scan_mask = 0; |
| 486 | 486 | ||
| 487 | /* ring ALL, type = 0 */ | 487 | /* ring ALL, type = 0 */ |
| 488 | static struct sub_op_bits sub_op_mi[] = { | 488 | static const struct sub_op_bits sub_op_mi[] = { |
| 489 | {31, 29}, | 489 | {31, 29}, |
| 490 | {28, 23}, | 490 | {28, 23}, |
| 491 | }; | 491 | }; |
| 492 | 492 | ||
| 493 | static struct decode_info decode_info_mi = { | 493 | static const struct decode_info decode_info_mi = { |
| 494 | "MI", | 494 | "MI", |
| 495 | OP_LEN_MI, | 495 | OP_LEN_MI, |
| 496 | ARRAY_SIZE(sub_op_mi), | 496 | ARRAY_SIZE(sub_op_mi), |
| @@ -498,12 +498,12 @@ static struct decode_info decode_info_mi = { | |||
| 498 | }; | 498 | }; |
| 499 | 499 | ||
| 500 | /* ring RCS, command type 2 */ | 500 | /* ring RCS, command type 2 */ |
| 501 | static struct sub_op_bits sub_op_2d[] = { | 501 | static const struct sub_op_bits sub_op_2d[] = { |
| 502 | {31, 29}, | 502 | {31, 29}, |
| 503 | {28, 22}, | 503 | {28, 22}, |
| 504 | }; | 504 | }; |
| 505 | 505 | ||
| 506 | static struct decode_info decode_info_2d = { | 506 | static const struct decode_info decode_info_2d = { |
| 507 | "2D", | 507 | "2D", |
| 508 | OP_LEN_2D, | 508 | OP_LEN_2D, |
| 509 | ARRAY_SIZE(sub_op_2d), | 509 | ARRAY_SIZE(sub_op_2d), |
| @@ -511,14 +511,14 @@ static struct decode_info decode_info_2d = { | |||
| 511 | }; | 511 | }; |
| 512 | 512 | ||
| 513 | /* ring RCS, command type 3 */ | 513 | /* ring RCS, command type 3 */ |
| 514 | static struct sub_op_bits sub_op_3d_media[] = { | 514 | static const struct sub_op_bits sub_op_3d_media[] = { |
| 515 | {31, 29}, | 515 | {31, 29}, |
| 516 | {28, 27}, | 516 | {28, 27}, |
| 517 | {26, 24}, | 517 | {26, 24}, |
| 518 | {23, 16}, | 518 | {23, 16}, |
| 519 | }; | 519 | }; |
| 520 | 520 | ||
| 521 | static struct decode_info decode_info_3d_media = { | 521 | static const struct decode_info decode_info_3d_media = { |
| 522 | "3D_Media", | 522 | "3D_Media", |
| 523 | OP_LEN_3D_MEDIA, | 523 | OP_LEN_3D_MEDIA, |
| 524 | ARRAY_SIZE(sub_op_3d_media), | 524 | ARRAY_SIZE(sub_op_3d_media), |
| @@ -526,7 +526,7 @@ static struct decode_info decode_info_3d_media = { | |||
| 526 | }; | 526 | }; |
| 527 | 527 | ||
| 528 | /* ring VCS, command type 3 */ | ||
