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authorKishon Vijay Abraham I <kishon@ti.com>2017-02-15 08:18:17 -0500
committerBjorn Helgaas <bhelgaas@google.com>2017-02-21 16:00:26 -0500
commitfeb85d9b1c47ea8dbcae559ff127b433fdb245b7 (patch)
tree456e5523951340162218118087acd49303d5fc05
parent314fc854f50317931fb4dfaab431695ab886e8de (diff)
PCI: dwc: Split pcie-designware.c into host and core files
Split pcie-designware.c into pcie-designware-host.c that contains the host specific parts of the driver and pcie-designware.c that contains the parts used by both host driver and endpoint driver. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat
-rw-r--r--drivers/pci/dwc/Makefile2
-rw-r--r--drivers/pci/dwc/pcie-designware-host.c635
-rw-r--r--drivers/pci/dwc/pcie-designware.c629
-rw-r--r--drivers/pci/dwc/pcie-designware.h8
4 files changed, 650 insertions, 624 deletions
diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile
index 7d27c143ae7a..3b57e55d97b3 100644
--- a/drivers/pci/dwc/Makefile
+++ b/drivers/pci/dwc/Makefile
@@ -1,4 +1,4 @@
1obj-$(CONFIG_PCIE_DW) += pcie-designware.o 1obj-$(CONFIG_PCIE_DW) += pcie-designware.o pcie-designware-host.o
2obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o 2obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
3obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o 3obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
4obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o 4obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
new file mode 100644
index 000000000000..5ba334938b52
--- /dev/null
+++ b/drivers/pci/dwc/pcie-designware-host.c
@@ -0,0 +1,635 @@
1/*
2 * Synopsys Designware PCIe host controller driver
3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Author: Jingoo Han <jg1.han@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/irqdomain.h>
15#include <linux/of_address.h>
16#include <linux/of_pci.h>
17#include <linux/pci_regs.h>
18#include <linux/platform_device.h>
19
20#include "pcie-designware.h"
21
22static struct pci_ops dw_pcie_ops;
23
24static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
25 u32 *val)
26{
27 struct dw_pcie *pci;
28
29 if (pp->ops->rd_own_conf)
30 return pp->ops->rd_own_conf(pp, where, size, val);
31
32 pci = to_dw_pcie_from_pp(pp);
33 return dw_pcie_read(pci->dbi_base + where, size, val);
34}
35
36static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
37 u32 val)
38{
39 struct dw_pcie *pci;
40
41 if (pp->ops->wr_own_conf)
42 return pp->ops->wr_own_conf(pp, where, size, val);
43
44 pci = to_dw_pcie_from_pp(pp);
45 return dw_pcie_write(pci->dbi_base + where, size, val);
46}
47
48static struct irq_chip dw_msi_irq_chip = {
49 .name = "PCI-MSI",
50 .irq_enable = pci_msi_unmask_irq,
51 .irq_disable = pci_msi_mask_irq,
52 .irq_mask = pci_msi_mask_irq,
53 .irq_unmask = pci_msi_unmask_irq,
54};
55
56/* MSI int handler */
57irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
58{
59 unsigned long val;
60 int i, pos, irq;
61 irqreturn_t ret = IRQ_NONE;
62
63 for (i = 0; i < MAX_MSI_CTRLS; i++) {
64 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
65 (u32 *)&val);
66 if (val) {
67 ret = IRQ_HANDLED;
68 pos = 0;
69 while ((pos = find_next_bit(&val, 32, pos)) != 32) {
70 irq = irq_find_mapping(pp->irq_domain,
71 i * 32 + pos);
72 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS +
73 i * 12, 4, 1 << pos);
74 generic_handle_irq(irq);
75 pos++;
76 }
77 }
78 }
79
80 return ret;
81}
82
83void dw_pcie_msi_init(struct pcie_port *pp)
84{
85 u64 msi_target;
86
87 pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
88 msi_target = virt_to_phys((void *)pp->msi_data);
89
90 /* program the msi_data */
91 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
92 (u32)(msi_target & 0xffffffff));
93 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4,
94 (u32)(msi_target >> 32 & 0xffffffff));
95}
96
97static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
98{
99 unsigned int res, bit, val;
100
101 res = (irq / 32) * 12;
102 bit = irq % 32;
103 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
104 val &= ~(1 << bit);
105 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
106}
107
108static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
109 unsigned int nvec, unsigned int pos)
110{
111 unsigned int i;
112
113 for (i = 0; i < nvec; i++) {
114 irq_set_msi_desc_off(irq_base, i, NULL);
115 /* Disable corresponding interrupt on MSI controller */
116 if (pp->ops->msi_clear_irq)
117 pp->ops->msi_clear_irq(pp, pos + i);
118 else
119 dw_pcie_msi_clear_irq(pp, pos + i);
120 }
121
122 bitmap_release_region(pp->msi_irq_in_use, pos, order_base_2(nvec));
123}
124
125static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
126{
127 unsigned int res, bit, val;
128
129 res = (irq / 32) * 12;
130 bit = irq % 32;
131 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
132 val |= 1 << bit;
133 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
134}
135
136static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
137{
138 int irq, pos0, i;
139 struct pcie_port *pp;
140
141 pp = (struct pcie_port *)msi_desc_to_pci_sysdata(desc);
142 pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS,
143 order_base_2(no_irqs));
144 if (pos0 < 0)
145 goto no_valid_irq;
146
147 irq = irq_find_mapping(pp->irq_domain, pos0);
148 if (!irq)
149 goto no_valid_irq;
150
151 /*
152 * irq_create_mapping (called from dw_pcie_host_init) pre-allocates
153 * descs so there is no need to allocate descs here. We can therefore
154 * assume that if irq_find_mapping above returns non-zero, then the
155 * descs are also successfully allocated.
156 */
157
158 for (i = 0; i < no_irqs; i++) {
159 if (irq_set_msi_desc_off(irq, i, desc) != 0) {
160 clear_irq_range(pp, irq, i, pos0);
161 goto no_valid_irq;
162 }
163 /*Enable corresponding interrupt in MSI interrupt controller */
164 if (pp->ops->msi_set_irq)
165 pp->ops->msi_set_irq(pp, pos0 + i);
166 else
167 dw_pcie_msi_set_irq(pp, pos0 + i);
168 }
169
170 *pos = pos0;
171 desc->nvec_used = no_irqs;
172 desc->msi_attrib.multiple = order_base_2(no_irqs);
173
174 return irq;
175
176no_valid_irq:
177 *pos = pos0;
178 return -ENOSPC;
179}
180
181static void dw_msi_setup_msg(struct pcie_port *pp, unsigned int irq, u32 pos)
182{
183 struct msi_msg msg;
184 u64 msi_target;
185
186 if (pp->ops->get_msi_addr)
187 msi_target = pp->ops->get_msi_addr(pp);
188 else
189 msi_target = virt_to_phys((void *)pp->msi_data);
190
191 msg.address_lo = (u32)(msi_target & 0xffffffff);
192 msg.address_hi = (u32)(msi_target >> 32 & 0xffffffff);
193
194 if (pp->ops->get_msi_data)
195 msg.data = pp->ops->get_msi_data(pp, pos);
196 else
197 msg.data = pos;
198
199 pci_write_msi_msg(irq, &msg);
200}
201
202static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
203 struct msi_desc *desc)
204{
205 int irq, pos;
206 struct pcie_port *pp = pdev->bus->sysdata;
207
208 if (desc->msi_attrib.is_msix)
209 return -EINVAL;
210
211 irq = assign_irq(1, desc, &pos);
212 if (irq < 0)
213 return irq;
214
215 dw_msi_setup_msg(pp, irq, pos);
216
217 return 0;
218}
219
220static int dw_msi_setup_irqs(struct msi_controller *chip, struct pci_dev *pdev,
221 int nvec, int type)
222{
223#ifdef CONFIG_PCI_MSI
224 int irq, pos;
225 struct msi_desc *desc;
226 struct pcie_port *pp = pdev->bus->sysdata;
227
228 /* MSI-X interrupts are not supported */
229 if (type == PCI_CAP_ID_MSIX)
230 return -EINVAL;
231
232 WARN_ON(!list_is_singular(&pdev->dev.msi_list));
233 desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list);
234
235 irq = assign_irq(nvec, desc, &pos);
236 if (irq < 0)
237 return irq;
238
239 dw_msi_setup_msg(pp, irq, pos);
240
241 return 0;
242#else
243 return -EINVAL;
244#endif
245}
246
247static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
248{
249 struct irq_data *data = irq_get_irq_data(irq);
250 struct msi_desc *msi = irq_data_get_msi_desc(data);
251 struct pcie_port *pp = (struct pcie_port *)msi_desc_to_pci_sysdata(msi);
252
253 clear_irq_range(pp, irq, 1, data->hwirq);
254}
255
256static struct msi_controller dw_pcie_msi_chip = {
257 .setup_irq = dw_msi_setup_irq,
258 .setup_irqs = dw_msi_setup_irqs,
259 .teardown_irq = dw_msi_teardown_irq,
260};
261
262static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
263 irq_hw_number_t hwirq)
264{
265 irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq);
266 irq_set_chip_data(irq, domain->host_data);
267
268 return 0;
269}
270
271static const struct irq_domain_ops msi_domain_ops = {
272 .map = dw_pcie_msi_map,
273};
274
275int dw_pcie_host_init(struct pcie_port *pp)
276{
277 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
278 struct device *dev = pci->dev;
279 struct device_node *np = dev->of_node;
280 struct platform_device *pdev = to_platform_device(dev);
281 struct pci_bus *bus, *child;
282 struct resource *cfg_res;
283 int i, ret;
284 LIST_HEAD(res);
285 struct resource_entry *win, *tmp;
286
287 cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
288 if (cfg_res) {
289 pp->cfg0_size = resource_size(cfg_res) / 2;
290 pp->cfg1_size = resource_size(cfg_res) / 2;
291 pp->cfg0_base = cfg_res->start;
292 pp->cfg1_base = cfg_res->start + pp->cfg0_size;
293 } else if (!pp->va_cfg0_base) {
294 dev_err(dev, "missing *config* reg space\n");
295 }
296
297 ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &pp->io_base);
298 if (ret)
299 return ret;
300
301 ret = devm_request_pci_bus_resources(dev, &res);
302 if (ret)
303 goto error;
304
305 /* Get the I/O and memory ranges from DT */
306 resource_list_for_each_entry_safe(win, tmp, &res) {
307 switch (resource_type(win->res)) {
308 case IORESOURCE_IO:
309 ret = pci_remap_iospace(win->res, pp->io_base);
310 if (ret) {
311 dev_warn(dev, "error %d: failed to map resource %pR\n",
312 ret, win->res);
313 resource_list_destroy_entry(win);
314 } else {
315 pp->io = win->res;
316 pp->io->name = "I/O";
317 pp->io_size = resource_size(pp->io);
318 pp->io_bus_addr = pp->io->start - win->offset;
319 }
320 break;
321 case IORESOURCE_MEM:
322 pp->mem = win->res;
323 pp->mem->name = "MEM";
324 pp->mem_size = resource_size(pp->mem);
325 pp->mem_bus_addr = pp->mem->start - win->offset;
326 break;
327 case 0:
328 pp->cfg = win->res;
329 pp->cfg0_size = resource_size(pp->cfg) / 2;
330 pp->cfg1_size = resource_size(pp->cfg) / 2;
331 pp->cfg0_base = pp->cfg->start;
332 pp->cfg1_base = pp->cfg->start + pp->cfg0_size;
333 break;
334 case IORESOURCE_BUS:
335 pp->busn = win->res;
336 break;
337 }
338 }
339
340 if (!pci->dbi_base) {
341 pci->dbi_base = devm_ioremap(dev, pp->cfg->start,
342 resource_size(pp->cfg));
343 if (!pci->dbi_base) {
344 dev_err(dev, "error with ioremap\n");
345 ret = -ENOMEM;
346 goto error;
347 }
348 }
349
350 pp->mem_base = pp->mem->start;
351
352 if (!pp->va_cfg0_base) {
353 pp->va_cfg0_base = devm_ioremap(dev, pp->cfg0_base,
354 pp->cfg0_size);
355 if (!pp->va_cfg0_base) {
356 dev_err(dev, "error with ioremap in function\n");
357 ret = -ENOMEM;
358 goto error;
359 }
360 }
361
362 if (!pp->va_cfg1_base) {
363 pp->va_cfg1_base = devm_ioremap(dev, pp->cfg1_base,
364 pp->cfg1_size);
365 if (!pp->va_cfg1_base) {
366 dev_err(dev, "error with ioremap\n");
367 ret = -ENOMEM;
368 goto error;
369 }
370 }
371
372 ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport);
373 if (ret)
374 pci->num_viewport = 2;
375
376 if (IS_ENABLED(CONFIG_PCI_MSI)) {
377 if (!pp->ops->msi_host_init) {
378 pp->irq_domain = irq_domain_add_linear(dev->of_node,
379 MAX_MSI_IRQS, &msi_domain_ops,
380 &dw_pcie_msi_chip);
381 if (!pp->irq_domain) {
382 dev_err(dev, "irq domain init failed\n");
383 ret = -ENXIO;
384 goto error;
385 }
386
387 for (i = 0; i < MAX_MSI_IRQS; i++)
388 irq_create_mapping(pp->irq_domain, i);
389 } else {
390 ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip);
391 if (ret < 0)
392 goto error;
393 }
394 }
395
396 if (pp->ops->host_init)
397 pp->ops->host_init(pp);
398
399 pp->root_bus_nr = pp->busn->start;
400 if (IS_ENABLED(CONFIG_PCI_MSI)) {
401 bus = pci_scan_root_bus_msi(dev, pp->root_bus_nr,
402 &dw_pcie_ops, pp, &res,
403 &dw_pcie_msi_chip);
404 dw_pcie_msi_chip.dev = dev;
405 } else
406 bus = pci_scan_root_bus(dev, pp->root_bus_nr, &dw_pcie_ops,
407 pp, &res);
408 if (!bus) {
409 ret = -ENOMEM;
410 goto error;
411 }
412
413 if (pp->ops->scan_bus)
414 pp->ops->scan_bus(pp);
415
416#ifdef CONFIG_ARM
417 /* support old dtbs that incorrectly describe IRQs */
418 pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
419#endif
420
421 pci_bus_size_bridges(bus);
422 pci_bus_assign_resources(bus);
423
424 list_for_each_entry(child, &bus->children, node)
425 pcie_bus_configure_settings(child);
426
427 pci_bus_add_devices(bus);
428 return 0;
429
430error:
431 pci_free_resource_list(&res);
432 return ret;
433}
434
435static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
436 u32 devfn, int where, int size, u32 *val)
437{
438 int ret, type;
439 u32 busdev, cfg_size;
440 u64 cpu_addr;
441 void __iomem *va_cfg_base;
442 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
443
444 if (pp->ops->rd_other_conf)
445 return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val);
446
447 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
448 PCIE_ATU_FUNC(PCI_FUNC(devfn));
449
450 if (bus->parent->number == pp->root_bus_nr) {
451 type = PCIE_ATU_TYPE_CFG0;
452 cpu_addr = pp->cfg0_base;
453 cfg_size = pp->cfg0_size;
454 va_cfg_base = pp->va_cfg0_base;
455 } else {
456 type = PCIE_ATU_TYPE_CFG1;
457 cpu_addr = pp->cfg1_base;
458 cfg_size = pp->cfg1_size;
459 va_cfg_base = pp->va_cfg1_base;
460 }
461
462 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
463 type, cpu_addr,
464 busdev, cfg_size);
465 ret = dw_pcie_read(va_cfg_base + where, size, val);
466 if (pci->num_viewport <= 2)
467 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
468 PCIE_ATU_TYPE_IO, pp->io_base,
469 pp->io_bus_addr, pp->io_size);
470
471 return ret;
472}
473
474static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
475 u32 devfn, int where, int size, u32 val)
476{
477 int ret, type;
478 u32 busdev, cfg_size;
479 u64 cpu_addr;
480 void __iomem *va_cfg_base;
481 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
482
483 if (pp->ops->wr_other_conf)
484 return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val);
485
486 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
487 PCIE_ATU_FUNC(PCI_FUNC(devfn));
488
489 if (bus->parent->number == pp->root_bus_nr) {
490 type = PCIE_ATU_TYPE_CFG0;
491 cpu_addr = pp->cfg0_base;
492 cfg_size = pp->cfg0_size;
493 va_cfg_base = pp->va_cfg0_base;
494 } else {
495 type = PCIE_ATU_TYPE_CFG1;
496 cpu_addr = pp->cfg1_base;
497 cfg_size = pp->cfg1_size;
498 va_cfg_base = pp->va_cfg1_base;
499 }
500
501 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
502 type, cpu_addr,
503 busdev, cfg_size);
504 ret = dw_pcie_write(va_cfg_base + where, size, val);
505 if (pci->num_viewport <= 2)
506 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
507 PCIE_ATU_TYPE_IO, pp->io_base,
508 pp->io_bus_addr, pp->io_size);
509
510 return ret;
511}
512
513static int dw_pcie_valid_device(struct pcie_port *pp, struct pci_bus *bus,
514 int dev)
515{
516 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
517
518 /* If there is no link, then there is no device */
519 if (bus->number != pp->root_bus_nr) {
520 if (!dw_pcie_link_up(pci))
521 return 0;
522 }
523
524 /* access only one slot on each root port */
525 if (bus->number == pp->root_bus_nr && dev > 0)
526 return 0;
527
528 return 1;
529}
530
531static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
532 int size, u32 *val)
533{
534 struct pcie_port *pp = bus->sysdata;
535
536 if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn))) {
537 *val = 0xffffffff;
538 return PCIBIOS_DEVICE_NOT_FOUND;
539 }
540
541 if (bus->number == pp->root_bus_nr)
542 return dw_pcie_rd_own_conf(pp, where, size, val);
543
544 return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val);
545}
546
547static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
548 int where, int size, u32 val)
549{
550 struct pcie_port *pp = bus->sysdata;
551
552 if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn)))
553 return PCIBIOS_DEVICE_NOT_FOUND;
554
555 if (bus->number == pp->root_bus_nr)
556 return dw_pcie_wr_own_conf(pp, where, size, val);
557
558 return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
559}
560
561static struct pci_ops dw_pcie_ops = {
562 .read = dw_pcie_rd_conf,
563 .write = dw_pcie_wr_conf,
564};
565
566static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
567{
568 u32 val;
569
570 val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
571 if (val == 0xffffffff)
572 return 1;
573
574 return 0;
575}
576
577void dw_pcie_setup_rc(struct pcie_port *pp)
578{
579 u32 val;
580 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
581
582 dw_pcie_setup(pci);
583
584 /* setup RC BARs */
585 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);
586 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
587
588 /* setup interrupt pins */
589 val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
590 val &= 0xffff00ff;
591 val |= 0x00000100;
592 dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
593
594 /* setup bus numbers */
595 val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
596 val &= 0xff000000;
597 val |= 0x00010100;
598 dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val);
599
600 /* setup command register */
601 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
602 val &= 0xffff0000;
603 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
604 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
605 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
606
607 /*
608 * If the platform provides ->rd_other_conf, it means the platform
609 * uses its own address translation component rather than ATU, so
610 * we should not program the ATU here.
611 */
612 if (!pp->ops->rd_other_conf) {
613 /* get iATU unroll support */
614 pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci);
615 dev_dbg(pci->dev, "iATU unroll: %s\n",
616 pci->iatu_unroll_enabled ? "enabled" : "disabled");
617
618 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,
619 PCIE_ATU_TYPE_MEM, pp->mem_base,
620 pp->mem_bus_addr, pp->mem_size);
621 if (pci->num_viewport > 2)
622 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX2,
623 PCIE_ATU_TYPE_IO, pp->io_base,
624 pp->io_bus_addr, pp->io_size);
625 }
626
627 dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
628
629 /* program correct class for RC */
630 dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
631
632 dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
633 val |= PORT_LOGIC_SPEED_CHANGE;
634 dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
635}
diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
index 622d41653f73..7e1fb7d6643c 100644
--- a/drivers/pci/dwc/pcie-designware.c
+++ b/drivers/pci/dwc/pcie-designware.c
@@ -11,17 +11,9 @@
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 */ 12 */
13 13
14#include <linux/irq.h>
15#include <linux/irqdomain.h>
16#include <linux/kernel.h>
17#include <linux/msi.h>
18#include <linux/of_address.h>
19#include <linux/of_pci.h>
20#include <linux/pci.h>
21#include <linux/pci_regs.h>
22#include <linux/platform_device.h>
23#include <linux/types.h>
24#include <linux/delay.h> 14#include <linux/delay.h>
15#include <linux/of.h>
16#include <linux/types.h>
25 17
26#include "pcie-designware.h" 18#include "pcie-designware.h"
27 19
@@ -31,8 +23,6 @@
31#define PCIE_PHY_DEBUG_R1_LINK_UP (0x1 << 4) 23#define PCIE_PHY_DEBUG_R1_LINK_UP (0x1 << 4)
32#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29) 24#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29)
33 25
34static struct pci_ops dw_pcie_ops;
35
36int dw_pcie_read(void __iomem *addr, int size, u32 *val) 26int dw_pcie_read(void __iomem *addr, int size, u32 *val)
37{ 27{
38 if ((uintptr_t)addr & (size - 1)) { 28 if ((uintptr_t)addr & (size - 1)) {
@@ -102,33 +92,8 @@ static void dw_pcie_writel_unroll(struct dw_pcie *pci, u32 index, u32 reg,
102 dw_pcie_writel_dbi(pci, offset + reg, val); 92 dw_pcie_writel_dbi(pci, offset + reg, val);
103} 93}
104 94
105static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, 95void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
106 u32 *val) 96 u64 cpu_addr, u64 pci_addr, u32 size)
107{
108 struct dw_pcie *pci;
109
110 if (pp->ops->rd_own_conf)
111 return pp->ops->rd_own_conf(pp, where, size, val);
112
113 pci = to_dw_pcie_from_pp(pp);
114 return dw_pcie_read(pci->dbi_base + where, size, val);
115}
116
117static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
118 u32 val)
119{
120 struct dw_pcie *pci;
121
122 if (pp->ops->wr_own_conf)
123 return pp->ops->wr_own_conf(pp, where, size, val);
124
125 pci = to_dw_pcie_from_pp(pp);
126 return dw_pcie_write(pci->dbi_base + where, size, val);
127}
128
129static void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
130 int type, u64 cpu_addr, u64 pci_addr,
131 u32 size)
132{ 97{
133 u32 retries, val; 98 u32 retries, val;
134 99
@@ -183,220 +148,6 @@ static void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
183 dev_err(pci->dev, "iATU is not being enabled\n"); 148 dev_err(pci->dev, "iATU is not being enabled\n");
184} 149}
185 150
186static struct irq_chip dw_msi_irq_chip = {
187 .name = "PCI-MSI",
188 .irq_enable = pci_msi_unmask_irq,
189 .irq_disable = pci_msi_mask_irq,
190 .irq_mask = pci_msi_mask_irq,
191 .irq_unmask = pci_msi_unmask_irq,
192};
193
194/* MSI int handler */
195irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
196{
197 unsigned long val;
198 int i, pos, irq;
199 irqreturn_t ret = IRQ_NONE;
200
201 for (i = 0; i < MAX_MSI_CTRLS; i++) {
202 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
203 (u32 *)&val);
204 if (val) {
205 ret = IRQ_HANDLED;
206 pos = 0;
207 while ((pos = find_next_bit(&val, 32, pos)) != 32) {
208 irq = irq_find_mapping(pp->irq_domain,
209 i * 32 + pos);
210 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS +
211 i * 12, 4, 1 << pos);
212 generic_handle_irq(irq);
213 pos++;
214 }
215 }
216 }
217
218 return ret;
219}
220
221void dw_pcie_msi_init(struct pcie_port *pp)
222{
223 u64 msi_target;
224
225 pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
226 msi_target = virt_to_phys((void *)pp->msi_data);
227
228 /* program the msi_data */
229 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
230 (u32)(msi_target & 0xffffffff));
231 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4,
232 (u32)(msi_target >> 32 & 0xffffffff));
233}
234
235static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
236{
237 unsigned int res, bit, val;
238
239 res = (irq / 32) * 12;
240 bit = irq % 32;
241 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
242 val &= ~(1 << bit);
243 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
244}
245
246static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
247 unsigned int nvec, unsigned int pos)
248{
249 unsigned int i;
250
251 for (i = 0; i < nvec; i++) {
252 irq_set_msi_desc_off(irq_base, i, NULL);
253 /* Disable corresponding interrupt on MSI controller */
254 if (pp->ops->msi_clear_irq)
255 pp->ops->msi_clear_irq(pp, pos + i);
256 else
257 dw_pcie_msi_clear_irq(pp, pos + i);
258 }
259
260 bitmap_release_region(pp->msi_irq_in_use, pos, order_base_2(nvec));
261}
262
263static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
264{
265 unsigned int res, bit, val;
266
267 res = (irq / 32) * 12;
268 bit = irq % 32;
269 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
270 val |= 1 << bit;
271 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
272}
273
274static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
275{
276 int irq, pos0, i;
277 struct pcie_port *pp;
278
279 pp = (struct pcie_port *)msi_desc_to_pci_sysdata(desc);
280 pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS,
281 order_base_2(no_irqs));
282 if (pos0 < 0)
283 goto no_valid_irq;
284
285 irq = irq_find_mapping(pp->irq_domain, pos0);
286 if (!irq)
287 goto no_valid_irq;
288
289 /*
290 * irq_create_mapping (called from dw_pcie_host_init) pre-allocates
291 * descs so there is no need to allocate descs here. We can therefore
292 * assume that if irq_find_mapping above returns non-zero, then the
293 * descs are also successfully allocated.
294 */
295
296 for (i = 0; i < no_irqs; i++) {
297 if (irq_set_msi_desc_off(irq, i, desc) != 0) {
298 clear_irq_range(pp, irq, i, pos0);
299 goto no_valid_irq;
300 }
301 /*Enable corresponding interrupt in MSI interrupt controller */
302 if (pp->ops->msi_set_irq)
303 pp->ops->msi_set_irq(pp, pos0 + i);
304 else
305 dw_pcie_msi_set_irq(pp, pos0 + i);
306 }
307
308 *pos = pos0;
309 desc->nvec_used = no_irqs;
310 desc->msi_attrib.multiple = order_base_2(no_irqs);
311
312 return irq;
313
314no_valid_irq:
315 *pos = pos0;
316 return -ENOSPC;
317}
318
319static void dw_msi_setup_msg(struct pcie_port *pp, unsigned int irq, u32 pos)
320{
321 struct msi_msg msg;
322 u64 msi_target;
323
324 if (pp->ops->get_msi_addr)
325 msi_target = pp->ops->get_msi_addr(pp);
326 else
327 msi_target = virt_to_phys((void *)pp->msi_data);
328
329 msg.address_lo = (u32)(msi_target & 0xffffffff);
330 msg.address_hi = (u32)(msi_target >> 32 & 0xffffffff);
331
332 if (pp->ops->get_msi_data)
333 msg.data = pp->ops->get_msi_data(pp, pos);
334 else
335 msg.data = pos;
336
337 pci_write_msi_msg(irq, &msg);
338}
339
340static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
341 struct msi_desc *desc)
342{
343 int irq, pos;
344 struct pcie_port *pp = pdev->bus->sysdata;
345
346 if (desc->msi_attrib.is_msix)
347 return -EINVAL;
348
349 irq = assign_irq(1, desc, &pos);
350 if (irq < 0)
351 return irq;
352
353 dw_msi_setup_msg(pp, irq, pos);
354
355 return 0;
356}
357
358static int dw_msi_setup_irqs(struct msi_controller *chip, struct pci_dev *pdev,
359 int nvec, int type)
360{
361#ifdef CONFIG_PCI_MSI
362 int irq, pos;
363 struct msi_desc *desc;
364 struct pcie_port *pp = pdev->bus->sysdata;
365
366 /* MSI-X interrupts are not supported */
367 if (type == PCI_CAP_ID_MSIX)
368 return -EINVAL;
369
370 WARN_ON(!list_is_singular(&pdev->dev.msi_list));
371 desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list);
372
373 irq = assign_irq(nvec, desc, &pos);
374 if (irq < 0)
375 return irq;
376
377 dw_msi_setup_msg(pp, irq, pos);
378
379 return 0;
380#else
381 return -EINVAL;
382#endif
383}
384
385static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
386{
387 struct irq_data *data = irq_get_irq_data(irq);
388 struct msi_desc *msi = irq_data_get_msi_desc(data);
389 struct pcie_port *pp = (struct pcie_port *)msi_desc_to_pci_sysdata(msi);
390
391 clear_irq_range(pp, irq, 1, data->hwirq);
392}
393
394static struct msi_controller dw_pcie_msi_chip = {
395 .setup_irq = dw_msi_setup_irq,
396 .setup_irqs = dw_msi_setup_irqs,
397 .teardown_irq = dw_msi_teardown_irq,
398};
399
400int dw_pcie_wait_for_link(struct dw_pcie *pci) 151int dw_pcie_wait_for_link(struct dw_pcie *pci)
401{ 152{
402 int retries; 153 int retries;
@@ -427,327 +178,11 @@ int dw_pcie_link_up(struct dw_pcie *pci)
427 (!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING))); 178 (!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING)));
428} 179}
429 180
430static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq, 181void dw_pcie_setup(struct dw_pcie *pci)
431 irq_hw_number_t hwirq)
432{
433 irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq);
434 irq_set_chip_data(irq, domain->host_data);
435
436 return 0;
437}
438
439static const struct irq_domain_ops msi_domain_ops = {
440 .map = dw_pcie_msi_map,
441};
442
443static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
444{
445 u32 val;
446
447 val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
448 if (val == 0xffffffff)
449 return 1;
450
451 return 0;
452}
453
454int dw_pcie_host_init(struct pcie_port *pp)
455{
456 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
457 struct device *dev = pci->dev;
458 struct device_node *np = dev->of_node;
459 struct platform_device *pdev = to_platform_device(dev);
460 struct pci_bus *bus, *child;
461 struct resource *cfg_res;
462 int i, ret;
463 LIST_HEAD(res);
464 struct resource_entry *win, *tmp;
465
466 cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
467 if (cfg_res) {
468 pp->cfg0_size = resource_size(cfg_res) / 2;
469 pp->cfg1_size = resource_size(cfg_res) / 2;
470 pp->cfg0_base = cfg_res->start;
471 pp->cfg1_base = cfg_res->start + pp->cfg0_size;
472 } else if (!pp->va_cfg0_base) {
473 dev_err(dev, "missing *config* reg space\n");
474 }
475
476 ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &pp->io_base);
477 if (ret)
478 return ret;
479
480 ret = devm_request_pci_bus_resources(dev, &res);
481 if (ret)
482 goto error;
483
484 /* Get the I/O and memory ranges from DT */
485 resource_list_for_each_entry_safe(win, tmp, &res) {
486 switch (resource_type(win->res)) {
487 case IORESOURCE_IO:
488 ret = pci_remap_iospace(win->res, pp->io_base);
489 if (ret) {
490 dev_warn(dev, "error %d: failed to map resource %pR\n",
491 ret, win->res);
492 resource_list_destroy_entry(win);
493 } else {
494 pp->io = win->res;
495 pp->io->name = "I/O";
496 pp->io_size = resource_size(pp->io);
497 pp->io_bus_addr = pp->io->start - win->offset;
498 }
499 break;
500 case IORESOURCE_MEM:
501 pp->mem = win->res;
502 pp->mem->name = "MEM";
503 pp->mem_size = resource_size(pp->mem);
504 pp->mem_bus_addr = pp->mem->start - win->offset;
505 break;
506 case 0:
507 pp->cfg = win->res;
508 pp->cfg0_size = resource_size(pp->cfg) / 2;
509 pp->cfg1_size = resource_size(pp->cfg) / 2;
510 pp->cfg0_base = pp->cfg->start;
511 pp->cfg1_base = pp->cfg->start + pp->cfg0_size;
512 break;
513 case IORESOURCE_BUS:
514 pp->busn = win->res;
515 break;
516 }
517 }
518
519 if (!pci->dbi_base) {
520 pci->dbi_base = devm_ioremap(dev, pp->cfg->start,
521 resource_size(pp->cfg));
522 if (!pci->dbi_base) {
523 dev_err(dev, "error with ioremap\n");
524 ret = -ENOMEM;
525 goto error;
526 }
527 }
528
529 pp->mem_base = pp->mem->start;
530
531 if (!pp->va_cfg0_base) {
532 pp->va_cfg0_base = devm_ioremap(dev, pp->cfg0_base,
533 pp->cfg0_size);
534 if (!pp->va_cfg0_base) {
535 dev_err(dev, "error with ioremap in function\n");
536 ret = -ENOMEM;
537 goto error;
538 }
539 }
540
541 if (!pp->va_cfg1_base) {
542 pp->va_cfg1_base = devm_ioremap(dev, pp->cfg1_base,
543 pp->cfg1_size);
544 if (!pp->va_cfg1_base) {
545 dev_err(dev, "error with ioremap\n");
546 ret = -ENOMEM;
547 goto error;
548 }
549 }
550
551 ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport);
552 if (ret)
553 pci->num_viewport = 2;
554
555 if (IS_ENABLED(CONFIG_PCI_MSI)) {
556 if (!pp->ops->msi_host_init) {
557 pp->irq_domain = irq_domain_add_linear(dev->of_node,
558 MAX_MSI_IRQS, &msi_domain_ops,
559 &dw_pcie_msi_chip);
560 if (!pp->irq_domain) {
561 dev_err(dev, "irq domain init failed\n");
562 ret = -ENXIO;
563 goto error;
564 }
565
566 for (i = 0; i < MAX_MSI_IRQS; i++)
567 irq_create_mapping(pp->irq_domain, i);
568 } else {
569 ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip);
570 if (ret < 0)
571 goto error;
572 }
573 }
574
575 if (pp->ops->host_init)
576 pp->ops->host_init(pp);
577
578 pp->root_bus_nr = pp->busn->start;
579 if (IS_ENABLED(CONFIG_PCI_MSI)) {
580 bus = pci_scan_root_bus_msi(dev, pp->root_bus_nr,
581 &dw_pcie_ops, pp, &res,
582 &dw_pcie_msi_chip);
583 dw_pcie_msi_chip.dev = dev;
584 } else
585 bus = pci_scan_root_bus(dev, pp->root_bus_nr, &dw_pcie_ops,
586 pp, &res);
587 if (!bus) {
588 ret = -ENOMEM;
589 goto error;
590 }
591
592 if (pp->ops->scan_bus)
593 pp->ops->scan_bus(pp);
594
595#ifdef CONFIG_ARM
596 /* support old dtbs that incorrectly describe IRQs */
597 pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
598#endif
599
600 pci_bus_size_bridges(bus);
601 pci_bus_assign_resources(bus);
602
603 list_for_each_entry(child, &bus->children, node)
604 pcie_bus_configure_settings(child);
605
606 pci_bus_add_devices(bus);
607 return 0;
608
609error:
610 pci_free_resource_list(&res);
611 return ret;
612}
613
614static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
615 u32 devfn, int where, int size, u32 *val)
616{
617 int ret, type;
618 u32 busdev, cfg_size;
619 u64 cpu_addr;
620 void __iomem *va_cfg_base;
621 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
622
623 if (pp->ops->rd_other_conf)
624 return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val);
625
626 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
627 PCIE_ATU_FUNC(PCI_FUNC(devfn));
628
629 if (bus->parent->number == pp->root_bus_nr) {
630 type = PCIE_ATU_TYPE_CFG0;
631 cpu_addr = pp->cfg0_base;
632 cfg_size = pp->cfg0_size;
633 va_cfg_base = pp->va_cfg0_base;
634 } else {
635 type = PCIE_ATU_TYPE_CFG1;
636 cpu_addr = pp->cfg1_base;
637 cfg_size = pp->cfg1_size;
638 va_cfg_base = pp->va_cfg1_base;
639 }
640
641 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
642 type, cpu_addr,
643 busdev, cfg_size);
644 ret = dw_pcie_read(va_cfg_base + where, size, val);
645 if (pci->num_viewport <= 2)
646 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
647 PCIE_ATU_TYPE_IO, pp->io_base,
648 pp->io_bus_addr, pp->io_size);
649
650 return ret;
651}
652
653static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
654 u32 devfn, int where, int size, u32 val)
655{
656 int ret, type;
657 u32 busdev, cfg_size;
658 u64 cpu_addr;
659 void __iomem *va_cfg_base;
660 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
661
662 if (pp->ops->wr_other_conf)
663 return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val);
664
665 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
666 PCIE_ATU_FUNC(PCI_FUNC(devfn));
667
668 if (bus->parent->number == pp->root_bus_nr) {
669 type = PCIE_ATU_TYPE_CFG0;
670 cpu_addr = pp->cfg0_base;
671 cfg_size = pp->cfg0_size;
672 va_cfg_base = pp->va_cfg0_base;
673 } else {
674 type = PCIE_ATU_TYPE_CFG1;
675 cpu_addr = pp->cfg1_base;
676 cfg_size = pp->cfg1_size;
677 va_cfg_base = pp->va_cfg1_base;
678 }
679
680 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
681 type, cpu_addr,
682 busdev, cfg_size);
683 ret = dw_pcie_write(va_cfg_base + where, size, val);
684 if (pci->num_viewport <= 2)
685 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
686 PCIE_ATU_TYPE_IO, pp->io_base,
687 pp->io_bus_addr, pp->io_size);
688
689 return ret;
690}
691
692static int dw_pcie_valid_device(struct pcie_port *pp, struct pci_bus *bus,
693 int dev)
694{
695 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
696
697 /* If there is no link, then there is no device */
698 if (bus->number != pp->root_bus_nr) {
699 if (!dw_pcie_link_up(pci))
700 return 0;
701 }
702
703 /* access only one slot on each root port */
704 if (bus->number == pp->root_bus_nr && dev > 0)
705 return 0;
706
707 return 1;
708}
709
710static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
711 int size, u32 *val)
712{
713 struct pcie_port *pp = bus->sysdata;
714
715 if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn))) {
716 *val = 0xffffffff;
717 return PCIBIOS_DEVICE_NOT_FOUND;
718 }
719
720 if (bus->number == pp->root_bus_nr)
721 return dw_pcie_rd_own_conf(pp, where, size, val);
722
723 return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val);
724}
725
726static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
727 int where, int size, u32 val)
728{
729 struct pcie_port *pp = bus->sysdata;
730
731 if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn)))
732 return PCIBIOS_DEVICE_NOT_FOUND;
733
734 if (bus->number == pp->root_bus_nr)
735 return dw_pcie_wr_own_conf(pp, where, size, val);
736
737 return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
738}
739
740static struct pci_ops dw_pcie_ops = {
741 .read = dw_pcie_rd_conf,
742 .write = dw_pcie_wr_conf,
743};
744
745void dw_pcie_setup_rc(struct pcie_port *pp)
746{ 182{
747 int ret; 183 int ret;
748 u32 lanes;
749 u32 val; 184 u32 val;
750 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 185 u32 lanes;
751 struct device *dev = pci->dev; 186 struct device *dev = pci->dev;
752 struct device_node *np = dev->of_node; 187 struct device_node *np = dev->of_node;
753 188
@@ -795,56 +230,4 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
795 break; 230 break;
796 } 231 }
797 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); 232 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
798
799 /* setup RC BARs */
800 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);
801 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
802
803 /* setup interrupt pins */
804 val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
805 val &= 0xffff00ff;
806 val |= 0x00000100;
807 dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
808
809 /* setup bus numbers */
810 val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
811 val &= 0xff000000;
812 val |= 0x00010100;
813 dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val);
814
815 /* setup command register */
816 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
817 val &= 0xffff0000;
818 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
819 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
820 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
821
822 /*
823 * If the platform provides ->rd_other_conf, it means the platform
824 * uses its own address translation component rather than ATU, so
825 * we should not program the ATU here.
826 */
827 if (!pp->ops->rd_other_conf) {
828 /* get iATU unroll support */
829 pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci);
830 dev_dbg(pci->dev, "iATU unroll: %s\n",
831 pci->iatu_unroll_enabled ? "enabled" : "disabled");
832
833 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,
834 PCIE_ATU_TYPE_MEM, pp->mem_base,
835 pp->mem_bus_addr, pp->mem_size);
836 if (pci->num_viewport > 2)
837 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX2,
838 PCIE_ATU_TYPE_IO, pp->io_base,
839 pp->io_bus_addr, pp->io_size);
840 }
841
842 dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
843
844 /* program correct class for RC */
845 dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
846
847 dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
848 val |= PORT_LOGIC_SPEED_CHANGE;
849 dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
850} 233}
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index 1fbe3b8d6f48..30547708f18e 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -14,6 +14,10 @@
14#ifndef _PCIE_DESIGNWARE_H 14#ifndef _PCIE_DESIGNWARE_H
15#define _PCIE_DESIGNWARE_H 15#define _PCIE_DESIGNWARE_H
16 16
17#include <linux/irq.h>
18#include <linux/msi.h>
19#include <linux/pci.h>
20
17/* Parameters for the waiting for link up routine */ 21/* Parameters for the waiting for link up routine */
18#define LINK_WAIT_MAX_RETRIES 10 22#define LINK_WAIT_MAX_RETRIES 10
19#define LINK_WAIT_USLEEP_MIN 90000 23#define LINK_WAIT_USLEEP_MIN 90000
@@ -166,4 +170,8 @@ u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg);
166void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val); 170void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val);
167int dw_pcie_link_up(struct dw_pcie *pci); 171int dw_pcie_link_up(struct dw_pcie *pci);
168int dw_pcie_wait_for_link(struct dw_pcie *pci); 172int dw_pcie_wait_for_link(struct dw_pcie *pci);
173void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
174 int type, u64 cpu_addr, u64 pci_addr,
175 u32 size);
176void dw_pcie_setup(struct dw_pcie *pci);
169#endif /* _PCIE_DESIGNWARE_H */ 177#endif /* _PCIE_DESIGNWARE_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-18 11:46:48 -0400