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authorJun Nie <jun.nie@linaro.org>2016-10-13 08:31:20 -0400
committerOlof Johansson <olof@lixom.net>2016-12-07 15:32:55 -0500
commitfe901d357895bad8b0311f86908dd674e636f0ea (patch)
tree0679ab591f67e604a4f442d617a4d417b866d1f7
parentc090959b9dd8c87703e275079aa4b4a824ba3f8e (diff)
arm64: dts: zx: Fix gic GICR property
GICR for multiple CPU can be described with start address and stride, or with multiple address. Current multiple address and stride are both used. Fix it. vmalloc patch 727a7f5a9 triggered this bug: [ 0.097146] Unable to handle kernel paging request at virtual address ffff000008060008 [ 0.097150] pgd = ffff000008602000 [ 0.097160] [ffff000008060008] *pgd=000000007fffe003, *pud=000000007fffd003, *pmd=000000007fffc003, *pte=0000000000000000 [ 0.097165] Internal error: Oops: 96000007 [#1] PREEMPT SMP [ 0.097170] Modules linked in: [ 0.097177] CPU: 1 PID: 0 Comm: swapper/1 Not tainted 4.8.0+ #1474 [ 0.097179] Hardware name: ZTE zx296718 evaluation board (DT) [ 0.097183] task: ffff80003e8c8b80 task.stack: ffff80003e8d0000 [ 0.097197] PC is at gic_populate_rdist+0x74/0x15c [ 0.097202] LR is at gic_starting_cpu+0xc/0x20 [ 0.097206] pc : [<ffff0000082b1b18>] lr : [<ffff0000082b26e0>] pstate: 600001c5 Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
-rw-r--r--arch/arm64/boot/dts/zte/zx296718.dtsi11
1 files changed, 3 insertions, 8 deletions
diff --git a/arch/arm64/boot/dts/zte/zx296718.dtsi b/arch/arm64/boot/dts/zte/zx296718.dtsi
index a223066f24ce..6b239a365f01 100644
--- a/arch/arm64/boot/dts/zte/zx296718.dtsi
+++ b/arch/arm64/boot/dts/zte/zx296718.dtsi
@@ -239,16 +239,11 @@
239 compatible = "arm,gic-v3"; 239 compatible = "arm,gic-v3";
240 #interrupt-cells = <3>; 240 #interrupt-cells = <3>;
241 #address-cells = <0>; 241 #address-cells = <0>;
242 #redistributor-regions = <6>; 242 #redistributor-regions = <1>;
243 redistributor-stride = <0x0 0x40000>; 243 redistributor-stride = <0x20000>;
244 interrupt-controller; 244 interrupt-controller;
245 reg = <0x02a00000 0x10000>, 245 reg = <0x02a00000 0x10000>,
246 <0x02b00000 0x20000>, 246 <0x02b00000 0xc0000>;
247 <0x02b20000 0x20000>,
248 <0x02b40000 0x20000>,
249 <0x02b60000 0x20000>,
250 <0x02b80000 0x20000>,
251 <0x02ba0000 0x20000>;
252 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 247 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
253 }; 248 };
254 249