diff options
author | Chunyan Zhang <zhang.chunyan@linaro.org> | 2015-07-15 03:05:48 -0400 |
---|---|---|
committer | Olof Johansson <olof@lixom.net> | 2015-07-15 06:00:22 -0400 |
commit | fe467ad1e430ffbde37a61a7dacf6218f420d78b (patch) | |
tree | 3bcb10575382fc564786ea394807ce3cd69acec8 | |
parent | bc0195aad0daa2ad5b0d76cce22b167bc3435590 (diff) |
arm64: dts: sprd: adding ETM entries to Spreadtrum SC9836
Since ETMv4 driver has been merged, this patch adds ETM nodes for SC9836,
and four funnel input ports to connect with ETM output ports.
Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
-rw-r--r-- | arch/arm64/boot/dts/sprd/sc9836.dtsi | 99 |
1 files changed, 94 insertions, 5 deletions
diff --git a/arch/arm64/boot/dts/sprd/sc9836.dtsi b/arch/arm64/boot/dts/sprd/sc9836.dtsi index ee34e1a36e03..63894c456969 100644 --- a/arch/arm64/boot/dts/sprd/sc9836.dtsi +++ b/arch/arm64/boot/dts/sprd/sc9836.dtsi | |||
@@ -16,28 +16,28 @@ | |||
16 | #address-cells = <2>; | 16 | #address-cells = <2>; |
17 | #size-cells = <0>; | 17 | #size-cells = <0>; |
18 | 18 | ||
19 | cpu@0 { | 19 | cpu0: cpu@0 { |
20 | device_type = "cpu"; | 20 | device_type = "cpu"; |
21 | compatible = "arm,cortex-a53", "arm,armv8"; | 21 | compatible = "arm,cortex-a53", "arm,armv8"; |
22 | reg = <0x0 0x0>; | 22 | reg = <0x0 0x0>; |
23 | enable-method = "psci"; | 23 | enable-method = "psci"; |
24 | }; | 24 | }; |
25 | 25 | ||
26 | cpu@1 { | 26 | cpu1: cpu@1 { |
27 | device_type = "cpu"; | 27 | device_type = "cpu"; |
28 | compatible = "arm,cortex-a53", "arm,armv8"; | 28 | compatible = "arm,cortex-a53", "arm,armv8"; |
29 | reg = <0x0 0x1>; | 29 | reg = <0x0 0x1>; |
30 | enable-method = "psci"; | 30 | enable-method = "psci"; |
31 | }; | 31 | }; |
32 | 32 | ||
33 | cpu@2 { | 33 | cpu2: cpu@2 { |
34 | device_type = "cpu"; | 34 | device_type = "cpu"; |
35 | compatible = "arm,cortex-a53", "arm,armv8"; | 35 | compatible = "arm,cortex-a53", "arm,armv8"; |
36 | reg = <0x0 0x2>; | 36 | reg = <0x0 0x2>; |
37 | enable-method = "psci"; | 37 | enable-method = "psci"; |
38 | }; | 38 | }; |
39 | 39 | ||
40 | cpu@3 { | 40 | cpu3: cpu@3 { |
41 | device_type = "cpu"; | 41 | device_type = "cpu"; |
42 | compatible = "arm,cortex-a53", "arm,armv8"; | 42 | compatible = "arm,cortex-a53", "arm,armv8"; |
43 | reg = <0x0 0x3>; | 43 | reg = <0x0 0x3>; |
@@ -75,14 +75,103 @@ | |||
75 | }; | 75 | }; |
76 | }; | 76 | }; |
77 | 77 | ||
78 | /* funnel input port 0~3 is reserved for ETMs */ | 78 | /* funnel input port 0-4 */ |
79 | port@1 { | 79 | port@1 { |
80 | reg = <0>; | ||
81 | funnel_in_port0: endpoint { | ||
82 | slave-mode; | ||
83 | remote-endpoint = <&etm0_out>; | ||
84 | }; | ||
85 | }; | ||
86 | |||
87 | port@2 { | ||
88 | reg = <1>; | ||
89 | funnel_in_port1: endpoint { | ||
90 | slave-mode; | ||
91 | remote-endpoint = <&etm1_out>; | ||
92 | }; | ||
93 | }; | ||
94 | |||
95 | port@3 { | ||
96 | reg = <2>; | ||
97 | funnel_in_port2: endpoint { | ||
98 | slave-mode; | ||
99 | remote-endpoint = <&etm2_out>; | ||
100 | }; | ||
101 | }; | ||
102 | |||
103 | port@4 { | ||
104 | reg = <3>; | ||
105 | funnel_in_port3: endpoint { | ||
106 | slave-mode; | ||
107 | remote-endpoint = <&etm3_out>; | ||
108 | }; | ||
109 | }; | ||
110 | |||
111 | port@5 { | ||
80 | reg = <4>; | 112 | reg = <4>; |
81 | funnel_in_port4: endpoint { | 113 | funnel_in_port4: endpoint { |
82 | slave-mode; | 114 | slave-mode; |
83 | remote-endpoint = <&stm_out>; | 115 | remote-endpoint = <&stm_out>; |
84 | }; | 116 | }; |
85 | }; | 117 | }; |
118 | /* Other input ports aren't connected to anyone */ | ||
119 | }; | ||
120 | }; | ||
121 | |||
122 | etm@10440000 { | ||
123 | compatible = "arm,coresight-etm4x", "arm,primecell"; | ||
124 | reg = <0 0x10440000 0 0x1000>; | ||
125 | |||
126 | cpu = <&cpu0>; | ||
127 | clocks = <&clk26mhz>; | ||
128 | clock-names = "apb_pclk"; | ||
129 | port { | ||
130 | etm0_out: endpoint { | ||
131 | remote-endpoint = <&funnel_in_port0>; | ||
132 | }; | ||
133 | }; | ||
134 | }; | ||
135 | |||
136 | etm@10540000 { | ||
137 | compatible = "arm,coresight-etm4x", "arm,primecell"; | ||
138 | reg = <0 0x10540000 0 0x1000>; | ||
139 | |||
140 | cpu = <&cpu1>; | ||
141 | clocks = <&clk26mhz>; | ||
142 | clock-names = "apb_pclk"; | ||
143 | port { | ||
144 | etm1_out: endpoint { | ||
145 | remote-endpoint = <&funnel_in_port1>; | ||
146 | }; | ||
147 | }; | ||
148 | }; | ||
149 | |||
150 | etm@10640000 { | ||
151 | compatible = "arm,coresight-etm4x", "arm,primecell"; | ||
152 | reg = <0 0x10640000 0 0x1000>; | ||
153 | |||
154 | cpu = <&cpu2>; | ||
155 | clocks = <&clk26mhz>; | ||
156 | clock-names = "apb_pclk"; | ||
157 | port { | ||
158 | etm2_out: endpoint { | ||
159 | remote-endpoint = <&funnel_in_port2>; | ||
160 | }; | ||
161 | }; | ||
162 | }; | ||
163 | |||
164 | etm@10740000 { | ||
165 | compatible = "arm,coresight-etm4x", "arm,primecell"; | ||
166 | reg = <0 0x10740000 0 0x1000>; | ||
167 | |||
168 | cpu = <&cpu3>; | ||
169 | clocks = <&clk26mhz>; | ||
170 | clock-names = "apb_pclk"; | ||
171 | port { | ||
172 | etm3_out: endpoint { | ||
173 | remote-endpoint = <&funnel_in_port3>; | ||
174 | }; | ||
86 | }; | 175 | }; |
87 | }; | 176 | }; |
88 | 177 | ||