diff options
author | Tony Cheng <tony.cheng@amd.com> | 2017-08-28 09:51:03 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 18:17:23 -0400 |
commit | fd96c1775a75c14bf15465af7040cc00855b1ec0 (patch) | |
tree | e0e24c08ed3deb777c0578646283934375e29d8b | |
parent | 7c228a1a910784801360db5aedd153db9f465b56 (diff) |
drm/amd/display: delete dead code
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index ee1b76c074e6..1b0f64756be6 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | |||
@@ -1312,8 +1312,9 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc) | |||
1312 | { | 1312 | { |
1313 | struct pp_smu_funcs_rv *pp = dc->res_pool->pp_smu; | 1313 | struct pp_smu_funcs_rv *pp = dc->res_pool->pp_smu; |
1314 | struct pp_smu_wm_range_sets ranges = {0}; | 1314 | struct pp_smu_wm_range_sets ranges = {0}; |
1315 | int max_fclk_khz, nom_fclk_khz, min_fclk_khz, max_dcfclk_khz, | 1315 | int max_fclk_khz, nom_fclk_khz, mid_fclk_khz, min_fclk_khz; |
1316 | nom_dcfclk_khz, mid_fclk_khz, min_dcfclk_khz, socclk_khz; | 1316 | int max_dcfclk_khz, min_dcfclk_khz; |
1317 | int socclk_khz; | ||
1317 | const int overdrive = 5000000; /* 5 GHz to cover Overdrive */ | 1318 | const int overdrive = 5000000; /* 5 GHz to cover Overdrive */ |
1318 | unsigned factor = (ddr4_dram_factor_single_Channel * dc->dcn_soc->number_of_channels); | 1319 | unsigned factor = (ddr4_dram_factor_single_Channel * dc->dcn_soc->number_of_channels); |
1319 | 1320 | ||
@@ -1326,7 +1327,6 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc) | |||
1326 | mid_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 * 1000000 / factor; | 1327 | mid_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 * 1000000 / factor; |
1327 | min_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000000 / 32; | 1328 | min_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000000 / 32; |
1328 | max_dcfclk_khz = dc->dcn_soc->dcfclkv_max0p9 * 1000; | 1329 | max_dcfclk_khz = dc->dcn_soc->dcfclkv_max0p9 * 1000; |
1329 | nom_dcfclk_khz = dc->dcn_soc->dcfclkv_nom0p8 * 1000; | ||
1330 | min_dcfclk_khz = dc->dcn_soc->dcfclkv_min0p65 * 1000; | 1330 | min_dcfclk_khz = dc->dcn_soc->dcfclkv_min0p65 * 1000; |
1331 | socclk_khz = dc->dcn_soc->socclk * 1000; | 1331 | socclk_khz = dc->dcn_soc->socclk * 1000; |
1332 | kernel_fpu_end(); | 1332 | kernel_fpu_end(); |