diff options
| author | Jianqun <jay.xu@rock-chips.com> | 2014-09-29 23:12:04 -0400 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2014-10-01 04:55:13 -0400 |
| commit | fc69ed70c16a31d6a77ec47a30a9fe941f763f1e (patch) | |
| tree | d29c2d76beb5b092267c8e4d69c2045b0d99abf6 | |
| parent | 0e5bdb3f9fa5c2bd4452c258de78122ef15f62d6 (diff) | |
clk: rockchip: rk3288: i2s_frac adds flag to set parent's rate
The relation of i2s nodes as follows:
i2s_src 0 0 594000000 0
i2s_frac 0 0 11289600 0
i2s_pre 0 0 11289600 0
sclk_i2s0 0 0 11289600 0
i2s0_clkout 0 0 11289600 0
hclk_i2s0 1 1 99000000 0
sclk_i2s0 is the master clock, when to set rate of sclk_i2s0, should
allow to set its parent's rate, by add flag CLK_SET_RATE_PARENT for
"i2s_frac", "i2s_pre", "i2s0_clkout" and "sclk_i2s0".
Tested on rk3288 board using max98090, with command "aplay <music.wav>"
Change-Id: I12faad082566532b65a7de8c0a6845e1c17870e6
Signed-off-by: Jianqun <jay.xu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3288.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index d053529113f8..b488f6a48d19 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c | |||
| @@ -300,15 +300,15 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { | |||
| 300 | COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0, | 300 | COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0, |
| 301 | RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS, | 301 | RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS, |
| 302 | RK3288_CLKGATE_CON(4), 1, GFLAGS), | 302 | RK3288_CLKGATE_CON(4), 1, GFLAGS), |
| 303 | COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", 0, | 303 | COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT, |
| 304 | RK3288_CLKSEL_CON(8), 0, | 304 | RK3288_CLKSEL_CON(8), 0, |
| 305 | RK3288_CLKGATE_CON(4), 2, GFLAGS), | 305 | RK3288_CLKGATE_CON(4), 2, GFLAGS), |
| 306 | MUX(0, "i2s_pre", mux_i2s_pre_p, 0, | 306 | MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT, |
| 307 | RK3288_CLKSEL_CON(4), 8, 2, MFLAGS), | 307 | RK3288_CLKSEL_CON(4), 8, 2, MFLAGS), |
| 308 | COMPOSITE_NODIV(0, "i2s0_clkout", mux_i2s_clkout_p, 0, | 308 | COMPOSITE_NODIV(0, "i2s0_clkout", mux_i2s_clkout_p, CLK_SET_RATE_PARENT, |
| 309 | RK3288_CLKSEL_CON(4), 12, 1, MFLAGS, | 309 | RK3288_CLKSEL_CON(4), 12, 1, MFLAGS, |
| 310 | RK3288_CLKGATE_CON(4), 0, GFLAGS), | 310 | RK3288_CLKGATE_CON(4), 0, GFLAGS), |
| 311 | GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", 0, | 311 | GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT, |
| 312 | RK3288_CLKGATE_CON(4), 3, GFLAGS), | 312 | RK3288_CLKGATE_CON(4), 3, GFLAGS), |
| 313 | 313 | ||
| 314 | MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0, | 314 | MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0, |