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authorNicolas Pitre <nicolas.pitre@linaro.org>2014-06-24 13:36:32 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2014-07-18 06:58:04 -0400
commitfbb0499091dc1132995214a47188214602fd75c9 (patch)
treeadae97ca27e1ac6823943156dac3c96729c3872c
parent3592d7e002438980f9ce4a399f21ec94cbf071ea (diff)
ARM: 8083/1: exynos: activate the CCI on boot CPU/cluster using the MCPM loopback
The Chromebook firmware doesn't enable the CCI for the boot cpu, and arguably it shouldn't have to either. Let's have the kernel handle the CCI on its own for the boot CPU the same way it does it for secondary CPUs by using the MCPM loopback. This allows to boot all 8 cores on exynos5420-peach-pit, exynos5800-peach-pi and ARM Chromebook 2. Signed-off-by: Nicolas Pitre <nico@linaro.org> Tested-by: Tushar Behera <tushar.b@samsung.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r--arch/arm/mach-exynos/mcpm-exynos.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c
index ace0ed617476..0d95bc8e49d8 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -289,6 +289,19 @@ static void __naked exynos_pm_power_up_setup(unsigned int affinity_level)
289 "b cci_enable_port_for_self"); 289 "b cci_enable_port_for_self");
290} 290}
291 291
292static void __init exynos_cache_off(void)
293{
294 if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) {
295 /* disable L2 prefetching on the Cortex-A15 */
296 asm volatile(
297 "mcr p15, 1, %0, c15, c0, 3\n\t"
298 "isb\n\t"
299 "dsb"
300 : : "r" (0x400));
301 }
302 exynos_v7_exit_coherency_flush(all);
303}
304
292static const struct of_device_id exynos_dt_mcpm_match[] = { 305static const struct of_device_id exynos_dt_mcpm_match[] = {
293 { .compatible = "samsung,exynos5420" }, 306 { .compatible = "samsung,exynos5420" },
294 { .compatible = "samsung,exynos5800" }, 307 { .compatible = "samsung,exynos5800" },
@@ -332,6 +345,8 @@ static int __init exynos_mcpm_init(void)
332 ret = mcpm_platform_register(&exynos_power_ops); 345 ret = mcpm_platform_register(&exynos_power_ops);
333 if (!ret) 346 if (!ret)
334 ret = mcpm_sync_init(exynos_pm_power_up_setup); 347 ret = mcpm_sync_init(exynos_pm_power_up_setup);
348 if (!ret)
349 ret = mcpm_loopback(exynos_cache_off); /* turn on the CCI */
335 if (ret) { 350 if (ret) {
336 iounmap(ns_sram_base_addr); 351 iounmap(ns_sram_base_addr);
337 return ret; 352 return ret;