aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorOlof Johansson <olof@lixom.net>2016-10-29 14:08:50 -0400
committerOlof Johansson <olof@lixom.net>2016-10-29 14:08:50 -0400
commitfbaff059c29e4002d8cf5dbb71ad812c1f3d976e (patch)
treee01083d4ee5d162fa84b955185c8c8b7af7b52c3
parent10e15a639caac3be3c142f8837a17520da84db9f (diff)
parent4edd601c5a9c5094daa714e65063e623826f3bcc (diff)
Merge tag 'imx-fixes-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into fixes
The i.MX fixes for 4.9: - A couple of patches from Fabio to fix the GPC power domain regression which is caused by PM Domain core change 0159ec670763dd ("PM / Domains: Verify the PM domain is present when adding a provider"), and a related kernel crash seen with multi_v7_defconfig build. - Correct the PHY ID mask for AR8031 to match phy driver code. - Apply new added timer erratum A008585 for LS1043A and LS2080A SoC. - Correct vf610 global timer IRQ flag to avoid warning from gic driver after commit 992345a58e0c ("irqchip/gic: WARN if setting the interrupt type for a PPI fails"). * tag 'imx-fixes-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: imx: mach-imx6q: Fix the PHY ID mask for AR8031 ARM: dts: vf610: fix IRQ flag of global timer ARM: imx: gpc: Fix the imx_gpc_genpd_init() error path ARM: imx: gpc: Initialize all power domains arm64: dts: Add timer erratum property for LS2080A and LS1043A Signed-off-by: Olof Johansson <olof@lixom.net>
-rw-r--r--arch/arm/boot/dts/vf500.dtsi2
-rw-r--r--arch/arm/mach-imx/gpc.c15
-rw-r--r--arch/arm/mach-imx/mach-imx6q.c2
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi1
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi1
5 files changed, 16 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi
index a3824e61bd72..d7fdb2a7d97b 100644
--- a/arch/arm/boot/dts/vf500.dtsi
+++ b/arch/arm/boot/dts/vf500.dtsi
@@ -70,7 +70,7 @@
70 global_timer: timer@40002200 { 70 global_timer: timer@40002200 {
71 compatible = "arm,cortex-a9-global-timer"; 71 compatible = "arm,cortex-a9-global-timer";
72 reg = <0x40002200 0x20>; 72 reg = <0x40002200 0x20>;
73 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; 73 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
74 interrupt-parent = <&intc>; 74 interrupt-parent = <&intc>;
75 clocks = <&clks VF610_CLK_PLATFORM_BUS>; 75 clocks = <&clks VF610_CLK_PLATFORM_BUS>;
76 }; 76 };
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index 0df062d8b2c9..b54db47f6f32 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -408,7 +408,7 @@ static struct genpd_onecell_data imx_gpc_onecell_data = {
408static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg) 408static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg)
409{ 409{
410 struct clk *clk; 410 struct clk *clk;
411 int i; 411 int i, ret;
412 412
413 imx6q_pu_domain.reg = pu_reg; 413 imx6q_pu_domain.reg = pu_reg;
414 414
@@ -430,13 +430,22 @@ static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg)
430 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) 430 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS))
431 return 0; 431 return 0;
432 432
433 pm_genpd_init(&imx6q_pu_domain.base, NULL, false); 433 for (i = 0; i < ARRAY_SIZE(imx_gpc_domains); i++)
434 return of_genpd_add_provider_onecell(dev->of_node, 434 pm_genpd_init(imx_gpc_domains[i], NULL, false);
435
436 ret = of_genpd_add_provider_onecell(dev->of_node,
435 &imx_gpc_onecell_data); 437 &imx_gpc_onecell_data);
438 if (ret)
439 goto power_off;
440
441 return 0;
436 442
443power_off:
444 imx6q_pm_pu_power_off(&imx6q_pu_domain.base);
437clk_err: 445clk_err:
438 while (i--) 446 while (i--)
439 clk_put(imx6q_pu_domain.clk[i]); 447 clk_put(imx6q_pu_domain.clk[i]);
448 imx6q_pu_domain.reg = NULL;
440 return -EINVAL; 449 return -EINVAL;
441} 450}
442 451
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 97fd25105e2c..45801b27ee5c 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -173,7 +173,7 @@ static void __init imx6q_enet_phy_init(void)
173 ksz9021rn_phy_fixup); 173 ksz9021rn_phy_fixup);
174 phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK, 174 phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
175 ksz9031rn_phy_fixup); 175 ksz9031rn_phy_fixup);
176 phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff, 176 phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffef,
177 ar8031_phy_fixup); 177 ar8031_phy_fixup);
178 phy_register_fixup_for_uid(PHY_ID_AR8035, 0xffffffef, 178 phy_register_fixup_for_uid(PHY_ID_AR8035, 0xffffffef,
179 ar8035_phy_fixup); 179 ar8035_phy_fixup);
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 220ac7057d12..97d331ec2500 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -123,6 +123,7 @@
123 <1 14 0xf08>, /* Physical Non-Secure PPI */ 123 <1 14 0xf08>, /* Physical Non-Secure PPI */
124 <1 11 0xf08>, /* Virtual PPI */ 124 <1 11 0xf08>, /* Virtual PPI */
125 <1 10 0xf08>; /* Hypervisor PPI */ 125 <1 10 0xf08>; /* Hypervisor PPI */
126 fsl,erratum-a008585;
126 }; 127 };
127 128
128 pmu { 129 pmu {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index 337da90bd7da..7f0dc13b4087 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -195,6 +195,7 @@
195 <1 14 4>, /* Physical Non-Secure PPI, active-low */ 195 <1 14 4>, /* Physical Non-Secure PPI, active-low */
196 <1 11 4>, /* Virtual PPI, active-low */ 196 <1 11 4>, /* Virtual PPI, active-low */
197 <1 10 4>; /* Hypervisor PPI, active-low */ 197 <1 10 4>; /* Hypervisor PPI, active-low */
198 fsl,erratum-a008585;
198 }; 199 };
199 200
200 pmu { 201 pmu {