diff options
author | Arun Easi <arun.easi@qlogic.com> | 2012-08-22 14:21:16 -0400 |
---|---|---|
committer | James Bottomley <JBottomley@Parallels.com> | 2012-09-24 04:10:50 -0400 |
commit | fafbda9f9cdeb3d29d8cb50ac029f704f52fac49 (patch) | |
tree | 53ddf9d94a3b9e81938d61670c2b5bd150714093 | |
parent | 711aa7f722821405125b2a3c6a3e6a3f275952bd (diff) |
[SCSI] qla2xxx: Use #defines instead of hardcoded values for intr status.
Signed-off-by: Arun Easi <arun.easi@qlogic.com>
Signed-off-by: Chad Dupuis <chad.dupuis@qlogic.com>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>
-rw-r--r-- | drivers/scsi/qla2xxx/qla_def.h | 11 | ||||
-rw-r--r-- | drivers/scsi/qla2xxx/qla_isr.c | 36 |
2 files changed, 29 insertions, 18 deletions
diff --git a/drivers/scsi/qla2xxx/qla_def.h b/drivers/scsi/qla2xxx/qla_def.h index ff8919293033..c4e77d7bb082 100644 --- a/drivers/scsi/qla2xxx/qla_def.h +++ b/drivers/scsi/qla2xxx/qla_def.h | |||
@@ -675,6 +675,17 @@ typedef struct { | |||
675 | /* 83XX FCoE specific */ | 675 | /* 83XX FCoE specific */ |
676 | #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */ | 676 | #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */ |
677 | 677 | ||
678 | /* Interrupt type codes */ | ||
679 | #define INTR_ROM_MB_SUCCESS 0x1 | ||
680 | #define INTR_ROM_MB_FAILED 0x2 | ||
681 | #define INTR_MB_SUCCESS 0x10 | ||
682 | #define INTR_MB_FAILED 0x11 | ||
683 | #define INTR_ASYNC_EVENT 0x12 | ||
684 | #define INTR_RSP_QUE_UPDATE 0x13 | ||
685 | #define INTR_RSP_QUE_UPDATE_83XX 0x14 | ||
686 | #define INTR_ATIO_QUE_UPDATE 0x1C | ||
687 | #define INTR_ATIO_RSP_QUE_UPDATE 0x1D | ||
688 | |||
678 | /* ISP mailbox loopback echo diagnostic error code */ | 689 | /* ISP mailbox loopback echo diagnostic error code */ |
679 | #define MBS_LB_RESET 0x17 | 690 | #define MBS_LB_RESET 0x17 |
680 | /* | 691 | /* |
diff --git a/drivers/scsi/qla2xxx/qla_isr.c b/drivers/scsi/qla2xxx/qla_isr.c index 686099267dd5..a551827d3edc 100644 --- a/drivers/scsi/qla2xxx/qla_isr.c +++ b/drivers/scsi/qla2xxx/qla_isr.c | |||
@@ -2522,29 +2522,29 @@ qla24xx_intr_handler(int irq, void *dev_id) | |||
2522 | break; | 2522 | break; |
2523 | 2523 | ||
2524 | switch (stat & 0xff) { | 2524 | switch (stat & 0xff) { |
2525 | case 0x1: | 2525 | case INTR_ROM_MB_SUCCESS: |
2526 | case 0x2: | 2526 | case INTR_ROM_MB_FAILED: |
2527 | case 0x10: | 2527 | case INTR_MB_SUCCESS: |
2528 | case 0x11: | 2528 | case INTR_MB_FAILED: |
2529 | qla24xx_mbx_completion(vha, MSW(stat)); | 2529 | qla24xx_mbx_completion(vha, MSW(stat)); |
2530 | status |= MBX_INTERRUPT; | 2530 | status |= MBX_INTERRUPT; |
2531 | 2531 | ||
2532 | break; | 2532 | break; |
2533 | case 0x12: | 2533 | case INTR_ASYNC_EVENT: |
2534 | mb[0] = MSW(stat); | 2534 | mb[0] = MSW(stat); |
2535 | mb[1] = RD_REG_WORD(®->mailbox1); | 2535 | mb[1] = RD_REG_WORD(®->mailbox1); |
2536 | mb[2] = RD_REG_WORD(®->mailbox2); | 2536 | mb[2] = RD_REG_WORD(®->mailbox2); |
2537 | mb[3] = RD_REG_WORD(®->mailbox3); | 2537 | mb[3] = RD_REG_WORD(®->mailbox3); |
2538 | qla2x00_async_event(vha, rsp, mb); | 2538 | qla2x00_async_event(vha, rsp, mb); |
2539 | break; | 2539 | break; |
2540 | case 0x13: | 2540 | case INTR_RSP_QUE_UPDATE: |
2541 | case 0x14: | 2541 | case INTR_RSP_QUE_UPDATE_83XX: |
2542 | qla24xx_process_response_queue(vha, rsp); | 2542 | qla24xx_process_response_queue(vha, rsp); |
2543 | break; | 2543 | break; |
2544 | case 0x1C: /* ATIO queue updated */ | 2544 | case INTR_ATIO_QUE_UPDATE: |
2545 | qlt_24xx_process_atio_queue(vha); | 2545 | qlt_24xx_process_atio_queue(vha); |
2546 | break; | 2546 | break; |
2547 | case 0x1D: /* ATIO and response queues updated */ | 2547 | case INTR_ATIO_RSP_QUE_UPDATE: |
2548 | qlt_24xx_process_atio_queue(vha); | 2548 | qlt_24xx_process_atio_queue(vha); |
2549 | qla24xx_process_response_queue(vha, rsp); | 2549 | qla24xx_process_response_queue(vha, rsp); |
2550 | break; | 2550 | break; |
@@ -2673,29 +2673,29 @@ qla24xx_msix_default(int irq, void *dev_id) | |||
2673 | break; | 2673 | break; |
2674 | 2674 | ||
2675 | switch (stat & 0xff) { | 2675 | switch (stat & 0xff) { |
2676 | case 0x1: | 2676 | case INTR_ROM_MB_SUCCESS: |
2677 | case 0x2: | 2677 | case INTR_ROM_MB_FAILED: |
2678 | case 0x10: | 2678 | case INTR_MB_SUCCESS: |
2679 | case 0x11: | 2679 | case INTR_MB_FAILED: |
2680 | qla24xx_mbx_completion(vha, MSW(stat)); | 2680 | qla24xx_mbx_completion(vha, MSW(stat)); |
2681 | status |= MBX_INTERRUPT; | 2681 | status |= MBX_INTERRUPT; |
2682 | 2682 | ||
2683 | break; | 2683 | break; |
2684 | case 0x12: | 2684 | case INTR_ASYNC_EVENT: |
2685 | mb[0] = MSW(stat); | 2685 | mb[0] = MSW(stat); |
2686 | mb[1] = RD_REG_WORD(®->mailbox1); | 2686 | mb[1] = RD_REG_WORD(®->mailbox1); |
2687 | mb[2] = RD_REG_WORD(®->mailbox2); | 2687 | mb[2] = RD_REG_WORD(®->mailbox2); |
2688 | mb[3] = RD_REG_WORD(®->mailbox3); | 2688 | mb[3] = RD_REG_WORD(®->mailbox3); |
2689 | qla2x00_async_event(vha, rsp, mb); | 2689 | qla2x00_async_event(vha, rsp, mb); |
2690 | break; | 2690 | break; |
2691 | case 0x13: | 2691 | case INTR_RSP_QUE_UPDATE: |
2692 | case 0x14: | 2692 | case INTR_RSP_QUE_UPDATE_83XX: |
2693 | qla24xx_process_response_queue(vha, rsp); | 2693 | qla24xx_process_response_queue(vha, rsp); |
2694 | break; | 2694 | break; |
2695 | case 0x1C: /* ATIO queue updated */ | 2695 | case INTR_ATIO_QUE_UPDATE: |
2696 | qlt_24xx_process_atio_queue(vha); | 2696 | qlt_24xx_process_atio_queue(vha); |
2697 | break; | 2697 | break; |
2698 | case 0x1D: /* ATIO and response queues updated */ | 2698 | case INTR_ATIO_RSP_QUE_UPDATE: |
2699 | qlt_24xx_process_atio_queue(vha); | 2699 | qlt_24xx_process_atio_queue(vha); |
2700 | qla24xx_process_response_queue(vha, rsp); | 2700 | qla24xx_process_response_queue(vha, rsp); |
2701 | break; | 2701 | break; |