diff options
author | Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> | 2017-07-26 07:28:10 -0400 |
---|---|---|
committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-08-16 04:18:00 -0400 |
commit | f9d130808c9aa74c34a6ed5eb536e19872065313 (patch) | |
tree | 37ae4655a25576ac83342fd4565e8a29d531be7e | |
parent | bf1a8aa0a2d6b0a6d8736de7ac07c886b092cbad (diff) |
pinctrl: sh-pfc: r8a7795: Change USB3_{OVC,PWEN} definitions
Since the latest datasheet revises the names, this patch changes
the definitions from USB3_{OVC,PWEN} to USB2_CH3_{OVC,PWEN}.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
-rw-r--r-- | drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 7df11d4e853a..947abbd94e6b 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c | |||
@@ -168,8 +168,8 @@ | |||
168 | #define GPSR5_0 F_(SCK0, IP11_27_24) | 168 | #define GPSR5_0 F_(SCK0, IP11_27_24) |
169 | 169 | ||
170 | /* GPSR6 */ | 170 | /* GPSR6 */ |
171 | #define GPSR6_31 F_(USB3_OVC, IP18_7_4) | 171 | #define GPSR6_31 F_(USB2_CH3_OVC, IP18_7_4) |
172 | #define GPSR6_30 F_(USB3_PWEN, IP18_3_0) | 172 | #define GPSR6_30 F_(USB2_CH3_PWEN, IP18_3_0) |
173 | #define GPSR6_29 F_(USB30_OVC, IP17_31_28) | 173 | #define GPSR6_29 F_(USB30_OVC, IP17_31_28) |
174 | #define GPSR6_28 F_(USB30_PWEN, IP17_27_24) | 174 | #define GPSR6_28 F_(USB30_PWEN, IP17_27_24) |
175 | #define GPSR6_27 F_(USB1_OVC, IP17_23_20) | 175 | #define GPSR6_27 F_(USB1_OVC, IP17_23_20) |
@@ -361,8 +361,8 @@ | |||
361 | #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0) | 361 | #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0) |
362 | #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0) | 362 | #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0) |
363 | #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | 363 | #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
364 | #define IP18_3_0 FM(USB3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) F_(0, 0) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) | 364 | #define IP18_3_0 FM(USB2_CH3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) F_(0, 0) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) |
365 | #define IP18_7_4 FM(USB3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) F_(0, 0) FM(FMIN_C) FM(FMIN_D) F_(0, 0) | 365 | #define IP18_7_4 FM(USB2_CH3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) F_(0, 0) FM(FMIN_C) FM(FMIN_D) F_(0, 0) |
366 | 366 | ||
367 | #define PINMUX_GPSR \ | 367 | #define PINMUX_GPSR \ |
368 | \ | 368 | \ |
@@ -1479,7 +1479,7 @@ static const u16 pinmux_data[] = { | |||
1479 | PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1), | 1479 | PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1), |
1480 | 1480 | ||
1481 | /* IPSR18 */ | 1481 | /* IPSR18 */ |
1482 | PINMUX_IPSR_GPSR(IP18_3_0, USB3_PWEN), | 1482 | PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN), |
1483 | PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B), | 1483 | PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B), |
1484 | PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1), | 1484 | PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1), |
1485 | PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4), | 1485 | PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4), |
@@ -1489,7 +1489,7 @@ static const u16 pinmux_data[] = { | |||
1489 | PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2), | 1489 | PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2), |
1490 | PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3), | 1490 | PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3), |
1491 | 1491 | ||
1492 | PINMUX_IPSR_GPSR(IP18_7_4, USB3_OVC), | 1492 | PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC), |
1493 | PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B), | 1493 | PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B), |
1494 | PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1), | 1494 | PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1), |
1495 | PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4), | 1495 | PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4), |
@@ -3961,8 +3961,8 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { | |||
3961 | { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */ | 3961 | { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */ |
3962 | { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */ | 3962 | { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */ |
3963 | { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */ | 3963 | { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */ |
3964 | { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB3_PWEN */ | 3964 | { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB2_CH3_PWEN */ |
3965 | { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB3_OVC */ | 3965 | { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB2_CH3_OVC */ |
3966 | } }, | 3966 | } }, |
3967 | { }, | 3967 | { }, |
3968 | }; | 3968 | }; |
@@ -4192,8 +4192,8 @@ static const struct sh_pfc_bias_info bias_info[] = { | |||
4192 | { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */ | 4192 | { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */ |
4193 | { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */ | 4193 | { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */ |
4194 | 4194 | ||
4195 | { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB3_OVC */ | 4195 | { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB2_CH3_OVC */ |
4196 | { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB3_PWEN */ | 4196 | { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB2_CH3_PWEN */ |
4197 | { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */ | 4197 | { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */ |
4198 | { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */ | 4198 | { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */ |
4199 | { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */ | 4199 | { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */ |