diff options
author | Peter Ujfalusi <peter.ujfalusi@ti.com> | 2015-10-16 03:18:03 -0400 |
---|---|---|
committer | Vinod Koul <vinod.koul@intel.com> | 2015-10-26 21:22:45 -0400 |
commit | f9425deb662ac07099ec151ffb4791eef48e9d83 (patch) | |
tree | 72ab0e34795644cbb03bf11e631863cafc585041 | |
parent | d9c345d18a8df5a5427cca80d2b9d981468ef270 (diff) |
dmaengine: edma: Merge map_dmach_to_queue into assign_channel_eventq
edma_assign_channel_eventq() is a wrapper around edma_map_dmach_to_queue()
We can merge the content of the later so we will have only one function
to be used for mapping channels to given eventq
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
-rw-r--r-- | drivers/dma/edma.c | 56 |
1 files changed, 22 insertions, 34 deletions
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 051a7c4593d4..eaf1f9e4bde0 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c | |||
@@ -391,22 +391,6 @@ static inline void clear_bits(int offset, int len, unsigned long *p) | |||
391 | clear_bit(offset + (len - 1), p); | 391 | clear_bit(offset + (len - 1), p); |
392 | } | 392 | } |
393 | 393 | ||
394 | static void edma_map_dmach_to_queue(struct edma_chan *echan, | ||
395 | enum dma_event_q queue_no) | ||
396 | { | ||
397 | struct edma_cc *ecc = echan->ecc; | ||
398 | int channel = EDMA_CHAN_SLOT(echan->ch_num); | ||
399 | int bit = (channel & 0x7) * 4; | ||
400 | |||
401 | /* default to low priority queue */ | ||
402 | if (queue_no == EVENTQ_DEFAULT) | ||
403 | queue_no = ecc->default_queue; | ||
404 | |||
405 | queue_no &= 7; | ||
406 | edma_modify_array(ecc, EDMA_DMAQNUM, (channel >> 3), ~(0x7 << bit), | ||
407 | queue_no << bit); | ||
408 | } | ||
409 | |||
410 | static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no, | 394 | static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no, |
411 | int priority) | 395 | int priority) |
412 | { | 396 | { |
@@ -723,6 +707,25 @@ static void edma_clean_channel(struct edma_chan *echan) | |||
723 | edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); | 707 | edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); |
724 | } | 708 | } |
725 | 709 | ||
710 | /* Move channel to a specific event queue */ | ||
711 | static void edma_assign_channel_eventq(struct edma_chan *echan, | ||
712 | enum dma_event_q eventq_no) | ||
713 | { | ||
714 | struct edma_cc *ecc = echan->ecc; | ||
715 | int channel = EDMA_CHAN_SLOT(echan->ch_num); | ||
716 | int bit = (channel & 0x7) * 4; | ||
717 | |||
718 | /* default to low priority queue */ | ||
719 | if (eventq_no == EVENTQ_DEFAULT) | ||
720 | eventq_no = ecc->default_queue; | ||
721 | if (eventq_no >= ecc->num_tc) | ||
722 | return; | ||
723 | |||
724 | eventq_no &= 7; | ||
725 | edma_modify_array(ecc, EDMA_DMAQNUM, (channel >> 3), ~(0x7 << bit), | ||
726 | eventq_no << bit); | ||
727 | } | ||
728 | |||
726 | static int edma_alloc_channel(struct edma_chan *echan, | 729 | static int edma_alloc_channel(struct edma_chan *echan, |
727 | enum dma_event_q eventq_no) | 730 | enum dma_event_q eventq_no) |
728 | { | 731 | { |
@@ -751,7 +754,7 @@ static int edma_alloc_channel(struct edma_chan *echan, | |||
751 | 754 | ||
752 | edma_setup_interrupt(echan, true); | 755 | edma_setup_interrupt(echan, true); |
753 | 756 | ||
754 | edma_map_dmach_to_queue(echan, eventq_no); | 757 | edma_assign_channel_eventq(echan, eventq_no); |
755 | 758 | ||
756 | return 0; | 759 | return 0; |
757 | } | 760 | } |
@@ -764,21 +767,6 @@ static void edma_free_channel(struct edma_chan *echan) | |||
764 | edma_setup_interrupt(echan, false); | 767 | edma_setup_interrupt(echan, false); |
765 | } | 768 | } |
766 | 769 | ||
767 | /* Move channel to a specific event queue */ | ||
768 | static void edma_assign_channel_eventq(struct edma_chan *echan, | ||
769 | enum dma_event_q eventq_no) | ||
770 | { | ||
771 | struct edma_cc *ecc = echan->ecc; | ||
772 | |||
773 | /* default to low priority queue */ | ||
774 | if (eventq_no == EVENTQ_DEFAULT) | ||
775 | eventq_no = ecc->default_queue; | ||
776 | if (eventq_no >= ecc->num_tc) | ||
777 | return; | ||
778 | |||
779 | edma_map_dmach_to_queue(echan, eventq_no); | ||
780 | } | ||
781 | |||
782 | static inline struct edma_cc *to_edma_cc(struct dma_device *d) | 770 | static inline struct edma_cc *to_edma_cc(struct dma_device *d) |
783 | { | 771 | { |
784 | return container_of(d, struct edma_cc, dma_slave); | 772 | return container_of(d, struct edma_cc, dma_slave); |
@@ -2154,8 +2142,8 @@ static int edma_probe(struct platform_device *pdev) | |||
2154 | 2142 | ||
2155 | for (i = 0; i < ecc->num_channels; i++) { | 2143 | for (i = 0; i < ecc->num_channels; i++) { |
2156 | /* Assign all channels to the default queue */ | 2144 | /* Assign all channels to the default queue */ |
2157 | edma_map_dmach_to_queue(&ecc->slave_chans[i], | 2145 | edma_assign_channel_eventq(&ecc->slave_chans[i], |
2158 | info->default_queue); | 2146 | info->default_queue); |
2159 | /* Set entry slot to the dummy slot */ | 2147 | /* Set entry slot to the dummy slot */ |
2160 | edma_set_chmap(&ecc->slave_chans[i], ecc->dummy_slot); | 2148 | edma_set_chmap(&ecc->slave_chans[i], ecc->dummy_slot); |
2161 | } | 2149 | } |