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authorAndreas Färber <afaerber@suse.de>2017-10-15 16:27:50 -0400
committerAndreas Färber <afaerber@suse.de>2017-10-26 03:11:54 -0400
commitf8b3436dad5c3911e2ef1a7aa037863cfc95686c (patch)
tree40afc976a91902483a6e5d1c52438a00161afb32
parentd938a964a966502955e3b4ee467b50d3d89e0cb7 (diff)
arm64: dts: realtek: Factor out common RTD129x parts
Prepares for RTD1293 and RTD1296. Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat
-rw-r--r--arch/arm64/boot/dts/realtek/rtd1295.dtsi65
-rw-r--r--arch/arm64/boot/dts/realtek/rtd129x.dtsi72
2 files changed, 76 insertions, 61 deletions
diff --git a/arch/arm64/boot/dts/realtek/rtd1295.dtsi b/arch/arm64/boot/dts/realtek/rtd1295.dtsi
index c8b7bb642a9a..8d9ac05d17dc 100644
--- a/arch/arm64/boot/dts/realtek/rtd1295.dtsi
+++ b/arch/arm64/boot/dts/realtek/rtd1295.dtsi
@@ -6,19 +6,10 @@
6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 */ 7 */
8 8
9/memreserve/ 0x0000000000000000 0x0000000000030000; 9#include "rtd129x.dtsi"
10/memreserve/ 0x000000000001f000 0x0000000000001000;
11/memreserve/ 0x0000000000030000 0x00000000000d0000;
12/memreserve/ 0x0000000001b00000 0x00000000004be000;
13/memreserve/ 0x0000000001ffe000 0x0000000000004000;
14
15#include <dt-bindings/interrupt-controller/arm-gic.h>
16 10
17/ { 11/ {
18 compatible = "realtek,rtd1295"; 12 compatible = "realtek,rtd1295";
19 interrupt-parent = <&gic>;
20 #address-cells = <1>;
21 #size-cells = <1>;
22 13
23 cpus { 14 cpus {
24 #address-cells = <2>; 15 #address-cells = <2>;
@@ -68,12 +59,6 @@
68 }; 59 };
69 }; 60 };
70 61
71 arm-pmu {
72 compatible = "arm,cortex-a53-pmu";
73 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
74 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
75 };
76
77 timer { 62 timer {
78 compatible = "arm,armv8-timer"; 63 compatible = "arm,armv8-timer";
79 interrupts = <GIC_PPI 13 64 interrupts = <GIC_PPI 13
@@ -85,50 +70,8 @@
85 <GIC_PPI 10 70 <GIC_PPI 10
86 (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>; 71 (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>;
87 }; 72 };
73};
88 74
89 soc { 75&arm_pmu {
90 compatible = "simple-bus"; 76 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
91 #address-cells = <1>;
92 #size-cells = <1>;
93 /* Exclude up to 2 GiB of RAM */
94 ranges = <0x80000000 0x80000000 0x80000000>;
95
96 uart0: serial@98007800 {
97 compatible = "snps,dw-apb-uart";
98 reg = <0x98007800 0x400>;
99 reg-shift = <2>;
100 reg-io-width = <4>;
101 clock-frequency = <27000000>;
102 status = "disabled";
103 };
104
105 uart1: serial@9801b200 {
106 compatible = "snps,dw-apb-uart";
107 reg = <0x9801b200 0x100>;
108 reg-shift = <2>;
109 reg-io-width = <4>;
110 clock-frequency = <432000000>;
111 status = "disabled";
112 };
113
114 uart2: serial@9801b400 {
115 compatible = "snps,dw-apb-uart";
116 reg = <0x9801b400 0x100>;
117 reg-shift = <2>;
118 reg-io-width = <4>;
119 clock-frequency = <432000000>;
120 status = "disabled";
121 };
122
123 gic: interrupt-controller@ff011000 {
124 compatible = "arm,gic-400";
125 reg = <0xff011000 0x1000>,
126 <0xff012000 0x2000>,
127 <0xff014000 0x2000>,
128 <0xff016000 0x2000>;
129 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
130 interrupt-controller;
131 #interrupt-cells = <3>;
132 };
133 };
134}; 77};
diff --git a/arch/arm64/boot/dts/realtek/rtd129x.dtsi b/arch/arm64/boot/dts/realtek/rtd129x.dtsi
new file mode 100644
index 000000000000..b9cb92466fc7
--- /dev/null
+++ b/arch/arm64/boot/dts/realtek/rtd129x.dtsi
@@ -0,0 +1,72 @@
1/*
2 * Realtek RTD1293/RTD1295/RTD1296 SoC
3 *
4 * Copyright (c) 2016-2017 Andreas Färber
5 *
6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 */
8
9/memreserve/ 0x0000000000000000 0x0000000000030000;
10/memreserve/ 0x000000000001f000 0x0000000000001000;
11/memreserve/ 0x0000000000030000 0x00000000000d0000;
12/memreserve/ 0x0000000001b00000 0x00000000004be000;
13/memreserve/ 0x0000000001ffe000 0x0000000000004000;
14
15#include <dt-bindings/interrupt-controller/arm-gic.h>
16
17/ {
18 interrupt-parent = <&gic>;
19 #address-cells = <1>;
20 #size-cells = <1>;
21
22 arm_pmu: arm-pmu {
23 compatible = "arm,cortex-a53-pmu";
24 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
25 };
26
27 soc {
28 compatible = "simple-bus";
29 #address-cells = <1>;
30 #size-cells = <1>;
31 /* Exclude up to 2 GiB of RAM */
32 ranges = <0x80000000 0x80000000 0x80000000>;
33
34 uart0: serial@98007800 {
35 compatible = "snps,dw-apb-uart";
36 reg = <0x98007800 0x400>;
37 reg-shift = <2>;
38 reg-io-width = <4>;
39 clock-frequency = <27000000>;
40 status = "disabled";
41 };
42
43 uart1: serial@9801b200 {
44 compatible = "snps,dw-apb-uart";
45 reg = <0x9801b200 0x100>;
46 reg-shift = <2>;
47 reg-io-width = <4>;
48 clock-frequency = <432000000>;
49 status = "disabled";
50 };
51
52 uart2: serial@9801b400 {
53 compatible = "snps,dw-apb-uart";
54 reg = <0x9801b400 0x100>;
55 reg-shift = <2>;
56 reg-io-width = <4>;
57 clock-frequency = <432000000>;
58 status = "disabled";
59 };
60
61 gic: interrupt-controller@ff011000 {
62 compatible = "arm,gic-400";
63 reg = <0xff011000 0x1000>,
64 <0xff012000 0x2000>,
65 <0xff014000 0x2000>,
66 <0xff016000 0x2000>;
67 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
68 interrupt-controller;
69 #interrupt-cells = <3>;
70 };
71 };
72};
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