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authorMark Yao <mark.yao@rock-chips.com>2015-12-14 20:57:13 -0500
committerMark Yao <mark.yao@rock-chips.com>2015-12-27 20:01:48 -0500
commitf7673453506035a904b6fb7a36dd6fb101366cd7 (patch)
tree3f4fc66d95f1cf5c459d82c4f07af9d2028054b9
parent1194fffbb102b1683bcbfc893df20bbf8a038468 (diff)
drm/rockchip: vop: add rk3036 vop support
RK3036 registers layout is quite difference with rk3288 layout, The IC design with different framework, rk3036 vop is VOP LITE, and rk3288 is VOP FULL. RK3036 support two overlay plane and one hwc plane, max output resolution is 1080p. it support IOMMU, and its IOMMU same as rk3288's. Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Diffstat
-rw-r--r--drivers/gpu/drm/rockchip/rockchip_vop_reg.c296
-rw-r--r--drivers/gpu/drm/rockchip/rockchip_vop_reg.h243
2 files changed, 336 insertions, 203 deletions
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 6495114277e0..3166b46a5893 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -25,7 +25,7 @@
25 .mask = _mask, \ 25 .mask = _mask, \
26 .shift = s,} 26 .shift = s,}
27 27
28static const uint32_t formats_01[] = { 28static const uint32_t formats_win_full[] = {
29 DRM_FORMAT_XRGB8888, 29 DRM_FORMAT_XRGB8888,
30 DRM_FORMAT_ARGB8888, 30 DRM_FORMAT_ARGB8888,
31 DRM_FORMAT_XBGR8888, 31 DRM_FORMAT_XBGR8888,
@@ -39,7 +39,7 @@ static const uint32_t formats_01[] = {
39 DRM_FORMAT_NV24, 39 DRM_FORMAT_NV24,
40}; 40};
41 41
42static const uint32_t formats_234[] = { 42static const uint32_t formats_win_lite[] = {
43 DRM_FORMAT_XRGB8888, 43 DRM_FORMAT_XRGB8888,
44 DRM_FORMAT_ARGB8888, 44 DRM_FORMAT_ARGB8888,
45 DRM_FORMAT_XBGR8888, 45 DRM_FORMAT_XBGR8888,
@@ -50,102 +50,103 @@ static const uint32_t formats_234[] = {
50 DRM_FORMAT_BGR565, 50 DRM_FORMAT_BGR565,
51}; 51};
52 52
53static const struct vop_scl_extension win_full_ext = { 53static const struct vop_scl_extension rk3288_win_full_scl_ext = {
54 .cbcr_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 31), 54 .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
55 .cbcr_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 30), 55 .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
56 .cbcr_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 28), 56 .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28),
57 .cbcr_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 26), 57 .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26),
58 .cbcr_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 24), 58 .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24),
59 .yrgb_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 23), 59 .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23),
60 .yrgb_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 22), 60 .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22),
61 .yrgb_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 20), 61 .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20),
62 .yrgb_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 18), 62 .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18),
63 .yrgb_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 16), 63 .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16),
64 .line_load_mode = VOP_REG(WIN0_CTRL1, 0x1, 15), 64 .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15),
65 .cbcr_axi_gather_num = VOP_REG(WIN0_CTRL1, 0x7, 12), 65 .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12),
66 .yrgb_axi_gather_num = VOP_REG(WIN0_CTRL1, 0xf, 8), 66 .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8),
67 .vsd_cbcr_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 7), 67 .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7),
68 .vsd_cbcr_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 6), 68 .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6),
69 .vsd_yrgb_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 5), 69 .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5),
70 .vsd_yrgb_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 4), 70 .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4),
71 .bic_coe_sel = VOP_REG(WIN0_CTRL1, 0x3, 2), 71 .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2),
72 .cbcr_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 1), 72 .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1),
73 .yrgb_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 0), 73 .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0),
74 .lb_mode = VOP_REG(WIN0_CTRL0, 0x7, 5), 74 .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5),
75}; 75};
76 76
77static const struct vop_scl_regs win_full_scl = { 77static const struct vop_scl_regs rk3288_win_full_scl = {
78 .scale_yrgb_x = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 78 .ext = &rk3288_win_full_scl_ext,
79 .scale_yrgb_y = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 79 .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
80 .scale_cbcr_x = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 80 .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
81 .scale_cbcr_y = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 16), 81 .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
82}; 82 .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
83 83};
84static const struct vop_win_phy win01_data = { 84
85 .scl = &win_full_scl, 85static const struct vop_win_phy rk3288_win01_data = {
86 .data_formats = formats_01, 86 .scl = &rk3288_win_full_scl,
87 .nformats = ARRAY_SIZE(formats_01), 87 .data_formats = formats_win_full,
88 .enable = VOP_REG(WIN0_CTRL0, 0x1, 0), 88 .nformats = ARRAY_SIZE(formats_win_full),
89 .format = VOP_REG(WIN0_CTRL0, 0x7, 1), 89 .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
90 .rb_swap = VOP_REG(WIN0_CTRL0, 0x1, 12), 90 .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
91 .act_info = VOP_REG(WIN0_ACT_INFO, 0x1fff1fff, 0), 91 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
92 .dsp_info = VOP_REG(WIN0_DSP_INFO, 0x0fff0fff, 0), 92 .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
93 .dsp_st = VOP_REG(WIN0_DSP_ST, 0x1fff1fff, 0), 93 .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
94 .yrgb_mst = VOP_REG(WIN0_YRGB_MST, 0xffffffff, 0), 94 .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
95 .uv_mst = VOP_REG(WIN0_CBR_MST, 0xffffffff, 0), 95 .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
96 .yrgb_vir = VOP_REG(WIN0_VIR, 0x3fff, 0), 96 .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
97 .uv_vir = VOP_REG(WIN0_VIR, 0x3fff, 16), 97 .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
98 .src_alpha_ctl = VOP_REG(WIN0_SRC_ALPHA_CTRL, 0xff, 0), 98 .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
99 .dst_alpha_ctl = VOP_REG(WIN0_DST_ALPHA_CTRL, 0xff, 0), 99 .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
100}; 100 .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
101 101};
102static const struct vop_win_phy win23_data = { 102
103 .data_formats = formats_234, 103static const struct vop_win_phy rk3288_win23_data = {
104 .nformats = ARRAY_SIZE(formats_234), 104 .data_formats = formats_win_lite,
105 .enable = VOP_REG(WIN2_CTRL0, 0x1, 0), 105 .nformats = ARRAY_SIZE(formats_win_lite),
106 .format = VOP_REG(WIN2_CTRL0, 0x7, 1), 106 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
107 .rb_swap = VOP_REG(WIN2_CTRL0, 0x1, 12), 107 .format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
108 .dsp_info = VOP_REG(WIN2_DSP_INFO0, 0x0fff0fff, 0), 108 .rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
109 .dsp_st = VOP_REG(WIN2_DSP_ST0, 0x1fff1fff, 0), 109 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
110 .yrgb_mst = VOP_REG(WIN2_MST0, 0xffffffff, 0), 110 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST0, 0x1fff1fff, 0),
111 .yrgb_vir = VOP_REG(WIN2_VIR0_1, 0x1fff, 0), 111 .yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffffffff, 0),
112 .src_alpha_ctl = VOP_REG(WIN2_SRC_ALPHA_CTRL, 0xff, 0), 112 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 0),
113 .dst_alpha_ctl = VOP_REG(WIN2_DST_ALPHA_CTRL, 0xff, 0), 113 .src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
114}; 114 .dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0),
115 115};
116static const struct vop_ctrl ctrl_data = { 116
117 .standby = VOP_REG(SYS_CTRL, 0x1, 22), 117static const struct vop_ctrl rk3288_ctrl_data = {
118 .gate_en = VOP_REG(SYS_CTRL, 0x1, 23), 118 .standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22),
119 .mmu_en = VOP_REG(SYS_CTRL, 0x1, 20), 119 .gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
120 .rgb_en = VOP_REG(SYS_CTRL, 0x1, 12), 120 .mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20),
121 .hdmi_en = VOP_REG(SYS_CTRL, 0x1, 13), 121 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
122 .edp_en = VOP_REG(SYS_CTRL, 0x1, 14), 122 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
123 .mipi_en = VOP_REG(SYS_CTRL, 0x1, 15), 123 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
124 .dither_down = VOP_REG(DSP_CTRL1, 0xf, 1), 124 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
125 .dither_up = VOP_REG(DSP_CTRL1, 0x1, 6), 125 .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
126 .data_blank = VOP_REG(DSP_CTRL0, 0x1, 19), 126 .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
127 .out_mode = VOP_REG(DSP_CTRL0, 0xf, 0), 127 .data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19),
128 .pin_pol = VOP_REG(DSP_CTRL0, 0xf, 4), 128 .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
129 .htotal_pw = VOP_REG(DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 129 .pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4),
130 .hact_st_end = VOP_REG(DSP_HACT_ST_END, 0x1fff1fff, 0), 130 .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
131 .vtotal_pw = VOP_REG(DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 131 .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
132 .vact_st_end = VOP_REG(DSP_VACT_ST_END, 0x1fff1fff, 0), 132 .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
133 .hpost_st_end = VOP_REG(POST_DSP_HACT_INFO, 0x1fff1fff, 0), 133 .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
134 .vpost_st_end = VOP_REG(POST_DSP_VACT_INFO, 0x1fff1fff, 0), 134 .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
135 .cfg_done = VOP_REG(REG_CFG_DONE, 0x1, 0), 135 .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
136}; 136 .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
137 137};
138static const struct vop_reg_data vop_init_reg_table[] = { 138
139 {SYS_CTRL, 0x00c00000}, 139static const struct vop_reg_data rk3288_init_reg_table[] = {
140 {DSP_CTRL0, 0x00000000}, 140 {RK3288_SYS_CTRL, 0x00c00000},
141 {WIN0_CTRL0, 0x00000080}, 141 {RK3288_DSP_CTRL0, 0x00000000},
142 {WIN1_CTRL0, 0x00000080}, 142 {RK3288_WIN0_CTRL0, 0x00000080},
143 {RK3288_WIN1_CTRL0, 0x00000080},
143 /* TODO: Win2/3 support multiple area function, but we haven't found 144 /* TODO: Win2/3 support multiple area function, but we haven't found
144 * a suitable way to use it yet, so let's just use them as other windows 145 * a suitable way to use it yet, so let's just use them as other windows
145 * with only area 0 enabled. 146 * with only area 0 enabled.
146 */ 147 */
147 {WIN2_CTRL0, 0x00000010}, 148 {RK3288_WIN2_CTRL0, 0x00000010},
148 {WIN3_CTRL0, 0x00000010}, 149 {RK3288_WIN3_CTRL0, 0x00000010},
149}; 150};
150 151
151/* 152/*
@@ -155,10 +156,14 @@ static const struct vop_reg_data vop_init_reg_table[] = {
155 * 156 *
156 */ 157 */
157static const struct vop_win_data rk3288_vop_win_data[] = { 158static const struct vop_win_data rk3288_vop_win_data[] = {
158 { .base = 0x00, .phy = &win01_data, .type = DRM_PLANE_TYPE_PRIMARY }, 159 { .base = 0x00, .phy = &rk3288_win01_data,
159 { .base = 0x40, .phy = &win01_data, .type = DRM_PLANE_TYPE_OVERLAY }, 160 .type = DRM_PLANE_TYPE_PRIMARY },
160 { .base = 0x00, .phy = &win23_data, .type = DRM_PLANE_TYPE_OVERLAY }, 161 { .base = 0x40, .phy = &rk3288_win01_data,
161 { .base = 0x50, .phy = &win23_data, .type = DRM_PLANE_TYPE_CURSOR }, 162 .type = DRM_PLANE_TYPE_OVERLAY },
163 { .base = 0x00, .phy = &rk3288_win23_data,
164 .type = DRM_PLANE_TYPE_OVERLAY },
165 { .base = 0x50, .phy = &rk3288_win23_data,
166 .type = DRM_PLANE_TYPE_CURSOR },
162}; 167};
163 168
164static const int rk3288_vop_intrs[] = { 169static const int rk3288_vop_intrs[] = {
@@ -171,23 +176,106 @@ static const int rk3288_vop_intrs[] = {
171static const struct vop_intr rk3288_vop_intr = { 176static const struct vop_intr rk3288_vop_intr = {
172 .intrs = rk3288_vop_intrs, 177 .intrs = rk3288_vop_intrs,
173 .nintrs = ARRAY_SIZE(rk3288_vop_intrs), 178 .nintrs = ARRAY_SIZE(rk3288_vop_intrs),
174 .status = VOP_REG(INTR_CTRL0, 0xf, 0), 179 .status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
175 .enable = VOP_REG(INTR_CTRL0, 0xf, 4), 180 .enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
176 .clear = VOP_REG(INTR_CTRL0, 0xf, 8), 181 .clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
177}; 182};
178 183
179static const struct vop_data rk3288_vop = { 184static const struct vop_data rk3288_vop = {
180 .init_table = vop_init_reg_table, 185 .init_table = rk3288_init_reg_table,
186 .table_size = ARRAY_SIZE(rk3288_init_reg_table),
181 .intr = &rk3288_vop_intr, 187 .intr = &rk3288_vop_intr,
182 .table_size = ARRAY_SIZE(vop_init_reg_table), 188 .ctrl = &rk3288_ctrl_data,
183 .ctrl = &ctrl_data,
184 .win = rk3288_vop_win_data, 189 .win = rk3288_vop_win_data,
185 .win_size = ARRAY_SIZE(rk3288_vop_win_data), 190 .win_size = ARRAY_SIZE(rk3288_vop_win_data),
186}; 191};
187 192
193static const struct vop_scl_regs rk3066_win_scl = {
194 .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
195 .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
196 .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
197 .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
198};
199
200static const struct vop_win_phy rk3036_win0_data = {
201 .scl = &rk3066_win_scl,
202 .data_formats = formats_win_full,
203 .nformats = ARRAY_SIZE(formats_win_full),
204 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
205 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3),
206 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15),
207 .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0),
208 .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0),
209 .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0),
210 .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0),
211 .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0),
212 .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0),
213};
214
215static const struct vop_win_phy rk3036_win1_data = {
216 .data_formats = formats_win_lite,
217 .nformats = ARRAY_SIZE(formats_win_lite),
218 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
219 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
220 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
221 .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0),
222 .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0),
223 .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0),
224 .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0),
225 .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
226};
227
228static const struct vop_win_data rk3036_vop_win_data[] = {
229 { .base = 0x00, .phy = &rk3036_win0_data,
230 .type = DRM_PLANE_TYPE_PRIMARY },
231 { .base = 0x00, .phy = &rk3036_win1_data,
232 .type = DRM_PLANE_TYPE_CURSOR },
233};
234
235static const int rk3036_vop_intrs[] = {
236 DSP_HOLD_VALID_INTR,
237 FS_INTR,
238 LINE_FLAG_INTR,
239 BUS_ERROR_INTR,
240};
241
242static const struct vop_intr rk3036_intr = {
243 .intrs = rk3036_vop_intrs,
244 .nintrs = ARRAY_SIZE(rk3036_vop_intrs),
245 .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0),
246 .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4),
247 .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8),
248};
249
250static const struct vop_ctrl rk3036_ctrl_data = {
251 .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
252 .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
253 .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
254 .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
255 .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
256 .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
257 .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
258 .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
259};
260
261static const struct vop_reg_data rk3036_vop_init_reg_table[] = {
262 {RK3036_DSP_CTRL1, 0x00000000},
263};
264
265static const struct vop_data rk3036_vop = {
266 .init_table = rk3036_vop_init_reg_table,
267 .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table),
268 .ctrl = &rk3036_ctrl_data,
269 .intr = &rk3036_intr,
270 .win = rk3036_vop_win_data,
271 .win_size = ARRAY_SIZE(rk3036_vop_win_data),
272};
273
188static const struct of_device_id vop_driver_dt_match[] = { 274static const struct of_device_id vop_driver_dt_match[] = {
189 { .compatible = "rockchip,rk3288-vop", 275 { .compatible = "rockchip,rk3288-vop",
190 .data = &rk3288_vop }, 276 .data = &rk3288_vop },
277 { .compatible = "rockchip,rk3036-vop",
278 .data = &rk3036_vop },
191 {}, 279 {},
192}; 280};
193MODULE_DEVICE_TABLE(of, vop_driver_dt_match); 281MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
index b0fa35d42878..d4b46cba2f26 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
@@ -15,110 +15,155 @@
15#ifndef _ROCKCHIP_VOP_REG_H 15#ifndef _ROCKCHIP_VOP_REG_H
16#define _ROCKCHIP_VOP_REG_H 16#define _ROCKCHIP_VOP_REG_H
17 17
18/* register definition */ 18/* rk3288 register definition */
19#define REG_CFG_DONE 0x0000 19#define RK3288_REG_CFG_DONE 0x0000
20#define VERSION_INFO 0x0004 20#define RK3288_VERSION_INFO 0x0004
21#define SYS_CTRL 0x0008 21#define RK3288_SYS_CTRL 0x0008
22#define SYS_CTRL1 0x000c 22#define RK3288_SYS_CTRL1 0x000c
23#define DSP_CTRL0 0x0010 23#define RK3288_DSP_CTRL0 0x0010
24#define DSP_CTRL1 0x0014 24#define RK3288_DSP_CTRL1 0x0014
25#define DSP_BG 0x0018 25#define RK3288_DSP_BG 0x0018
26#define MCU_CTRL 0x001c 26#define RK3288_MCU_CTRL 0x001c
27#define INTR_CTRL0 0x0020 27#define RK3288_INTR_CTRL0 0x0020
28#define INTR_CTRL1 0x0024 28#define RK3288_INTR_CTRL1 0x0024
29#define WIN0_CTRL0 0x0030 29#define RK3288_WIN0_CTRL0 0x0030
30#define WIN0_CTRL1 0x0034 30#define RK3288_WIN0_CTRL1 0x0034
31#define WIN0_COLOR_KEY 0x0038 31#define RK3288_WIN0_COLOR_KEY 0x0038
32#define WIN0_VIR 0x003c 32#define RK3288_WIN0_VIR 0x003c
33#define WIN0_YRGB_MST 0x0040 33#define RK3288_WIN0_YRGB_MST 0x0040
34#define WIN0_CBR_MST 0x0044 34#define RK3288_WIN0_CBR_MST 0x0044
35#define WIN0_ACT_INFO 0x0048 35#define RK3288_WIN0_ACT_INFO 0x0048
36#define WIN0_DSP_INFO 0x004c 36#define RK3288_WIN0_DSP_INFO 0x004c
37#define WIN0_DSP_ST 0x0050 37#define RK3288_WIN0_DSP_ST 0x0050
38#define WIN0_SCL_FACTOR_YRGB 0x0054 38#define RK3288_WIN0_SCL_FACTOR_YRGB 0x0054
39#define WIN0_SCL_FACTOR_CBR 0x0058 39#define RK3288_WIN0_SCL_FACTOR_CBR 0x0058
40#define WIN0_SCL_OFFSET 0x005c 40#define RK3288_WIN0_SCL_OFFSET 0x005c
41#define WIN0_SRC_ALPHA_CTRL 0x0060 41#define RK3288_WIN0_SRC_ALPHA_CTRL 0x0060
42#define WIN0_DST_ALPHA_CTRL 0x0064 42#define RK3288_WIN0_DST_ALPHA_CTRL 0x0064
43#define WIN0_FADING_CTRL 0x0068 43#define RK3288_WIN0_FADING_CTRL 0x0068
44
44/* win1 register */ 45/* win1 register */
45#define WIN1_CTRL0 0x0070 46#define RK3288_WIN1_CTRL0 0x0070
46#define WIN1_CTRL1 0x0074 47#define RK3288_WIN1_CTRL1 0x0074
47#define WIN1_COLOR_KEY 0x0078 48#define RK3288_WIN1_COLOR_KEY 0x0078
48#define WIN1_VIR 0x007c 49#define RK3288_WIN1_VIR 0x007c
49#define WIN1_YRGB_MST 0x0080 50#define RK3288_WIN1_YRGB_MST 0x0080
50#define WIN1_CBR_MST 0x0084 51#define RK3288_WIN1_CBR_MST 0x0084
51#define WIN1_ACT_INFO 0x0088 52#define RK3288_WIN1_ACT_INFO 0x0088
52#define WIN1_DSP_INFO 0x008c 53#define RK3288_WIN1_DSP_INFO 0x008c
53#define WIN1_DSP_ST 0x0090 54#define RK3288_WIN1_DSP_ST 0x0090
54#define WIN1_SCL_FACTOR_YRGB 0x0094 55#define RK3288_WIN1_SCL_FACTOR_YRGB 0x0094
55#define WIN1_SCL_FACTOR_CBR 0x0098 56#define RK3288_WIN1_SCL_FACTOR_CBR 0x0098
56#define WIN1_SCL_OFFSET 0x009c 57#define RK3288_WIN1_SCL_OFFSET 0x009c
57#define WIN1_SRC_ALPHA_CTRL 0x00a0 58#define RK3288_WIN1_SRC_ALPHA_CTRL 0x00a0
58#define WIN1_DST_ALPHA_CTRL 0x00a4 59#define RK3288_WIN1_DST_ALPHA_CTRL 0x00a4
59#define WIN1_FADING_CTRL 0x00a8 60#define RK3288_WIN1_FADING_CTRL 0x00a8
60/* win2 register */ 61/* win2 register */
61#define WIN2_CTRL0 0x00b0 62#define RK3288_WIN2_CTRL0 0x00b0
62#define WIN2_CTRL1 0x00b4 63#define RK3288_WIN2_CTRL1 0x00b4
63#define WIN2_VIR0_1 0x00b8 64#define RK3288_WIN2_VIR0_1 0x00b8
64#define WIN2_VIR2_3 0x00bc 65#define RK3288_WIN2_VIR2_3 0x00bc
65#define WIN2_MST0 0x00c0 66#define RK3288_WIN2_MST0 0x00c0
66#define WIN2_DSP_INFO0 0x00c4 67#define RK3288_WIN2_DSP_INFO0 0x00c4
67#define WIN2_DSP_ST0 0x00c8 68#define RK3288_WIN2_DSP_ST0 0x00c8
68#define WIN2_COLOR_KEY 0x00cc 69#define RK3288_WIN2_COLOR_KEY 0x00cc
69#define WIN2_MST1 0x00d0 70#define RK3288_WIN2_MST1 0x00d0
70#define WIN2_DSP_INFO1 0x00d4 71#define RK3288_WIN2_DSP_INFO1 0x00d4
71#define WIN2_DSP_ST1 0x00d8 72#define RK3288_WIN2_DSP_ST1 0x00d8
72#define WIN2_SRC_ALPHA_CTRL 0x00dc 73#define RK3288_WIN2_SRC_ALPHA_CTRL 0x00dc
73#define WIN2_MST2 0x00e0 74#define RK3288_WIN2_MST2 0x00e0
74#define WIN2_DSP_INFO2 0x00e4 75#define RK3288_WIN2_DSP_INFO2 0x00e4
75#define WIN2_DSP_ST2 0x00e8 76#define RK3288_WIN2_DSP_ST2 0x00e8
76#define WIN2_DST_ALPHA_CTRL 0x00ec 77#define RK3288_WIN2_DST_ALPHA_CTRL 0x00ec
77#define WIN2_MST3 0x00f0 78#define RK3288_WIN2_MST3 0x00f0
78#define WIN2_DSP_INFO3 0x00f4 79#define RK3288_WIN2_DSP_INFO3 0x00f4
79#define WIN2_DSP_ST3 0x00f8 80#define RK3288_WIN2_DSP_ST3 0x00f8
80#define WIN2_FADING_CTRL 0x00fc 81#define RK3288_WIN2_FADING_CTRL 0x00fc
81/* win3 register */ 82/* win3 register */
82#define WIN3_CTRL0 0x0100 83#define RK3288_WIN3_CTRL0 0x0100
83#define WIN3_CTRL1 0x0104 84#define RK3288_WIN3_CTRL1 0x0104
84#define WIN3_VIR0_1 0x0108 85#define RK3288_WIN3_VIR0_1 0x0108
85#define WIN3_VIR2_3 0x010c 86#define RK3288_WIN3_VIR2_3 0x010c
86#define WIN3_MST0 0x0110 87#define RK3288_WIN3_MST0 0x0110
87#define WIN3_DSP_INFO0 0x0114 88#define RK3288_WIN3_DSP_INFO0 0x0114
88#define WIN3_DSP_ST0 0x0118 89#define RK3288_WIN3_DSP_ST0 0x0118
89#define WIN3_COLOR_KEY 0x011c 90#define RK3288_WIN3_COLOR_KEY 0x011c
90#define WIN3_MST1 0x0120 91#define RK3288_WIN3_MST1 0x0120
91#define WIN3_DSP_INFO1 0x0124 92#define RK3288_WIN3_DSP_INFO1 0x0124
92#define WIN3_DSP_ST1 0x0128 93#define RK3288_WIN3_DSP_ST1 0x0128
93#define WIN3_SRC_ALPHA_CTRL 0x012c 94#define RK3288_WIN3_SRC_ALPHA_CTRL 0x012c
94#define WIN3_MST2 0x0130 95#define RK3288_WIN3_MST2 0x0130
95#define WIN3_DSP_INFO2 0x0134 96#define RK3288_WIN3_DSP_INFO2 0x0134
96#define WIN3_DSP_ST2 0x0138 97#define RK3288_WIN3_DSP_ST2 0x0138
97#define WIN3_DST_ALPHA_CTRL 0x013c 98#define RK3288_WIN3_DST_ALPHA_CTRL 0x013c
98#define WIN3_MST3 0x0140 99#define RK3288_WIN3_MST3 0x0140
99#define WIN3_DSP_INFO3 0x0144 100#define RK3288_WIN3_DSP_INFO3 0x0144
100#define WIN3_DSP_ST3 0x0148 101#define RK3288_WIN3_DSP_ST3 0x0148
101#define WIN3_FADING_CTRL 0x014c 102#define RK3288_WIN3_FADING_CTRL 0x014c
102/* hwc register */ 103/* hwc register */
103#define HWC_CTRL0 0x0150 104#define RK3288_HWC_CTRL0 0x0150
104#define HWC_CTRL1 0x0154 105#define RK3288_HWC_CTRL1 0x0154
105#define HWC_MST 0x0158 106#define RK3288_HWC_MST 0x0158
106#define HWC_DSP_ST 0x015c 107#define RK3288_HWC_DSP_ST 0x015c
107#define HWC_SRC_ALPHA_CTRL 0x0160 108#define RK3288_HWC_SRC_ALPHA_CTRL 0x0160
108#define HWC_DST_ALPHA_CTRL 0x0164 109#define RK3288_HWC_DST_ALPHA_CTRL 0x0164
109#define HWC_FADING_CTRL 0x0168 110#define RK3288_HWC_FADING_CTRL 0x0168
110/* post process register */ 111/* post process register */
111#define POST_DSP_HACT_INFO 0x0170 112#define RK3288_POST_DSP_HACT_INFO 0x0170
112#define POST_DSP_VACT_INFO 0x0174 113#define RK3288_POST_DSP_VACT_INFO 0x0174
113#define POST_SCL_FACTOR_YRGB 0x0178 114#define RK3288_POST_SCL_FACTOR_YRGB 0x0178
114#define POST_SCL_CTRL 0x0180 115#define RK3288_POST_SCL_CTRL 0x0180
115#define POST_DSP_VACT_INFO_F1 0x0184 116#define RK3288_POST_DSP_VACT_INFO_F1 0x0184
116#define DSP_HTOTAL_HS_END 0x0188 117#define RK3288_DSP_HTOTAL_HS_END 0x0188
117#define DSP_HACT_ST_END 0x018c 118#define RK3288_DSP_HACT_ST_END 0x018c
118#define DSP_VTOTAL_VS_END 0x0190 119#define RK3288_DSP_VTOTAL_VS_END 0x0190
119#define DSP_VACT_ST_END 0x0194 120#define RK3288_DSP_VACT_ST_END 0x0194
120#define DSP_VS_ST_END_F1 0x0198 121#define RK3288_DSP_VS_ST_END_F1 0x0198
121#define DSP_VACT_ST_END_F1 0x019c 122#define RK3288_DSP_VACT_ST_END_F1 0x019c
122/* register definition end */ 123/* register definition end */
123 124
125/* rk3036 register definition */
126#define RK3036_SYS_CTRL 0x00
127#define RK3036_DSP_CTRL0 0x04
128#define RK3036_DSP_CTRL1 0x08
129#define RK3036_INT_STATUS 0x10
130#define RK3036_ALPHA_CTRL 0x14
131#define RK3036_WIN0_COLOR_KEY 0x18
132#define RK3036_WIN1_COLOR_KEY 0x1c
133#define RK3036_WIN0_YRGB_MST 0x20
134#define RK3036_WIN0_CBR_MST 0x24
135#define RK3036_WIN1_VIR 0x28
136#define RK3036_AXI_BUS_CTRL 0x2c
137#define RK3036_WIN0_VIR 0x30
138#define RK3036_WIN0_ACT_INFO 0x34
139#define RK3036_WIN0_DSP_INFO 0x38
140#define RK3036_WIN0_DSP_ST 0x3c
141#define RK3036_WIN0_SCL_FACTOR_YRGB 0x40
142#define RK3036_WIN0_SCL_FACTOR_CBR 0x44
143#define RK3036_WIN0_SCL_OFFSET 0x48
144#define RK3036_HWC_MST 0x58
145#define RK3036_HWC_DSP_ST 0x5c
146#define RK3036_DSP_HTOTAL_HS_END 0x6c
147#define RK3036_DSP_HACT_ST_END 0x70
148#define RK3036_DSP_VTOTAL_VS_END 0x74
149#define RK3036_DSP_VACT_ST_END 0x78
150#define RK3036_DSP_VS_ST_END_F1 0x7c
151#define RK3036_DSP_VACT_ST_END_F1 0x80
152#define RK3036_GATHER_TRANSFER 0x84
153#define RK3036_VERSION_INFO 0x94
154#define RK3036_REG_CFG_DONE 0x90
155#define RK3036_WIN1_MST 0xa0
156#define RK3036_WIN1_ACT_INFO 0xb4
157#define RK3036_WIN1_DSP_INFO 0xb8
158#define RK3036_WIN1_DSP_ST 0xbc
159#define RK3036_WIN1_SCL_FACTOR_YRGB 0xc0
160#define RK3036_WIN1_SCL_OFFSET 0xc8
161#define RK3036_BCSH_CTRL 0xd0
162#define RK3036_BCSH_COLOR_BAR 0xd4
163#define RK3036_BCSH_BCS 0xd8
164#define RK3036_BCSH_H 0xdc
165#define RK3036_WIN1_LUT_ADDR 0x400
166#define RK3036_HWC_LUT_ADDR 0x800
167/* rk3036 register definition end */
168
124#endif /* _ROCKCHIP_VOP_REG_H */ 169#endif /* _ROCKCHIP_VOP_REG_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 06:08:56 -0400