aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorUlrich Hecht <ulrich.hecht+renesas@gmail.com>2014-12-10 09:45:26 -0500
committerSimon Horman <horms+renesas@verge.net.au>2014-12-21 03:09:24 -0500
commitf73e1e28b5ed9bbb2358606b5abf76d3f94fe8cf (patch)
treeb148edc56e7b4b6aa67fbfa67afc7ee577967113
parent1a9a658113c33235ca12e622d91331dd91c61035 (diff)
ARM: shmobile: sh73a0: add MSTP clock assignments to DT
Assigns clocks to cmt1, i2c*, mmcif, sdhi*, and scif*. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
-rw-r--r--arch/arm/boot/dts/sh73a0.dtsi29
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 3f21b3257679..cca22ec59a2e 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -56,6 +56,8 @@
56 56
57 renesas,channels-mask = <0x3f>; 57 renesas,channels-mask = <0x3f>;
58 58
59 clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
60 clock-names = "fck";
59 status = "disabled"; 61 status = "disabled";
60 }; 62 };
61 63
@@ -145,6 +147,7 @@
145 0 168 IRQ_TYPE_LEVEL_HIGH 147 0 168 IRQ_TYPE_LEVEL_HIGH
146 0 169 IRQ_TYPE_LEVEL_HIGH 148 0 169 IRQ_TYPE_LEVEL_HIGH
147 0 170 IRQ_TYPE_LEVEL_HIGH>; 149 0 170 IRQ_TYPE_LEVEL_HIGH>;
150 clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
148 status = "disabled"; 151 status = "disabled";
149 }; 152 };
150 153
@@ -157,6 +160,7 @@
157 0 52 IRQ_TYPE_LEVEL_HIGH 160 0 52 IRQ_TYPE_LEVEL_HIGH
158 0 53 IRQ_TYPE_LEVEL_HIGH 161 0 53 IRQ_TYPE_LEVEL_HIGH
159 0 54 IRQ_TYPE_LEVEL_HIGH>; 162 0 54 IRQ_TYPE_LEVEL_HIGH>;
163 clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
160 status = "disabled"; 164 status = "disabled";
161 }; 165 };
162 166
@@ -169,6 +173,7 @@
169 0 172 IRQ_TYPE_LEVEL_HIGH 173 0 172 IRQ_TYPE_LEVEL_HIGH
170 0 173 IRQ_TYPE_LEVEL_HIGH 174 0 173 IRQ_TYPE_LEVEL_HIGH
171 0 174 IRQ_TYPE_LEVEL_HIGH>; 175 0 174 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
172 status = "disabled"; 177 status = "disabled";
173 }; 178 };
174 179
@@ -181,6 +186,7 @@
181 0 184 IRQ_TYPE_LEVEL_HIGH 186 0 184 IRQ_TYPE_LEVEL_HIGH
182 0 185 IRQ_TYPE_LEVEL_HIGH 187 0 185 IRQ_TYPE_LEVEL_HIGH
183 0 186 IRQ_TYPE_LEVEL_HIGH>; 188 0 186 IRQ_TYPE_LEVEL_HIGH>;
189 clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
184 status = "disabled"; 190 status = "disabled";
185 }; 191 };
186 192
@@ -193,6 +199,7 @@
193 0 188 IRQ_TYPE_LEVEL_HIGH 199 0 188 IRQ_TYPE_LEVEL_HIGH
194 0 189 IRQ_TYPE_LEVEL_HIGH 200 0 189 IRQ_TYPE_LEVEL_HIGH
195 0 190 IRQ_TYPE_LEVEL_HIGH>; 201 0 190 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
196 status = "disabled"; 203 status = "disabled";
197 }; 204 };
198 205
@@ -201,6 +208,7 @@
201 reg = <0xe6bd0000 0x100>; 208 reg = <0xe6bd0000 0x100>;
202 interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH 209 interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH
203 0 141 IRQ_TYPE_LEVEL_HIGH>; 210 0 141 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
204 reg-io-width = <4>; 212 reg-io-width = <4>;
205 status = "disabled"; 213 status = "disabled";
206 }; 214 };
@@ -211,6 +219,7 @@
211 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH 219 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH
212 0 84 IRQ_TYPE_LEVEL_HIGH 220 0 84 IRQ_TYPE_LEVEL_HIGH
213 0 85 IRQ_TYPE_LEVEL_HIGH>; 221 0 85 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
214 cap-sd-highspeed; 223 cap-sd-highspeed;
215 status = "disabled"; 224 status = "disabled";
216 }; 225 };
@@ -221,6 +230,7 @@
221 reg = <0xee120000 0x100>; 230 reg = <0xee120000 0x100>;
222 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH 231 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH
223 0 89 IRQ_TYPE_LEVEL_HIGH>; 232 0 89 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
224 toshiba,mmc-wrprotect-disable; 234 toshiba,mmc-wrprotect-disable;
225 cap-sd-highspeed; 235 cap-sd-highspeed;
226 status = "disabled"; 236 status = "disabled";
@@ -231,6 +241,7 @@
231 reg = <0xee140000 0x100>; 241 reg = <0xee140000 0x100>;
232 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH 242 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH
233 0 105 IRQ_TYPE_LEVEL_HIGH>; 243 0 105 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
234 toshiba,mmc-wrprotect-disable; 245 toshiba,mmc-wrprotect-disable;
235 cap-sd-highspeed; 246 cap-sd-highspeed;
236 status = "disabled"; 247 status = "disabled";
@@ -240,6 +251,8 @@
240 compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 251 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
241 reg = <0xe6c40000 0x100>; 252 reg = <0xe6c40000 0x100>;
242 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; 253 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
255 clock-names = "sci_ick";
243 status = "disabled"; 256 status = "disabled";
244 }; 257 };
245 258
@@ -247,6 +260,8 @@
247 compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 260 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
248 reg = <0xe6c50000 0x100>; 261 reg = <0xe6c50000 0x100>;
249 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; 262 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
263 clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
264 clock-names = "sci_ick";
250 status = "disabled"; 265 status = "disabled";
251 }; 266 };
252 267
@@ -254,6 +269,8 @@
254 compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 269 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
255 reg = <0xe6c60000 0x100>; 270 reg = <0xe6c60000 0x100>;
256 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; 271 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
272 clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
273 clock-names = "sci_ick";
257 status = "disabled"; 274 status = "disabled";
258 }; 275 };
259 276
@@ -261,6 +278,8 @@
261 compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 278 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
262 reg = <0xe6c70000 0x100>; 279 reg = <0xe6c70000 0x100>;
263 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; 280 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
282 clock-names = "sci_ick";
264 status = "disabled"; 283 status = "disabled";
265 }; 284 };
266 285
@@ -268,6 +287,8 @@
268 compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 287 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
269 reg = <0xe6c80000 0x100>; 288 reg = <0xe6c80000 0x100>;
270 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; 289 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
291 clock-names = "sci_ick";
271 status = "disabled"; 292 status = "disabled";
272 }; 293 };
273 294
@@ -275,6 +296,8 @@
275 compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 296 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
276 reg = <0xe6cb0000 0x100>; 297 reg = <0xe6cb0000 0x100>;
277 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; 298 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
300 clock-names = "sci_ick";
278 status = "disabled"; 301 status = "disabled";
279 }; 302 };
280 303
@@ -282,6 +305,8 @@
282 compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 305 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
283 reg = <0xe6cc0000 0x100>; 306 reg = <0xe6cc0000 0x100>;
284 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; 307 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
309 clock-names = "sci_ick";
285 status = "disabled"; 310 status = "disabled";
286 }; 311 };
287 312
@@ -289,6 +314,8 @@
289 compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 314 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
290 reg = <0xe6cd0000 0x100>; 315 reg = <0xe6cd0000 0x100>;
291 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>; 316 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
317 clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
318 clock-names = "sci_ick";
292 status = "disabled"; 319 status = "disabled";
293 }; 320 };
294 321
@@ -296,6 +323,8 @@
296 compatible = "renesas,scifb-sh73a0", "renesas,scifb"; 323 compatible = "renesas,scifb-sh73a0", "renesas,scifb";
297 reg = <0xe6c30000 0x100>; 324 reg = <0xe6c30000 0x100>;
298 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 325 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
327 clock-names = "sci_ick";
299 status = "disabled"; 328 status = "disabled";
300 }; 329 };
301 330