aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorChien Tin Tung <chien.tin.tung@intel.com>2017-08-08 21:38:43 -0400
committerDoug Ledford <dledford@redhat.com>2017-08-16 11:27:44 -0400
commitf67ace2d8868d06710ceea1b10b124eead5040da (patch)
tree4ac7ede457cbb693c120d646ab6b84f54bb7c42d
parenta7d2e03928c1936004750c56faf7534c8534f875 (diff)
i40iw: Fix parsing of query/commit FPM buffers
Parsing of commit/query Host Memory Cache Function Private Memory is not skipping over reserved fields and incorrectly assigning those values into object's base/cnt/max_cnt fields. Skip over reserved fields and set correct values. Also correct memory alignment requirement for commit/query FPM buffers. Signed-off-by: Chien Tin Tung <chien.tin.tung@intel.com> Signed-off-by: Shiraz Saleem <shiraz.saleem@intel.com> Signed-off-by: Christopher N Bednarz <christopher.n.bednarz@intel.com> Signed-off-by: Henry Orosco <henry.orosco@intel.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
-rw-r--r--drivers/infiniband/hw/i40iw/i40iw_ctrl.c121
-rw-r--r--drivers/infiniband/hw/i40iw/i40iw_d.h4
2 files changed, 83 insertions, 42 deletions
diff --git a/drivers/infiniband/hw/i40iw/i40iw_ctrl.c b/drivers/infiniband/hw/i40iw/i40iw_ctrl.c
index 9ec1ae9a82c9..ef4a73cd1710 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_ctrl.c
+++ b/drivers/infiniband/hw/i40iw/i40iw_ctrl.c
@@ -130,20 +130,32 @@ static enum i40iw_status_code i40iw_sc_parse_fpm_commit_buf(
130 u64 base = 0; 130 u64 base = 0;
131 u32 i, j; 131 u32 i, j;
132 u32 k = 0; 132 u32 k = 0;
133 u32 low;
134 133
135 /* copy base values in obj_info */ 134 /* copy base values in obj_info */
136 for (i = I40IW_HMC_IW_QP, j = 0; 135 for (i = I40IW_HMC_IW_QP, j = 0; i <= I40IW_HMC_IW_PBLE; i++, j += 8) {
137 i <= I40IW_HMC_IW_PBLE; i++, j += 8) { 136 if ((i == I40IW_HMC_IW_SRQ) ||
137 (i == I40IW_HMC_IW_FSIMC) ||
138 (i == I40IW_HMC_IW_FSIAV)) {
139 info[i].base = 0;
140 info[i].cnt = 0;
141 continue;
142 }
138 get_64bit_val(buf, j, &temp); 143 get_64bit_val(buf, j, &temp);
139 info[i].base = RS_64_1(temp, 32) * 512; 144 info[i].base = RS_64_1(temp, 32) * 512;
140 if (info[i].base > base) { 145 if (info[i].base > base) {
141 base = info[i].base; 146 base = info[i].base;
142 k = i; 147 k = i;
143 } 148 }
144 low = (u32)(temp); 149 if (i == I40IW_HMC_IW_APBVT_ENTRY) {
145 if (low) 150 info[i].cnt = 1;
146 info[i].cnt = low; 151 continue;
152 }
153 if (i == I40IW_HMC_IW_QP)
154 info[i].cnt = (u32)RS_64(temp, I40IW_QUERY_FPM_MAX_QPS);
155 else if (i == I40IW_HMC_IW_CQ)
156 info[i].cnt = (u32)RS_64(temp, I40IW_QUERY_FPM_MAX_CQS);
157 else
158 info[i].cnt = (u32)(temp);
147 } 159 }
148 size = info[k].cnt * info[k].size + info[k].base; 160 size = info[k].cnt * info[k].size + info[k].base;
149 if (size & 0x1FFFFF) 161 if (size & 0x1FFFFF)
@@ -155,6 +167,31 @@ static enum i40iw_status_code i40iw_sc_parse_fpm_commit_buf(
155} 167}
156 168
157/** 169/**
170 * i40iw_sc_decode_fpm_query() - Decode a 64 bit value into max count and size
171 * @buf: ptr to fpm query buffer
172 * @buf_idx: index into buf
173 * @info: ptr to i40iw_hmc_obj_info struct
174 * @rsrc_idx: resource index into info
175 *
176 * Decode a 64 bit value from fpm query buffer into max count and size
177 */
178static u64 i40iw_sc_decode_fpm_query(u64 *buf,
179 u32 buf_idx,
180 struct i40iw_hmc_obj_info *obj_info,
181 u32 rsrc_idx)
182{
183 u64 temp;
184 u32 size;
185
186 get_64bit_val(buf, buf_idx, &temp);
187 obj_info[rsrc_idx].max_cnt = (u32)temp;
188 size = (u32)RS_64_1(temp, 32);
189 obj_info[rsrc_idx].size = LS_64_1(1, size);
190
191 return temp;
192}
193
194/**
158 * i40iw_sc_parse_fpm_query_buf() - parses fpm query buffer 195 * i40iw_sc_parse_fpm_query_buf() - parses fpm query buffer
159 * @buf: ptr to fpm query buffer 196 * @buf: ptr to fpm query buffer
160 * @info: ptr to i40iw_hmc_obj_info struct 197 * @info: ptr to i40iw_hmc_obj_info struct
@@ -168,9 +205,9 @@ static enum i40iw_status_code i40iw_sc_parse_fpm_query_buf(
168 struct i40iw_hmc_info *hmc_info, 205 struct i40iw_hmc_info *hmc_info,
169 struct i40iw_hmc_fpm_misc *hmc_fpm_misc) 206 struct i40iw_hmc_fpm_misc *hmc_fpm_misc)
170{ 207{
171 u64 temp;
172 struct i40iw_hmc_obj_info *obj_info; 208 struct i40iw_hmc_obj_info *obj_info;
173 u32 i, j, size; 209 u64 temp;
210 u32 size;
174 u16 max_pe_sds; 211 u16 max_pe_sds;
175 212
176 obj_info = hmc_info->hmc_obj; 213 obj_info = hmc_info->hmc_obj;
@@ -185,41 +222,52 @@ static enum i40iw_status_code i40iw_sc_parse_fpm_query_buf(
185 hmc_fpm_misc->max_sds = max_pe_sds; 222 hmc_fpm_misc->max_sds = max_pe_sds;
186 hmc_info->sd_table.sd_cnt = max_pe_sds + hmc_info->first_sd_index; 223 hmc_info->sd_table.sd_cnt = max_pe_sds + hmc_info->first_sd_index;
187 224
188 for (i = I40IW_HMC_IW_QP, j = 8; 225 get_64bit_val(buf, 8, &temp);
189 i <= I40IW_HMC_IW_ARP; i++, j += 8) { 226 obj_info[I40IW_HMC_IW_QP].max_cnt = (u32)RS_64(temp, I40IW_QUERY_FPM_MAX_QPS);
190 get_64bit_val(buf, j, &temp); 227 size = (u32)RS_64_1(temp, 32);
191 if (i == I40IW_HMC_IW_QP) 228 obj_info[I40IW_HMC_IW_QP].size = LS_64_1(1, size);
192 obj_info[i].max_cnt = (u32)RS_64(temp, I40IW_QUERY_FPM_MAX_QPS);
193 else if (i == I40IW_HMC_IW_CQ)
194 obj_info[i].max_cnt = (u32)RS_64(temp, I40IW_QUERY_FPM_MAX_CQS);
195 else
196 obj_info[i].max_cnt = (u32)temp;
197 229
198 size = (u32)RS_64_1(temp, 32); 230 get_64bit_val(buf, 16, &temp);
199 obj_info[i].size = ((u64)1 << size); 231 obj_info[I40IW_HMC_IW_CQ].max_cnt = (u32)RS_64(temp, I40IW_QUERY_FPM_MAX_CQS);
200 } 232 size = (u32)RS_64_1(temp, 32);
201 for (i = I40IW_HMC_IW_MR, j = 48; 233 obj_info[I40IW_HMC_IW_CQ].size = LS_64_1(1, size);
202 i <= I40IW_HMC_IW_PBLE; i++, j += 8) { 234
203 get_64bit_val(buf, j, &temp); 235 i40iw_sc_decode_fpm_query(buf, 32, obj_info, I40IW_HMC_IW_HTE);
204 obj_info[i].max_cnt = (u32)temp; 236 i40iw_sc_decode_fpm_query(buf, 40, obj_info, I40IW_HMC_IW_ARP);
205 size = (u32)RS_64_1(temp, 32); 237
206 obj_info[i].size = LS_64_1(1, size); 238 obj_info[I40IW_HMC_IW_APBVT_ENTRY].size = 8192;
207 } 239 obj_info[I40IW_HMC_IW_APBVT_ENTRY].max_cnt = 1;
240
241 i40iw_sc_decode_fpm_query(buf, 48, obj_info, I40IW_HMC_IW_MR);
242 i40iw_sc_decode_fpm_query(buf, 56, obj_info, I40IW_HMC_IW_XF);
208 243
209 get_64bit_val(buf, 120, &temp);
210 hmc_fpm_misc->max_ceqs = (u8)RS_64(temp, I40IW_QUERY_FPM_MAX_CEQS);
211 get_64bit_val(buf, 120, &temp);
212 hmc_fpm_misc->ht_multiplier = RS_64(temp, I40IW_QUERY_FPM_HTMULTIPLIER);
213 get_64bit_val(buf, 120, &temp);
214 hmc_fpm_misc->timer_bucket = RS_64(temp, I40IW_QUERY_FPM_TIMERBUCKET);
215 get_64bit_val(buf, 64, &temp); 244 get_64bit_val(buf, 64, &temp);
245 obj_info[I40IW_HMC_IW_XFFL].max_cnt = (u32)temp;
246 obj_info[I40IW_HMC_IW_XFFL].size = 4;
216 hmc_fpm_misc->xf_block_size = RS_64(temp, I40IW_QUERY_FPM_XFBLOCKSIZE); 247 hmc_fpm_misc->xf_block_size = RS_64(temp, I40IW_QUERY_FPM_XFBLOCKSIZE);
217 if (!hmc_fpm_misc->xf_block_size) 248 if (!hmc_fpm_misc->xf_block_size)
218 return I40IW_ERR_INVALID_SIZE; 249 return I40IW_ERR_INVALID_SIZE;
250
251 i40iw_sc_decode_fpm_query(buf, 72, obj_info, I40IW_HMC_IW_Q1);
252
219 get_64bit_val(buf, 80, &temp); 253 get_64bit_val(buf, 80, &temp);
254 obj_info[I40IW_HMC_IW_Q1FL].max_cnt = (u32)temp;
255 obj_info[I40IW_HMC_IW_Q1FL].size = 4;
220 hmc_fpm_misc->q1_block_size = RS_64(temp, I40IW_QUERY_FPM_Q1BLOCKSIZE); 256 hmc_fpm_misc->q1_block_size = RS_64(temp, I40IW_QUERY_FPM_Q1BLOCKSIZE);
221 if (!hmc_fpm_misc->q1_block_size) 257 if (!hmc_fpm_misc->q1_block_size)
222 return I40IW_ERR_INVALID_SIZE; 258 return I40IW_ERR_INVALID_SIZE;
259
260 i40iw_sc_decode_fpm_query(buf, 88, obj_info, I40IW_HMC_IW_TIMER);
261
262 get_64bit_val(buf, 112, &temp);
263 obj_info[I40IW_HMC_IW_PBLE].max_cnt = (u32)temp;
264 obj_info[I40IW_HMC_IW_PBLE].size = 8;
265
266 get_64bit_val(buf, 120, &temp);
267 hmc_fpm_misc->max_ceqs = (u8)RS_64(temp, I40IW_QUERY_FPM_MAX_CEQS);
268 hmc_fpm_misc->ht_multiplier = RS_64(temp, I40IW_QUERY_FPM_HTMULTIPLIER);
269 hmc_fpm_misc->timer_bucket = RS_64(temp, I40IW_QUERY_FPM_TIMERBUCKET);
270
223 return 0; 271 return 0;
224} 272}
225 273
@@ -3392,13 +3440,6 @@ enum i40iw_status_code i40iw_sc_init_iw_hmc(struct i40iw_sc_dev *dev, u8 hmc_fn_
3392 hmc_info->sd_table.sd_entry = virt_mem.va; 3440 hmc_info->sd_table.sd_entry = virt_mem.va;
3393 } 3441 }
3394 3442
3395 /* fill size of objects which are fixed */
3396 hmc_info->hmc_obj[I40IW_HMC_IW_XFFL].size = 4;
3397 hmc_info->hmc_obj[I40IW_HMC_IW_Q1FL].size = 4;
3398 hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].size = 8;
3399 hmc_info->hmc_obj[I40IW_HMC_IW_APBVT_ENTRY].size = 8192;
3400 hmc_info->hmc_obj[I40IW_HMC_IW_APBVT_ENTRY].max_cnt = 1;
3401
3402 return ret_code; 3443 return ret_code;
3403} 3444}
3404 3445
diff --git a/drivers/infiniband/hw/i40iw/i40iw_d.h b/drivers/infiniband/hw/i40iw/i40iw_d.h
index a39ac12b6a7e..2ebaadbed379 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_d.h
+++ b/drivers/infiniband/hw/i40iw/i40iw_d.h
@@ -1507,8 +1507,8 @@ enum {
1507 I40IW_CQ0_ALIGNMENT_MASK = (256 - 1), 1507 I40IW_CQ0_ALIGNMENT_MASK = (256 - 1),
1508 I40IW_HOST_CTX_ALIGNMENT_MASK = (4 - 1), 1508 I40IW_HOST_CTX_ALIGNMENT_MASK = (4 - 1),
1509 I40IW_SHADOWAREA_MASK = (128 - 1), 1509 I40IW_SHADOWAREA_MASK = (128 - 1),
1510 I40IW_FPM_QUERY_BUF_ALIGNMENT_MASK = 0, 1510 I40IW_FPM_QUERY_BUF_ALIGNMENT_MASK = (4 - 1),
1511 I40IW_FPM_COMMIT_BUF_ALIGNMENT_MASK = 0 1511 I40IW_FPM_COMMIT_BUF_ALIGNMENT_MASK = (4 - 1)
1512}; 1512};
1513 1513
1514enum i40iw_alignment { 1514enum i40iw_alignment {