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authorArnd Bergmann <arnd@arndb.de>2016-09-21 16:37:18 -0400
committerArnd Bergmann <arnd@arndb.de>2016-09-21 16:37:18 -0400
commitf5f8aaf98d886165bcc4310017633bb630712d5f (patch)
treef000fe502768ceeb587db62fcc6b81b4d712a83d
parentc55b2d989a5b2ef85ad28229484279ac7c2c412a (diff)
parentc336dc7dac0747f6a4901bcd5a497e1b3fb265d7 (diff)
Merge tag 'mvebu-drivers-4.9-1' of git://git.infradead.org/linux-mvebu into next/drivers
Pull "mvebu drivers for 4.9 (part 1)" from Gregory CLEMENT: - Add pinctrl and clk support for the Orion5x SoC mv88f5181 variant * tag 'mvebu-drivers-4.9-1' of git://git.infradead.org/linux-mvebu: pinctrl: mvebu: orion5x: Generalise mv88f5181l support for 88f5181 clk: mvebu: Add clk support for the orion5x SoC mv88f5181
-rw-r--r--Documentation/devicetree/bindings/clock/mvebu-core-clock.txt1
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt4
-rw-r--r--drivers/clk/mvebu/orion.c70
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-orion.c23
4 files changed, 86 insertions, 12 deletions
diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
index 670c2af3e931..eb985a633d59 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
@@ -52,6 +52,7 @@ Required properties:
52 "marvell,dove-core-clock" - for Dove SoC core clocks 52 "marvell,dove-core-clock" - for Dove SoC core clocks
53 "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180) 53 "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
54 "marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC 54 "marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
55 "marvell,mv88f5181-core-clock" - for Orion MV88F5181 SoC
55 "marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC 56 "marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC
56 "marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC 57 "marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC
57 "marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC 58 "marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
index 27570a3a1741..ec8aa3c6936b 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
@@ -4,7 +4,9 @@ Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
4part and usage. 4part and usage.
5 5
6Required properties: 6Required properties:
7- compatible: "marvell,88f5181l-pinctrl", "marvell,88f5182-pinctrl", 7- compatible: "marvell,88f5181-pinctrl",
8 "marvell,88f5181l-pinctrl",
9 "marvell,88f5182-pinctrl",
8 "marvell,88f5281-pinctrl" 10 "marvell,88f5281-pinctrl"
9 11
10- reg: two register areas, the first one describing the first two 12- reg: two register areas, the first one describing the first two
diff --git a/drivers/clk/mvebu/orion.c b/drivers/clk/mvebu/orion.c
index fd129566c1ce..a6e5bee23385 100644
--- a/drivers/clk/mvebu/orion.c
+++ b/drivers/clk/mvebu/orion.c
@@ -21,6 +21,76 @@ static const struct coreclk_ratio orion_coreclk_ratios[] __initconst = {
21}; 21};
22 22
23/* 23/*
24 * Orion 5181
25 */
26
27#define SAR_MV88F5181_TCLK_FREQ 8
28#define SAR_MV88F5181_TCLK_FREQ_MASK 0x3
29
30static u32 __init mv88f5181_get_tclk_freq(void __iomem *sar)
31{
32 u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) &
33 SAR_MV88F5181_TCLK_FREQ_MASK;
34 if (opt == 0)
35 return 133333333;
36 else if (opt == 1)
37 return 150000000;
38 else if (opt == 2)
39 return 166666667;
40 else
41 return 0;
42}
43
44#define SAR_MV88F5181_CPU_FREQ 4
45#define SAR_MV88F5181_CPU_FREQ_MASK 0xf
46
47static u32 __init mv88f5181_get_cpu_freq(void __iomem *sar)
48{
49 u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
50 SAR_MV88F5181_CPU_FREQ_MASK;
51 if (opt == 0)
52 return 333333333;
53 else if (opt == 1 || opt == 2)
54 return 400000000;
55 else if (opt == 3)
56 return 500000000;
57 else
58 return 0;
59}
60
61static void __init mv88f5181_get_clk_ratio(void __iomem *sar, int id,
62 int *mult, int *div)
63{
64 u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
65 SAR_MV88F5181_CPU_FREQ_MASK;
66 if (opt == 0 || opt == 1) {
67 *mult = 1;
68 *div = 2;
69 } else if (opt == 2 || opt == 3) {
70 *mult = 1;
71 *div = 3;
72 } else {
73 *mult = 0;
74 *div = 1;
75 }
76}
77
78static const struct coreclk_soc_desc mv88f5181_coreclks = {
79 .get_tclk_freq = mv88f5181_get_tclk_freq,
80 .get_cpu_freq = mv88f5181_get_cpu_freq,
81 .get_clk_ratio = mv88f5181_get_clk_ratio,
82 .ratios = orion_coreclk_ratios,
83 .num_ratios = ARRAY_SIZE(orion_coreclk_ratios),
84};
85
86static void __init mv88f5181_clk_init(struct device_node *np)
87{
88 return mvebu_coreclk_setup(np, &mv88f5181_coreclks);
89}
90
91CLK_OF_DECLARE(mv88f5181_clk, "marvell,mv88f5181-core-clock", mv88f5181_clk_init);
92
93/*
24 * Orion 5182 94 * Orion 5182
25 */ 95 */
26 96
diff --git a/drivers/pinctrl/mvebu/pinctrl-orion.c b/drivers/pinctrl/mvebu/pinctrl-orion.c
index 345c3df669a0..84e144167b44 100644
--- a/drivers/pinctrl/mvebu/pinctrl-orion.c
+++ b/drivers/pinctrl/mvebu/pinctrl-orion.c
@@ -64,11 +64,11 @@ static int orion_mpp_ctrl_set(unsigned pid, unsigned long config)
64 return 0; 64 return 0;
65} 65}
66 66
67#define V(f5181l, f5182, f5281) \ 67#define V(f5181, f5182, f5281) \
68 ((f5181l << 0) | (f5182 << 1) | (f5281 << 2)) 68 ((f5181 << 0) | (f5182 << 1) | (f5281 << 2))
69 69
70enum orion_variant { 70enum orion_variant {
71 V_5181L = V(1, 0, 0), 71 V_5181 = V(1, 0, 0),
72 V_5182 = V(0, 1, 0), 72 V_5182 = V(0, 1, 0),
73 V_5281 = V(0, 0, 1), 73 V_5281 = V(0, 0, 1),
74 V_ALL = V(1, 1, 1), 74 V_ALL = V(1, 1, 1),
@@ -103,13 +103,13 @@ static struct mvebu_mpp_mode orion_mpp_modes[] = {
103 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL), 103 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
104 MPP_VAR_FUNCTION(0x2, "pci", "req5", V_ALL), 104 MPP_VAR_FUNCTION(0x2, "pci", "req5", V_ALL),
105 MPP_VAR_FUNCTION(0x4, "nand", "re0", V_5182 | V_5281), 105 MPP_VAR_FUNCTION(0x4, "nand", "re0", V_5182 | V_5281),
106 MPP_VAR_FUNCTION(0x5, "pci-1", "clk", V_5181L), 106 MPP_VAR_FUNCTION(0x5, "pci-1", "clk", V_5181),
107 MPP_VAR_FUNCTION(0x5, "sata0", "act", V_5182)), 107 MPP_VAR_FUNCTION(0x5, "sata0", "act", V_5182)),
108 MPP_MODE(7, 108 MPP_MODE(7,
109 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL), 109 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
110 MPP_VAR_FUNCTION(0x2, "pci", "gnt5", V_ALL), 110 MPP_VAR_FUNCTION(0x2, "pci", "gnt5", V_ALL),
111 MPP_VAR_FUNCTION(0x4, "nand", "we0", V_5182 | V_5281), 111 MPP_VAR_FUNCTION(0x4, "nand", "we0", V_5182 | V_5281),
112 MPP_VAR_FUNCTION(0x5, "pci-1", "clk", V_5181L), 112 MPP_VAR_FUNCTION(0x5, "pci-1", "clk", V_5181),
113 MPP_VAR_FUNCTION(0x5, "sata1", "act", V_5182)), 113 MPP_VAR_FUNCTION(0x5, "sata1", "act", V_5182)),
114 MPP_MODE(8, 114 MPP_MODE(8,
115 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL), 115 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
@@ -165,7 +165,7 @@ static struct mvebu_mpp_ctrl orion_mpp_controls[] = {
165 MPP_FUNC_CTRL(0, 19, NULL, orion_mpp_ctrl), 165 MPP_FUNC_CTRL(0, 19, NULL, orion_mpp_ctrl),
166}; 166};
167 167
168static struct pinctrl_gpio_range mv88f5181l_gpio_ranges[] = { 168static struct pinctrl_gpio_range mv88f5181_gpio_ranges[] = {
169 MPP_GPIO_RANGE(0, 0, 0, 16), 169 MPP_GPIO_RANGE(0, 0, 0, 16),
170}; 170};
171 171
@@ -177,14 +177,14 @@ static struct pinctrl_gpio_range mv88f5281_gpio_ranges[] = {
177 MPP_GPIO_RANGE(0, 0, 0, 16), 177 MPP_GPIO_RANGE(0, 0, 0, 16),
178}; 178};
179 179
180static struct mvebu_pinctrl_soc_info mv88f5181l_info = { 180static struct mvebu_pinctrl_soc_info mv88f5181_info = {
181 .variant = V_5181L, 181 .variant = V_5181,
182 .controls = orion_mpp_controls, 182 .controls = orion_mpp_controls,
183 .ncontrols = ARRAY_SIZE(orion_mpp_controls), 183 .ncontrols = ARRAY_SIZE(orion_mpp_controls),
184 .modes = orion_mpp_modes, 184 .modes = orion_mpp_modes,
185 .nmodes = ARRAY_SIZE(orion_mpp_modes), 185 .nmodes = ARRAY_SIZE(orion_mpp_modes),
186 .gpioranges = mv88f5181l_gpio_ranges, 186 .gpioranges = mv88f5181_gpio_ranges,
187 .ngpioranges = ARRAY_SIZE(mv88f5181l_gpio_ranges), 187 .ngpioranges = ARRAY_SIZE(mv88f5181_gpio_ranges),
188}; 188};
189 189
190static struct mvebu_pinctrl_soc_info mv88f5182_info = { 190static struct mvebu_pinctrl_soc_info mv88f5182_info = {
@@ -212,7 +212,8 @@ static struct mvebu_pinctrl_soc_info mv88f5281_info = {
212 * muxing, they are identical. 212 * muxing, they are identical.
213 */ 213 */
214static const struct of_device_id orion_pinctrl_of_match[] = { 214static const struct of_device_id orion_pinctrl_of_match[] = {
215 { .compatible = "marvell,88f5181l-pinctrl", .data = &mv88f5181l_info }, 215 { .compatible = "marvell,88f5181-pinctrl", .data = &mv88f5181_info },
216 { .compatible = "marvell,88f5181l-pinctrl", .data = &mv88f5181_info },
216 { .compatible = "marvell,88f5182-pinctrl", .data = &mv88f5182_info }, 217 { .compatible = "marvell,88f5182-pinctrl", .data = &mv88f5182_info },
217 { .compatible = "marvell,88f5281-pinctrl", .data = &mv88f5281_info }, 218 { .compatible = "marvell,88f5281-pinctrl", .data = &mv88f5281_info },
218 { } 219 { }