drm/amd/display: fix warning on raven hotplug

[Why]
Hotplug on raven results in REG_WAIT_TIMEOUT warning
due to failing attempt to lock disabled otg for the hubp
interdependent pipes programming.

[How]
Don't setup pipe interdependencies for disabled otg.
Also removed the unnecessary duplicate logic checks.

Signed-off-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 6 insertions, 13 deletions

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 91e015e14355..58a12ddf12f3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2355,29 +2355,22 @@ static void dcn10_apply_ctx_for_surface(
                         top_pipe_to_program->plane_state->update_flags.bits.full_update)
                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-
+                        tg = pipe_ctx->stream_res.tg;
                         /* Skip inactive pipes and ones already updated */
                         if (!pipe_ctx->stream || pipe_ctx->stream == stream
-                                        || !pipe_ctx->plane_state)
+                                        || !pipe_ctx->plane_state
+                                        || !tg->funcs->is_tg_enabled(tg))
                                 continue;
 
-                        pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
+                        tg->funcs->lock(tg);
 
                         pipe_ctx->plane_res.hubp->funcs->hubp_setup_interdependent(
                                 pipe_ctx->plane_res.hubp,
                                 &pipe_ctx->dlg_regs,
                                 &pipe_ctx->ttu_regs);
-                }
-
-        for (i = 0; i < dc->res_pool->pipe_count; i++) {
-                struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 
-                if (!pipe_ctx->stream || pipe_ctx->stream == stream
-                                || !pipe_ctx->plane_state)
-                        continue;
-
-                dcn10_pipe_control_lock(dc, pipe_ctx, false);
-        }
+                        tg->funcs->unlock(tg);
+                }
 
         if (num_planes == 0)
                 false_optc_underflow_wa(dc, stream, tg);