Merge branch 'clockevents/4.13' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core

Pull clockevents updates from Daniel Lezcano:

 - Made the tcb_clksrc endianess agnostic as the AVR32 support is gone
   (Alexandre Belloni)

 - Unmap io region on failure at init time in the fsl_ftm_timer (Arvind Yadav)

 - Fix a bad return value for the mips-gic-timer at init time (Christophe
   Jaillet)

 - Fix invalid iomap check and switch the sun4i timer to use the common timer
   init routine (Daniel Lezcano)

6 files changed, 117 insertions, 128 deletions

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 4be163bca8a8..88818a43d6e9 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -108,6 +108,7 @@ config SUN4I_TIMER
         depends on GENERIC_CLOCKEVENTS
         depends on HAS_IOMEM
         select CLKSRC_MMIO
+        select TIMER_OF
         help
           Enables support for the Sun4i timer.
 
diff --git a/drivers/clocksource/fsl_ftm_timer.c b/drivers/clocksource/fsl_ftm_timer.c
index 3121e2d96c91..3ee7e6fea621 100644
--- a/drivers/clocksource/fsl_ftm_timer.c
+++ b/drivers/clocksource/fsl_ftm_timer.c
@@ -329,13 +329,13 @@ static int __init ftm_timer_init(struct device_node *np)
         priv->clkevt_base = of_iomap(np, 0);
         if (!priv->clkevt_base) {
                 pr_err("ftm: unable to map event timer registers\n");
-                goto err;
+                goto err_clkevt;
         }
 
         priv->clksrc_base = of_iomap(np, 1);
         if (!priv->clksrc_base) {
                 pr_err("ftm: unable to map source timer registers\n");
-                goto err;
+                goto err_clksrc;
         }
 
         ret = -EINVAL;
@@ -366,6 +366,10 @@ static int __init ftm_timer_init(struct device_node *np)
         return 0;
 
 err:
+        iounmap(priv->clksrc_base);
+err_clksrc:
+        iounmap(priv->clkevt_base);
+err_clkevt:
         kfree(priv);
         return ret;
 }
diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c
index e31e08326024..17b861ea2626 100644
--- a/drivers/clocksource/mips-gic-timer.c
+++ b/drivers/clocksource/mips-gic-timer.c
@@ -167,10 +167,11 @@ static int __init gic_clocksource_of_init(struct device_node *node)
 
         clk = of_clk_get(node, 0);
         if (!IS_ERR(clk)) {
-                if (clk_prepare_enable(clk) < 0) {
+                ret = clk_prepare_enable(clk);
+                if (ret < 0) {
                         pr_err("GIC failed to enable clock\n");
                         clk_put(clk);
-                        return PTR_ERR(clk);
+                        return ret;
                 }
 
                 gic_frequency = clk_get_rate(clk);
diff --git a/drivers/clocksource/sun4i_timer.c b/drivers/clocksource/sun4i_timer.c
index 3e4bc64ff176..6e0180aaf784 100644
--- a/drivers/clocksource/sun4i_timer.c
+++ b/drivers/clocksource/sun4i_timer.c
@@ -24,6 +24,8 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 
+#include "timer-of.h"
+
 #define TIMER_IRQ_EN_REG        0x00
 #define TIMER_IRQ_EN(val)               BIT(val)
 #define TIMER_IRQ_ST_REG        0x04
@@ -39,38 +41,37 @@
 
 #define TIMER_SYNC_TICKS        3
 
-static void __iomem *timer_base;
-static u32 ticks_per_jiffy;
-
 /*
  * When we disable a timer, we need to wait at least for 2 cycles of
  * the timer source clock. We will use for that the clocksource timer
  * that is already setup and runs at the same frequency than the other
  * timers, and we never will be disabled.
  */
-static void sun4i_clkevt_sync(void)
+static void sun4i_clkevt_sync(void __iomem *base)
 {
-        u32 old = readl(timer_base + TIMER_CNTVAL_REG(1));
+        u32 old = readl(base + TIMER_CNTVAL_REG(1));
 
-        while ((old - readl(timer_base + TIMER_CNTVAL_REG(1))) < TIMER_SYNC_TICKS)
+        while ((old - readl(base + TIMER_CNTVAL_REG(1))) < TIMER_SYNC_TICKS)
                 cpu_relax();
 }
 
-static void sun4i_clkevt_time_stop(u8 timer)
+static void sun4i_clkevt_time_stop(void __iomem *base, u8 timer)
 {
-        u32 val = readl(timer_base + TIMER_CTL_REG(timer));
-        writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
-        sun4i_clkevt_sync();
+        u32 val = readl(base + TIMER_CTL_REG(timer));
+        writel(val & ~TIMER_CTL_ENABLE, base + TIMER_CTL_REG(timer));
+        sun4i_clkevt_sync(base);
 }
 
-static void sun4i_clkevt_time_setup(u8 timer, unsigned long delay)
+static void sun4i_clkevt_time_setup(void __iomem *base, u8 timer,
+                                    unsigned long delay)
 {
-        writel(delay, timer_base + TIMER_INTVAL_REG(timer));
+        writel(delay, base + TIMER_INTVAL_REG(timer));
 }
 
-static void sun4i_clkevt_time_start(u8 timer, bool periodic)
+static void sun4i_clkevt_time_start(void __iomem *base, u8 timer,
+                                    bool periodic)
 {
-        u32 val = readl(timer_base + TIMER_CTL_REG(timer));
+        u32 val = readl(base + TIMER_CTL_REG(timer));
 
         if (periodic)
                 val &= ~TIMER_CTL_ONESHOT;
@@ -78,115 +79,106 @@ static void sun4i_clkevt_time_start(u8 timer, bool periodic)
                 val |= TIMER_CTL_ONESHOT;
 
         writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
-               timer_base + TIMER_CTL_REG(timer));
+               base + TIMER_CTL_REG(timer));
 }
 
 static int sun4i_clkevt_shutdown(struct clock_event_device *evt)
 {
-        sun4i_clkevt_time_stop(0);
+        struct timer_of *to = to_timer_of(evt);
+
+        sun4i_clkevt_time_stop(timer_of_base(to), 0);
+
         return 0;
 }
 
 static int sun4i_clkevt_set_oneshot(struct clock_event_device *evt)
 {
-        sun4i_clkevt_time_stop(0);
-        sun4i_clkevt_time_start(0, false);
+        struct timer_of *to = to_timer_of(evt);
+
+        sun4i_clkevt_time_stop(timer_of_base(to), 0);
+        sun4i_clkevt_time_start(timer_of_base(to), 0, false);
+
         return 0;
 }
 
 static int sun4i_clkevt_set_periodic(struct clock_event_device *evt)
 {
-        sun4i_clkevt_time_stop(0);
-        sun4i_clkevt_time_setup(0, ticks_per_jiffy);
-        sun4i_clkevt_time_start(0, true);
+        struct timer_of *to = to_timer_of(evt);
+
+        sun4i_clkevt_time_stop(timer_of_base(to), 0);
+        sun4i_clkevt_time_setup(timer_of_base(to), 0, timer_of_period(to));
+        sun4i_clkevt_time_start(timer_of_base(to), 0, true);
+
         return 0;
 }
 
 static int sun4i_clkevt_next_event(unsigned long evt,
-                                   struct clock_event_device *unused)
+                                   struct clock_event_device *clkevt)
 {
-        sun4i_clkevt_time_stop(0);
-        sun4i_clkevt_time_setup(0, evt - TIMER_SYNC_TICKS);
-        sun4i_clkevt_time_start(0, false);
+        struct timer_of *to = to_timer_of(clkevt);
+
+        sun4i_clkevt_time_stop(timer_of_base(to), 0);
+        sun4i_clkevt_time_setup(timer_of_base(to), 0, evt - TIMER_SYNC_TICKS);
+        sun4i_clkevt_time_start(timer_of_base(to), 0, false);
 
         return 0;
 }
 
-static struct clock_event_device sun4i_clockevent = {
-        .name = "sun4i_tick",
-        .rating = 350,
-        .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-        .set_state_shutdown = sun4i_clkevt_shutdown,
-        .set_state_periodic = sun4i_clkevt_set_periodic,
-        .set_state_oneshot = sun4i_clkevt_set_oneshot,
-        .tick_resume = sun4i_clkevt_shutdown,
-        .set_next_event = sun4i_clkevt_next_event,
-};
-
-static void sun4i_timer_clear_interrupt(void)
+static void sun4i_timer_clear_interrupt(void __iomem *base)
 {
-        writel(TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_ST_REG);
+        writel(TIMER_IRQ_EN(0), base + TIMER_IRQ_ST_REG);
 }
 
 static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
 {
         struct clock_event_device *evt = (struct clock_event_device *)dev_id;
+        struct timer_of *to = to_timer_of(evt);
 
-        sun4i_timer_clear_interrupt();
+        sun4i_timer_clear_interrupt(timer_of_base(to));
         evt->event_handler(evt);
 
         return IRQ_HANDLED;
 }
 
-static struct irqaction sun4i_timer_irq = {
-        .name = "sun4i_timer0",
-        .flags = IRQF_TIMER | IRQF_IRQPOLL,
-        .handler = sun4i_timer_interrupt,
-        .dev_id = &sun4i_clockevent,
+static struct timer_of to = {
+        .flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE,
+
+        .clkevt = {
+                .name = "sun4i_tick",
+                .rating = 350,
+                .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+                .set_state_shutdown = sun4i_clkevt_shutdown,
+                .set_state_periodic = sun4i_clkevt_set_periodic,
+                .set_state_oneshot = sun4i_clkevt_set_oneshot,
+                .tick_resume = sun4i_clkevt_shutdown,
+                .set_next_event = sun4i_clkevt_next_event,
+                .cpumask = cpu_possible_mask,
+        },
+
+        .of_irq = {
+                .handler = sun4i_timer_interrupt,
+                .flags = IRQF_TIMER | IRQF_IRQPOLL,
+        },
 };
 
 static u64 notrace sun4i_timer_sched_read(void)
 {
-        return ~readl(timer_base + TIMER_CNTVAL_REG(1));
+        return ~readl(timer_of_base(&to) + TIMER_CNTVAL_REG(1));
 }
 
 static int __init sun4i_timer_init(struct device_node *node)
 {
-        unsigned long rate = 0;
-        struct clk *clk;
-        int ret, irq;
+        int ret;
         u32 val;
 
-        timer_base = of_iomap(node, 0);
-        if (!timer_base) {
-                pr_crit("Can't map registers\n");
-                return -ENXIO;
-        }
-
-        irq = irq_of_parse_and_map(node, 0);
-        if (irq <= 0) {
-                pr_crit("Can't parse IRQ\n");
-                return -EINVAL;
-        }
-
-        clk = of_clk_get(node, 0);
-        if (IS_ERR(clk)) {
-                pr_crit("Can't get timer clock\n");
-                return PTR_ERR(clk);
-        }
-
-        ret = clk_prepare_enable(clk);
-        if (ret) {
-                pr_err("Failed to prepare clock\n");
+        ret = timer_of_init(node, &to);
+        if (ret)
                 return ret;
-        }
-
-        rate = clk_get_rate(clk);
 
-        writel(~0, timer_base + TIMER_INTVAL_REG(1));
+        writel(~0, timer_of_base(&to) + TIMER_INTVAL_REG(1));
         writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD |
                TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
-               timer_base + TIMER_CTL_REG(1));
+               timer_of_base(&to) + TIMER_CTL_REG(1));
 
         /*
          * sched_clock_register does not have priorities, and on sun6i and
@@ -195,41 +187,32 @@ static int __init sun4i_timer_init(struct device_node *node)
         if (of_machine_is_compatible("allwinner,sun4i-a10") ||
             of_machine_is_compatible("allwinner,sun5i-a13") ||
             of_machine_is_compatible("allwinner,sun5i-a10s"))
-                sched_clock_register(sun4i_timer_sched_read, 32, rate);
+                sched_clock_register(sun4i_timer_sched_read, 32,
+                                     timer_of_rate(&to));
 
-        ret = clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
-                                    rate, 350, 32, clocksource_mmio_readl_down);
+        ret = clocksource_mmio_init(timer_of_base(&to) + TIMER_CNTVAL_REG(1),
+                                    node->name, timer_of_rate(&to), 350, 32,
+                                    clocksource_mmio_readl_down);
         if (ret) {
                 pr_err("Failed to register clocksource\n");
                 return ret;
         }
 
-        ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
-
         writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
-               timer_base + TIMER_CTL_REG(0));
+               timer_of_base(&to) + TIMER_CTL_REG(0));
 
         /* Make sure timer is stopped before playing with interrupts */
-        sun4i_clkevt_time_stop(0);
+        sun4i_clkevt_time_stop(timer_of_base(&to), 0);
 
         /* clear timer0 interrupt */
-        sun4i_timer_clear_interrupt();
-
-        sun4i_clockevent.cpumask = cpu_possible_mask;
-        sun4i_clockevent.irq = irq;
+        sun4i_timer_clear_interrupt(timer_of_base(&to));
 
-        clockevents_config_and_register(&sun4i_clockevent, rate,
+        clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
                                         TIMER_SYNC_TICKS, 0xffffffff);
 
-        ret = setup_irq(irq, &sun4i_timer_irq);
-        if (ret) {
-                pr_err("failed to setup irq %d\n", irq);
-                return ret;
-        }
-
         /* Enable timer0 interrupt */
-        val = readl(timer_base + TIMER_IRQ_EN_REG);
-        writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
+        val = readl(timer_of_base(&to) + TIMER_IRQ_EN_REG);
+        writel(val | TIMER_IRQ_EN(0), timer_of_base(&to) + TIMER_IRQ_EN_REG);
 
         return ret;
 }
diff --git a/drivers/clocksource/tcb_clksrc.c b/drivers/clocksource/tcb_clksrc.c
index 828729c70a0c..59e8aee0ec16 100644
--- a/drivers/clocksource/tcb_clksrc.c
+++ b/drivers/clocksource/tcb_clksrc.c
@@ -57,9 +57,9 @@ static u64 tc_get_cycles(struct clocksource *cs)
 
         raw_local_irq_save(flags);
         do {
-                upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV));
-                lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
-        } while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)));
+                upper = readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV));
+                lower = readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV));
+        } while (upper != readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV)));
 
         raw_local_irq_restore(flags);
         return (upper << 16) | lower;
@@ -67,7 +67,7 @@ static u64 tc_get_cycles(struct clocksource *cs)
 
 static u64 tc_get_cycles32(struct clocksource *cs)
 {
-        return __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
+        return readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV));
 }
 
 void tc_clksrc_suspend(struct clocksource *cs)
@@ -147,8 +147,8 @@ static int tc_shutdown(struct clock_event_device *d)
         struct tc_clkevt_device *tcd = to_tc_clkevt(d);
         void __iomem            *regs = tcd->regs;
 
-        __raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
-        __raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
+        writel(0xff, regs + ATMEL_TC_REG(2, IDR));
+        writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
         if (!clockevent_state_detached(d))
                 clk_disable(tcd->clk);
 
@@ -166,9 +166,9 @@ static int tc_set_oneshot(struct clock_event_device *d)
         clk_enable(tcd->clk);
 
         /* slow clock, count up to RC, then irq and stop */
-        __raw_writel(timer_clock | ATMEL_TC_CPCSTOP | ATMEL_TC_WAVE |
+        writel(timer_clock | ATMEL_TC_CPCSTOP | ATMEL_TC_WAVE |
                      ATMEL_TC_WAVESEL_UP_AUTO, regs + ATMEL_TC_REG(2, CMR));
-        __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
+        writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
 
         /* set_next_event() configures and starts the timer */
         return 0;
@@ -188,25 +188,25 @@ static int tc_set_periodic(struct clock_event_device *d)
         clk_enable(tcd->clk);
 
         /* slow clock, count up to RC, then irq and restart */
-        __raw_writel(timer_clock | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
+        writel(timer_clock | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
                      regs + ATMEL_TC_REG(2, CMR));
-        __raw_writel((32768 + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
+        writel((32768 + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
 
         /* Enable clock and interrupts on RC compare */
-        __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
+        writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
 
         /* go go gadget! */
-        __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, regs +
+        writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, regs +
                      ATMEL_TC_REG(2, CCR));
         return 0;
 }
 
 static int tc_next_event(unsigned long delta, struct clock_event_device *d)
 {
-        __raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
+        writel_relaxed(delta, tcaddr + ATMEL_TC_REG(2, RC));
 
         /* go go gadget! */
-        __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
+        writel_relaxed(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
                         tcaddr + ATMEL_TC_REG(2, CCR));
         return 0;
 }
@@ -230,7 +230,7 @@ static irqreturn_t ch2_irq(int irq, void *handle)
         struct tc_clkevt_device *dev = handle;
         unsigned int            sr;
 
-        sr = __raw_readl(dev->regs + ATMEL_TC_REG(2, SR));
+        sr = readl_relaxed(dev->regs + ATMEL_TC_REG(2, SR));
         if (sr & ATMEL_TC_CPCS) {
                 dev->clkevt.event_handler(&dev->clkevt);
                 return IRQ_HANDLED;
@@ -290,43 +290,43 @@ static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
 static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx)
 {
         /* channel 0:  waveform mode, input mclk/8, clock TIOA0 on overflow */
-        __raw_writel(mck_divisor_idx                    /* likely divide-by-8 */
+        writel(mck_divisor_idx                  /* likely divide-by-8 */
                         | ATMEL_TC_WAVE
                         | ATMEL_TC_WAVESEL_UP           /* free-run */
                         | ATMEL_TC_ACPA_SET             /* TIOA0 rises at 0 */
                         | ATMEL_TC_ACPC_CLEAR,          /* (duty cycle 50%) */
                         tcaddr + ATMEL_TC_REG(0, CMR));
-        __raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
-        __raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
-        __raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));      /* no irqs */
-        __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
+        writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
+        writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
+        writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));    /* no irqs */
+        writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
 
         /* channel 1:  waveform mode, input TIOA0 */
-        __raw_writel(ATMEL_TC_XC1                       /* input: TIOA0 */
+        writel(ATMEL_TC_XC1                     /* input: TIOA0 */
                         | ATMEL_TC_WAVE
                         | ATMEL_TC_WAVESEL_UP,          /* free-run */
                         tcaddr + ATMEL_TC_REG(1, CMR));
-        __raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));      /* no irqs */
-        __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
+        writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));    /* no irqs */
+        writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
 
         /* chain channel 0 to channel 1*/
-        __raw_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
+        writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
         /* then reset all the timers */
-        __raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
+        writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
 }
 
 static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_idx)
 {
         /* channel 0:  waveform mode, input mclk/8 */
-        __raw_writel(mck_divisor_idx                    /* likely divide-by-8 */
+        writel(mck_divisor_idx                  /* likely divide-by-8 */
                         | ATMEL_TC_WAVE
                         | ATMEL_TC_WAVESEL_UP,          /* free-run */
                         tcaddr + ATMEL_TC_REG(0, CMR));
-        __raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));      /* no irqs */
-        __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
+        writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));    /* no irqs */
+        writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
 
         /* then reset all the timers */
-        __raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
+        writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
 }
 
 static int __init tcb_clksrc_init(void)
diff --git a/drivers/clocksource/timer-of.c b/drivers/clocksource/timer-of.c
index 64b1c2081a67..f6e7491c873c 100644
--- a/drivers/clocksource/timer-of.c
+++ b/drivers/clocksource/timer-of.c
@@ -120,7 +120,7 @@ static __init int timer_base_init(struct device_node *np,
         const char *name = of_base->name ? of_base->name : np->full_name;
 
         of_base->base = of_io_request_and_map(np, of_base->index, name);
-        if (of_base->base) {
+        if (!of_base->base) {
                 pr_err("Failed to iomap (%s)\n", name);
                 return -ENXIO;
         }