diff options
| author | Vineet Gupta <vgupta@synopsys.com> | 2015-07-29 09:50:58 -0400 |
|---|---|---|
| committer | Vineet Gupta <vgupta@synopsys.com> | 2015-08-03 23:56:31 -0400 |
| commit | f5959cb0c34c5c7f9f387e5d8fe1ec831ccb42ac (patch) | |
| tree | 646f0fc7d94072c3f974caa3b0b6033defc6bbe8 | |
| parent | 6de7abfbad1c6a45893a47a17c2ac91b551aa90d (diff) | |
Revert "ARCv2: STAR 9000837815 workaround hardware exclusive transactions livelock"
Extended testing of quad core configuration revealed that this fix was
insufficient. Specifically LTP open posix shm_op/23-1 would cause the
hardware livelock in llock/scond loop in update_cpu_load_active()
So remove this and make way for a proper workaround
This reverts commit a5c8b52abe677977883655166796f167ef1e0084.
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| -rw-r--r-- | arch/arc/include/asm/atomic.h | 14 |
1 files changed, 2 insertions, 12 deletions
diff --git a/arch/arc/include/asm/atomic.h b/arch/arc/include/asm/atomic.h index 03484cb4d16d..20b7dc17979e 100644 --- a/arch/arc/include/asm/atomic.h +++ b/arch/arc/include/asm/atomic.h | |||
| @@ -23,21 +23,13 @@ | |||
| 23 | 23 | ||
| 24 | #define atomic_set(v, i) (((v)->counter) = (i)) | 24 | #define atomic_set(v, i) (((v)->counter) = (i)) |
| 25 | 25 | ||
| 26 | #ifdef CONFIG_ISA_ARCV2 | ||
| 27 | #define PREFETCHW " prefetchw [%1] \n" | ||
| 28 | #else | ||
| 29 | #define PREFETCHW | ||
| 30 | #endif | ||
| 31 | |||
| 32 | #define ATOMIC_OP(op, c_op, asm_op) \ | 26 | #define ATOMIC_OP(op, c_op, asm_op) \ |
| 33 | static inline void atomic_##op(int i, atomic_t *v) \ | 27 | static inline void atomic_##op(int i, atomic_t *v) \ |
| 34 | { \ | 28 | { \ |
| 35 | unsigned int temp; \ | 29 | unsigned int temp; \ |
| 36 | \ | 30 | \ |
| 37 | __asm__ __volatile__( \ | 31 | __asm__ __volatile__( \ |
| 38 | "1: \n" \ | 32 | "1: llock %0, [%1] \n" \ |
| 39 | PREFETCHW \ | ||
| 40 | " llock %0, [%1] \n" \ | ||
| 41 | " " #asm_op " %0, %0, %2 \n" \ | 33 | " " #asm_op " %0, %0, %2 \n" \ |
| 42 | " scond %0, [%1] \n" \ | 34 | " scond %0, [%1] \n" \ |
| 43 | " bnz 1b \n" \ | 35 | " bnz 1b \n" \ |
| @@ -58,9 +50,7 @@ static inline int atomic_##op##_return(int i, atomic_t *v) \ | |||
| 58 | smp_mb(); \ | 50 | smp_mb(); \ |
| 59 | \ | 51 | \ |
| 60 | __asm__ __volatile__( \ | 52 | __asm__ __volatile__( \ |
| 61 | "1: \n" \ | 53 | "1: llock %0, [%1] \n" \ |
| 62 | PREFETCHW \ | ||
| 63 | " llock %0, [%1] \n" \ | ||
| 64 | " " #asm_op " %0, %0, %2 \n" \ | 54 | " " #asm_op " %0, %0, %2 \n" \ |
| 65 | " scond %0, [%1] \n" \ | 55 | " scond %0, [%1] \n" \ |
| 66 | " bnz 1b \n" \ | 56 | " bnz 1b \n" \ |