diff options
| author | Thierry Reding <treding@nvidia.com> | 2017-06-26 11:33:12 -0400 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2017-12-13 06:42:30 -0500 |
| commit | f580fd3f9d78cf0425ab98950796c578d8a82167 (patch) | |
| tree | 5ab1276160226e5cae7291f12c822fcb9bec656a | |
| parent | 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323 (diff) | |
dt-bindings: misc: Add Tegra186 MISC registers bindings
The MISC register block found on Tegra186 SoCs contains registers that
can be used to identify a given chip and various strapping options.
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt new file mode 100644 index 000000000000..892ba4384abc --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt | |||
| @@ -0,0 +1,12 @@ | |||
| 1 | NVIDIA Tegra186 MISC register block | ||
| 2 | |||
| 3 | The MISC register block found on Tegra186 SoCs contains registers that can be | ||
| 4 | used to identify a given chip and various strapping options. | ||
| 5 | |||
| 6 | Required properties: | ||
| 7 | - compatible: Must be: | ||
| 8 | - Tegra186: "nvidia,tegra186-misc" | ||
| 9 | - reg: Should contain 2 entries: The first entry gives the physical address | ||
| 10 | and length of the register region which contains revision and debug | ||
| 11 | features. The second entry specifies the physical address and length | ||
| 12 | of the register region indicating the strapping options. | ||