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authorBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>2015-08-11 18:38:45 -0400
committerKukjin Kim <kgene@kernel.org>2015-08-13 13:06:15 -0400
commitf44997412e5b39b6a1231f16555120c5b2aae0ed (patch)
treeb1b733dcd06ac715fb994a65dd8f896b6eba2e4c
parent48816affd931c44045913873dff21693cd7fc948 (diff)
ARM: dts: add CPU OPP and regulator supply property for exynos4x12
For Exynos4x12 platforms, add CPU operating points (using opp-v2 bindings) and CPU regulator supply properties for migrating from Exynos specific cpufreq driver to using generic cpufreq driver. Based on the earlier work by Thomas Abraham. Cc: Doug Anderson <dianders@chromium.org> Cc: Andreas Faerber <afaerber@suse.de> Cc: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Tested-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Tested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
Diffstat
-rw-r--r--arch/arm/boot/dts/exynos4212.dtsi81
-rw-r--r--arch/arm/boot/dts/exynos4412-odroid-common.dtsi4
-rw-r--r--arch/arm/boot/dts/exynos4412-origen.dts4
-rw-r--r--arch/arm/boot/dts/exynos4412-trats2.dts4
-rw-r--r--arch/arm/boot/dts/exynos4412.dtsi83
5 files changed, 176 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index d9c8efeef208..538901123d37 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -30,6 +30,9 @@
30 device_type = "cpu"; 30 device_type = "cpu";
31 compatible = "arm,cortex-a9"; 31 compatible = "arm,cortex-a9";
32 reg = <0xA00>; 32 reg = <0xA00>;
33 clocks = <&clock CLK_ARM_CLK>;
34 clock-names = "cpu";
35 operating-points-v2 = <&cpu0_opp_table>;
33 cooling-min-level = <13>; 36 cooling-min-level = <13>;
34 cooling-max-level = <7>; 37 cooling-max-level = <7>;
35 #cooling-cells = <2>; /* min followed by max */ 38 #cooling-cells = <2>; /* min followed by max */
@@ -39,6 +42,84 @@
39 device_type = "cpu"; 42 device_type = "cpu";
40 compatible = "arm,cortex-a9"; 43 compatible = "arm,cortex-a9";
41 reg = <0xA01>; 44 reg = <0xA01>;
45 operating-points-v2 = <&cpu0_opp_table>;
46 };
47 };
48
49 cpu0_opp_table: opp_table0 {
50 compatible = "operating-points-v2";
51 opp-shared;
52
53 opp00 {
54 opp-hz = /bits/ 64 <200000000>;
55 opp-microvolt = <900000>;
56 clock-latency-ns = <200000>;
57 };
58 opp01 {
59 opp-hz = /bits/ 64 <300000000>;
60 opp-microvolt = <900000>;
61 clock-latency-ns = <200000>;
62 };
63 opp02 {
64 opp-hz = /bits/ 64 <400000000>;
65 opp-microvolt = <925000>;
66 clock-latency-ns = <200000>;
67 };
68 opp03 {
69 opp-hz = /bits/ 64 <500000000>;
70 opp-microvolt = <950000>;
71 clock-latency-ns = <200000>;
72 };
73 opp04 {
74 opp-hz = /bits/ 64 <600000000>;
75 opp-microvolt = <975000>;
76 clock-latency-ns = <200000>;
77 };
78 opp05 {
79 opp-hz = /bits/ 64 <700000000>;
80 opp-microvolt = <987500>;
81 clock-latency-ns = <200000>;
82 };
83 opp06 {
84 opp-hz = /bits/ 64 <800000000>;
85 opp-microvolt = <1000000>;
86 clock-latency-ns = <200000>;
87 };
88 opp07 {
89 opp-hz = /bits/ 64 <900000000>;
90 opp-microvolt = <1037500>;
91 clock-latency-ns = <200000>;
92 };
93 opp08 {
94 opp-hz = /bits/ 64 <1000000000>;
95 opp-microvolt = <1087500>;
96 clock-latency-ns = <200000>;
97 };
98 opp09 {
99 opp-hz = /bits/ 64 <1100000000>;
100 opp-microvolt = <1137500>;
101 clock-latency-ns = <200000>;
102 };
103 opp10 {
104 opp-hz = /bits/ 64 <1200000000>;
105 opp-microvolt = <1187500>;
106 clock-latency-ns = <200000>;
107 };
108 opp11 {
109 opp-hz = /bits/ 64 <1300000000>;
110 opp-microvolt = <1250000>;
111 clock-latency-ns = <200000>;
112 };
113 opp12 {
114 opp-hz = /bits/ 64 <1400000000>;
115 opp-microvolt = <1287500>;
116 clock-latency-ns = <200000>;
117 };
118 opp13 {
119 opp-hz = /bits/ 64 <1500000000>;
120 opp-microvolt = <1350000>;
121 clock-latency-ns = <200000>;
122 turbo-mode;
42 }; 123 };
43 }; 124 };
44}; 125};
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index ca7d168d1dd6..db52841297a5 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -107,6 +107,10 @@
107 }; 107 };
108}; 108};
109 109
110&cpu0 {
111 cpu0-supply = <&buck2_reg>;
112};
113
110/* RSTN signal for eMMC */ 114/* RSTN signal for eMMC */
111&sd1_cd { 115&sd1_cd {
112 samsung,pin-pud = <0>; 116 samsung,pin-pud = <0>;
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index 84c76310b312..9d528af68c1a 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -78,6 +78,10 @@
78 }; 78 };
79}; 79};
80 80
81&cpu0 {
82 cpu0-supply = <&buck2_reg>;
83};
84
81&fimd { 85&fimd {
82 pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>; 86 pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>;
83 pinctrl-names = "default"; 87 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index 884840059018..2a1ebb76ebe0 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -288,6 +288,10 @@
288 status = "okay"; 288 status = "okay";
289}; 289};
290 290
291&cpu0 {
292 cpu0-supply = <&buck2_reg>;
293};
294
291&csis_0 { 295&csis_0 {
292 status = "okay"; 296 status = "okay";
293 vddcore-supply = <&ldo8_reg>; 297 vddcore-supply = <&ldo8_reg>;
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index b78ada70bd05..ca0e3c15977f 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -30,6 +30,9 @@
30 device_type = "cpu"; 30 device_type = "cpu";
31 compatible = "arm,cortex-a9"; 31 compatible = "arm,cortex-a9";
32 reg = <0xA00>; 32 reg = <0xA00>;
33 clocks = <&clock CLK_ARM_CLK>;
34 clock-names = "cpu";
35 operating-points-v2 = <&cpu0_opp_table>;
33 cooling-min-level = <13>; 36 cooling-min-level = <13>;
34 cooling-max-level = <7>; 37 cooling-max-level = <7>;
35 #cooling-cells = <2>; /* min followed by max */ 38 #cooling-cells = <2>; /* min followed by max */
@@ -39,18 +42,98 @@
39 device_type = "cpu"; 42 device_type = "cpu";
40 compatible = "arm,cortex-a9"; 43 compatible = "arm,cortex-a9";
41 reg = <0xA01>; 44 reg = <0xA01>;
45 operating-points-v2 = <&cpu0_opp_table>;
42 }; 46 };
43 47
44 cpu@A02 { 48 cpu@A02 {
45 device_type = "cpu"; 49 device_type = "cpu";
46 compatible = "arm,cortex-a9"; 50 compatible = "arm,cortex-a9";
47 reg = <0xA02>; 51 reg = <0xA02>;
52 operating-points-v2 = <&cpu0_opp_table>;
48 }; 53 };
49 54
50 cpu@A03 { 55 cpu@A03 {
51 device_type = "cpu"; 56 device_type = "cpu";
52 compatible = "arm,cortex-a9"; 57 compatible = "arm,cortex-a9";
53 reg = <0xA03>; 58 reg = <0xA03>;
59 operating-points-v2 = <&cpu0_opp_table>;
60 };
61 };
62
63 cpu0_opp_table: opp_table0 {
64 compatible = "operating-points-v2";
65 opp-shared;
66
67 opp00 {
68 opp-hz = /bits/ 64 <200000000>;
69 opp-microvolt = <900000>;
70 clock-latency-ns = <200000>;
71 };
72 opp01 {
73 opp-hz = /bits/ 64 <300000000>;
74 opp-microvolt = <900000>;
75 clock-latency-ns = <200000>;
76 };
77 opp02 {
78 opp-hz = /bits/ 64 <400000000>;
79 opp-microvolt = <925000>;
80 clock-latency-ns = <200000>;
81 };
82 opp03 {
83 opp-hz = /bits/ 64 <500000000>;
84 opp-microvolt = <950000>;
85 clock-latency-ns = <200000>;
86 };
87 opp04 {
88 opp-hz = /bits/ 64 <600000000>;
89 opp-microvolt = <975000>;
90 clock-latency-ns = <200000>;
91 };
92 opp05 {
93 opp-hz = /bits/ 64 <700000000>;
94 opp-microvolt = <987500>;
95 clock-latency-ns = <200000>;
96 };
97 opp06 {
98 opp-hz = /bits/ 64 <800000000>;
99 opp-microvolt = <1000000>;
100 clock-latency-ns = <200000>;
101 };
102 opp07 {
103 opp-hz = /bits/ 64 <900000000>;
104 opp-microvolt = <1037500>;
105 clock-latency-ns = <200000>;
106 };
107 opp08 {
108 opp-hz = /bits/ 64 <1000000000>;
109 opp-microvolt = <1087500>;
110 clock-latency-ns = <200000>;
111 };
112 opp09 {
113 opp-hz = /bits/ 64 <1100000000>;
114 opp-microvolt = <1137500>;
115 clock-latency-ns = <200000>;
116 };
117 opp10 {
118 opp-hz = /bits/ 64 <1200000000>;
119 opp-microvolt = <1187500>;
120 clock-latency-ns = <200000>;
121 };
122 opp11 {
123 opp-hz = /bits/ 64 <1300000000>;
124 opp-microvolt = <1250000>;
125 clock-latency-ns = <200000>;
126 };
127 opp12 {
128 opp-hz = /bits/ 64 <1400000000>;
129 opp-microvolt = <1287500>;
130 clock-latency-ns = <200000>;
131 };
132 opp13 {
133 opp-hz = /bits/ 64 <1500000000>;
134 opp-microvolt = <1350000>;
135 clock-latency-ns = <200000>;
136 turbo-mode;
54 }; 137 };
55 }; 138 };
56 139
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