aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorMark Brown <broonie@kernel.org>2015-06-05 13:54:46 -0400
committerMark Brown <broonie@kernel.org>2015-06-05 13:54:46 -0400
commitf3b368d3b9a22bb1ddc80808a64ecb7559791e87 (patch)
treeffe7f0c236b24d441fd779a839f7a1224e6be8e6
parent977732b06045a508edc7b105e9fef524163616df (diff)
parent345b0f50e74671fd8299e26c73ab50c5a0cf6ed9 (diff)
Merge remote-tracking branch 'asoc/topic/rt5645' into asoc-next
Diffstat
-rw-r--r--include/sound/rt5645.h3
-rw-r--r--sound/soc/codecs/rt5645.c1078
-rw-r--r--sound/soc/codecs/rt5645.h30
-rw-r--r--sound/soc/intel/boards/cht_bsw_rt5645.c2
4 files changed, 847 insertions, 266 deletions
diff --git a/include/sound/rt5645.h b/include/sound/rt5645.h
index 120d9610054e..652cb9e4afe5 100644
--- a/include/sound/rt5645.h
+++ b/include/sound/rt5645.h
@@ -15,7 +15,6 @@ struct rt5645_platform_data {
15 /* IN2 can optionally be differential */ 15 /* IN2 can optionally be differential */
16 bool in2_diff; 16 bool in2_diff;
17 17
18 bool dmic_en;
19 unsigned int dmic1_data_pin; 18 unsigned int dmic1_data_pin;
20 /* 0 = IN2N; 1 = GPIO5; 2 = GPIO11 */ 19 /* 0 = IN2N; 1 = GPIO5; 2 = GPIO11 */
21 unsigned int dmic2_data_pin; 20 unsigned int dmic2_data_pin;
@@ -24,8 +23,6 @@ struct rt5645_platform_data {
24 unsigned int hp_det_gpio; 23 unsigned int hp_det_gpio;
25 bool gpio_hp_det_active_high; 24 bool gpio_hp_det_active_high;
26 25
27 /* true if codec's jd function is used */
28 bool en_jd_func;
29 unsigned int jd_mode; 26 unsigned int jd_mode;
30}; 27};
31 28
diff --git a/sound/soc/codecs/rt5645.c b/sound/soc/codecs/rt5645.c
index 5da29374cd1d..d5f0f5680d3b 100644
--- a/sound/soc/codecs/rt5645.c
+++ b/sound/soc/codecs/rt5645.c
@@ -18,7 +18,9 @@
18#include <linux/platform_device.h> 18#include <linux/platform_device.h>
19#include <linux/spi/spi.h> 19#include <linux/spi/spi.h>
20#include <linux/gpio.h> 20#include <linux/gpio.h>
21#include <linux/gpio/consumer.h>
21#include <linux/acpi.h> 22#include <linux/acpi.h>
23#include <linux/dmi.h>
22#include <sound/core.h> 24#include <sound/core.h>
23#include <sound/pcm.h> 25#include <sound/pcm.h>
24#include <sound/pcm_params.h> 26#include <sound/pcm_params.h>
@@ -415,9 +417,9 @@ static bool rt5645_readable_register(struct device *dev, unsigned int reg)
415} 417}
416 418
417static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0); 419static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
418static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0); 420static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
419static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0); 421static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
420static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0); 422static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
421static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 423static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
422 424
423/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 425/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
@@ -432,30 +434,6 @@ static unsigned int bst_tlv[] = {
432 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0), 434 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
433}; 435};
434 436
435static const char * const rt5645_tdm_data_swap_select[] = {
436 "L/R", "R/L", "L/L", "R/R"
437};
438
439static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum,
440 RT5645_TDM_CTRL_1, 6, rt5645_tdm_data_swap_select);
441
442static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum,
443 RT5645_TDM_CTRL_1, 4, rt5645_tdm_data_swap_select);
444
445static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum,
446 RT5645_TDM_CTRL_1, 2, rt5645_tdm_data_swap_select);
447
448static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot6_7_enum,
449 RT5645_TDM_CTRL_1, 0, rt5645_tdm_data_swap_select);
450
451static const char * const rt5645_tdm_adc_data_select[] = {
452 "1/2/R", "2/1/R", "R/1/2", "R/2/1"
453};
454
455static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_sel_enum,
456 RT5645_TDM_CTRL_1, 8,
457 rt5645_tdm_adc_data_select);
458
459static const struct snd_kcontrol_new rt5645_snd_controls[] = { 437static const struct snd_kcontrol_new rt5645_snd_controls[] = {
460 /* Speaker Output Volume */ 438 /* Speaker Output Volume */
461 SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL, 439 SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL,
@@ -481,9 +459,9 @@ static const struct snd_kcontrol_new rt5645_snd_controls[] = {
481 SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL, 459 SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL,
482 RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1), 460 RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1),
483 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL, 461 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL,
484 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 175, 0, dac_vol_tlv), 462 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
485 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL, 463 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL,
486 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 175, 0, dac_vol_tlv), 464 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
487 465
488 /* IN1/IN2 Control */ 466 /* IN1/IN2 Control */
489 SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1, 467 SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1,
@@ -499,11 +477,11 @@ static const struct snd_kcontrol_new rt5645_snd_controls[] = {
499 SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL, 477 SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL,
500 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1), 478 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
501 SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL, 479 SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL,
502 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 127, 0, adc_vol_tlv), 480 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
503 SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL, 481 SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL,
504 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1), 482 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
505 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL, 483 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL,
506 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 127, 0, adc_vol_tlv), 484 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
507 485
508 /* ADC Boost Volume Control */ 486 /* ADC Boost Volume Control */
509 SOC_DOUBLE_TLV("STO1 ADC Boost Gain", RT5645_ADC_BST_VOL1, 487 SOC_DOUBLE_TLV("STO1 ADC Boost Gain", RT5645_ADC_BST_VOL1,
@@ -516,17 +494,6 @@ static const struct snd_kcontrol_new rt5645_snd_controls[] = {
516 /* I2S2 function select */ 494 /* I2S2 function select */
517 SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT, 495 SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT,
518 1, 1), 496 1, 1),
519
520 /* TDM */
521 SOC_ENUM("TDM Adc Slot0 1 Data", rt5645_tdm_adc_slot0_1_enum),
522 SOC_ENUM("TDM Adc Slot2 3 Data", rt5645_tdm_adc_slot2_3_enum),
523 SOC_ENUM("TDM Adc Slot4 5 Data", rt5645_tdm_adc_slot4_5_enum),
524 SOC_ENUM("TDM Adc Slot6 7 Data", rt5645_tdm_adc_slot6_7_enum),
525 SOC_ENUM("TDM IF1 ADC DATA Sel", rt5645_tdm_adc_sel_enum),
526 SOC_SINGLE("TDM IF1_DAC1_L Sel", RT5645_TDM_CTRL_3, 12, 7, 0),
527 SOC_SINGLE("TDM IF1_DAC1_R Sel", RT5645_TDM_CTRL_3, 8, 7, 0),
528 SOC_SINGLE("TDM IF1_DAC2_L Sel", RT5645_TDM_CTRL_3, 4, 7, 0),
529 SOC_SINGLE("TDM IF1_DAC2_R Sel", RT5645_TDM_CTRL_3, 0, 7, 0),
530}; 497};
531 498
532/** 499/**
@@ -1093,7 +1060,8 @@ static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux =
1093 1060
1094/* MX-77 [9:8] */ 1061/* MX-77 [9:8] */
1095static const char * const rt5645_if1_adc_in_src[] = { 1062static const char * const rt5645_if1_adc_in_src[] = {
1096 "IF_ADC1", "IF_ADC2", "VAD_ADC" 1063 "IF_ADC1/IF_ADC2/VAD_ADC", "IF_ADC2/IF_ADC1/VAD_ADC",
1064 "VAD_ADC/IF_ADC1/IF_ADC2", "VAD_ADC/IF_ADC2/IF_ADC1"
1097}; 1065};
1098 1066
1099static SOC_ENUM_SINGLE_DECL( 1067static SOC_ENUM_SINGLE_DECL(
@@ -1103,6 +1071,140 @@ static SOC_ENUM_SINGLE_DECL(
1103static const struct snd_kcontrol_new rt5645_if1_adc_in_mux = 1071static const struct snd_kcontrol_new rt5645_if1_adc_in_mux =
1104 SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum); 1072 SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum);
1105 1073
1074/* MX-78 [4:0] */
1075static const char * const rt5650_if1_adc_in_src[] = {
1076 "IF_ADC1/IF_ADC2/DAC_REF/Null",
1077 "IF_ADC1/IF_ADC2/Null/DAC_REF",
1078 "IF_ADC1/DAC_REF/IF_ADC2/Null",
1079 "IF_ADC1/DAC_REF/Null/IF_ADC2",
1080 "IF_ADC1/Null/DAC_REF/IF_ADC2",
1081 "IF_ADC1/Null/IF_ADC2/DAC_REF",
1082
1083 "IF_ADC2/IF_ADC1/DAC_REF/Null",
1084 "IF_ADC2/IF_ADC1/Null/DAC_REF",
1085 "IF_ADC2/DAC_REF/IF_ADC1/Null",
1086 "IF_ADC2/DAC_REF/Null/IF_ADC1",
1087 "IF_ADC2/Null/DAC_REF/IF_ADC1",
1088 "IF_ADC2/Null/IF_ADC1/DAC_REF",
1089
1090 "DAC_REF/IF_ADC1/IF_ADC2/Null",
1091 "DAC_REF/IF_ADC1/Null/IF_ADC2",
1092 "DAC_REF/IF_ADC2/IF_ADC1/Null",
1093 "DAC_REF/IF_ADC2/Null/IF_ADC1",
1094 "DAC_REF/Null/IF_ADC1/IF_ADC2",
1095 "DAC_REF/Null/IF_ADC2/IF_ADC1",
1096
1097 "Null/IF_ADC1/IF_ADC2/DAC_REF",
1098 "Null/IF_ADC1/DAC_REF/IF_ADC2",
1099 "Null/IF_ADC2/IF_ADC1/DAC_REF",
1100 "Null/IF_ADC2/DAC_REF/IF_ADC1",
1101 "Null/DAC_REF/IF_ADC1/IF_ADC2",
1102 "Null/DAC_REF/IF_ADC2/IF_ADC1",
1103};
1104
1105static SOC_ENUM_SINGLE_DECL(
1106 rt5650_if1_adc_in_enum, RT5645_TDM_CTRL_2,
1107 0, rt5650_if1_adc_in_src);
1108
1109static const struct snd_kcontrol_new rt5650_if1_adc_in_mux =
1110 SOC_DAPM_ENUM("IF1 ADC IN source", rt5650_if1_adc_in_enum);
1111
1112/* MX-78 [15:14][13:12][11:10] */
1113static const char * const rt5645_tdm_adc_swap_select[] = {
1114 "L/R", "R/L", "L/L", "R/R"
1115};
1116
1117static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot0_1_enum,
1118 RT5645_TDM_CTRL_2, 14, rt5645_tdm_adc_swap_select);
1119
1120static const struct snd_kcontrol_new rt5650_if1_adc1_in_mux =
1121 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5650_tdm_adc_slot0_1_enum);
1122
1123static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot2_3_enum,
1124 RT5645_TDM_CTRL_2, 12, rt5645_tdm_adc_swap_select);
1125
1126static const struct snd_kcontrol_new rt5650_if1_adc2_in_mux =
1127 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5650_tdm_adc_slot2_3_enum);
1128
1129static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot4_5_enum,
1130 RT5645_TDM_CTRL_2, 10, rt5645_tdm_adc_swap_select);
1131
1132static const struct snd_kcontrol_new rt5650_if1_adc3_in_mux =
1133 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5650_tdm_adc_slot4_5_enum);
1134
1135/* MX-77 [7:6][5:4][3:2] */
1136static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum,
1137 RT5645_TDM_CTRL_1, 6, rt5645_tdm_adc_swap_select);
1138
1139static const struct snd_kcontrol_new rt5645_if1_adc1_in_mux =
1140 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5645_tdm_adc_slot0_1_enum);
1141
1142static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum,
1143 RT5645_TDM_CTRL_1, 4, rt5645_tdm_adc_swap_select);
1144
1145static const struct snd_kcontrol_new rt5645_if1_adc2_in_mux =
1146 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5645_tdm_adc_slot2_3_enum);
1147
1148static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum,
1149 RT5645_TDM_CTRL_1, 2, rt5645_tdm_adc_swap_select);
1150
1151static const struct snd_kcontrol_new rt5645_if1_adc3_in_mux =
1152 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5645_tdm_adc_slot4_5_enum);
1153
1154/* MX-79 [14:12][10:8][6:4][2:0] */
1155static const char * const rt5645_tdm_dac_swap_select[] = {
1156 "Slot0", "Slot1", "Slot2", "Slot3"
1157};
1158
1159static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac0_enum,
1160 RT5645_TDM_CTRL_3, 12, rt5645_tdm_dac_swap_select);
1161
1162static const struct snd_kcontrol_new rt5645_if1_dac0_tdm_sel_mux =
1163 SOC_DAPM_ENUM("IF1 DAC0 source", rt5645_tdm_dac0_enum);
1164
1165static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac1_enum,
1166 RT5645_TDM_CTRL_3, 8, rt5645_tdm_dac_swap_select);
1167
1168static const struct snd_kcontrol_new rt5645_if1_dac1_tdm_sel_mux =
1169 SOC_DAPM_ENUM("IF1 DAC1 source", rt5645_tdm_dac1_enum);
1170
1171static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac2_enum,
1172 RT5645_TDM_CTRL_3, 4, rt5645_tdm_dac_swap_select);
1173
1174static const struct snd_kcontrol_new rt5645_if1_dac2_tdm_sel_mux =
1175 SOC_DAPM_ENUM("IF1 DAC2 source", rt5645_tdm_dac2_enum);
1176
1177static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac3_enum,
1178 RT5645_TDM_CTRL_3, 0, rt5645_tdm_dac_swap_select);
1179
1180static const struct snd_kcontrol_new rt5645_if1_dac3_tdm_sel_mux =
1181 SOC_DAPM_ENUM("IF1 DAC3 source", rt5645_tdm_dac3_enum);
1182
1183/* MX-7a [14:12][10:8][6:4][2:0] */
1184static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac0_enum,
1185 RT5650_TDM_CTRL_4, 12, rt5645_tdm_dac_swap_select);
1186
1187static const struct snd_kcontrol_new rt5650_if1_dac0_tdm_sel_mux =
1188 SOC_DAPM_ENUM("IF1 DAC0 source", rt5650_tdm_dac0_enum);
1189
1190static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac1_enum,
1191 RT5650_TDM_CTRL_4, 8, rt5645_tdm_dac_swap_select);
1192
1193static const struct snd_kcontrol_new rt5650_if1_dac1_tdm_sel_mux =
1194 SOC_DAPM_ENUM("IF1 DAC1 source", rt5650_tdm_dac1_enum);
1195
1196static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac2_enum,
1197 RT5650_TDM_CTRL_4, 4, rt5645_tdm_dac_swap_select);
1198
1199static const struct snd_kcontrol_new rt5650_if1_dac2_tdm_sel_mux =
1200 SOC_DAPM_ENUM("IF1 DAC2 source", rt5650_tdm_dac2_enum);
1201
1202static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac3_enum,
1203 RT5650_TDM_CTRL_4, 0, rt5645_tdm_dac_swap_select);
1204
1205static const struct snd_kcontrol_new rt5650_if1_dac3_tdm_sel_mux =
1206 SOC_DAPM_ENUM("IF1 DAC3 source", rt5650_tdm_dac3_enum);
1207
1106/* MX-2d [3] [2] */ 1208/* MX-2d [3] [2] */
1107static const char * const rt5650_a_dac1_src[] = { 1209static const char * const rt5650_a_dac1_src[] = {
1108 "DAC1", "Stereo DAC Mixer" 1210 "DAC1", "Stereo DAC Mixer"
@@ -1227,52 +1329,79 @@ static void hp_amp_power(struct snd_soc_codec *codec, int on)
1227 1329
1228 if (on) { 1330 if (on) {
1229 if (hp_amp_power_count <= 0) { 1331 if (hp_amp_power_count <= 0) {
1230 /* depop parameters */ 1332 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1231 snd_soc_update_bits(codec, RT5645_DEPOP_M2, 1333 snd_soc_write(codec, RT5645_CHARGE_PUMP,
1232 RT5645_DEPOP_MASK, RT5645_DEPOP_MAN); 1334 0x0e06);
1233 snd_soc_write(codec, RT5645_DEPOP_M1, 0x000d); 1335 snd_soc_write(codec, RT5645_DEPOP_M1, 0x001d);
1234 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1336 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1235 RT5645_HP_DCC_INT1, 0x9f01); 1337 0x3e, 0x7400);
1236 mdelay(150); 1338 snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737);
1237 /* headphone amp power on */ 1339 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1238 snd_soc_update_bits(codec, RT5645_PWR_ANLG1, 1340 RT5645_MAMP_INT_REG2, 0xfc00);
1239 RT5645_PWR_FV1 | RT5645_PWR_FV2 , 0); 1341 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1140);
1240 snd_soc_update_bits(codec, RT5645_PWR_VOL, 1342 } else {
1241 RT5645_PWR_HV_L | RT5645_PWR_HV_R, 1343 /* depop parameters */
1242 RT5645_PWR_HV_L | RT5645_PWR_HV_R); 1344 snd_soc_update_bits(codec, RT5645_DEPOP_M2,
1243 snd_soc_update_bits(codec, RT5645_PWR_ANLG1, 1345 RT5645_DEPOP_MASK, RT5645_DEPOP_MAN);
1244 RT5645_PWR_HP_L | RT5645_PWR_HP_R | 1346 snd_soc_write(codec, RT5645_DEPOP_M1, 0x000d);
1245 RT5645_PWR_HA, 1347 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1246 RT5645_PWR_HP_L | RT5645_PWR_HP_R | 1348 RT5645_HP_DCC_INT1, 0x9f01);
1247 RT5645_PWR_HA); 1349 mdelay(150);
1248 mdelay(5); 1350 /* headphone amp power on */
1249 snd_soc_update_bits(codec, RT5645_PWR_ANLG1, 1351 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1250 RT5645_PWR_FV1 | RT5645_PWR_FV2, 1352 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0);
1251 RT5645_PWR_FV1 | RT5645_PWR_FV2); 1353 snd_soc_update_bits(codec, RT5645_PWR_VOL,
1252 1354 RT5645_PWR_HV_L | RT5645_PWR_HV_R,
1253 snd_soc_update_bits(codec, RT5645_DEPOP_M1, 1355 RT5645_PWR_HV_L | RT5645_PWR_HV_R);
1254 RT5645_HP_CO_MASK | RT5645_HP_SG_MASK, 1356 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1255 RT5645_HP_CO_EN | RT5645_HP_SG_EN); 1357 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1256 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1358 RT5645_PWR_HA,
1257 0x14, 0x1aaa); 1359 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1258 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1360 RT5645_PWR_HA);
1259 0x24, 0x0430); 1361 mdelay(5);
1362 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1363 RT5645_PWR_FV1 | RT5645_PWR_FV2,
1364 RT5645_PWR_FV1 | RT5645_PWR_FV2);
1365
1366 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1367 RT5645_HP_CO_MASK | RT5645_HP_SG_MASK,
1368 RT5645_HP_CO_EN | RT5645_HP_SG_EN);
1369 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1370 0x14, 0x1aaa);
1371 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1372 0x24, 0x0430);
1373 }
1260 } 1374 }
1261 hp_amp_power_count++; 1375 hp_amp_power_count++;
1262 } else { 1376 } else {
1263 hp_amp_power_count--; 1377 hp_amp_power_count--;
1264 if (hp_amp_power_count <= 0) { 1378 if (hp_amp_power_count <= 0) {
1265 snd_soc_update_bits(codec, RT5645_DEPOP_M1, 1379 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1266 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK | 1380 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1267 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS | 1381 0x3e, 0x7400);
1268 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS); 1382 snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737);
1269 /* headphone amp power down */ 1383 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1270 snd_soc_write(codec, RT5645_DEPOP_M1, 0x0000); 1384 RT5645_MAMP_INT_REG2, 0xfc00);
1271 snd_soc_update_bits(codec, RT5645_PWR_ANLG1, 1385 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1140);
1272 RT5645_PWR_HP_L | RT5645_PWR_HP_R | 1386 msleep(100);
1273 RT5645_PWR_HA, 0); 1387 snd_soc_write(codec, RT5645_DEPOP_M1, 0x0001);
1274 snd_soc_update_bits(codec, RT5645_DEPOP_M2, 1388
1275 RT5645_DEPOP_MASK, 0); 1389 } else {
1390 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1391 RT5645_HP_SG_MASK |
1392 RT5645_HP_L_SMT_MASK |
1393 RT5645_HP_R_SMT_MASK,
1394 RT5645_HP_SG_DIS |
1395 RT5645_HP_L_SMT_DIS |
1396 RT5645_HP_R_SMT_DIS);
1397 /* headphone amp power down */
1398 snd_soc_write(codec, RT5645_DEPOP_M1, 0x0000);
1399 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1400 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1401 RT5645_PWR_HA, 0);
1402 snd_soc_update_bits(codec, RT5645_DEPOP_M2,
1403 RT5645_DEPOP_MASK, 0);
1404 }
1276 } 1405 }
1277 } 1406 }
1278} 1407}
@@ -1287,56 +1416,52 @@ static int rt5645_hp_event(struct snd_soc_dapm_widget *w,
1287 case SND_SOC_DAPM_POST_PMU: 1416 case SND_SOC_DAPM_POST_PMU:
1288 hp_amp_power(codec, 1); 1417 hp_amp_power(codec, 1);
1289 /* headphone unmute sequence */ 1418 /* headphone unmute sequence */
1290 if (rt5645->codec_type == CODEC_TYPE_RT5650) { 1419 if (rt5645->codec_type == CODEC_TYPE_RT5645) {
1291 snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737);
1292 } else {
1293 snd_soc_update_bits(codec, RT5645_DEPOP_M3, 1420 snd_soc_update_bits(codec, RT5645_DEPOP_M3,
1294 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK | 1421 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1295 RT5645_CP_FQ3_MASK, 1422 RT5645_CP_FQ3_MASK,
1296 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) | 1423 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) |
1297 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) | 1424 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1298 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT)); 1425 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT));
1426 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1427 RT5645_MAMP_INT_REG2, 0xfc00);
1428 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1429 RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN);
1430 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1431 RT5645_RSTN_MASK, RT5645_RSTN_EN);
1432 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1433 RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK |
1434 RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS |
1435 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1436 msleep(40);
1437 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1438 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
1439 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
1440 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
1299 } 1441 }
1300 regmap_write(rt5645->regmap,
1301 RT5645_PR_BASE + RT5645_MAMP_INT_REG2, 0xfc00);
1302 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1303 RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN);
1304 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1305 RT5645_RSTN_MASK, RT5645_RSTN_EN);
1306 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1307 RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK |
1308 RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS |
1309 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1310 msleep(40);
1311 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1312 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
1313 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
1314 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
1315 break; 1442 break;
1316 1443
1317 case SND_SOC_DAPM_PRE_PMD: 1444 case SND_SOC_DAPM_PRE_PMD:
1318 /* headphone mute sequence */ 1445 /* headphone mute sequence */
1319 if (rt5645->codec_type == CODEC_TYPE_RT5650) { 1446 if (rt5645->codec_type == CODEC_TYPE_RT5645) {
1320 snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737);
1321 } else {
1322 snd_soc_update_bits(codec, RT5645_DEPOP_M3, 1447 snd_soc_update_bits(codec, RT5645_DEPOP_M3,
1323 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK | 1448 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1324 RT5645_CP_FQ3_MASK, 1449 RT5645_CP_FQ3_MASK,
1325 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) | 1450 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) |
1326 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) | 1451 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1327 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT)); 1452 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT));
1453 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1454 RT5645_MAMP_INT_REG2, 0xfc00);
1455 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1456 RT5645_HP_SG_MASK, RT5645_HP_SG_EN);
1457 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1458 RT5645_RSTP_MASK, RT5645_RSTP_EN);
1459 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1460 RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK |
1461 RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS |
1462 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1463 msleep(30);
1328 } 1464 }
1329 regmap_write(rt5645->regmap,
1330 RT5645_PR_BASE + RT5645_MAMP_INT_REG2, 0xfc00);
1331 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1332 RT5645_HP_SG_MASK, RT5645_HP_SG_EN);
1333 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1334 RT5645_RSTP_MASK, RT5645_RSTP_EN);
1335 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1336 RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK |
1337 RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS |
1338 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1339 msleep(30);
1340 hp_amp_power(codec, 0); 1465 hp_amp_power(codec, 0);
1341 break; 1466 break;
1342 1467
@@ -1571,20 +1696,50 @@ static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = {
1571 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), 1696 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1572 1697
1573 /* IF1 2 Mux */ 1698 /* IF1 2 Mux */
1574 SND_SOC_DAPM_MUX("IF1 ADC Mux", SND_SOC_NOPM, 1699 SND_SOC_DAPM_MUX("RT5645 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
1700 0, 0, &rt5645_if1_adc1_in_mux),
1701 SND_SOC_DAPM_MUX("RT5645 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
1702 0, 0, &rt5645_if1_adc2_in_mux),
1703 SND_SOC_DAPM_MUX("RT5645 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
1704 0, 0, &rt5645_if1_adc3_in_mux),
1705 SND_SOC_DAPM_MUX("RT5645 IF1 ADC Mux", SND_SOC_NOPM,
1575 0, 0, &rt5645_if1_adc_in_mux), 1706 0, 0, &rt5645_if1_adc_in_mux),
1707
1708 SND_SOC_DAPM_MUX("RT5650 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
1709 0, 0, &rt5650_if1_adc1_in_mux),
1710 SND_SOC_DAPM_MUX("RT5650 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
1711 0, 0, &rt5650_if1_adc2_in_mux),
1712 SND_SOC_DAPM_MUX("RT5650 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
1713 0, 0, &rt5650_if1_adc3_in_mux),
1714 SND_SOC_DAPM_MUX("RT5650 IF1 ADC Mux", SND_SOC_NOPM,
1715 0, 0, &rt5650_if1_adc_in_mux),
1716
1576 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM, 1717 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM,
1577 0, 0, &rt5645_if2_adc_in_mux), 1718 0, 0, &rt5645_if2_adc_in_mux),
1578 1719
1579 /* Digital Interface */ 1720 /* Digital Interface */
1580 SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1, 1721 SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1,
1581 RT5645_PWR_I2S1_BIT, 0, NULL, 0), 1722 RT5645_PWR_I2S1_BIT, 0, NULL, 0),
1723 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
1582 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 1724 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1583 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), 1725 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1584 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0), 1726 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1585 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0), 1727 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
1586 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0), 1728 &rt5645_if1_dac0_tdm_sel_mux),
1587 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0), 1729 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
1730 &rt5645_if1_dac1_tdm_sel_mux),
1731 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
1732 &rt5645_if1_dac2_tdm_sel_mux),
1733 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
1734 &rt5645_if1_dac3_tdm_sel_mux),
1735 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
1736 &rt5650_if1_dac0_tdm_sel_mux),
1737 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
1738 &rt5650_if1_dac1_tdm_sel_mux),
1739 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
1740 &rt5650_if1_dac2_tdm_sel_mux),
1741 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
1742 &rt5650_if1_dac3_tdm_sel_mux),
1588 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 1743 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1589 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), 1744 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1590 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), 1745 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
@@ -1848,42 +2003,32 @@ static const struct snd_soc_dapm_route rt5645_dapm_routes[] = {
1848 { "IF_ADC2", NULL, "Mono ADC MIXR" }, 2003 { "IF_ADC2", NULL, "Mono ADC MIXR" },
1849 { "VAD_ADC", NULL, "VAD ADC Mux" }, 2004 { "VAD_ADC", NULL, "VAD ADC Mux" },
1850 2005
1851 { "IF1 ADC Mux", "IF_ADC1", "IF_ADC1" },
1852 { "IF1 ADC Mux", "IF_ADC2", "IF_ADC2" },
1853 { "IF1 ADC Mux", "VAD_ADC", "VAD_ADC" },
1854
1855 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" }, 2006 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
1856 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" }, 2007 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
1857 { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" }, 2008 { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },
1858 2009
1859 { "IF1 ADC", NULL, "I2S1" }, 2010 { "IF1 ADC", NULL, "I2S1" },
1860 { "IF1 ADC", NULL, "IF1 ADC Mux" },
1861 { "IF2 ADC", NULL, "I2S2" }, 2011 { "IF2 ADC", NULL, "I2S2" },
1862 { "IF2 ADC", NULL, "IF2 ADC Mux" }, 2012 { "IF2 ADC", NULL, "IF2 ADC Mux" },
1863 2013
1864 { "AIF1TX", NULL, "IF1 ADC" },
1865 { "AIF1TX", NULL, "IF2 ADC" },
1866 { "AIF2TX", NULL, "IF2 ADC" }, 2014 { "AIF2TX", NULL, "IF2 ADC" },
1867 2015
2016 { "IF1 DAC0", NULL, "AIF1RX" },
1868 { "IF1 DAC1", NULL, "AIF1RX" }, 2017 { "IF1 DAC1", NULL, "AIF1RX" },
1869 { "IF1 DAC2", NULL, "AIF1RX" }, 2018 { "IF1 DAC2", NULL, "AIF1RX" },
2019 { "IF1 DAC3", NULL, "AIF1RX" },
1870 { "IF2 DAC", NULL, "AIF2RX" }, 2020 { "IF2 DAC", NULL, "AIF2RX" },
1871 2021
2022 { "IF1 DAC0", NULL, "I2S1" },
1872 { "IF1 DAC1", NULL, "I2S1" }, 2023 { "IF1 DAC1", NULL, "I2S1" },
1873 { "IF1 DAC2", NULL, "I2S1" }, 2024 { "IF1 DAC2", NULL, "I2S1" },
2025 { "IF1 DAC3", NULL, "I2S1" },
1874 { "IF2 DAC", NULL, "I2S2" }, 2026 { "IF2 DAC", NULL, "I2S2" },
1875 2027
1876 { "IF1 DAC2 L", NULL, "IF1 DAC2" },
1877 { "IF1 DAC2 R", NULL, "IF1 DAC2" },
1878 { "IF1 DAC1 L", NULL, "IF1 DAC1" },
1879 { "IF1 DAC1 R", NULL, "IF1 DAC1" },
1880 { "IF2 DAC L", NULL, "IF2 DAC" }, 2028 { "IF2 DAC L", NULL, "IF2 DAC" },
1881 { "IF2 DAC R", NULL, "IF2 DAC" }, 2029 { "IF2 DAC R", NULL, "IF2 DAC" },
1882 2030
1883 { "DAC1 L Mux", "IF1 DAC", "IF1 DAC1 L" },
1884 { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" }, 2031 { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },
1885
1886 { "DAC1 R Mux", "IF1 DAC", "IF1 DAC1 R" },
1887 { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" }, 2032 { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },
1888 2033
1889 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" }, 2034 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
@@ -1893,14 +2038,12 @@ static const struct snd_soc_dapm_route rt5645_dapm_routes[] = {
1893 { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" }, 2038 { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },
1894 { "DAC1 MIXR", NULL, "dac stereo1 filter" }, 2039 { "DAC1 MIXR", NULL, "dac stereo1 filter" },
1895 2040
1896 { "DAC L2 Mux", "IF1 DAC", "IF1 DAC2 L" },
1897 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" }, 2041 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
1898 { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" }, 2042 { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" },
1899 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" }, 2043 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
1900 { "DAC L2 Volume", NULL, "DAC L2 Mux" }, 2044 { "DAC L2 Volume", NULL, "DAC L2 Mux" },
1901 { "DAC L2 Volume", NULL, "dac mono left filter" }, 2045 { "DAC L2 Volume", NULL, "dac mono left filter" },
1902 2046
1903 { "DAC R2 Mux", "IF1 DAC", "IF1 DAC2 R" },
1904 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" }, 2047 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
1905 { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" }, 2048 { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" },
1906 { "DAC R2 Mux", "Haptic", "Haptic Generator" }, 2049 { "DAC R2 Mux", "Haptic", "Haptic Generator" },
@@ -2038,6 +2181,80 @@ static const struct snd_soc_dapm_route rt5650_specific_dapm_routes[] = {
2038 { "DAC R1", NULL, "A DAC1 R Mux" }, 2181 { "DAC R1", NULL, "A DAC1 R Mux" },
2039 { "DAC L2", NULL, "A DAC2 L Mux" }, 2182 { "DAC L2", NULL, "A DAC2 L Mux" },
2040 { "DAC R2", NULL, "A DAC2 R Mux" }, 2183 { "DAC R2", NULL, "A DAC2 R Mux" },
2184
2185 { "RT5650 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
2186 { "RT5650 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
2187 { "RT5650 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
2188 { "RT5650 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
2189
2190 { "RT5650 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
2191 { "RT5650 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
2192 { "RT5650 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
2193 { "RT5650 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
2194
2195 { "RT5650 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
2196 { "RT5650 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
2197 { "RT5650 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
2198 { "RT5650 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
2199
2200 { "IF1 ADC", NULL, "RT5650 IF1 ADC1 Swap Mux" },
2201 { "IF1 ADC", NULL, "RT5650 IF1 ADC2 Swap Mux" },
2202 { "IF1 ADC", NULL, "RT5650 IF1 ADC3 Swap Mux" },
2203
2204 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/DAC_REF/Null", "IF1 ADC" },
2205 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/Null/DAC_REF", "IF1 ADC" },
2206 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/IF_ADC2/Null", "IF1 ADC" },
2207 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/Null/IF_ADC2", "IF1 ADC" },
2208 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/DAC_REF/IF_ADC2", "IF1 ADC" },
2209 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/IF_ADC2/DAC_REF", "IF1 ADC" },
2210
2211 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/DAC_REF/Null", "IF1 ADC" },
2212 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/Null/DAC_REF", "IF1 ADC" },
2213 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/IF_ADC1/Null", "IF1 ADC" },
2214 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/Null/IF_ADC1", "IF1 ADC" },
2215 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/DAC_REF/IF_ADC1", "IF1 ADC" },
2216 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/IF_ADC1/DAC_REF", "IF1 ADC" },
2217
2218 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/IF_ADC2/Null", "IF1 ADC" },
2219 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/Null/IF_ADC2", "IF1 ADC" },
2220 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/IF_ADC1/Null", "IF1 ADC" },
2221 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/Null/IF_ADC1", "IF1 ADC" },
2222 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC1/IF_ADC2", "IF1 ADC" },
2223 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC2/IF_ADC1", "IF1 ADC" },
2224
2225 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/IF_ADC2/DAC_REF", "IF1 ADC" },
2226 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/DAC_REF/IF_ADC2", "IF1 ADC" },
2227 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/IF_ADC1/DAC_REF", "IF1 ADC" },
2228 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/DAC_REF/IF_ADC1", "IF1 ADC" },
2229 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC1/IF_ADC2", "IF1 ADC" },
2230 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC2/IF_ADC1", "IF1 ADC" },
2231 { "AIF1TX", NULL, "RT5650 IF1 ADC Mux" },
2232
2233 { "RT5650 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
2234 { "RT5650 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
2235 { "RT5650 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
2236 { "RT5650 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
2237
2238 { "RT5650 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
2239 { "RT5650 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
2240 { "RT5650 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
2241 { "RT5650 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
2242
2243 { "RT5650 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
2244 { "RT5650 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
2245 { "RT5650 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
2246 { "RT5650 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
2247
2248 { "RT5650 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
2249 { "RT5650 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
2250 { "RT5650 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
2251 { "RT5650 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
2252
2253 { "DAC1 L Mux", "IF1 DAC", "RT5650 IF1 DAC1 L Mux" },
2254 { "DAC1 R Mux", "IF1 DAC", "RT5650 IF1 DAC1 R Mux" },
2255
2256 { "DAC L2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 L Mux" },
2257 { "DAC R2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 R Mux" },
2041}; 2258};
2042 2259
2043static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = { 2260static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = {
@@ -2045,6 +2262,57 @@ static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = {
2045 { "DAC R1", NULL, "Stereo DAC MIXR" }, 2262 { "DAC R1", NULL, "Stereo DAC MIXR" },
2046 { "DAC L2", NULL, "Mono DAC MIXL" }, 2263 { "DAC L2", NULL, "Mono DAC MIXL" },
2047 { "DAC R2", NULL, "Mono DAC MIXR" }, 2264 { "DAC R2", NULL, "Mono DAC MIXR" },
2265
2266 { "RT5645 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
2267 { "RT5645 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
2268 { "RT5645 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
2269 { "RT5645 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
2270
2271 { "RT5645 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
2272 { "RT5645 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
2273 { "RT5645 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
2274 { "RT5645 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
2275
2276 { "RT5645 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
2277 { "RT5645 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
2278 { "RT5645 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
2279 { "RT5645 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
2280
2281 { "IF1 ADC", NULL, "RT5645 IF1 ADC1 Swap Mux" },
2282 { "IF1 ADC", NULL, "RT5645 IF1 ADC2 Swap Mux" },
2283 { "IF1 ADC", NULL, "RT5645 IF1 ADC3 Swap Mux" },
2284
2285 { "RT5645 IF1 ADC Mux", "IF_ADC1/IF_ADC2/VAD_ADC", "IF1 ADC" },
2286 { "RT5645 IF1 ADC Mux", "IF_ADC2/IF_ADC1/VAD_ADC", "IF1 ADC" },
2287 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC1/IF_ADC2", "IF1 ADC" },
2288 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC2/IF_ADC1", "IF1 ADC" },
2289 { "AIF1TX", NULL, "RT5645 IF1 ADC Mux" },
2290
2291 { "RT5645 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
2292 { "RT5645 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
2293 { "RT5645 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
2294 { "RT5645 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
2295
2296 { "RT5645 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
2297 { "RT5645 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
2298 { "RT5645 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
2299 { "RT5645 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
2300
2301 { "RT5645 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
2302 { "RT5645 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
2303 { "RT5645 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
2304 { "RT5645 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
2305
2306 { "RT5645 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
2307 { "RT5645 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
2308 { "RT5645 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
2309 { "RT5645 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
2310
2311 { "DAC1 L Mux", "IF1 DAC", "RT5645 IF1 DAC1 L Mux" },
2312 { "DAC1 R Mux", "IF1 DAC", "RT5645 IF1 DAC1 R Mux" },
2313
2314 { "DAC L2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 L Mux" },
2315 { "DAC R2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 R Mux" },
2048}; 2316};
2049 2317
2050static int rt5645_hw_params(struct snd_pcm_substream *substream, 2318static int rt5645_hw_params(struct snd_pcm_substream *substream,
@@ -2102,9 +2370,8 @@ static int rt5645_hw_params(struct snd_pcm_substream *substream,
2102 2370
2103 switch (dai->id) { 2371 switch (dai->id) {
2104 case RT5645_AIF1: 2372 case RT5645_AIF1:
2105 mask_clk = RT5645_I2S_BCLK_MS1_MASK | RT5645_I2S_PD1_MASK; 2373 mask_clk = RT5645_I2S_PD1_MASK;
2106 val_clk = bclk_ms << RT5645_I2S_BCLK_MS1_SFT | 2374 val_clk = pre_div << RT5645_I2S_PD1_SFT;
2107 pre_div << RT5645_I2S_PD1_SFT;
2108 snd_soc_update_bits(codec, RT5645_I2S1_SDP, 2375 snd_soc_update_bits(codec, RT5645_I2S1_SDP,
2109 (0x3 << dl_sft), (val_len << dl_sft)); 2376 (0x3 << dl_sft), (val_len << dl_sft));
2110 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk); 2377 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
@@ -2369,6 +2636,8 @@ static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2369static int rt5645_set_bias_level(struct snd_soc_codec *codec, 2636static int rt5645_set_bias_level(struct snd_soc_codec *codec,
2370 enum snd_soc_bias_level level) 2637 enum snd_soc_bias_level level)
2371{ 2638{
2639 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2640
2372 switch (level) { 2641 switch (level) {
2373 case SND_SOC_BIAS_PREPARE: 2642 case SND_SOC_BIAS_PREPARE:
2374 if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level) { 2643 if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level) {
@@ -2399,8 +2668,9 @@ static int rt5645_set_bias_level(struct snd_soc_codec *codec,
2399 2668
2400 case SND_SOC_BIAS_OFF: 2669 case SND_SOC_BIAS_OFF:
2401 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1100); 2670 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1100);
2402 snd_soc_update_bits(codec, RT5645_GEN_CTRL1, 2671 if (!rt5645->en_button_func)
2403 RT5645_DIG_GATE_CTRL, 0); 2672 snd_soc_update_bits(codec, RT5645_GEN_CTRL1,
2673 RT5645_DIG_GATE_CTRL, 0);
2404 snd_soc_update_bits(codec, RT5645_PWR_ANLG1, 2674 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2405 RT5645_PWR_VREF1 | RT5645_PWR_MB | 2675 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2406 RT5645_PWR_BG | RT5645_PWR_VREF2 | 2676 RT5645_PWR_BG | RT5645_PWR_VREF2 |
@@ -2414,67 +2684,218 @@ static int rt5645_set_bias_level(struct snd_soc_codec *codec,
2414 return 0; 2684 return 0;
2415} 2685}
2416 2686
2417static int rt5645_jack_detect(struct snd_soc_codec *codec) 2687static int rt5650_calibration(struct rt5645_priv *rt5645)
2418{ 2688{
2419 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 2689 int val, i;
2420 int gpio_state, jack_type = 0; 2690 int ret = -1;
2421 unsigned int val;
2422 2691
2423 if (!gpio_is_valid(rt5645->pdata.hp_det_gpio)) { 2692 regcache_cache_bypass(rt5645->regmap, true);
2424 dev_err(codec->dev, "invalid gpio\n"); 2693 regmap_write(rt5645->regmap, RT5645_RESET, 0);
2425 return -EINVAL; 2694 regmap_write(rt5645->regmap, RT5645_GEN_CTRL3, 0x0800);
2695 regmap_write(rt5645->regmap, RT5645_PR_BASE + RT5645_CHOP_DAC_ADC,
2696 0x3600);
2697 regmap_write(rt5645->regmap, RT5645_PR_BASE + 0x25, 0x7000);
2698 regmap_write(rt5645->regmap, RT5645_I2S1_SDP, 0x8008);
2699 /* headset type */
2700 regmap_write(rt5645->regmap, RT5645_GEN_CTRL1, 0x2061);
2701 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0006);
2702 regmap_write(rt5645->regmap, RT5645_PWR_ANLG1, 0x2012);
2703 regmap_write(rt5645->regmap, RT5645_PWR_MIXER, 0x0002);
2704 regmap_write(rt5645->regmap, RT5645_PWR_VOL, 0x0020);
2705 regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0);
2706 regmap_write(rt5645->regmap, RT5645_IN1_CTRL1, 0x0006);
2707 regmap_write(rt5645->regmap, RT5645_IN1_CTRL2, 0x1827);
2708 regmap_write(rt5645->regmap, RT5645_IN1_CTRL2, 0x0827);
2709 msleep(400);
2710 /* Inline command */
2711 regmap_write(rt5645->regmap, RT5645_DEPOP_M1, 0x0001);
2712 regmap_write(rt5645->regmap, RT5650_4BTN_IL_CMD2, 0xc000);
2713 regmap_write(rt5645->regmap, RT5650_4BTN_IL_CMD1, 0x0008);
2714 /* Calbration */
2715 regmap_write(rt5645->regmap, RT5645_GLB_CLK, 0x8000);
2716 regmap_write(rt5645->regmap, RT5645_DEPOP_M1, 0x0000);
2717 regmap_write(rt5645->regmap, RT5650_4BTN_IL_CMD2, 0xc000);
2718 regmap_write(rt5645->regmap, RT5650_4BTN_IL_CMD1, 0x0008);
2719 regmap_write(rt5645->regmap, RT5645_PWR_DIG2, 0x8800);
2720 regmap_write(rt5645->regmap, RT5645_PWR_ANLG1, 0xe8fa);
2721 regmap_write(rt5645->regmap, RT5645_PWR_ANLG2, 0x8c04);
2722 regmap_write(rt5645->regmap, RT5645_DEPOP_M2, 0x3100);
2723 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0e06);
2724 regmap_write(rt5645->regmap, RT5645_BASS_BACK, 0x8a13);
2725 regmap_write(rt5645->regmap, RT5645_GEN_CTRL3, 0x0820);
2726 regmap_write(rt5645->regmap, RT5645_DEPOP_M1, 0x000d);
2727 /* Power on and Calbration */
2728 regmap_write(rt5645->regmap, RT5645_PR_BASE + RT5645_HP_DCC_INT1,
2729 0x9f01);
2730 msleep(200);
2731 for (i = 0; i < 5; i++) {
2732 regmap_read(rt5645->regmap, RT5645_PR_BASE + 0x7a, &val);
2733 if (val != 0 && val != 0x3f3f) {
2734 ret = 0;
2735 break;
2736 }
2737 msleep(50);
2426 } 2738 }
2427 gpio_state = gpio_get_value(rt5645->pdata.hp_det_gpio); 2739 pr_debug("%s: PR-7A = 0x%x\n", __func__, val);
2740
2741 /* mute */
2742 regmap_write(rt5645->regmap, RT5645_PR_BASE + 0x3e, 0x7400);
2743 regmap_write(rt5645->regmap, RT5645_DEPOP_M3, 0x0737);
2744 regmap_write(rt5645->regmap, RT5645_PR_BASE + RT5645_MAMP_INT_REG2,
2745 0xfc00);
2746 regmap_write(rt5645->regmap, RT5645_DEPOP_M2, 0x1140);
2747 regmap_write(rt5645->regmap, RT5645_DEPOP_M1, 0x0000);
2748 regmap_write(rt5645->regmap, RT5645_GEN_CTRL2, 0x4020);
2749 regmap_write(rt5645->regmap, RT5645_PWR_ANLG2, 0x0006);
2750 regmap_write(rt5645->regmap, RT5645_PWR_DIG2, 0x0000);
2751 msleep(350);
2752
2753 regcache_cache_bypass(rt5645->regmap, false);
2754
2755 return ret;
2756}
2428 2757
2429 dev_dbg(codec->dev, "gpio = %d(%d)\n", rt5645->pdata.hp_det_gpio, 2758static void rt5645_enable_push_button_irq(struct snd_soc_codec *codec,
2430 gpio_state); 2759 bool enable)
2760{
2761 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2431 2762
2432 if ((rt5645->pdata.gpio_hp_det_active_high && gpio_state) || 2763 if (enable) {
2433 (!rt5645->pdata.gpio_hp_det_active_high && !gpio_state)) { 2764 snd_soc_dapm_force_enable_pin_unlocked(&codec->dapm,
2434 snd_soc_dapm_force_enable_pin(&codec->dapm, "micbias1"); 2765 "ADC L power");
2435 snd_soc_dapm_force_enable_pin(&codec->dapm, "micbias2"); 2766 snd_soc_dapm_force_enable_pin_unlocked(&codec->dapm,
2436 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2"); 2767 "ADC R power");
2437 snd_soc_dapm_force_enable_pin(&codec->dapm, "Mic Det Power"); 2768 snd_soc_dapm_force_enable_pin_unlocked(&codec->dapm,
2438 snd_soc_dapm_sync(&codec->dapm); 2769 "LDO2");
2770 snd_soc_dapm_force_enable_pin_unlocked(&codec->dapm,
2771 "Mic Det Power");
2772 snd_soc_dapm_sync_unlocked(&codec->dapm);
2773 snd_soc_update_bits(codec,
2774 RT5645_INT_IRQ_ST, 0x8, 0x8);
2775 snd_soc_update_bits(codec,
2776 RT5650_4BTN_IL_CMD2, 0x8000, 0x8000);
2777 snd_soc_read(codec, RT5650_4BTN_IL_CMD1);
2778 pr_debug("%s read %x = %x\n", __func__, RT5650_4BTN_IL_CMD1,
2779 snd_soc_read(codec, RT5650_4BTN_IL_CMD1));
2780 } else {
2781 snd_soc_update_bits(codec, RT5650_4BTN_IL_CMD2, 0x8000, 0x0);
2782 snd_soc_update_bits(codec, RT5645_INT_IRQ_ST, 0x8, 0x0);
2783 snd_soc_dapm_disable_pin_unlocked(&codec->dapm,
2784 "ADC L power");
2785 snd_soc_dapm_disable_pin_unlocked(&codec->dapm,
2786 "ADC R power");
2787 if (rt5645->pdata.jd_mode == 0)
2788 snd_soc_dapm_disable_pin_unlocked(&codec->dapm,
2789 "LDO2");
2790 snd_soc_dapm_disable_pin_unlocked(&codec->dapm,
2791 "Mic Det Power");
2792 snd_soc_dapm_sync_unlocked(&codec->dapm);
2793 }
2794}
2439 2795
2440 snd_soc_write(codec, RT5645_IN1_CTRL1, 0x0006); 2796static int rt5645_jack_detect(struct snd_soc_codec *codec, int jack_insert)
2441 snd_soc_write(codec, RT5645_JD_CTRL3, 0x00b0); 2797{
2798 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2799 unsigned int val;
2442 2800
2443 snd_soc_update_bits(codec, RT5645_IN1_CTRL2, 2801 if (jack_insert) {
2444 RT5645_CBJ_MN_JD, 0); 2802 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0006);
2445 snd_soc_update_bits(codec, RT5645_IN1_CTRL2, 2803
2446 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD); 2804 if (codec->component.card->instantiated) {
2805 /* for jack type detect */
2806 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
2807 snd_soc_dapm_force_enable_pin(&codec->dapm,
2808 "Mic Det Power");
2809 snd_soc_dapm_sync(&codec->dapm);
2810 } else {
2811 /* Power up necessary bits for JD if dapm is
2812 not ready yet */
2813 regmap_update_bits(rt5645->regmap, RT5645_PWR_ANLG1,
2814 RT5645_PWR_MB | RT5645_PWR_VREF2,
2815 RT5645_PWR_MB | RT5645_PWR_VREF2);
2816 regmap_update_bits(rt5645->regmap, RT5645_PWR_MIXER,
2817 RT5645_PWR_LDO2, RT5645_PWR_LDO2);
2818 regmap_update_bits(rt5645->regmap, RT5645_PWR_VOL,
2819 RT5645_PWR_MIC_DET, RT5645_PWR_MIC_DET);
2820 }
2447 2821
2448 msleep(400); 2822 regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0);
2449 val = snd_soc_read(codec, RT5645_IN1_CTRL3) & 0x7; 2823 regmap_write(rt5645->regmap, RT5645_IN1_CTRL1, 0x0006);
2824 regmap_update_bits(rt5645->regmap,
2825 RT5645_IN1_CTRL2, 0x1000, 0x1000);
2826 msleep(100);
2827 regmap_update_bits(rt5645->regmap,
2828 RT5645_IN1_CTRL2, 0x1000, 0x0000);
2829
2830 msleep(450);
2831 regmap_read(rt5645->regmap, RT5645_IN1_CTRL3, &val);
2832 val &= 0x7;
2450 dev_dbg(codec->dev, "val = %d\n", val); 2833 dev_dbg(codec->dev, "val = %d\n", val);
2451 2834
2452 if (val == 1 || val == 2) 2835 if (val == 1 || val == 2) {
2453 jack_type = SND_JACK_HEADSET; 2836 rt5645->jack_type = SND_JACK_HEADSET;
2454 else 2837 if (rt5645->en_button_func) {
2455 jack_type = SND_JACK_HEADPHONE; 2838 rt5645_enable_push_button_irq(codec, true);
2839 }
2840 } else {
2841 if (codec->component.card->instantiated) {
2842 snd_soc_dapm_disable_pin(&codec->dapm,
2843 "Mic Det Power");
2844 snd_soc_dapm_sync(&codec->dapm);
2845 } else
2846 regmap_update_bits(rt5645->regmap,
2847 RT5645_PWR_VOL, RT5645_PWR_MIC_DET, 0);
2848 rt5645->jack_type = SND_JACK_HEADPHONE;
2849 }
2456 2850
2457 snd_soc_dapm_disable_pin(&codec->dapm, "micbias1"); 2851 } else { /* jack out */
2458 snd_soc_dapm_disable_pin(&codec->dapm, "micbias2"); 2852 rt5645->jack_type = 0;
2459 if (rt5645->pdata.jd_mode == 0) 2853 if (rt5645->en_button_func)
2460 snd_soc_dapm_disable_pin(&codec->dapm, "LDO2"); 2854 rt5645_enable_push_button_irq(codec, false);
2461 snd_soc_dapm_disable_pin(&codec->dapm, "Mic Det Power"); 2855 else {
2462 snd_soc_dapm_sync(&codec->dapm); 2856 if (codec->component.card->instantiated) {
2857 if (rt5645->pdata.jd_mode == 0)
2858 snd_soc_dapm_disable_pin(&codec->dapm,
2859 "LDO2");
2860 snd_soc_dapm_disable_pin(&codec->dapm,
2861 "Mic Det Power");
2862 snd_soc_dapm_sync(&codec->dapm);
2863 } else {
2864 if (rt5645->pdata.jd_mode == 0)
2865 regmap_update_bits(rt5645->regmap,
2866 RT5645_PWR_MIXER,
2867 RT5645_PWR_LDO2, 0);
2868 regmap_update_bits(rt5645->regmap,
2869 RT5645_PWR_VOL, RT5645_PWR_MIC_DET, 0);
2870 }
2871 }
2463 } 2872 }
2464 2873
2465 snd_soc_jack_report(rt5645->hp_jack, jack_type, SND_JACK_HEADPHONE); 2874 return rt5645->jack_type;
2466 snd_soc_jack_report(rt5645->mic_jack, jack_type, SND_JACK_MICROPHONE);
2467 return 0;
2468} 2875}
2469 2876
2877static int rt5645_irq_detection(struct rt5645_priv *rt5645);
2878static irqreturn_t rt5645_irq(int irq, void *data);
2879
2470int rt5645_set_jack_detect(struct snd_soc_codec *codec, 2880int rt5645_set_jack_detect(struct snd_soc_codec *codec,
2471 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack) 2881 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack,
2882 struct snd_soc_jack *btn_jack)
2472{ 2883{
2473 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 2884 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2474 2885
2475 rt5645->hp_jack = hp_jack; 2886 rt5645->hp_jack = hp_jack;
2476 rt5645->mic_jack = mic_jack; 2887 rt5645->mic_jack = mic_jack;
2477 rt5645_jack_detect(codec); 2888 rt5645->btn_jack = btn_jack;
2889 if (rt5645->btn_jack && rt5645->codec_type == CODEC_TYPE_RT5650) {
2890 rt5645->en_button_func = true;
2891 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2892 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
2893 regmap_update_bits(rt5645->regmap, RT5645_DEPOP_M1,
2894 RT5645_HP_CB_MASK, RT5645_HP_CB_PU);
2895 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL1,
2896 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
2897 }
2898 rt5645_irq(0, rt5645);
2478 2899
2479 return 0; 2900 return 0;
2480} 2901}
@@ -2485,7 +2906,7 @@ static void rt5645_jack_detect_work(struct work_struct *work)
2485 struct rt5645_priv *rt5645 = 2906 struct rt5645_priv *rt5645 =
2486 container_of(work, struct rt5645_priv, jack_detect_work.work); 2907 container_of(work, struct rt5645_priv, jack_detect_work.work);
2487 2908
2488 rt5645_jack_detect(rt5645->codec); 2909 rt5645_irq_detection(rt5645);
2489} 2910}
2490 2911
2491static irqreturn_t rt5645_irq(int irq, void *data) 2912static irqreturn_t rt5645_irq(int irq, void *data)
@@ -2498,6 +2919,126 @@ static irqreturn_t rt5645_irq(int irq, void *data)
2498 return IRQ_HANDLED; 2919 return IRQ_HANDLED;
2499} 2920}
2500 2921
2922static int rt5645_button_detect(struct snd_soc_codec *codec)
2923{
2924 int btn_type, val;
2925
2926 val = snd_soc_read(codec, RT5650_4BTN_IL_CMD1);
2927 pr_debug("val=0x%x\n", val);
2928 btn_type = val & 0xfff0;
2929 snd_soc_write(codec, RT5650_4BTN_IL_CMD1, val);
2930
2931 return btn_type;
2932}
2933
2934static int rt5645_irq_detection(struct rt5645_priv *rt5645)
2935{
2936 int val, btn_type, gpio_state = 0, report = 0;
2937
2938 switch (rt5645->pdata.jd_mode) {
2939 case 0: /* Not using rt5645 JD */
2940 if (gpio_is_valid(rt5645->pdata.hp_det_gpio)) {
2941 gpio_state = gpio_get_value(rt5645->pdata.hp_det_gpio);
2942 dev_dbg(rt5645->codec->dev, "gpio = %d(%d)\n",
2943 rt5645->pdata.hp_det_gpio, gpio_state);
2944 }
2945 if ((rt5645->pdata.gpio_hp_det_active_high && gpio_state) ||
2946 (!rt5645->pdata.gpio_hp_det_active_high &&
2947 !gpio_state)) {
2948 report = rt5645_jack_detect(rt5645->codec, 1);
2949 } else {
2950 report = rt5645_jack_detect(rt5645->codec, 0);
2951 }
2952 snd_soc_jack_report(rt5645->hp_jack,
2953 report, SND_JACK_HEADPHONE);
2954 snd_soc_jack_report(rt5645->mic_jack,
2955 report, SND_JACK_MICROPHONE);
2956 return report;
2957 case 1: /* 2 port */
2958 val = snd_soc_read(rt5645->codec, RT5645_A_JD_CTRL1) & 0x0070;
2959 break;
2960 default: /* 1 port */
2961 val = snd_soc_read(rt5645->codec, RT5645_A_JD_CTRL1) & 0x0020;
2962 break;
2963
2964 }
2965
2966 switch (val) {
2967 /* jack in */
2968 case 0x30: /* 2 port */
2969 case 0x0: /* 1 port or 2 port */
2970 if (rt5645->jack_type == 0) {
2971 report = rt5645_jack_detect(rt5645->codec, 1);
2972 /* for push button and jack out */
2973 break;
2974 }
2975 btn_type = 0;
2976 if (snd_soc_read(rt5645->codec, RT5645_INT_IRQ_ST) & 0x4) {
2977 /* button pressed */
2978 report = SND_JACK_HEADSET;
2979 btn_type = rt5645_button_detect(rt5645->codec);
2980 /* rt5650 can report three kinds of button behavior,
2981 one click, double click and hold. However,
2982 currently we will report button pressed/released
2983 event. So all the three button behaviors are
2984 treated as button pressed. */
2985 switch (btn_type) {
2986 case 0x8000:
2987 case 0x4000:
2988 case 0x2000:
2989 report |= SND_JACK_BTN_0;
2990 break;
2991 case 0x1000:
2992 case 0x0800:
2993 case 0x0400:
2994 report |= SND_JACK_BTN_1;
2995 break;
2996 case 0x0200:
2997 case 0x0100:
2998 case 0x0080:
2999 report |= SND_JACK_BTN_2;
3000 break;
3001 case 0x0040:
3002 case 0x0020:
3003 case 0x0010:
3004 report |= SND_JACK_BTN_3;
3005 break;
3006 case 0x0000: /* unpressed */
3007 break;
3008 default:
3009 dev_err(rt5645->codec->dev,
3010 "Unexpected button code 0x%04x\n",
3011 btn_type);
3012 break;
3013 }
3014 }
3015 if (btn_type == 0)/* button release */
3016 report = rt5645->jack_type;
3017
3018 break;
3019 /* jack out */
3020 case 0x70: /* 2 port */
3021 case 0x10: /* 2 port */
3022 case 0x20: /* 1 port */
3023 report = 0;
3024 snd_soc_update_bits(rt5645->codec,
3025 RT5645_INT_IRQ_ST, 0x1, 0x0);
3026 rt5645_jack_detect(rt5645->codec, 0);
3027 break;
3028 default:
3029 break;
3030 }
3031
3032 snd_soc_jack_report(rt5645->hp_jack, report, SND_JACK_HEADPHONE);
3033 snd_soc_jack_report(rt5645->mic_jack, report, SND_JACK_MICROPHONE);
3034 if (rt5645->en_button_func)
3035 snd_soc_jack_report(rt5645->btn_jack,
3036 report, SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3037 SND_JACK_BTN_2 | SND_JACK_BTN_3);
3038
3039 return report;
3040}
3041
2501static int rt5645_probe(struct snd_soc_codec *codec) 3042static int rt5645_probe(struct snd_soc_codec *codec)
2502{ 3043{
2503 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 3044 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
@@ -2522,10 +3063,8 @@ static int rt5645_probe(struct snd_soc_codec *codec)
2522 3063
2523 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF); 3064 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
2524 3065
2525 snd_soc_update_bits(codec, RT5645_CHARGE_PUMP, 0x0300, 0x0200);
2526
2527 /* for JD function */ 3066 /* for JD function */
2528 if (rt5645->pdata.en_jd_func) { 3067 if (rt5645->pdata.jd_mode) {
2529 snd_soc_dapm_force_enable_pin(&codec->dapm, "JD Power"); 3068 snd_soc_dapm_force_enable_pin(&codec->dapm, "JD Power");
2530 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2"); 3069 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
2531 snd_soc_dapm_sync(&codec->dapm); 3070 snd_soc_dapm_sync(&codec->dapm);
@@ -2665,6 +3204,32 @@ static struct acpi_device_id rt5645_acpi_match[] = {
2665MODULE_DEVICE_TABLE(acpi, rt5645_acpi_match); 3204MODULE_DEVICE_TABLE(acpi, rt5645_acpi_match);
2666#endif 3205#endif
2667 3206
3207static struct rt5645_platform_data *rt5645_pdata;
3208
3209static struct rt5645_platform_data strago_platform_data = {
3210 .dmic1_data_pin = RT5645_DMIC1_DISABLE,
3211 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
3212 .jd_mode = 3,
3213};
3214
3215static int strago_quirk_cb(const struct dmi_system_id *id)
3216{
3217 rt5645_pdata = &strago_platform_data;
3218
3219 return 1;
3220}
3221
3222static struct dmi_system_id dmi_platform_intel_braswell[] = {
3223 {
3224 .ident = "Intel Strago",
3225 .callback = strago_quirk_cb,
3226 .matches = {
3227 DMI_MATCH(DMI_PRODUCT_NAME, "Strago"),
3228 },
3229 },
3230 { }
3231};
3232
2668static int rt5645_i2c_probe(struct i2c_client *i2c, 3233static int rt5645_i2c_probe(struct i2c_client *i2c,
2669 const struct i2c_device_id *id) 3234 const struct i2c_device_id *id)
2670{ 3235{
@@ -2672,6 +3237,7 @@ static int rt5645_i2c_probe(struct i2c_client *i2c,
2672 struct rt5645_priv *rt5645; 3237 struct rt5645_priv *rt5645;
2673 int ret; 3238 int ret;
2674 unsigned int val; 3239 unsigned int val;
3240 struct gpio_desc *gpiod;
2675 3241
2676 rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv), 3242 rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv),
2677 GFP_KERNEL); 3243 GFP_KERNEL);
@@ -2681,8 +3247,23 @@ static int rt5645_i2c_probe(struct i2c_client *i2c,
2681 rt5645->i2c = i2c; 3247 rt5645->i2c = i2c;
2682 i2c_set_clientdata(i2c, rt5645); 3248 i2c_set_clientdata(i2c, rt5645);
2683 3249
2684 if (pdata) 3250 if (pdata) {
2685 rt5645->pdata = *pdata; 3251 rt5645->pdata = *pdata;
3252 } else {
3253 if (dmi_check_system(dmi_platform_intel_braswell)) {
3254 rt5645->pdata = *rt5645_pdata;
3255 gpiod = devm_gpiod_get_index(&i2c->dev, "rt5645", 0);
3256
3257 if (IS_ERR(gpiod) || gpiod_direction_input(gpiod)) {
3258 rt5645->pdata.hp_det_gpio = -1;
3259 dev_err(&i2c->dev, "failed to initialize gpiod\n");
3260 } else {
3261 rt5645->pdata.hp_det_gpio = desc_to_gpio(gpiod);
3262 rt5645->pdata.gpio_hp_det_active_high
3263 = !gpiod_is_active_low(gpiod);
3264 }
3265 }
3266 }
2686 3267
2687 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap); 3268 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap);
2688 if (IS_ERR(rt5645->regmap)) { 3269 if (IS_ERR(rt5645->regmap)) {
@@ -2708,6 +3289,13 @@ static int rt5645_i2c_probe(struct i2c_client *i2c,
2708 return -ENODEV; 3289 return -ENODEV;
2709 } 3290 }
2710 3291
3292 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
3293 ret = rt5650_calibration(rt5645);
3294
3295 if (ret < 0)
3296 pr_err("calibration failed!\n");
3297 }
3298
2711 regmap_write(rt5645->regmap, RT5645_RESET, 0); 3299 regmap_write(rt5645->regmap, RT5645_RESET, 0);
2712 3300
2713 ret = regmap_register_patch(rt5645->regmap, init_list, 3301 ret = regmap_register_patch(rt5645->regmap, init_list,
@@ -2727,84 +3315,76 @@ static int rt5645_i2c_probe(struct i2c_client *i2c,
2727 regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL, 3315 regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL,
2728 RT5645_IN_DF2, RT5645_IN_DF2); 3316 RT5645_IN_DF2, RT5645_IN_DF2);
2729 3317
2730 if (rt5645->pdata.dmic_en) { 3318 if (rt5645->pdata.dmic1_data_pin || rt5645->pdata.dmic2_data_pin) {
2731 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 3319 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2732 RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL); 3320 RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL);
3321 }
3322 switch (rt5645->pdata.dmic1_data_pin) {
3323 case RT5645_DMIC_DATA_IN2N:
3324 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3325 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N);
3326 break;
2733 3327
2734 switch (rt5645->pdata.dmic1_data_pin) { 3328 case RT5645_DMIC_DATA_GPIO5:
2735 case RT5645_DMIC_DATA_IN2N: 3329 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2736 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 3330 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5);
2737 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N); 3331 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2738 break; 3332 RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA);
2739 3333 break;
2740 case RT5645_DMIC_DATA_GPIO5:
2741 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2742 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5);
2743 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2744 RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA);
2745 break;
2746
2747 case RT5645_DMIC_DATA_GPIO11:
2748 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2749 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11);
2750 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2751 RT5645_GP11_PIN_MASK,
2752 RT5645_GP11_PIN_DMIC1_SDA);
2753 break;
2754 3334
2755 default: 3335 case RT5645_DMIC_DATA_GPIO11:
2756 break; 3336 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2757 } 3337 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11);
3338 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3339 RT5645_GP11_PIN_MASK,
3340 RT5645_GP11_PIN_DMIC1_SDA);
3341 break;
2758 3342
2759 switch (rt5645->pdata.dmic2_data_pin) { 3343 default:
2760 case RT5645_DMIC_DATA_IN2P: 3344 break;
2761 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 3345 }
2762 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P);
2763 break;
2764 3346
2765 case RT5645_DMIC_DATA_GPIO6: 3347 switch (rt5645->pdata.dmic2_data_pin) {
2766 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 3348 case RT5645_DMIC_DATA_IN2P:
2767 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6); 3349 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2768 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 3350 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P);
2769 RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA); 3351 break;
2770 break;
2771 3352
2772 case RT5645_DMIC_DATA_GPIO10: 3353 case RT5645_DMIC_DATA_GPIO6:
2773 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 3354 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2774 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10); 3355 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6);
2775 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 3356 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2776 RT5645_GP10_PIN_MASK, 3357 RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA);
2777 RT5645_GP10_PIN_DMIC2_SDA); 3358 break;
2778 break;
2779 3359
2780 case RT5645_DMIC_DATA_GPIO12: 3360 case RT5645_DMIC_DATA_GPIO10:
2781 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 3361 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2782 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO12); 3362 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10);
2783 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 3363 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2784 RT5645_GP12_PIN_MASK, 3364 RT5645_GP10_PIN_MASK,
2785 RT5645_GP12_PIN_DMIC2_SDA); 3365 RT5645_GP10_PIN_DMIC2_SDA);
2786 break; 3366 break;
2787 3367
2788 default: 3368 case RT5645_DMIC_DATA_GPIO12:
2789 break; 3369 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2790 } 3370 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO12);
3371 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3372 RT5645_GP12_PIN_MASK,
3373 RT5645_GP12_PIN_DMIC2_SDA);
3374 break;
2791 3375
3376 default:
3377 break;
2792 } 3378 }
2793 3379
2794 if (rt5645->pdata.en_jd_func) { 3380 if (rt5645->pdata.jd_mode) {
2795 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3, 3381 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
2796 RT5645_IRQ_CLK_GATE_CTRL | RT5645_MICINDET_MANU, 3382 RT5645_IRQ_CLK_GATE_CTRL,
2797 RT5645_IRQ_CLK_GATE_CTRL | RT5645_MICINDET_MANU); 3383 RT5645_IRQ_CLK_GATE_CTRL);
2798 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, 3384 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
2799 RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN); 3385 RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN);
2800 regmap_update_bits(rt5645->regmap, RT5645_JD_CTRL3,
2801 RT5645_JD_CBJ_EN | RT5645_JD_CBJ_POL,
2802 RT5645_JD_CBJ_EN | RT5645_JD_CBJ_POL);
2803 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS, 3386 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
2804 RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT); 3387 RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT);
2805 }
2806
2807 if (rt5645->pdata.jd_mode) {
2808 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, 3388 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
2809 RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN); 3389 RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN);
2810 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3, 3390 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
diff --git a/sound/soc/codecs/rt5645.h b/sound/soc/codecs/rt5645.h
index db78e9462876..9ec4e899795d 100644
--- a/sound/soc/codecs/rt5645.h
+++ b/sound/soc/codecs/rt5645.h
@@ -105,6 +105,7 @@
105#define RT5645_TDM_CTRL_1 0x77 105#define RT5645_TDM_CTRL_1 0x77
106#define RT5645_TDM_CTRL_2 0x78 106#define RT5645_TDM_CTRL_2 0x78
107#define RT5645_TDM_CTRL_3 0x79 107#define RT5645_TDM_CTRL_3 0x79
108#define RT5650_TDM_CTRL_4 0x7a
108 109
109/* Function - Analog */ 110/* Function - Analog */
110#define RT5645_GLB_CLK 0x80 111#define RT5645_GLB_CLK 0x80
@@ -942,10 +943,6 @@
942#define RT5645_I2S2_SDI_I2S2 (0x1 << 6) 943#define RT5645_I2S2_SDI_I2S2 (0x1 << 6)
943 944
944/* ADC/DAC Clock Control 1 (0x73) */ 945/* ADC/DAC Clock Control 1 (0x73) */
945#define RT5645_I2S_BCLK_MS1_MASK (0x1 << 15)
946#define RT5645_I2S_BCLK_MS1_SFT 15
947#define RT5645_I2S_BCLK_MS1_32 (0x0 << 15)
948#define RT5645_I2S_BCLK_MS1_64 (0x1 << 15)
949#define RT5645_I2S_PD1_MASK (0x7 << 12) 946#define RT5645_I2S_PD1_MASK (0x7 << 12)
950#define RT5645_I2S_PD1_SFT 12 947#define RT5645_I2S_PD1_SFT 12
951#define RT5645_I2S_PD1_1 (0x0 << 12) 948#define RT5645_I2S_PD1_1 (0x0 << 12)
@@ -1067,13 +1064,14 @@
1067#define RT5645_SCLK_SRC_SFT 14 1064#define RT5645_SCLK_SRC_SFT 14
1068#define RT5645_SCLK_SRC_MCLK (0x0 << 14) 1065#define RT5645_SCLK_SRC_MCLK (0x0 << 14)
1069#define RT5645_SCLK_SRC_PLL1 (0x1 << 14) 1066#define RT5645_SCLK_SRC_PLL1 (0x1 << 14)
1070#define RT5645_SCLK_SRC_RCCLK (0x2 << 14) /* 15MHz */ 1067#define RT5645_SCLK_SRC_RCCLK (0x2 << 14)
1071#define RT5645_PLL1_SRC_MASK (0x3 << 12) 1068#define RT5645_PLL1_SRC_MASK (0x7 << 11)
1072#define RT5645_PLL1_SRC_SFT 12 1069#define RT5645_PLL1_SRC_SFT 11
1073#define RT5645_PLL1_SRC_MCLK (0x0 << 12) 1070#define RT5645_PLL1_SRC_MCLK (0x0 << 11)
1074#define RT5645_PLL1_SRC_BCLK1 (0x1 << 12) 1071#define RT5645_PLL1_SRC_BCLK1 (0x1 << 11)
1075#define RT5645_PLL1_SRC_BCLK2 (0x2 << 12) 1072#define RT5645_PLL1_SRC_BCLK2 (0x2 << 11)
1076#define RT5645_PLL1_SRC_BCLK3 (0x3 << 12) 1073#define RT5645_PLL1_SRC_BCLK3 (0x3 << 11)
1074#define RT5645_PLL1_SRC_RCCLK (0x4 << 11)
1077#define RT5645_PLL1_PD_MASK (0x1 << 3) 1075#define RT5645_PLL1_PD_MASK (0x1 << 3)
1078#define RT5645_PLL1_PD_SFT 3 1076#define RT5645_PLL1_PD_SFT 3
1079#define RT5645_PLL1_PD_1 (0x0 << 3) 1077#define RT5645_PLL1_PD_1 (0x0 << 3)
@@ -2147,6 +2145,7 @@ enum {
2147}; 2145};
2148 2146
2149enum { 2147enum {
2148 RT5645_DMIC1_DISABLE,
2150 RT5645_DMIC_DATA_IN2P, 2149 RT5645_DMIC_DATA_IN2P,
2151 RT5645_DMIC_DATA_GPIO6, 2150 RT5645_DMIC_DATA_GPIO6,
2152 RT5645_DMIC_DATA_GPIO10, 2151 RT5645_DMIC_DATA_GPIO10,
@@ -2154,6 +2153,7 @@ enum {
2154}; 2153};
2155 2154
2156enum { 2155enum {
2156 RT5645_DMIC2_DISABLE,
2157 RT5645_DMIC_DATA_IN2N, 2157 RT5645_DMIC_DATA_IN2N,
2158 RT5645_DMIC_DATA_GPIO5, 2158 RT5645_DMIC_DATA_GPIO5,
2159 RT5645_DMIC_DATA_GPIO11, 2159 RT5645_DMIC_DATA_GPIO11,
@@ -2184,6 +2184,7 @@ struct rt5645_priv {
2184 struct i2c_client *i2c; 2184 struct i2c_client *i2c;
2185 struct snd_soc_jack *hp_jack; 2185 struct snd_soc_jack *hp_jack;
2186 struct snd_soc_jack *mic_jack; 2186 struct snd_soc_jack *mic_jack;
2187 struct snd_soc_jack *btn_jack;
2187 struct delayed_work jack_detect_work; 2188 struct delayed_work jack_detect_work;
2188 2189
2189 int codec_type; 2190 int codec_type;
@@ -2196,9 +2197,12 @@ struct rt5645_priv {
2196 int pll_src; 2197 int pll_src;
2197 int pll_in; 2198 int pll_in;
2198 int pll_out; 2199 int pll_out;
2200
2201 int jack_type;
2202 bool en_button_func;
2199}; 2203};
2200 2204
2201int rt5645_set_jack_detect(struct snd_soc_codec *codec, 2205int rt5645_set_jack_detect(struct snd_soc_codec *codec,
2202 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack); 2206 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack,
2203 2207 struct snd_soc_jack *btn_jack);
2204#endif /* __RT5645_H__ */ 2208#endif /* __RT5645_H__ */
diff --git a/sound/soc/intel/boards/cht_bsw_rt5645.c b/sound/soc/intel/boards/cht_bsw_rt5645.c
index 20a28b22e30f..26e01f36b704 100644
--- a/sound/soc/intel/boards/cht_bsw_rt5645.c
+++ b/sound/soc/intel/boards/cht_bsw_rt5645.c
@@ -185,7 +185,7 @@ static int cht_codec_init(struct snd_soc_pcm_runtime *runtime)
185 return ret; 185 return ret;
186 } 186 }
187 187
188 rt5645_set_jack_detect(codec, &ctx->hp_jack, &ctx->mic_jack); 188 rt5645_set_jack_detect(codec, &ctx->hp_jack, &ctx->mic_jack, NULL);
189 189
190 return ret; 190 return ret;
191} 191}
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 06:20:53 -0400