diff options
author | Ingo Molnar <mingo@kernel.org> | 2017-10-31 08:17:23 -0400 |
---|---|---|
committer | Ingo Molnar <mingo@kernel.org> | 2017-11-07 04:57:47 -0500 |
commit | f3a624e901c633593156f7b00ca743a6204a29bc (patch) | |
tree | 3658ca5fbf6973cb69f67d9cbdb6376d3e81ffda | |
parent | acbc845ffefd9fb70466182cd8555a26189462b2 (diff) |
x86/cpufeatures: Fix various details in the feature definitions
Kept this commit separate from the re-tabulation changes, to make
the changes easier to review:
- add better explanation for entries with no explanation
- fix/enhance the text of some of the entries
- fix the vertical alignment of some of the feature number definitions
- fix inconsistent capitalization
- ... and lots of other small details
i.e. make it all more of a coherent unit, instead of a patchwork of years of additions.
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/20171031121723.28524-4-mingo@kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
-rw-r--r-- | arch/x86/include/asm/cpufeatures.h | 149 |
1 files changed, 74 insertions, 75 deletions
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index ad1b835001cc..cdf5be866863 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h | |||
@@ -20,14 +20,12 @@ | |||
20 | * Note: If the comment begins with a quoted string, that string is used | 20 | * Note: If the comment begins with a quoted string, that string is used |
21 | * in /proc/cpuinfo instead of the macro name. If the string is "", | 21 | * in /proc/cpuinfo instead of the macro name. If the string is "", |
22 | * this feature bit is not displayed in /proc/cpuinfo at all. | 22 | * this feature bit is not displayed in /proc/cpuinfo at all. |
23 | */ | 23 | * |
24 | |||
25 | /* | ||
26 | * When adding new features here that depend on other features, | 24 | * When adding new features here that depend on other features, |
27 | * please update the table in kernel/cpu/cpuid-deps.c | 25 | * please update the table in kernel/cpu/cpuid-deps.c as well. |
28 | */ | 26 | */ |
29 | 27 | ||
30 | /* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */ | 28 | /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */ |
31 | #define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */ | 29 | #define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */ |
32 | #define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */ | 30 | #define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */ |
33 | #define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */ | 31 | #define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */ |
@@ -42,8 +40,7 @@ | |||
42 | #define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */ | 40 | #define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */ |
43 | #define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */ | 41 | #define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */ |
44 | #define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */ | 42 | #define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */ |
45 | #define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions */ | 43 | #define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions (plus FCMOVcc, FCOMI with FPU) */ |
46 | /* (plus FCMOVcc, FCOMI with FPU) */ | ||
47 | #define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */ | 44 | #define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */ |
48 | #define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */ | 45 | #define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */ |
49 | #define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */ | 46 | #define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */ |
@@ -63,15 +60,15 @@ | |||
63 | /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ | 60 | /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ |
64 | /* Don't duplicate feature flags which are redundant with Intel! */ | 61 | /* Don't duplicate feature flags which are redundant with Intel! */ |
65 | #define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */ | 62 | #define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */ |
66 | #define X86_FEATURE_MP ( 1*32+19) /* MP Capable. */ | 63 | #define X86_FEATURE_MP ( 1*32+19) /* MP Capable */ |
67 | #define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */ | 64 | #define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */ |
68 | #define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */ | 65 | #define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */ |
69 | #define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */ | 66 | #define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */ |
70 | #define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */ | 67 | #define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */ |
71 | #define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */ | 68 | #define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */ |
72 | #define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64) */ | 69 | #define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64, 64-bit support) */ |
73 | #define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow! extensions */ | 70 | #define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow extensions */ |
74 | #define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow! */ | 71 | #define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow */ |
75 | 72 | ||
76 | /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */ | 73 | /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */ |
77 | #define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */ | 74 | #define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */ |
@@ -84,66 +81,67 @@ | |||
84 | #define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */ | 81 | #define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */ |
85 | #define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */ | 82 | #define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */ |
86 | #define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */ | 83 | #define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */ |
87 | /* cpu types for specific tunings: */ | 84 | |
85 | /* CPU types for specific tunings: */ | ||
88 | #define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */ | 86 | #define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */ |
89 | #define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */ | 87 | #define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */ |
90 | #define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */ | 88 | #define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */ |
91 | #define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */ | 89 | #define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */ |
92 | #define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */ | 90 | #define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */ |
93 | #define X86_FEATURE_UP ( 3*32+ 9) /* smp kernel running on up */ | 91 | #define X86_FEATURE_UP ( 3*32+ 9) /* SMP kernel running on UP */ |
94 | #define X86_FEATURE_ART ( 3*32+10) /* Platform has always running timer (ART) */ | 92 | #define X86_FEATURE_ART ( 3*32+10) /* Always running timer (ART) */ |
95 | #define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */ | 93 | #define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */ |
96 | #define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */ | 94 | #define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */ |
97 | #define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */ | 95 | #define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */ |
98 | #define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in ia32 userspace */ | 96 | #define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in IA32 userspace */ |
99 | #define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in ia32 userspace */ | 97 | #define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */ |
100 | #define X86_FEATURE_REP_GOOD ( 3*32+16) /* rep microcode works well */ | 98 | #define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */ |
101 | #define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" Mfence synchronizes RDTSC */ | 99 | #define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" MFENCE synchronizes RDTSC */ |
102 | #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" Lfence synchronizes RDTSC */ | 100 | #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" LFENCE synchronizes RDTSC */ |
103 | #define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */ | 101 | #define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */ |
104 | #define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ | 102 | #define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ |
105 | #define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */ | 103 | #define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */ |
106 | #define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */ | 104 | #define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* CPU topology enum extensions */ |
107 | #define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */ | 105 | #define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */ |
108 | #define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */ | 106 | #define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */ |
109 | #define X86_FEATURE_CPUID ( 3*32+25) /* CPU has CPUID instruction itself */ | 107 | #define X86_FEATURE_CPUID ( 3*32+25) /* CPU has CPUID instruction itself */ |
110 | #define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */ | 108 | #define X86_FEATURE_EXTD_APICID ( 3*32+26) /* Extended APICID (8 bits) */ |
111 | #define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */ | 109 | #define X86_FEATURE_AMD_DCM ( 3*32+27) /* AMD multi-node processor */ |
112 | #define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */ | 110 | #define X86_FEATURE_APERFMPERF ( 3*32+28) /* P-State hardware coordination feedback capability (APERF/MPERF MSRs) */ |
113 | #define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */ | 111 | #define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */ |
114 | #define X86_FEATURE_TSC_KNOWN_FREQ ( 3*32+31) /* TSC has known frequency */ | 112 | #define X86_FEATURE_TSC_KNOWN_FREQ ( 3*32+31) /* TSC has known frequency */ |
115 | 113 | ||
116 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ | 114 | /* Intel-defined CPU features, CPUID level 0x00000001 (ECX), word 4 */ |
117 | #define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */ | 115 | #define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */ |
118 | #define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */ | 116 | #define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */ |
119 | #define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */ | 117 | #define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */ |
120 | #define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" Monitor/Mwait support */ | 118 | #define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" MONITOR/MWAIT support */ |
121 | #define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */ | 119 | #define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL-qualified (filtered) Debug Store */ |
122 | #define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */ | 120 | #define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */ |
123 | #define X86_FEATURE_SMX ( 4*32+ 6) /* Safer mode */ | 121 | #define X86_FEATURE_SMX ( 4*32+ 6) /* Safer Mode eXtensions */ |
124 | #define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */ | 122 | #define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */ |
125 | #define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */ | 123 | #define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */ |
126 | #define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */ | 124 | #define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */ |
127 | #define X86_FEATURE_CID ( 4*32+10) /* Context ID */ | 125 | #define X86_FEATURE_CID ( 4*32+10) /* Context ID */ |
128 | #define X86_FEATURE_SDBG ( 4*32+11) /* Silicon Debug */ | 126 | #define X86_FEATURE_SDBG ( 4*32+11) /* Silicon Debug */ |
129 | #define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */ | 127 | #define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */ |
130 | #define X86_FEATURE_CX16 ( 4*32+13) /* CMPXCHG16B */ | 128 | #define X86_FEATURE_CX16 ( 4*32+13) /* CMPXCHG16B instruction */ |
131 | #define X86_FEATURE_XTPR ( 4*32+14) /* Send Task Priority Messages */ | 129 | #define X86_FEATURE_XTPR ( 4*32+14) /* Send Task Priority Messages */ |
132 | #define X86_FEATURE_PDCM ( 4*32+15) /* Performance Capabilities */ | 130 | #define X86_FEATURE_PDCM ( 4*32+15) /* Perf/Debug Capabilities MSR */ |
133 | #define X86_FEATURE_PCID ( 4*32+17) /* Process Context Identifiers */ | 131 | #define X86_FEATURE_PCID ( 4*32+17) /* Process Context Identifiers */ |
134 | #define X86_FEATURE_DCA ( 4*32+18) /* Direct Cache Access */ | 132 | #define X86_FEATURE_DCA ( 4*32+18) /* Direct Cache Access */ |
135 | #define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */ | 133 | #define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */ |
136 | #define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */ | 134 | #define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */ |
137 | #define X86_FEATURE_X2APIC ( 4*32+21) /* x2APIC */ | 135 | #define X86_FEATURE_X2APIC ( 4*32+21) /* X2APIC */ |
138 | #define X86_FEATURE_MOVBE ( 4*32+22) /* MOVBE instruction */ | 136 | #define X86_FEATURE_MOVBE ( 4*32+22) /* MOVBE instruction */ |
139 | #define X86_FEATURE_POPCNT ( 4*32+23) /* POPCNT instruction */ | 137 | #define X86_FEATURE_POPCNT ( 4*32+23) /* POPCNT instruction */ |
140 | #define X86_FEATURE_TSC_DEADLINE_TIMER ( 4*32+24) /* Tsc deadline timer */ | 138 | #define X86_FEATURE_TSC_DEADLINE_TIMER ( 4*32+24) /* TSC deadline timer */ |
141 | #define X86_FEATURE_AES ( 4*32+25) /* AES instructions */ | 139 | #define X86_FEATURE_AES ( 4*32+25) /* AES instructions */ |
142 | #define X86_FEATURE_XSAVE ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ | 140 | #define X86_FEATURE_XSAVE ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV instructions */ |
143 | #define X86_FEATURE_OSXSAVE ( 4*32+27) /* "" XSAVE enabled in the OS */ | 141 | #define X86_FEATURE_OSXSAVE ( 4*32+27) /* "" XSAVE instruction enabled in the OS */ |
144 | #define X86_FEATURE_AVX ( 4*32+28) /* Advanced Vector Extensions */ | 142 | #define X86_FEATURE_AVX ( 4*32+28) /* Advanced Vector Extensions */ |
145 | #define X86_FEATURE_F16C ( 4*32+29) /* 16-bit fp conversions */ | 143 | #define X86_FEATURE_F16C ( 4*32+29) /* 16-bit FP conversions */ |
146 | #define X86_FEATURE_RDRAND ( 4*32+30) /* The RDRAND instruction */ | 144 | #define X86_FEATURE_RDRAND ( 4*32+30) /* RDRAND instruction */ |
147 | #define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */ | 145 | #define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */ |
148 | 146 | ||
149 | /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ | 147 | /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ |
@@ -158,10 +156,10 @@ | |||
158 | #define X86_FEATURE_PMM ( 5*32+12) /* PadLock Montgomery Multiplier */ | 156 | #define X86_FEATURE_PMM ( 5*32+12) /* PadLock Montgomery Multiplier */ |
159 | #define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */ | 157 | #define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */ |
160 | 158 | ||
161 | /* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ | 159 | /* More extended AMD flags: CPUID level 0x80000001, ECX, word 6 */ |
162 | #define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */ | 160 | #define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */ |
163 | #define X86_FEATURE_CMP_LEGACY ( 6*32+ 1) /* If yes HyperThreading not valid */ | 161 | #define X86_FEATURE_CMP_LEGACY ( 6*32+ 1) /* If yes HyperThreading not valid */ |
164 | #define X86_FEATURE_SVM ( 6*32+ 2) /* Secure virtual machine */ | 162 | #define X86_FEATURE_SVM ( 6*32+ 2) /* Secure Virtual Machine */ |
165 | #define X86_FEATURE_EXTAPIC ( 6*32+ 3) /* Extended APIC space */ | 163 | #define X86_FEATURE_EXTAPIC ( 6*32+ 3) /* Extended APIC space */ |
166 | #define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */ | 164 | #define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */ |
167 | #define X86_FEATURE_ABM ( 6*32+ 5) /* Advanced bit manipulation */ | 165 | #define X86_FEATURE_ABM ( 6*32+ 5) /* Advanced bit manipulation */ |
@@ -175,16 +173,16 @@ | |||
175 | #define X86_FEATURE_WDT ( 6*32+13) /* Watchdog timer */ | 173 | #define X86_FEATURE_WDT ( 6*32+13) /* Watchdog timer */ |
176 | #define X86_FEATURE_LWP ( 6*32+15) /* Light Weight Profiling */ | 174 | #define X86_FEATURE_LWP ( 6*32+15) /* Light Weight Profiling */ |
177 | #define X86_FEATURE_FMA4 ( 6*32+16) /* 4 operands MAC instructions */ | 175 | #define X86_FEATURE_FMA4 ( 6*32+16) /* 4 operands MAC instructions */ |
178 | #define X86_FEATURE_TCE ( 6*32+17) /* translation cache extension */ | 176 | #define X86_FEATURE_TCE ( 6*32+17) /* Translation Cache Extension */ |
179 | #define X86_FEATURE_NODEID_MSR ( 6*32+19) /* NodeId MSR */ | 177 | #define X86_FEATURE_NODEID_MSR ( 6*32+19) /* NodeId MSR */ |
180 | #define X86_FEATURE_TBM ( 6*32+21) /* trailing bit manipulations */ | 178 | #define X86_FEATURE_TBM ( 6*32+21) /* Trailing Bit Manipulations */ |
181 | #define X86_FEATURE_TOPOEXT ( 6*32+22) /* topology extensions CPUID leafs */ | 179 | #define X86_FEATURE_TOPOEXT ( 6*32+22) /* Topology extensions CPUID leafs */ |
182 | #define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* core performance counter extensions */ | 180 | #define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* Core performance counter extensions */ |
183 | #define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */ | 181 | #define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */ |
184 | #define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */ | 182 | #define X86_FEATURE_BPEXT ( 6*32+26) /* Data breakpoint extension */ |
185 | #define X86_FEATURE_PTSC ( 6*32+27) /* performance time-stamp counter */ | 183 | #define X86_FEATURE_PTSC ( 6*32+27) /* Performance time-stamp counter */ |
186 | #define X86_FEATURE_PERFCTR_LLC ( 6*32+28) /* Last Level Cache performance counter extensions */ | 184 | #define X86_FEATURE_PERFCTR_LLC ( 6*32+28) /* Last Level Cache performance counter extensions */ |
187 | #define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */ | 185 | #define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX instructions) */ |
188 | 186 | ||
189 | /* | 187 | /* |
190 | * Auxiliary flags: Linux defined - For features scattered in various | 188 | * Auxiliary flags: Linux defined - For features scattered in various |
@@ -192,7 +190,7 @@ | |||
192 | * | 190 | * |
193 | * Reuse free bits when adding new feature flags! | 191 | * Reuse free bits when adding new feature flags! |
194 | */ | 192 | */ |
195 | #define X86_FEATURE_RING3MWAIT ( 7*32+ 0) /* Ring 3 MONITOR/MWAIT */ | 193 | #define X86_FEATURE_RING3MWAIT ( 7*32+ 0) /* Ring 3 MONITOR/MWAIT instructions */ |
196 | #define X86_FEATURE_CPUID_FAULT ( 7*32+ 1) /* Intel CPUID faulting */ | 194 | #define X86_FEATURE_CPUID_FAULT ( 7*32+ 1) /* Intel CPUID faulting */ |
197 | #define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */ | 195 | #define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */ |
198 | #define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ | 196 | #define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ |
@@ -206,8 +204,8 @@ | |||
206 | 204 | ||
207 | #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */ | 205 | #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */ |
208 | #define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */ | 206 | #define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */ |
209 | #define X86_FEATURE_AVX512_4VNNIW (7*32+16) /* AVX-512 Neural Network Instructions */ | 207 | #define X86_FEATURE_AVX512_4VNNIW ( 7*32+16) /* AVX-512 Neural Network Instructions */ |
210 | #define X86_FEATURE_AVX512_4FMAPS (7*32+17) /* AVX-512 Multiply Accumulation Single precision */ | 208 | #define X86_FEATURE_AVX512_4FMAPS ( 7*32+17) /* AVX-512 Multiply Accumulation Single precision */ |
211 | 209 | ||
212 | #define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */ | 210 | #define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */ |
213 | 211 | ||
@@ -218,19 +216,19 @@ | |||
218 | #define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */ | 216 | #define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */ |
219 | #define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */ | 217 | #define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */ |
220 | 218 | ||
221 | #define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer vmmcall to vmcall */ | 219 | #define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer VMMCALL to VMCALL */ |
222 | #define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */ | 220 | #define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */ |
223 | 221 | ||
224 | 222 | ||
225 | /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */ | 223 | /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */ |
226 | #define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/ | 224 | #define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/ |
227 | #define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3b */ | 225 | #define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3B */ |
228 | #define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */ | 226 | #define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */ |
229 | #define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */ | 227 | #define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */ |
230 | #define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */ | 228 | #define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */ |
231 | #define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */ | 229 | #define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */ |
232 | #define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */ | 230 | #define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */ |
233 | #define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB */ | 231 | #define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB instructions */ |
234 | #define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */ | 232 | #define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */ |
235 | #define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */ | 233 | #define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */ |
236 | #define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */ | 234 | #define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */ |
@@ -238,8 +236,8 @@ | |||
238 | #define X86_FEATURE_RDT_A ( 9*32+15) /* Resource Director Technology Allocation */ | 236 | #define X86_FEATURE_RDT_A ( 9*32+15) /* Resource Director Technology Allocation */ |
239 | #define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */ | 237 | #define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */ |
240 | #define X86_FEATURE_AVX512DQ ( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */ | 238 | #define X86_FEATURE_AVX512DQ ( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */ |
241 | #define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */ | 239 | #define X86_FEATURE_RDSEED ( 9*32+18) /* RDSEED instruction */ |
242 | #define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX instructions */ | 240 | #define X86_FEATURE_ADX ( 9*32+19) /* ADCX and ADOX instructions */ |
243 | #define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */ | 241 | #define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */ |
244 | #define X86_FEATURE_AVX512IFMA ( 9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */ | 242 | #define X86_FEATURE_AVX512IFMA ( 9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */ |
245 | #define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */ | 243 | #define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */ |
@@ -251,25 +249,25 @@ | |||
251 | #define X86_FEATURE_AVX512BW ( 9*32+30) /* AVX-512 BW (Byte/Word granular) Instructions */ | 249 | #define X86_FEATURE_AVX512BW ( 9*32+30) /* AVX-512 BW (Byte/Word granular) Instructions */ |
252 | #define X86_FEATURE_AVX512VL ( 9*32+31) /* AVX-512 VL (128/256 Vector Length) Extensions */ | 250 | #define X86_FEATURE_AVX512VL ( 9*32+31) /* AVX-512 VL (128/256 Vector Length) Extensions */ |
253 | 251 | ||
254 | /* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */ | 252 | /* Extended state features, CPUID level 0x0000000d:1 (EAX), word 10 */ |
255 | #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ | 253 | #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT instruction */ |
256 | #define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC */ | 254 | #define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC instruction */ |
257 | #define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 */ | 255 | #define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 instruction */ |
258 | #define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS */ | 256 | #define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS instructions */ |
259 | 257 | ||
260 | /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (edx), word 11 */ | 258 | /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (EDX), word 11 */ |
261 | #define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */ | 259 | #define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */ |
262 | 260 | ||
263 | /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */ | 261 | /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (EDX), word 12 */ |
264 | #define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */ | 262 | #define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring */ |
265 | #define X86_FEATURE_CQM_MBM_TOTAL (12*32+ 1) /* LLC Total MBM monitoring */ | 263 | #define X86_FEATURE_CQM_MBM_TOTAL (12*32+ 1) /* LLC Total MBM monitoring */ |
266 | #define X86_FEATURE_CQM_MBM_LOCAL (12*32+ 2) /* LLC Local MBM monitoring */ | 264 | #define X86_FEATURE_CQM_MBM_LOCAL (12*32+ 2) /* LLC Local MBM monitoring */ |
267 | 265 | ||
268 | /* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */ | 266 | /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ |
269 | #define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */ | 267 | #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ |
270 | #define X86_FEATURE_IRPERF (13*32+1) /* Instructions Retired Count */ | 268 | #define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */ |
271 | 269 | ||
272 | /* Thermal and Power Management Leaf, CPUID level 0x00000006 (eax), word 14 */ | 270 | /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ |
273 | #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ | 271 | #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ |
274 | #define X86_FEATURE_IDA (14*32+ 1) /* Intel Dynamic Acceleration */ | 272 | #define X86_FEATURE_IDA (14*32+ 1) /* Intel Dynamic Acceleration */ |
275 | #define X86_FEATURE_ARAT (14*32+ 2) /* Always Running APIC Timer */ | 273 | #define X86_FEATURE_ARAT (14*32+ 2) /* Always Running APIC Timer */ |
@@ -281,7 +279,7 @@ | |||
281 | #define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */ | 279 | #define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */ |
282 | #define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */ | 280 | #define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */ |
283 | 281 | ||
284 | /* AMD SVM Feature Identification, CPUID level 0x8000000a (edx), word 15 */ | 282 | /* AMD SVM Feature Identification, CPUID level 0x8000000a (EDX), word 15 */ |
285 | #define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */ | 283 | #define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */ |
286 | #define X86_FEATURE_LBRV (15*32+ 1) /* LBR Virtualization support */ | 284 | #define X86_FEATURE_LBRV (15*32+ 1) /* LBR Virtualization support */ |
287 | #define X86_FEATURE_SVML (15*32+ 2) /* "svm_lock" SVM locking MSR */ | 285 | #define X86_FEATURE_SVML (15*32+ 2) /* "svm_lock" SVM locking MSR */ |
@@ -296,24 +294,24 @@ | |||
296 | #define X86_FEATURE_V_VMSAVE_VMLOAD (15*32+15) /* Virtual VMSAVE VMLOAD */ | 294 | #define X86_FEATURE_V_VMSAVE_VMLOAD (15*32+15) /* Virtual VMSAVE VMLOAD */ |
297 | #define X86_FEATURE_VGIF (15*32+16) /* Virtual GIF */ | 295 | #define X86_FEATURE_VGIF (15*32+16) /* Virtual GIF */ |
298 | 296 | ||
299 | /* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx), word 16 */ | 297 | /* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */ |
300 | #define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/ | 298 | #define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/ |
301 | #define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */ | 299 | #define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */ |
302 | #define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */ | 300 | #define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */ |
303 | #define X86_FEATURE_AVX512_VBMI2 (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */ | 301 | #define X86_FEATURE_AVX512_VBMI2 (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */ |
304 | #define X86_FEATURE_GFNI (16*32+ 8) /* Galois Field New Instructions */ | 302 | #define X86_FEATURE_GFNI (16*32+ 8) /* Galois Field New Instructions */ |
305 | #define X86_FEATURE_VAES (16*32+ 9) /* Vector AES */ | 303 | #define X86_FEATURE_VAES (16*32+ 9) /* Vector AES */ |
306 | #define X86_FEATURE_VPCLMULQDQ (16*32+ 10) /* Carry-Less Multiplication Double Quadword */ | 304 | #define X86_FEATURE_VPCLMULQDQ (16*32+10) /* Carry-Less Multiplication Double Quadword */ |
307 | #define X86_FEATURE_AVX512_VNNI (16*32+ 11) /* Vector Neural Network Instructions */ | 305 | #define X86_FEATURE_AVX512_VNNI (16*32+11) /* Vector Neural Network Instructions */ |
308 | #define X86_FEATURE_AVX512_BITALG (16*32+12) /* Support for VPOPCNT[B,W] and VPSHUF-BITQMB */ | 306 | #define X86_FEATURE_AVX512_BITALG (16*32+12) /* Support for VPOPCNT[B,W] and VPSHUF-BITQMB instructions */ |
309 | #define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */ | 307 | #define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */ |
310 | #define X86_FEATURE_LA57 (16*32+16) /* 5-level page tables */ | 308 | #define X86_FEATURE_LA57 (16*32+16) /* 5-level page tables */ |
311 | #define X86_FEATURE_RDPID (16*32+22) /* RDPID instruction */ | 309 | #define X86_FEATURE_RDPID (16*32+22) /* RDPID instruction */ |
312 | 310 | ||
313 | /* AMD-defined CPU features, CPUID level 0x80000007 (ebx), word 17 */ | 311 | /* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */ |
314 | #define X86_FEATURE_OVERFLOW_RECOV (17*32+0) /* MCA overflow recovery support */ | 312 | #define X86_FEATURE_OVERFLOW_RECOV (17*32+ 0) /* MCA overflow recovery support */ |
315 | #define X86_FEATURE_SUCCOR (17*32+1) /* Uncorrectable error containment and recovery */ | 313 | #define X86_FEATURE_SUCCOR (17*32+ 1) /* Uncorrectable error containment and recovery */ |
316 | #define X86_FEATURE_SMCA (17*32+3) /* Scalable MCA */ | 314 | #define X86_FEATURE_SMCA (17*32+ 3) /* Scalable MCA */ |
317 | 315 | ||
318 | /* | 316 | /* |
319 | * BUG word(s) | 317 | * BUG word(s) |
@@ -340,4 +338,5 @@ | |||
340 | #define X86_BUG_SWAPGS_FENCE X86_BUG(11) /* SWAPGS without input dep on GS */ | 338 | #define X86_BUG_SWAPGS_FENCE X86_BUG(11) /* SWAPGS without input dep on GS */ |
341 | #define X86_BUG_MONITOR X86_BUG(12) /* IPI required to wake up remote CPU */ | 339 | #define X86_BUG_MONITOR X86_BUG(12) /* IPI required to wake up remote CPU */ |
342 | #define X86_BUG_AMD_E400 X86_BUG(13) /* CPU is among the affected by Erratum 400 */ | 340 | #define X86_BUG_AMD_E400 X86_BUG(13) /* CPU is among the affected by Erratum 400 */ |
341 | |||
343 | #endif /* _ASM_X86_CPUFEATURES_H */ | 342 | #endif /* _ASM_X86_CPUFEATURES_H */ |