ARCv2: boot log: updates for HS48: dual-issue, ECC, Loop Buffer

Print the hardware support for ECC, Loop Buffer as well as the runtime
enabled status

Note that unlike the existing boot printing, this one is not read from
pre-decoded hardware capabilty info cached in cpuinfo[] struct.
Instead we read the AUX regs on the spot and print it, without botherign
to save anywhere.

There is no point in saving static hardware capabilites in memory when
its use is very sporadic and non-performance critical, mainly for
/proc/cpuinfo. This gets worse in SMP, given it is per-cpu, and pretty
much exactly same across all cpus. So only info needed at runtime
(e.g. TLB geometry) needs to be cached in cpuinfo[]. So going fwd
we will start converting code to this paradigm.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

2 files changed, 71 insertions, 5 deletions

diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index b1c56d35f2a9..49bfbd879caa 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -11,12 +11,14 @@
 
 /* Build Configuration Registers */
 #define ARC_REG_AUX_DCCM        0x18    /* DCCM Base Addr ARCv2 */
+#define ARC_REG_ERP_CTRL        0x3F    /* ARCv2 Error protection control */
 #define ARC_REG_DCCM_BASE_BUILD 0x61    /* DCCM Base Addr ARCompact */
 #define ARC_REG_CRC_BCR         0x62
 #define ARC_REG_VECBASE_BCR     0x68
 #define ARC_REG_PERIBASE_BCR    0x69
 #define ARC_REG_FP_BCR          0x6B    /* ARCompact: Single-Precision FPU */
 #define ARC_REG_DPFP_BCR        0x6C    /* ARCompact: Dbl Precision FPU */
+#define ARC_REG_ERP_BUILD       0xc7    /* ARCv2 Error protection Build: ECC/Parity */
 #define ARC_REG_FP_V2_BCR       0xc8    /* ARCv2 FPU */
 #define ARC_REG_SLC_BCR         0xce
 #define ARC_REG_DCCM_BUILD      0x74    /* DCCM size (common) */
@@ -32,11 +34,14 @@
 #define ARC_REG_D_UNCACH_BCR    0x6A
 #define ARC_REG_BPU_BCR         0xc0
 #define ARC_REG_ISA_CFG_BCR     0xc1
+#define ARC_REG_LPB_BUILD       0xE9    /* ARCv2 Loop Buffer Build */
 #define ARC_REG_RTT_BCR         0xF2
 #define ARC_REG_IRQ_BCR         0xF3
+#define ARC_REG_MICRO_ARCH_BCR  0xF9    /* ARCv2 Product revision */
 #define ARC_REG_SMART_BCR       0xFF
 #define ARC_REG_CLUSTER_BCR     0xcf
 #define ARC_REG_AUX_ICCM        0x208   /* ICCM Base Addr (ARCv2) */
+#define ARC_REG_LPB_CTRL        0x488   /* ARCv2 Loop Buffer control */
 
 /* Common for ARCompact and ARCv2 status register */
 #define ARC_REG_STATUS32        0x0A
@@ -229,6 +234,32 @@ struct bcr_bpu_arcv2 {
 #endif
 };
 
+/* Error Protection Build: ECC/Parity */
+struct bcr_erp {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+        unsigned int pad3:5, mmu:3, pad2:4, ic:3, dc:3, pad1:6, ver:8;
+#else
+        unsigned int ver:8, pad1:6, dc:3, ic:3, pad2:4, mmu:3, pad3:5;
+#endif
+};
+
+/* Error Protection Control */
+struct ctl_erp {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+        unsigned int pad2:27, mpd:1, pad1:2, dpd:1, dpi:1;
+#else
+        unsigned int dpi:1, dpd:1, pad1:2, mpd:1, pad2:27;
+#endif
+};
+
+struct bcr_lpb {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+        unsigned int pad:16, entries:8, ver:8;
+#else
+        unsigned int ver:8, entries:8, pad:16;
+#endif
+};
+
 struct bcr_generic {
 #ifdef CONFIG_CPU_BIG_ENDIAN
         unsigned int info:24, ver:8;
@@ -270,7 +301,7 @@ struct cpuinfo_arc {
         struct cpuinfo_arc_ccm iccm, dccm;
         struct {
                 unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2,
-                             fpu_sp:1, fpu_dp:1, dual_iss_enb:1, dual_iss_exist:1, pad2:4,
+                             fpu_sp:1, fpu_dp:1, dual:1, dual_enb:1, pad2:4,
                              debug:1, ap:1, smart:1, rtt:1, pad3:4,
                              timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;
         } extn;
diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index fb83844daeea..7ef7d9a8ff89 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -199,8 +199,10 @@ static void read_arc_build_cfg_regs(void)
                         unsigned int exec_ctrl;
 
                         READ_BCR(AUX_EXEC_CTRL, exec_ctrl);
-                        cpu->extn.dual_iss_exist = 1;
-                        cpu->extn.dual_iss_enb = exec_ctrl & 1;
+                        cpu->extn.dual_enb = exec_ctrl & 1;
+
+                        /* dual issue always present for this core */
+                        cpu->extn.dual = 1;
                 }
         }
 
@@ -253,7 +255,7 @@ static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
                        cpu_id, cpu->name, cpu->details,
                        is_isa_arcompact() ? "ARCompact" : "ARCv2",
                        IS_AVAIL1(cpu->isa.be, "[Big-Endian]"),
-                       IS_AVAIL3(cpu->extn.dual_iss_exist, cpu->extn.dual_iss_enb, " Dual-Issue"));
+                       IS_AVAIL3(cpu->extn.dual, cpu->extn.dual_enb, " Dual-Issue "));
 
         n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s%s%s\nISA Extn\t: ",
                        IS_AVAIL1(cpu->extn.timer0, "Timer0 "),
@@ -293,11 +295,26 @@ static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
 
         if (cpu->bpu.ver)
                 n += scnprintf(buf + n, len - n,
-                              "BPU\t\t: %s%s match, cache:%d, Predict Table:%d\n",
+                              "BPU\t\t: %s%s match, cache:%d, Predict Table:%d",
                               IS_AVAIL1(cpu->bpu.full, "full"),
                               IS_AVAIL1(!cpu->bpu.full, "partial"),
                               cpu->bpu.num_cache, cpu->bpu.num_pred);
 
+        if (is_isa_arcv2()) {
+                struct bcr_lpb lpb;
+
+                READ_BCR(ARC_REG_LPB_BUILD, lpb);
+                if (lpb.ver) {
+                        unsigned int ctl;
+                        ctl = read_aux_reg(ARC_REG_LPB_CTRL);
+
+                        n += scnprintf(buf + n, len - n, " Loop Buffer:%d %s",
+                                lpb.entries,
+                                IS_DISABLED_RUN(!ctl));
+                }
+        }
+
+        n += scnprintf(buf + n, len - n, "\n");
         return buf;
 }
 
@@ -326,6 +343,24 @@ static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len)
                                cpu->dccm.base_addr, TO_KB(cpu->dccm.sz),
                                cpu->iccm.base_addr, TO_KB(cpu->iccm.sz));
 
+        if (is_isa_arcv2()) {
+
+                /* Error Protection: ECC/Parity */
+                struct bcr_erp erp;
+                READ_BCR(ARC_REG_ERP_BUILD, erp);
+
+                if (erp.ver) {
+                        struct  ctl_erp ctl;
+                        READ_BCR(ARC_REG_ERP_CTRL, ctl);
+
+                        /* inverted bits: 0 means enabled */
+                        n += scnprintf(buf + n, len - n, "Extn [ECC]\t: %s%s%s%s%s%s\n",
+                                IS_AVAIL3(erp.ic,  !ctl.dpi, "IC "),
+                                IS_AVAIL3(erp.dc,  !ctl.dpd, "DC "),
+                                IS_AVAIL3(erp.mmu, !ctl.mpd, "MMU "));
+                }
+        }
+
         n += scnprintf(buf + n, len - n, "OS ABI [v%d]\t: %s\n",
                         EF_ARC_OSABI_CURRENT >> 8,
                         EF_ARC_OSABI_CURRENT == EF_ARC_OSABI_V3 ?