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authorAlex Deucher <alexander.deucher@amd.com>2016-01-27 11:09:50 -0500
committerAlex Deucher <alexander.deucher@amd.com>2016-02-10 14:17:02 -0500
commitf2802faa052994bf2a57094f0aad788c675ab519 (patch)
tree397bea16d50020424044adb491e9e8593fbcd187
parent5d37a63d2612a4f2eb77784a41b9a7a7d1d4315e (diff)
drm/amd: add dce8 enum register header
This adds the DCE8 enum header. Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_enum.h1117
1 files changed, 1117 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_enum.h
new file mode 100644
index 000000000000..6bea30ef3df5
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_enum.h
@@ -0,0 +1,1117 @@
1/*
2 * DCE_8_0 Register documentation
3 *
4 * Copyright (C) 2016 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef DCE_8_0_ENUM_H
25#define DCE_8_0_ENUM_H
26
27typedef enum SurfaceEndian {
28 ENDIAN_NONE = 0x0,
29 ENDIAN_8IN16 = 0x1,
30 ENDIAN_8IN32 = 0x2,
31 ENDIAN_8IN64 = 0x3,
32} SurfaceEndian;
33typedef enum ArrayMode {
34 ARRAY_LINEAR_GENERAL = 0x0,
35 ARRAY_LINEAR_ALIGNED = 0x1,
36 ARRAY_1D_TILED_THIN1 = 0x2,
37 ARRAY_1D_TILED_THICK = 0x3,
38 ARRAY_2D_TILED_THIN1 = 0x4,
39 ARRAY_PRT_TILED_THIN1 = 0x5,
40 ARRAY_PRT_2D_TILED_THIN1 = 0x6,
41 ARRAY_2D_TILED_THICK = 0x7,
42 ARRAY_2D_TILED_XTHICK = 0x8,
43 ARRAY_PRT_TILED_THICK = 0x9,
44 ARRAY_PRT_2D_TILED_THICK = 0xa,
45 ARRAY_PRT_3D_TILED_THIN1 = 0xb,
46 ARRAY_3D_TILED_THIN1 = 0xc,
47 ARRAY_3D_TILED_THICK = 0xd,
48 ARRAY_3D_TILED_XTHICK = 0xe,
49 ARRAY_PRT_3D_TILED_THICK = 0xf,
50} ArrayMode;
51typedef enum PipeTiling {
52 CONFIG_1_PIPE = 0x0,
53 CONFIG_2_PIPE = 0x1,
54 CONFIG_4_PIPE = 0x2,
55 CONFIG_8_PIPE = 0x3,
56} PipeTiling;
57typedef enum BankTiling {
58 CONFIG_4_BANK = 0x0,
59 CONFIG_8_BANK = 0x1,
60} BankTiling;
61typedef enum GroupInterleave {
62 CONFIG_256B_GROUP = 0x0,
63 CONFIG_512B_GROUP = 0x1,
64} GroupInterleave;
65typedef enum RowTiling {
66 CONFIG_1KB_ROW = 0x0,
67 CONFIG_2KB_ROW = 0x1,
68 CONFIG_4KB_ROW = 0x2,
69 CONFIG_8KB_ROW = 0x3,
70 CONFIG_1KB_ROW_OPT = 0x4,
71 CONFIG_2KB_ROW_OPT = 0x5,
72 CONFIG_4KB_ROW_OPT = 0x6,
73 CONFIG_8KB_ROW_OPT = 0x7,
74} RowTiling;
75typedef enum BankSwapBytes {
76 CONFIG_128B_SWAPS = 0x0,
77 CONFIG_256B_SWAPS = 0x1,
78 CONFIG_512B_SWAPS = 0x2,
79 CONFIG_1KB_SWAPS = 0x3,
80} BankSwapBytes;
81typedef enum SampleSplitBytes {
82 CONFIG_1KB_SPLIT = 0x0,
83 CONFIG_2KB_SPLIT = 0x1,
84 CONFIG_4KB_SPLIT = 0x2,
85 CONFIG_8KB_SPLIT = 0x3,
86} SampleSplitBytes;
87typedef enum NumPipes {
88 ADDR_CONFIG_1_PIPE = 0x0,
89 ADDR_CONFIG_2_PIPE = 0x1,
90 ADDR_CONFIG_4_PIPE = 0x2,
91 ADDR_CONFIG_8_PIPE = 0x3,
92} NumPipes;
93typedef enum PipeInterleaveSize {
94 ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
95 ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
96} PipeInterleaveSize;
97typedef enum BankInterleaveSize {
98 ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
99 ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
100 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
101 ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
102} BankInterleaveSize;
103typedef enum NumShaderEngines {
104 ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
105 ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
106} NumShaderEngines;
107typedef enum ShaderEngineTileSize {
108 ADDR_CONFIG_SE_TILE_16 = 0x0,
109 ADDR_CONFIG_SE_TILE_32 = 0x1,
110} ShaderEngineTileSize;
111typedef enum NumGPUs {
112 ADDR_CONFIG_1_GPU = 0x0,
113 ADDR_CONFIG_2_GPU = 0x1,
114 ADDR_CONFIG_4_GPU = 0x2,
115} NumGPUs;
116typedef enum MultiGPUTileSize {
117 ADDR_CONFIG_GPU_TILE_16 = 0x0,
118 ADDR_CONFIG_GPU_TILE_32 = 0x1,
119 ADDR_CONFIG_GPU_TILE_64 = 0x2,
120 ADDR_CONFIG_GPU_TILE_128 = 0x3,
121} MultiGPUTileSize;
122typedef enum RowSize {
123 ADDR_CONFIG_1KB_ROW = 0x0,
124 ADDR_CONFIG_2KB_ROW = 0x1,
125 ADDR_CONFIG_4KB_ROW = 0x2,
126} RowSize;
127typedef enum NumLowerPipes {
128 ADDR_CONFIG_1_LOWER_PIPES = 0x0,
129 ADDR_CONFIG_2_LOWER_PIPES = 0x1,
130} NumLowerPipes;
131typedef enum DebugBlockId {
132 DBG_CLIENT_BLKID_RESERVED = 0x0,
133 DBG_CLIENT_BLKID_dbg = 0x1,
134 DBG_CLIENT_BLKID_uvdu_0 = 0x2,
135 DBG_CLIENT_BLKID_uvdu_1 = 0x3,
136 DBG_CLIENT_BLKID_uvdu_2 = 0x4,
137 DBG_CLIENT_BLKID_uvdu_3 = 0x5,
138 DBG_CLIENT_BLKID_uvdu_4 = 0x6,
139 DBG_CLIENT_BLKID_uvdu_5 = 0x7,
140 DBG_CLIENT_BLKID_uvdu_6 = 0x8,
141 DBG_CLIENT_BLKID_uvdm_0 = 0x9,
142 DBG_CLIENT_BLKID_uvdm_1 = 0xa,
143 DBG_CLIENT_BLKID_uvdm_2 = 0xb,
144 DBG_CLIENT_BLKID_uvdm_3 = 0xc,
145 DBG_CLIENT_BLKID_vcea_0 = 0xd,
146 DBG_CLIENT_BLKID_vcea_1 = 0xe,
147 DBG_CLIENT_BLKID_vcea_2 = 0xf,
148 DBG_CLIENT_BLKID_vcea_3 = 0x10,
149 DBG_CLIENT_BLKID_vcea_4 = 0x11,
150 DBG_CLIENT_BLKID_vcea_5 = 0x12,
151 DBG_CLIENT_BLKID_vcea_6 = 0x13,
152 DBG_CLIENT_BLKID_vceb_0 = 0x14,
153 DBG_CLIENT_BLKID_vceb_1 = 0x15,
154 DBG_CLIENT_BLKID_vceb_2 = 0x16,
155 DBG_CLIENT_BLKID_dco = 0x17,
156 DBG_CLIENT_BLKID_xdma = 0x18,
157 DBG_CLIENT_BLKID_smu_0 = 0x19,
158 DBG_CLIENT_BLKID_smu_1 = 0x1a,
159 DBG_CLIENT_BLKID_smu_2 = 0x1b,
160 DBG_CLIENT_BLKID_gck = 0x1c,
161 DBG_CLIENT_BLKID_tmonw0 = 0x1d,
162 DBG_CLIENT_BLKID_tmonw1 = 0x1e,
163 DBG_CLIENT_BLKID_grbm = 0x1f,
164 DBG_CLIENT_BLKID_rlc = 0x20,
165 DBG_CLIENT_BLKID_ds0 = 0x21,
166 DBG_CLIENT_BLKID_cpg_0 = 0x22,
167 DBG_CLIENT_BLKID_cpg_1 = 0x23,
168 DBG_CLIENT_BLKID_cpc_0 = 0x24,
169 DBG_CLIENT_BLKID_cpc_1 = 0x25,
170 DBG_CLIENT_BLKID_cpf = 0x26,
171 DBG_CLIENT_BLKID_scf0 = 0x27,
172 DBG_CLIENT_BLKID_scf1 = 0x28,
173 DBG_CLIENT_BLKID_scf2 = 0x29,
174 DBG_CLIENT_BLKID_scf3 = 0x2a,
175 DBG_CLIENT_BLKID_pc0 = 0x2b,
176 DBG_CLIENT_BLKID_pc1 = 0x2c,
177 DBG_CLIENT_BLKID_pc2 = 0x2d,
178 DBG_CLIENT_BLKID_pc3 = 0x2e,
179 DBG_CLIENT_BLKID_vgt0 = 0x2f,
180 DBG_CLIENT_BLKID_vgt1 = 0x30,
181 DBG_CLIENT_BLKID_vgt2 = 0x31,
182 DBG_CLIENT_BLKID_vgt3 = 0x32,
183 DBG_CLIENT_BLKID_sx00 = 0x33,
184 DBG_CLIENT_BLKID_sx10 = 0x34,
185 DBG_CLIENT_BLKID_sx20 = 0x35,
186 DBG_CLIENT_BLKID_sx30 = 0x36,
187 DBG_CLIENT_BLKID_cb001 = 0x37,
188 DBG_CLIENT_BLKID_cb200 = 0x38,
189 DBG_CLIENT_BLKID_cb201 = 0x39,
190 DBG_CLIENT_BLKID_cbr0 = 0x3a,
191 DBG_CLIENT_BLKID_cb000 = 0x3b,
192 DBG_CLIENT_BLKID_cb101 = 0x3c,
193 DBG_CLIENT_BLKID_cb300 = 0x3d,
194 DBG_CLIENT_BLKID_cb301 = 0x3e,
195 DBG_CLIENT_BLKID_cbr1 = 0x3f,
196 DBG_CLIENT_BLKID_cb100 = 0x40,
197 DBG_CLIENT_BLKID_ia0 = 0x41,
198 DBG_CLIENT_BLKID_ia1 = 0x42,
199 DBG_CLIENT_BLKID_bci0 = 0x43,
200 DBG_CLIENT_BLKID_bci1 = 0x44,
201 DBG_CLIENT_BLKID_bci2 = 0x45,
202 DBG_CLIENT_BLKID_bci3 = 0x46,
203 DBG_CLIENT_BLKID_pa0 = 0x47,
204 DBG_CLIENT_BLKID_pa1 = 0x48,
205 DBG_CLIENT_BLKID_spim0 = 0x49,
206 DBG_CLIENT_BLKID_spim1 = 0x4a,
207 DBG_CLIENT_BLKID_spim2 = 0x4b,
208 DBG_CLIENT_BLKID_spim3 = 0x4c,
209 DBG_CLIENT_BLKID_sdma = 0x4d,
210 DBG_CLIENT_BLKID_ih = 0x4e,
211 DBG_CLIENT_BLKID_sem = 0x4f,
212 DBG_CLIENT_BLKID_srbm = 0x50,
213 DBG_CLIENT_BLKID_hdp = 0x51,
214 DBG_CLIENT_BLKID_acp_0 = 0x52,
215 DBG_CLIENT_BLKID_acp_1 = 0x53,
216 DBG_CLIENT_BLKID_sam = 0x54,
217 DBG_CLIENT_BLKID_mcc0 = 0x55,
218 DBG_CLIENT_BLKID_mcc1 = 0x56,
219 DBG_CLIENT_BLKID_mcc2 = 0x57,
220 DBG_CLIENT_BLKID_mcc3 = 0x58,
221 DBG_CLIENT_BLKID_mcd0 = 0x59,
222 DBG_CLIENT_BLKID_mcd1 = 0x5a,
223 DBG_CLIENT_BLKID_mcd2 = 0x5b,
224 DBG_CLIENT_BLKID_mcd3 = 0x5c,
225 DBG_CLIENT_BLKID_mcb = 0x5d,
226 DBG_CLIENT_BLKID_vmc = 0x5e,
227 DBG_CLIENT_BLKID_gmcon = 0x5f,
228 DBG_CLIENT_BLKID_gdc_0 = 0x60,
229 DBG_CLIENT_BLKID_gdc_1 = 0x61,
230 DBG_CLIENT_BLKID_gdc_2 = 0x62,
231 DBG_CLIENT_BLKID_gdc_3 = 0x63,
232 DBG_CLIENT_BLKID_gdc_4 = 0x64,
233 DBG_CLIENT_BLKID_gdc_5 = 0x65,
234 DBG_CLIENT_BLKID_gdc_6 = 0x66,
235 DBG_CLIENT_BLKID_gdc_7 = 0x67,
236 DBG_CLIENT_BLKID_gdc_8 = 0x68,
237 DBG_CLIENT_BLKID_gdc_9 = 0x69,
238 DBG_CLIENT_BLKID_gdc_10 = 0x6a,
239 DBG_CLIENT_BLKID_gdc_11 = 0x6b,
240 DBG_CLIENT_BLKID_gdc_12 = 0x6c,
241 DBG_CLIENT_BLKID_gdc_13 = 0x6d,
242 DBG_CLIENT_BLKID_gdc_14 = 0x6e,
243 DBG_CLIENT_BLKID_gdc_15 = 0x6f,
244 DBG_CLIENT_BLKID_gdc_16 = 0x70,
245 DBG_CLIENT_BLKID_gdc_17 = 0x71,
246 DBG_CLIENT_BLKID_gdc_18 = 0x72,
247 DBG_CLIENT_BLKID_gdc_19 = 0x73,
248 DBG_CLIENT_BLKID_gdc_20 = 0x74,
249 DBG_CLIENT_BLKID_gdc_21 = 0x75,
250 DBG_CLIENT_BLKID_gdc_22 = 0x76,
251 DBG_CLIENT_BLKID_wd = 0x77,
252 DBG_CLIENT_BLKID_sdma_0 = 0x78,
253 DBG_CLIENT_BLKID_sdma_1 = 0x79,
254} DebugBlockId;
255typedef enum DebugBlockId_OLD {
256 DBG_BLOCK_ID_RESERVED = 0x0,
257 DBG_BLOCK_ID_DBG = 0x1,
258 DBG_BLOCK_ID_VMC = 0x2,
259 DBG_BLOCK_ID_PDMA = 0x3,
260 DBG_BLOCK_ID_CG = 0x4,
261 DBG_BLOCK_ID_SRBM = 0x5,
262 DBG_BLOCK_ID_GRBM = 0x6,
263 DBG_BLOCK_ID_RLC = 0x7,
264 DBG_BLOCK_ID_CSC = 0x8,
265 DBG_BLOCK_ID_SEM = 0x9,
266 DBG_BLOCK_ID_IH = 0xa,
267 DBG_BLOCK_ID_SC = 0xb,
268 DBG_BLOCK_ID_SQ = 0xc,
269 DBG_BLOCK_ID_AVP = 0xd,
270 DBG_BLOCK_ID_GMCON = 0xe,
271 DBG_BLOCK_ID_SMU = 0xf,
272 DBG_BLOCK_ID_DMA0 = 0x10,
273 DBG_BLOCK_ID_DMA1 = 0x11,
274 DBG_BLOCK_ID_SPIM = 0x12,
275 DBG_BLOCK_ID_GDS = 0x13,
276 DBG_BLOCK_ID_SPIS = 0x14,
277 DBG_BLOCK_ID_UNUSED0 = 0x15,
278 DBG_BLOCK_ID_PA0 = 0x16,
279 DBG_BLOCK_ID_PA1 = 0x17,
280 DBG_BLOCK_ID_CP0 = 0x18,
281 DBG_BLOCK_ID_CP1 = 0x19,
282 DBG_BLOCK_ID_CP2 = 0x1a,
283 DBG_BLOCK_ID_UNUSED1 = 0x1b,
284 DBG_BLOCK_ID_UVDU = 0x1c,
285 DBG_BLOCK_ID_UVDM = 0x1d,
286 DBG_BLOCK_ID_VCE = 0x1e,
287 DBG_BLOCK_ID_UNUSED2 = 0x1f,
288 DBG_BLOCK_ID_VGT0 = 0x20,
289 DBG_BLOCK_ID_VGT1 = 0x21,
290 DBG_BLOCK_ID_IA = 0x22,
291 DBG_BLOCK_ID_UNUSED3 = 0x23,
292 DBG_BLOCK_ID_SCT0 = 0x24,
293 DBG_BLOCK_ID_SCT1 = 0x25,
294 DBG_BLOCK_ID_SPM0 = 0x26,
295 DBG_BLOCK_ID_SPM1 = 0x27,
296 DBG_BLOCK_ID_TCAA = 0x28,
297 DBG_BLOCK_ID_TCAB = 0x29,
298 DBG_BLOCK_ID_TCCA = 0x2a,
299 DBG_BLOCK_ID_TCCB = 0x2b,
300 DBG_BLOCK_ID_MCC0 = 0x2c,
301 DBG_BLOCK_ID_MCC1 = 0x2d,
302 DBG_BLOCK_ID_MCC2 = 0x2e,
303 DBG_BLOCK_ID_MCC3 = 0x2f,
304 DBG_BLOCK_ID_SX0 = 0x30,
305 DBG_BLOCK_ID_SX1 = 0x31,
306 DBG_BLOCK_ID_SX2 = 0x32,
307 DBG_BLOCK_ID_SX3 = 0x33,
308 DBG_BLOCK_ID_UNUSED4 = 0x34,
309 DBG_BLOCK_ID_UNUSED5 = 0x35,
310 DBG_BLOCK_ID_UNUSED6 = 0x36,
311 DBG_BLOCK_ID_UNUSED7 = 0x37,
312 DBG_BLOCK_ID_PC0 = 0x38,
313 DBG_BLOCK_ID_PC1 = 0x39,
314 DBG_BLOCK_ID_UNUSED8 = 0x3a,
315 DBG_BLOCK_ID_UNUSED9 = 0x3b,
316 DBG_BLOCK_ID_UNUSED10 = 0x3c,
317 DBG_BLOCK_ID_UNUSED11 = 0x3d,
318 DBG_BLOCK_ID_MCB = 0x3e,
319 DBG_BLOCK_ID_UNUSED12 = 0x3f,
320 DBG_BLOCK_ID_SCB0 = 0x40,
321 DBG_BLOCK_ID_SCB1 = 0x41,
322 DBG_BLOCK_ID_UNUSED13 = 0x42,
323 DBG_BLOCK_ID_UNUSED14 = 0x43,
324 DBG_BLOCK_ID_SCF0 = 0x44,
325 DBG_BLOCK_ID_SCF1 = 0x45,
326 DBG_BLOCK_ID_UNUSED15 = 0x46,
327 DBG_BLOCK_ID_UNUSED16 = 0x47,
328 DBG_BLOCK_ID_BCI0 = 0x48,
329 DBG_BLOCK_ID_BCI1 = 0x49,
330 DBG_BLOCK_ID_BCI2 = 0x4a,
331 DBG_BLOCK_ID_BCI3 = 0x4b,
332 DBG_BLOCK_ID_UNUSED17 = 0x4c,
333 DBG_BLOCK_ID_UNUSED18 = 0x4d,
334 DBG_BLOCK_ID_UNUSED19 = 0x4e,
335 DBG_BLOCK_ID_UNUSED20 = 0x4f,
336 DBG_BLOCK_ID_CB00 = 0x50,
337 DBG_BLOCK_ID_CB01 = 0x51,
338 DBG_BLOCK_ID_CB02 = 0x52,
339 DBG_BLOCK_ID_CB03 = 0x53,
340 DBG_BLOCK_ID_CB04 = 0x54,
341 DBG_BLOCK_ID_UNUSED21 = 0x55,
342 DBG_BLOCK_ID_UNUSED22 = 0x56,
343 DBG_BLOCK_ID_UNUSED23 = 0x57,
344 DBG_BLOCK_ID_CB10 = 0x58,
345 DBG_BLOCK_ID_CB11 = 0x59,
346 DBG_BLOCK_ID_CB12 = 0x5a,
347 DBG_BLOCK_ID_CB13 = 0x5b,
348 DBG_BLOCK_ID_CB14 = 0x5c,
349 DBG_BLOCK_ID_UNUSED24 = 0x5d,
350 DBG_BLOCK_ID_UNUSED25 = 0x5e,
351 DBG_BLOCK_ID_UNUSED26 = 0x5f,
352 DBG_BLOCK_ID_TCP0 = 0x60,
353 DBG_BLOCK_ID_TCP1 = 0x61,
354 DBG_BLOCK_ID_TCP2 = 0x62,
355 DBG_BLOCK_ID_TCP3 = 0x63,
356 DBG_BLOCK_ID_TCP4 = 0x64,
357 DBG_BLOCK_ID_TCP5 = 0x65,
358 DBG_BLOCK_ID_TCP6 = 0x66,
359 DBG_BLOCK_ID_TCP7 = 0x67,
360 DBG_BLOCK_ID_TCP8 = 0x68,
361 DBG_BLOCK_ID_TCP9 = 0x69,
362 DBG_BLOCK_ID_TCP10 = 0x6a,
363 DBG_BLOCK_ID_TCP11 = 0x6b,
364 DBG_BLOCK_ID_TCP12 = 0x6c,
365 DBG_BLOCK_ID_TCP13 = 0x6d,
366 DBG_BLOCK_ID_TCP14 = 0x6e,
367 DBG_BLOCK_ID_TCP15 = 0x6f,
368 DBG_BLOCK_ID_TCP16 = 0x70,
369 DBG_BLOCK_ID_TCP17 = 0x71,
370 DBG_BLOCK_ID_TCP18 = 0x72,
371 DBG_BLOCK_ID_TCP19 = 0x73,
372 DBG_BLOCK_ID_TCP20 = 0x74,
373 DBG_BLOCK_ID_TCP21 = 0x75,
374 DBG_BLOCK_ID_TCP22 = 0x76,
375 DBG_BLOCK_ID_TCP23 = 0x77,
376 DBG_BLOCK_ID_TCP_RESERVED0 = 0x78,
377 DBG_BLOCK_ID_TCP_RESERVED1 = 0x79,
378 DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a,
379 DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b,
380 DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c,
381 DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d,
382 DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e,
383 DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f,
384 DBG_BLOCK_ID_DB00 = 0x80,
385 DBG_BLOCK_ID_DB01 = 0x81,
386 DBG_BLOCK_ID_DB02 = 0x82,
387 DBG_BLOCK_ID_DB03 = 0x83,
388 DBG_BLOCK_ID_DB04 = 0x84,
389 DBG_BLOCK_ID_UNUSED27 = 0x85,
390 DBG_BLOCK_ID_UNUSED28 = 0x86,
391 DBG_BLOCK_ID_UNUSED29 = 0x87,
392 DBG_BLOCK_ID_DB10 = 0x88,
393 DBG_BLOCK_ID_DB11 = 0x89,
394 DBG_BLOCK_ID_DB12 = 0x8a,
395 DBG_BLOCK_ID_DB13 = 0x8b,
396 DBG_BLOCK_ID_DB14 = 0x8c,
397 DBG_BLOCK_ID_UNUSED30 = 0x8d,
398 DBG_BLOCK_ID_UNUSED31 = 0x8e,
399 DBG_BLOCK_ID_UNUSED32 = 0x8f,
400 DBG_BLOCK_ID_TCC0 = 0x90,
401 DBG_BLOCK_ID_TCC1 = 0x91,
402 DBG_BLOCK_ID_TCC2 = 0x92,
403 DBG_BLOCK_ID_TCC3 = 0x93,
404 DBG_BLOCK_ID_TCC4 = 0x94,
405 DBG_BLOCK_ID_TCC5 = 0x95,
406 DBG_BLOCK_ID_TCC6 = 0x96,
407 DBG_BLOCK_ID_TCC7 = 0x97,
408 DBG_BLOCK_ID_SPS00 = 0x98,
409 DBG_BLOCK_ID_SPS01 = 0x99,
410 DBG_BLOCK_ID_SPS02 = 0x9a,
411 DBG_BLOCK_ID_SPS10 = 0x9b,
412 DBG_BLOCK_ID_SPS11 = 0x9c,
413 DBG_BLOCK_ID_SPS12 = 0x9d,
414 DBG_BLOCK_ID_UNUSED33 = 0x9e,
415 DBG_BLOCK_ID_UNUSED34 = 0x9f,
416 DBG_BLOCK_ID_TA00 = 0xa0,
417 DBG_BLOCK_ID_TA01 = 0xa1,
418 DBG_BLOCK_ID_TA02 = 0xa2,
419 DBG_BLOCK_ID_TA03 = 0xa3,
420 DBG_BLOCK_ID_TA04 = 0xa4,
421 DBG_BLOCK_ID_TA05 = 0xa5,
422 DBG_BLOCK_ID_TA06 = 0xa6,
423 DBG_BLOCK_ID_TA07 = 0xa7,
424 DBG_BLOCK_ID_TA08 = 0xa8,
425 DBG_BLOCK_ID_TA09 = 0xa9,
426 DBG_BLOCK_ID_TA0A = 0xaa,
427 DBG_BLOCK_ID_TA0B = 0xab,
428 DBG_BLOCK_ID_UNUSED35 = 0xac,
429 DBG_BLOCK_ID_UNUSED36 = 0xad,
430 DBG_BLOCK_ID_UNUSED37 = 0xae,
431 DBG_BLOCK_ID_UNUSED38 = 0xaf,
432 DBG_BLOCK_ID_TA10 = 0xb0,
433 DBG_BLOCK_ID_TA11 = 0xb1,
434 DBG_BLOCK_ID_TA12 = 0xb2,
435 DBG_BLOCK_ID_TA13 = 0xb3,
436 DBG_BLOCK_ID_TA14 = 0xb4,
437 DBG_BLOCK_ID_TA15 = 0xb5,
438 DBG_BLOCK_ID_TA16 = 0xb6,
439 DBG_BLOCK_ID_TA17 = 0xb7,
440 DBG_BLOCK_ID_TA18 = 0xb8,
441 DBG_BLOCK_ID_TA19 = 0xb9,
442 DBG_BLOCK_ID_TA1A = 0xba,
443 DBG_BLOCK_ID_TA1B = 0xbb,
444 DBG_BLOCK_ID_UNUSED39 = 0xbc,
445 DBG_BLOCK_ID_UNUSED40 = 0xbd,
446 DBG_BLOCK_ID_UNUSED41 = 0xbe,
447 DBG_BLOCK_ID_UNUSED42 = 0xbf,
448 DBG_BLOCK_ID_TD00 = 0xc0,
449 DBG_BLOCK_ID_TD01 = 0xc1,
450 DBG_BLOCK_ID_TD02 = 0xc2,
451 DBG_BLOCK_ID_TD03 = 0xc3,
452 DBG_BLOCK_ID_TD04 = 0xc4,
453 DBG_BLOCK_ID_TD05 = 0xc5,
454 DBG_BLOCK_ID_TD06 = 0xc6,
455 DBG_BLOCK_ID_TD07 = 0xc7,
456 DBG_BLOCK_ID_TD08 = 0xc8,
457 DBG_BLOCK_ID_TD09 = 0xc9,
458 DBG_BLOCK_ID_TD0A = 0xca,
459 DBG_BLOCK_ID_TD0B = 0xcb,
460 DBG_BLOCK_ID_UNUSED43 = 0xcc,
461 DBG_BLOCK_ID_UNUSED44 = 0xcd,
462 DBG_BLOCK_ID_UNUSED45 = 0xce,
463 DBG_BLOCK_ID_UNUSED46 = 0xcf,
464 DBG_BLOCK_ID_TD10 = 0xd0,
465 DBG_BLOCK_ID_TD11 = 0xd1,
466 DBG_BLOCK_ID_TD12 = 0xd2,
467 DBG_BLOCK_ID_TD13 = 0xd3,
468 DBG_BLOCK_ID_TD14 = 0xd4,
469 DBG_BLOCK_ID_TD15 = 0xd5,
470 DBG_BLOCK_ID_TD16 = 0xd6,
471 DBG_BLOCK_ID_TD17 = 0xd7,
472 DBG_BLOCK_ID_TD18 = 0xd8,
473 DBG_BLOCK_ID_TD19 = 0xd9,
474 DBG_BLOCK_ID_TD1A = 0xda,
475 DBG_BLOCK_ID_TD1B = 0xdb,
476 DBG_BLOCK_ID_UNUSED47 = 0xdc,
477 DBG_BLOCK_ID_UNUSED48 = 0xdd,
478 DBG_BLOCK_ID_UNUSED49 = 0xde,
479 DBG_BLOCK_ID_UNUSED50 = 0xdf,
480 DBG_BLOCK_ID_MCD0 = 0xe0,
481 DBG_BLOCK_ID_MCD1 = 0xe1,
482 DBG_BLOCK_ID_MCD2 = 0xe2,
483 DBG_BLOCK_ID_MCD3 = 0xe3,
484 DBG_BLOCK_ID_MCD4 = 0xe4,
485 DBG_BLOCK_ID_MCD5 = 0xe5,
486 DBG_BLOCK_ID_UNUSED51 = 0xe6,
487 DBG_BLOCK_ID_UNUSED52 = 0xe7,
488} DebugBlockId_OLD;
489typedef enum DebugBlockId_BY2 {
490 DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
491 DBG_BLOCK_ID_VMC_BY2 = 0x1,
492 DBG_BLOCK_ID_CG_BY2 = 0x2,
493 DBG_BLOCK_ID_GRBM_BY2 = 0x3,
494 DBG_BLOCK_ID_CSC_BY2 = 0x4,
495 DBG_BLOCK_ID_IH_BY2 = 0x5,
496 DBG_BLOCK_ID_SQ_BY2 = 0x6,
497 DBG_BLOCK_ID_GMCON_BY2 = 0x7,
498 DBG_BLOCK_ID_DMA0_BY2 = 0x8,
499 DBG_BLOCK_ID_SPIM_BY2 = 0x9,
500 DBG_BLOCK_ID_SPIS_BY2 = 0xa,
501 DBG_BLOCK_ID_PA0_BY2 = 0xb,
502 DBG_BLOCK_ID_CP0_BY2 = 0xc,
503 DBG_BLOCK_ID_CP2_BY2 = 0xd,
504 DBG_BLOCK_ID_UVDU_BY2 = 0xe,
505 DBG_BLOCK_ID_VCE_BY2 = 0xf,
506 DBG_BLOCK_ID_VGT0_BY2 = 0x10,
507 DBG_BLOCK_ID_IA_BY2 = 0x11,
508 DBG_BLOCK_ID_SCT0_BY2 = 0x12,
509 DBG_BLOCK_ID_SPM0_BY2 = 0x13,
510 DBG_BLOCK_ID_TCAA_BY2 = 0x14,
511 DBG_BLOCK_ID_TCCA_BY2 = 0x15,
512 DBG_BLOCK_ID_MCC0_BY2 = 0x16,
513 DBG_BLOCK_ID_MCC2_BY2 = 0x17,
514 DBG_BLOCK_ID_SX0_BY2 = 0x18,
515 DBG_BLOCK_ID_SX2_BY2 = 0x19,
516 DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a,
517 DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b,
518 DBG_BLOCK_ID_PC0_BY2 = 0x1c,
519 DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d,
520 DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e,
521 DBG_BLOCK_ID_MCB_BY2 = 0x1f,
522 DBG_BLOCK_ID_SCB0_BY2 = 0x20,
523 DBG_BLOCK_ID_UNUSED13_BY2 = 0x21,
524 DBG_BLOCK_ID_SCF0_BY2 = 0x22,
525 DBG_BLOCK_ID_UNUSED15_BY2 = 0x23,
526 DBG_BLOCK_ID_BCI0_BY2 = 0x24,
527 DBG_BLOCK_ID_BCI2_BY2 = 0x25,
528 DBG_BLOCK_ID_UNUSED17_BY2 = 0x26,
529 DBG_BLOCK_ID_UNUSED19_BY2 = 0x27,
530 DBG_BLOCK_ID_CB00_BY2 = 0x28,
531 DBG_BLOCK_ID_CB02_BY2 = 0x29,
532 DBG_BLOCK_ID_CB04_BY2 = 0x2a,
533 DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b,
534 DBG_BLOCK_ID_CB10_BY2 = 0x2c,
535 DBG_BLOCK_ID_CB12_BY2 = 0x2d,
536 DBG_BLOCK_ID_CB14_BY2 = 0x2e,
537 DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f,
538 DBG_BLOCK_ID_TCP0_BY2 = 0x30,
539 DBG_BLOCK_ID_TCP2_BY2 = 0x31,
540 DBG_BLOCK_ID_TCP4_BY2 = 0x32,
541 DBG_BLOCK_ID_TCP6_BY2 = 0x33,
542 DBG_BLOCK_ID_TCP8_BY2 = 0x34,
543 DBG_BLOCK_ID_TCP10_BY2 = 0x35,
544 DBG_BLOCK_ID_TCP12_BY2 = 0x36,
545 DBG_BLOCK_ID_TCP14_BY2 = 0x37,
546 DBG_BLOCK_ID_TCP16_BY2 = 0x38,
547 DBG_BLOCK_ID_TCP18_BY2 = 0x39,
548 DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
549 DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
550 DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
551 DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
552 DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
553 DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
554 DBG_BLOCK_ID_DB00_BY2 = 0x40,
555 DBG_BLOCK_ID_DB02_BY2 = 0x41,
556 DBG_BLOCK_ID_DB04_BY2 = 0x42,
557 DBG_BLOCK_ID_UNUSED28_BY2 = 0x43,
558 DBG_BLOCK_ID_DB10_BY2 = 0x44,
559 DBG_BLOCK_ID_DB12_BY2 = 0x45,
560 DBG_BLOCK_ID_DB14_BY2 = 0x46,
561 DBG_BLOCK_ID_UNUSED31_BY2 = 0x47,
562 DBG_BLOCK_ID_TCC0_BY2 = 0x48,
563 DBG_BLOCK_ID_TCC2_BY2 = 0x49,
564 DBG_BLOCK_ID_TCC4_BY2 = 0x4a,
565 DBG_BLOCK_ID_TCC6_BY2 = 0x4b,
566 DBG_BLOCK_ID_SPS00_BY2 = 0x4c,
567 DBG_BLOCK_ID_SPS02_BY2 = 0x4d,
568 DBG_BLOCK_ID_SPS11_BY2 = 0x4e,
569 DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f,
570 DBG_BLOCK_ID_TA00_BY2 = 0x50,
571 DBG_BLOCK_ID_TA02_BY2 = 0x51,
572 DBG_BLOCK_ID_TA04_BY2 = 0x52,
573 DBG_BLOCK_ID_TA06_BY2 = 0x53,
574 DBG_BLOCK_ID_TA08_BY2 = 0x54,
575 DBG_BLOCK_ID_TA0A_BY2 = 0x55,
576 DBG_BLOCK_ID_UNUSED35_BY2 = 0x56,
577 DBG_BLOCK_ID_UNUSED37_BY2 = 0x57,
578 DBG_BLOCK_ID_TA10_BY2 = 0x58,
579 DBG_BLOCK_ID_TA12_BY2 = 0x59,
580 DBG_BLOCK_ID_TA14_BY2 = 0x5a,
581 DBG_BLOCK_ID_TA16_BY2 = 0x5b,
582 DBG_BLOCK_ID_TA18_BY2 = 0x5c,
583 DBG_BLOCK_ID_TA1A_BY2 = 0x5d,
584 DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e,
585 DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f,
586 DBG_BLOCK_ID_TD00_BY2 = 0x60,
587 DBG_BLOCK_ID_TD02_BY2 = 0x61,
588 DBG_BLOCK_ID_TD04_BY2 = 0x62,
589 DBG_BLOCK_ID_TD06_BY2 = 0x63,
590 DBG_BLOCK_ID_TD08_BY2 = 0x64,
591 DBG_BLOCK_ID_TD0A_BY2 = 0x65,
592 DBG_BLOCK_ID_UNUSED43_BY2 = 0x66,
593 DBG_BLOCK_ID_UNUSED45_BY2 = 0x67,
594 DBG_BLOCK_ID_TD10_BY2 = 0x68,
595 DBG_BLOCK_ID_TD12_BY2 = 0x69,
596 DBG_BLOCK_ID_TD14_BY2 = 0x6a,
597 DBG_BLOCK_ID_TD16_BY2 = 0x6b,
598 DBG_BLOCK_ID_TD18_BY2 = 0x6c,
599 DBG_BLOCK_ID_TD1A_BY2 = 0x6d,
600 DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e,
601 DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f,
602 DBG_BLOCK_ID_MCD0_BY2 = 0x70,
603 DBG_BLOCK_ID_MCD2_BY2 = 0x71,
604 DBG_BLOCK_ID_MCD4_BY2 = 0x72,
605 DBG_BLOCK_ID_UNUSED51_BY2 = 0x73,
606} DebugBlockId_BY2;
607typedef enum DebugBlockId_BY4 {
608 DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
609 DBG_BLOCK_ID_CG_BY4 = 0x1,
610 DBG_BLOCK_ID_CSC_BY4 = 0x2,
611 DBG_BLOCK_ID_SQ_BY4 = 0x3,
612 DBG_BLOCK_ID_DMA0_BY4 = 0x4,
613 DBG_BLOCK_ID_SPIS_BY4 = 0x5,
614 DBG_BLOCK_ID_CP0_BY4 = 0x6,
615 DBG_BLOCK_ID_UVDU_BY4 = 0x7,
616 DBG_BLOCK_ID_VGT0_BY4 = 0x8,
617 DBG_BLOCK_ID_SCT0_BY4 = 0x9,
618 DBG_BLOCK_ID_TCAA_BY4 = 0xa,
619 DBG_BLOCK_ID_MCC0_BY4 = 0xb,
620 DBG_BLOCK_ID_SX0_BY4 = 0xc,
621 DBG_BLOCK_ID_UNUSED4_BY4 = 0xd,
622 DBG_BLOCK_ID_PC0_BY4 = 0xe,
623 DBG_BLOCK_ID_UNUSED10_BY4 = 0xf,
624 DBG_BLOCK_ID_SCB0_BY4 = 0x10,
625 DBG_BLOCK_ID_SCF0_BY4 = 0x11,
626 DBG_BLOCK_ID_BCI0_BY4 = 0x12,
627 DBG_BLOCK_ID_UNUSED17_BY4 = 0x13,
628 DBG_BLOCK_ID_CB00_BY4 = 0x14,
629 DBG_BLOCK_ID_CB04_BY4 = 0x15,
630 DBG_BLOCK_ID_CB10_BY4 = 0x16,
631 DBG_BLOCK_ID_CB14_BY4 = 0x17,
632 DBG_BLOCK_ID_TCP0_BY4 = 0x18,
633 DBG_BLOCK_ID_TCP4_BY4 = 0x19,
634 DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
635 DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
636 DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
637 DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
638 DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
639 DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
640 DBG_BLOCK_ID_DB_BY4 = 0x20,
641 DBG_BLOCK_ID_DB04_BY4 = 0x21,
642 DBG_BLOCK_ID_DB10_BY4 = 0x22,
643 DBG_BLOCK_ID_DB14_BY4 = 0x23,
644 DBG_BLOCK_ID_TCC0_BY4 = 0x24,
645 DBG_BLOCK_ID_TCC4_BY4 = 0x25,
646 DBG_BLOCK_ID_SPS00_BY4 = 0x26,
647 DBG_BLOCK_ID_SPS11_BY4 = 0x27,
648 DBG_BLOCK_ID_TA00_BY4 = 0x28,
649 DBG_BLOCK_ID_TA04_BY4 = 0x29,
650 DBG_BLOCK_ID_TA08_BY4 = 0x2a,
651 DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b,
652 DBG_BLOCK_ID_TA10_BY4 = 0x2c,
653 DBG_BLOCK_ID_TA14_BY4 = 0x2d,
654 DBG_BLOCK_ID_TA18_BY4 = 0x2e,
655 DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f,
656 DBG_BLOCK_ID_TD00_BY4 = 0x30,
657 DBG_BLOCK_ID_TD04_BY4 = 0x31,
658 DBG_BLOCK_ID_TD08_BY4 = 0x32,
659 DBG_BLOCK_ID_UNUSED43_BY4 = 0x33,
660 DBG_BLOCK_ID_TD10_BY4 = 0x34,
661 DBG_BLOCK_ID_TD14_BY4 = 0x35,
662 DBG_BLOCK_ID_TD18_BY4 = 0x36,
663 DBG_BLOCK_ID_UNUSED47_BY4 = 0x37,
664 DBG_BLOCK_ID_MCD0_BY4 = 0x38,
665 DBG_BLOCK_ID_MCD4_BY4 = 0x39,
666} DebugBlockId_BY4;
667typedef enum DebugBlockId_BY8 {
668 DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
669 DBG_BLOCK_ID_CSC_BY8 = 0x1,
670 DBG_BLOCK_ID_DMA0_BY8 = 0x2,
671 DBG_BLOCK_ID_CP0_BY8 = 0x3,
672 DBG_BLOCK_ID_VGT0_BY8 = 0x4,
673 DBG_BLOCK_ID_TCAA_BY8 = 0x5,
674 DBG_BLOCK_ID_SX0_BY8 = 0x6,
675 DBG_BLOCK_ID_PC0_BY8 = 0x7,
676 DBG_BLOCK_ID_SCB0_BY8 = 0x8,
677 DBG_BLOCK_ID_BCI0_BY8 = 0x9,
678 DBG_BLOCK_ID_CB00_BY8 = 0xa,
679 DBG_BLOCK_ID_CB10_BY8 = 0xb,
680 DBG_BLOCK_ID_TCP0_BY8 = 0xc,
681 DBG_BLOCK_ID_TCP8_BY8 = 0xd,
682 DBG_BLOCK_ID_TCP16_BY8 = 0xe,
683 DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
684 DBG_BLOCK_ID_DB00_BY8 = 0x10,
685 DBG_BLOCK_ID_DB10_BY8 = 0x11,
686 DBG_BLOCK_ID_TCC0_BY8 = 0x12,
687 DBG_BLOCK_ID_SPS00_BY8 = 0x13,
688 DBG_BLOCK_ID_TA00_BY8 = 0x14,
689 DBG_BLOCK_ID_TA08_BY8 = 0x15,
690 DBG_BLOCK_ID_TA10_BY8 = 0x16,
691 DBG_BLOCK_ID_TA18_BY8 = 0x17,
692 DBG_BLOCK_ID_TD00_BY8 = 0x18,
693 DBG_BLOCK_ID_TD08_BY8 = 0x19,
694 DBG_BLOCK_ID_TD10_BY8 = 0x1a,
695 DBG_BLOCK_ID_TD18_BY8 = 0x1b,
696 DBG_BLOCK_ID_MCD0_BY8 = 0x1c,
697} DebugBlockId_BY8;
698typedef enum DebugBlockId_BY16 {
699 DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
700 DBG_BLOCK_ID_DMA0_BY16 = 0x1,
701 DBG_BLOCK_ID_VGT0_BY16 = 0x2,
702 DBG_BLOCK_ID_SX0_BY16 = 0x3,
703 DBG_BLOCK_ID_SCB0_BY16 = 0x4,
704 DBG_BLOCK_ID_CB00_BY16 = 0x5,
705 DBG_BLOCK_ID_TCP0_BY16 = 0x6,
706 DBG_BLOCK_ID_TCP16_BY16 = 0x7,
707 DBG_BLOCK_ID_DB00_BY16 = 0x8,
708 DBG_BLOCK_ID_TCC0_BY16 = 0x9,
709 DBG_BLOCK_ID_TA00_BY16 = 0xa,
710 DBG_BLOCK_ID_TA10_BY16 = 0xb,
711 DBG_BLOCK_ID_TD00_BY16 = 0xc,
712 DBG_BLOCK_ID_TD10_BY16 = 0xd,
713 DBG_BLOCK_ID_MCD0_BY16 = 0xe,
714} DebugBlockId_BY16;
715typedef enum CompareRef {
716 REF_NEVER = 0x0,
717 REF_LESS = 0x1,
718 REF_EQUAL = 0x2,
719 REF_LEQUAL = 0x3,
720 REF_GREATER = 0x4,
721 REF_NOTEQUAL = 0x5,
722 REF_GEQUAL = 0x6,
723 REF_ALWAYS = 0x7,
724} CompareRef;
725typedef enum ReadSize {
726 READ_256_BITS = 0x0,
727 READ_512_BITS = 0x1,
728} ReadSize;
729typedef enum DepthFormat {
730 DEPTH_INVALID = 0x0,
731 DEPTH_16 = 0x1,
732 DEPTH_X8_24 = 0x2,
733 DEPTH_8_24 = 0x3,
734 DEPTH_X8_24_FLOAT = 0x4,
735 DEPTH_8_24_FLOAT = 0x5,
736 DEPTH_32_FLOAT = 0x6,
737 DEPTH_X24_8_32_FLOAT = 0x7,
738} DepthFormat;
739typedef enum ZFormat {
740 Z_INVALID = 0x0,
741 Z_16 = 0x1,
742 Z_24 = 0x2,
743 Z_32_FLOAT = 0x3,
744} ZFormat;
745typedef enum StencilFormat {
746 STENCIL_INVALID = 0x0,
747 STENCIL_8 = 0x1,
748} StencilFormat;
749typedef enum CmaskMode {
750 CMASK_CLEAR_NONE = 0x0,
751 CMASK_CLEAR_ONE = 0x1,
752 CMASK_CLEAR_ALL = 0x2,
753 CMASK_ANY_EXPANDED = 0x3,
754 CMASK_ALPHA0_FRAG1 = 0x4,
755 CMASK_ALPHA0_FRAG2 = 0x5,
756 CMASK_ALPHA0_FRAG4 = 0x6,
757 CMASK_ALPHA0_FRAGS = 0x7,
758 CMASK_ALPHA1_FRAG1 = 0x8,
759 CMASK_ALPHA1_FRAG2 = 0x9,
760 CMASK_ALPHA1_FRAG4 = 0xa,
761 CMASK_ALPHA1_FRAGS = 0xb,
762 CMASK_ALPHAX_FRAG1 = 0xc,
763 CMASK_ALPHAX_FRAG2 = 0xd,
764 CMASK_ALPHAX_FRAG4 = 0xe,
765 CMASK_ALPHAX_FRAGS = 0xf,
766} CmaskMode;
767typedef enum QuadExportFormat {
768 EXPORT_UNUSED = 0x0,
769 EXPORT_32_R = 0x1,
770 EXPORT_32_GR = 0x2,
771 EXPORT_32_AR = 0x3,
772 EXPORT_FP16_ABGR = 0x4,
773 EXPORT_UNSIGNED16_ABGR = 0x5,
774 EXPORT_SIGNED16_ABGR = 0x6,
775 EXPORT_32_ABGR = 0x7,
776} QuadExportFormat;
777typedef enum QuadExportFormatOld {
778 EXPORT_4P_32BPC_ABGR = 0x0,
779 EXPORT_4P_16BPC_ABGR = 0x1,
780 EXPORT_4P_32BPC_GR = 0x2,
781 EXPORT_4P_32BPC_AR = 0x3,
782 EXPORT_2P_32BPC_ABGR = 0x4,
783 EXPORT_8P_32BPC_R = 0x5,
784} QuadExportFormatOld;
785typedef enum ColorFormat {
786 COLOR_INVALID = 0x0,
787 COLOR_8 = 0x1,
788 COLOR_16 = 0x2,
789 COLOR_8_8 = 0x3,
790 COLOR_32 = 0x4,
791 COLOR_16_16 = 0x5,
792 COLOR_10_11_11 = 0x6,
793 COLOR_11_11_10 = 0x7,
794 COLOR_10_10_10_2 = 0x8,
795 COLOR_2_10_10_10 = 0x9,
796 COLOR_8_8_8_8 = 0xa,
797 COLOR_32_32 = 0xb,
798 COLOR_16_16_16_16 = 0xc,
799 COLOR_RESERVED_13 = 0xd,
800 COLOR_32_32_32_32 = 0xe,
801 COLOR_RESERVED_15 = 0xf,
802 COLOR_5_6_5 = 0x10,
803 COLOR_1_5_5_5 = 0x11,
804 COLOR_5_5_5_1 = 0x12,
805 COLOR_4_4_4_4 = 0x13,
806 COLOR_8_24 = 0x14,
807 COLOR_24_8 = 0x15,
808 COLOR_X24_8_32_FLOAT = 0x16,
809 COLOR_RESERVED_23 = 0x17,
810} ColorFormat;
811typedef enum SurfaceFormat {
812 FMT_INVALID = 0x0,
813 FMT_8 = 0x1,
814 FMT_16 = 0x2,
815 FMT_8_8 = 0x3,
816 FMT_32 = 0x4,
817 FMT_16_16 = 0x5,
818 FMT_10_11_11 = 0x6,
819 FMT_11_11_10 = 0x7,
820 FMT_10_10_10_2 = 0x8,
821 FMT_2_10_10_10 = 0x9,
822 FMT_8_8_8_8 = 0xa,
823 FMT_32_32 = 0xb,
824 FMT_16_16_16_16 = 0xc,
825 FMT_32_32_32 = 0xd,
826 FMT_32_32_32_32 = 0xe,
827 FMT_RESERVED_4 = 0xf,
828 FMT_5_6_5 = 0x10,
829 FMT_1_5_5_5 = 0x11,
830 FMT_5_5_5_1 = 0x12,
831 FMT_4_4_4_4 = 0x13,
832 FMT_8_24 = 0x14,
833 FMT_24_8 = 0x15,
834 FMT_X24_8_32_FLOAT = 0x16,
835 FMT_RESERVED_33 = 0x17,
836 FMT_11_11_10_FLOAT = 0x18,
837 FMT_16_FLOAT = 0x19,
838 FMT_32_FLOAT = 0x1a,
839 FMT_16_16_FLOAT = 0x1b,
840 FMT_8_24_FLOAT = 0x1c,
841 FMT_24_8_FLOAT = 0x1d,
842 FMT_32_32_FLOAT = 0x1e,
843 FMT_10_11_11_FLOAT = 0x1f,
844 FMT_16_16_16_16_FLOAT = 0x20,
845 FMT_3_3_2 = 0x21,
846 FMT_6_5_5 = 0x22,
847 FMT_32_32_32_32_FLOAT = 0x23,
848 FMT_RESERVED_36 = 0x24,
849 FMT_1 = 0x25,
850 FMT_1_REVERSED = 0x26,
851 FMT_GB_GR = 0x27,
852 FMT_BG_RG = 0x28,
853 FMT_32_AS_8 = 0x29,
854 FMT_32_AS_8_8 = 0x2a,
855 FMT_5_9_9_9_SHAREDEXP = 0x2b,
856 FMT_8_8_8 = 0x2c,
857 FMT_16_16_16 = 0x2d,
858 FMT_16_16_16_FLOAT = 0x2e,
859 FMT_4_4 = 0x2f,
860 FMT_32_32_32_FLOAT = 0x30,
861 FMT_BC1 = 0x31,
862 FMT_BC2 = 0x32,
863 FMT_BC3 = 0x33,
864 FMT_BC4 = 0x34,
865 FMT_BC5 = 0x35,
866 FMT_BC6 = 0x36,
867 FMT_BC7 = 0x37,
868 FMT_32_AS_32_32_32_32 = 0x38,
869 FMT_APC3 = 0x39,
870 FMT_APC4 = 0x3a,
871 FMT_APC5 = 0x3b,
872 FMT_APC6 = 0x3c,
873 FMT_APC7 = 0x3d,
874 FMT_CTX1 = 0x3e,
875 FMT_RESERVED_63 = 0x3f,
876} SurfaceFormat;
877typedef enum BUF_DATA_FORMAT {
878 BUF_DATA_FORMAT_INVALID = 0x0,
879 BUF_DATA_FORMAT_8 = 0x1,
880 BUF_DATA_FORMAT_16 = 0x2,
881 BUF_DATA_FORMAT_8_8 = 0x3,
882 BUF_DATA_FORMAT_32 = 0x4,
883 BUF_DATA_FORMAT_16_16 = 0x5,
884 BUF_DATA_FORMAT_10_11_11 = 0x6,
885 BUF_DATA_FORMAT_11_11_10 = 0x7,
886 BUF_DATA_FORMAT_10_10_10_2 = 0x8,
887 BUF_DATA_FORMAT_2_10_10_10 = 0x9,
888 BUF_DATA_FORMAT_8_8_8_8 = 0xa,
889 BUF_DATA_FORMAT_32_32 = 0xb,
890 BUF_DATA_FORMAT_16_16_16_16 = 0xc,
891 BUF_DATA_FORMAT_32_32_32 = 0xd,
892 BUF_DATA_FORMAT_32_32_32_32 = 0xe,
893 BUF_DATA_FORMAT_RESERVED_15 = 0xf,
894} BUF_DATA_FORMAT;
895typedef enum IMG_DATA_FORMAT {
896 IMG_DATA_FORMAT_INVALID = 0x0,
897 IMG_DATA_FORMAT_8 = 0x1,
898 IMG_DATA_FORMAT_16 = 0x2,
899 IMG_DATA_FORMAT_8_8 = 0x3,
900 IMG_DATA_FORMAT_32 = 0x4,
901 IMG_DATA_FORMAT_16_16 = 0x5,
902 IMG_DATA_FORMAT_10_11_11 = 0x6,
903 IMG_DATA_FORMAT_11_11_10 = 0x7,
904 IMG_DATA_FORMAT_10_10_10_2 = 0x8,
905 IMG_DATA_FORMAT_2_10_10_10 = 0x9,
906 IMG_DATA_FORMAT_8_8_8_8 = 0xa,
907 IMG_DATA_FORMAT_32_32 = 0xb,
908 IMG_DATA_FORMAT_16_16_16_16 = 0xc,
909 IMG_DATA_FORMAT_32_32_32 = 0xd,
910 IMG_DATA_FORMAT_32_32_32_32 = 0xe,
911 IMG_DATA_FORMAT_RESERVED_15 = 0xf,
912 IMG_DATA_FORMAT_5_6_5 = 0x10,
913 IMG_DATA_FORMAT_1_5_5_5 = 0x11,
914 IMG_DATA_FORMAT_5_5_5_1 = 0x12,
915 IMG_DATA_FORMAT_4_4_4_4 = 0x13,
916 IMG_DATA_FORMAT_8_24 = 0x14,
917 IMG_DATA_FORMAT_24_8 = 0x15,
918 IMG_DATA_FORMAT_X24_8_32 = 0x16,
919 IMG_DATA_FORMAT_RESERVED_23 = 0x17,
920 IMG_DATA_FORMAT_RESERVED_24 = 0x18,
921 IMG_DATA_FORMAT_RESERVED_25 = 0x19,
922 IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
923 IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
924 IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
925 IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
926 IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
927 IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
928 IMG_DATA_FORMAT_GB_GR = 0x20,
929 IMG_DATA_FORMAT_BG_RG = 0x21,
930 IMG_DATA_FORMAT_5_9_9_9 = 0x22,
931 IMG_DATA_FORMAT_BC1 = 0x23,
932 IMG_DATA_FORMAT_BC2 = 0x24,
933 IMG_DATA_FORMAT_BC3 = 0x25,
934 IMG_DATA_FORMAT_BC4 = 0x26,
935 IMG_DATA_FORMAT_BC5 = 0x27,
936 IMG_DATA_FORMAT_BC6 = 0x28,
937 IMG_DATA_FORMAT_BC7 = 0x29,
938 IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
939 IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
940 IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
941 IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
942 IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
943 IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
944 IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
945 IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
946 IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
947 IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
948 IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
949 IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
950 IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
951 IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
952 IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
953 IMG_DATA_FORMAT_4_4 = 0x39,
954 IMG_DATA_FORMAT_6_5_5 = 0x3a,
955 IMG_DATA_FORMAT_1 = 0x3b,
956 IMG_DATA_FORMAT_1_REVERSED = 0x3c,
957 IMG_DATA_FORMAT_32_AS_8 = 0x3d,
958 IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
959 IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
960} IMG_DATA_FORMAT;
961typedef enum BUF_NUM_FORMAT {
962 BUF_NUM_FORMAT_UNORM = 0x0,
963 BUF_NUM_FORMAT_SNORM = 0x1,
964 BUF_NUM_FORMAT_USCALED = 0x2,
965 BUF_NUM_FORMAT_SSCALED = 0x3,
966 BUF_NUM_FORMAT_UINT = 0x4,
967 BUF_NUM_FORMAT_SINT = 0x5,
968 BUF_NUM_FORMAT_SNORM_OGL = 0x6,
969 BUF_NUM_FORMAT_FLOAT = 0x7,
970} BUF_NUM_FORMAT;
971typedef enum IMG_NUM_FORMAT {
972 IMG_NUM_FORMAT_UNORM = 0x0,
973 IMG_NUM_FORMAT_SNORM = 0x1,
974 IMG_NUM_FORMAT_USCALED = 0x2,
975 IMG_NUM_FORMAT_SSCALED = 0x3,
976 IMG_NUM_FORMAT_UINT = 0x4,
977 IMG_NUM_FORMAT_SINT = 0x5,
978 IMG_NUM_FORMAT_SNORM_OGL = 0x6,
979 IMG_NUM_FORMAT_FLOAT = 0x7,
980 IMG_NUM_FORMAT_RESERVED_8 = 0x8,
981 IMG_NUM_FORMAT_SRGB = 0x9,
982 IMG_NUM_FORMAT_UBNORM = 0xa,
983 IMG_NUM_FORMAT_UBNORM_OGL = 0xb,
984 IMG_NUM_FORMAT_UBINT = 0xc,
985 IMG_NUM_FORMAT_UBSCALED = 0xd,
986 IMG_NUM_FORMAT_RESERVED_14 = 0xe,
987 IMG_NUM_FORMAT_RESERVED_15 = 0xf,
988} IMG_NUM_FORMAT;
989typedef enum TileType {
990 ARRAY_COLOR_TILE = 0x0,
991 ARRAY_DEPTH_TILE = 0x1,
992} TileType;
993typedef enum NonDispTilingOrder {
994 ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
995 ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
996} NonDispTilingOrder;
997typedef enum MicroTileMode {
998 ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
999 ADDR_SURF_THIN_MICRO_TILING = 0x1,
1000 ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
1001 ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
1002 ADDR_SURF_THICK_MICRO_TILING = 0x4,
1003} MicroTileMode;
1004typedef enum TileSplit {
1005 ADDR_SURF_TILE_SPLIT_64B = 0x0,
1006 ADDR_SURF_TILE_SPLIT_128B = 0x1,
1007 ADDR_SURF_TILE_SPLIT_256B = 0x2,
1008 ADDR_SURF_TILE_SPLIT_512B = 0x3,
1009 ADDR_SURF_TILE_SPLIT_1KB = 0x4,
1010 ADDR_SURF_TILE_SPLIT_2KB = 0x5,
1011 ADDR_SURF_TILE_SPLIT_4KB = 0x6,
1012} TileSplit;
1013typedef enum SampleSplit {
1014 ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
1015 ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
1016 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
1017 ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
1018} SampleSplit;
1019typedef enum PipeConfig {
1020 ADDR_SURF_P2 = 0x0,
1021 ADDR_SURF_P2_RESERVED0 = 0x1,
1022 ADDR_SURF_P2_RESERVED1 = 0x2,
1023 ADDR_SURF_P2_RESERVED2 = 0x3,
1024 ADDR_SURF_P4_8x16 = 0x4,
1025 ADDR_SURF_P4_16x16 = 0x5,
1026 ADDR_SURF_P4_16x32 = 0x6,
1027 ADDR_SURF_P4_32x32 = 0x7,
1028 ADDR_SURF_P8_16x16_8x16 = 0x8,
1029 ADDR_SURF_P8_16x32_8x16 = 0x9,
1030 ADDR_SURF_P8_32x32_8x16 = 0xa,
1031 ADDR_SURF_P8_16x32_16x16 = 0xb,
1032 ADDR_SURF_P8_32x32_16x16 = 0xc,
1033 ADDR_SURF_P8_32x32_16x32 = 0xd,
1034 ADDR_SURF_P8_32x64_32x32 = 0xe,
1035} PipeConfig;
1036typedef enum NumBanks {
1037 ADDR_SURF_2_BANK = 0x0,
1038 ADDR_SURF_4_BANK = 0x1,
1039 ADDR_SURF_8_BANK = 0x2,
1040 ADDR_SURF_16_BANK = 0x3,
1041} NumBanks;
1042typedef enum BankWidth {
1043 ADDR_SURF_BANK_WIDTH_1 = 0x0,
1044 ADDR_SURF_BANK_WIDTH_2 = 0x1,
1045 ADDR_SURF_BANK_WIDTH_4 = 0x2,
1046 ADDR_SURF_BANK_WIDTH_8 = 0x3,
1047} BankWidth;
1048typedef enum BankHeight {
1049 ADDR_SURF_BANK_HEIGHT_1 = 0x0,
1050 ADDR_SURF_BANK_HEIGHT_2 = 0x1,
1051 ADDR_SURF_BANK_HEIGHT_4 = 0x2,
1052 ADDR_SURF_BANK_HEIGHT_8 = 0x3,
1053} BankHeight;
1054typedef enum BankWidthHeight {
1055 ADDR_SURF_BANK_WH_1 = 0x0,
1056 ADDR_SURF_BANK_WH_2 = 0x1,
1057 ADDR_SURF_BANK_WH_4 = 0x2,
1058 ADDR_SURF_BANK_WH_8 = 0x3,
1059} BankWidthHeight;
1060typedef enum MacroTileAspect {
1061 ADDR_SURF_MACRO_ASPECT_1 = 0x0,
1062 ADDR_SURF_MACRO_ASPECT_2 = 0x1,
1063 ADDR_SURF_MACRO_ASPECT_4 = 0x2,
1064 ADDR_SURF_MACRO_ASPECT_8 = 0x3,
1065} MacroTileAspect;
1066typedef enum TCC_CACHE_POLICIES {
1067 TCC_CACHE_POLICY_LRU = 0x0,
1068 TCC_CACHE_POLICY_STREAM = 0x1,
1069 TCC_CACHE_POLICY_BYPASS = 0x2,
1070} TCC_CACHE_POLICIES;
1071typedef enum PERFMON_COUNTER_MODE {
1072 PERFMON_COUNTER_MODE_ACCUM = 0x0,
1073 PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
1074 PERFMON_COUNTER_MODE_MAX = 0x2,
1075 PERFMON_COUNTER_MODE_DIRTY = 0x3,
1076 PERFMON_COUNTER_MODE_SAMPLE = 0x4,
1077 PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
1078 PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
1079 PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
1080 PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
1081 PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
1082 PERFMON_COUNTER_MODE_RESERVED = 0xf,
1083} PERFMON_COUNTER_MODE;
1084typedef enum PERFMON_SPM_MODE {
1085 PERFMON_SPM_MODE_OFF = 0x0,
1086 PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
1087 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
1088 PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
1089 PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
1090 PERFMON_SPM_MODE_RESERVED_5 = 0x5,
1091 PERFMON_SPM_MODE_RESERVED_6 = 0x6,
1092 PERFMON_SPM_MODE_RESERVED_7 = 0x7,
1093 PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
1094 PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
1095 PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
1096} PERFMON_SPM_MODE;
1097typedef enum SurfaceTiling {
1098 ARRAY_LINEAR = 0x0,
1099 ARRAY_TILED = 0x1,
1100} SurfaceTiling;
1101typedef enum SurfaceArray {
1102 ARRAY_1D = 0x0,
1103 ARRAY_2D = 0x1,
1104 ARRAY_3D = 0x2,
1105 ARRAY_3D_SLICE = 0x3,
1106} SurfaceArray;
1107typedef enum ColorArray {
1108 ARRAY_2D_ALT_COLOR = 0x0,
1109 ARRAY_2D_COLOR = 0x1,
1110 ARRAY_3D_SLICE_COLOR = 0x3,
1111} ColorArray;
1112typedef enum DepthArray {
1113 ARRAY_2D_ALT_DEPTH = 0x0,
1114 ARRAY_2D_DEPTH = 0x1,
1115} DepthArray;
1116
1117#endif /* DCE_8_0_ENUM_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-27 14:42:14 -0400