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authorOlof Johansson <olof@lixom.net>2018-09-23 09:31:04 -0400
committerOlof Johansson <olof@lixom.net>2018-09-23 09:31:04 -0400
commitf240bd3b4b91430aaa5eb6be8a14812eff8f9f32 (patch)
tree47064314bf7d78ff6c30799a0fe54c5ad8c60626
parent6302cbe759e261f22fa603ac653328b4b9615adf (diff)
parent42e54f6467ecc25f464d74c0fcea0c9fab1c2e3b (diff)
Merge tag 'am654-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into next/dt
TI AM654 support for v4.20 merge window. This branch adds changes for the Texas Instruments AM654 SoC. Included changes are: - Add uart nodes - Change address cells and size-cells of interconnect tfrom 1 to 2 - Add secure proxy instance for main domain - Add DMSC support * tag 'am654-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux: arm64: dts: ti: k3-am6: Add Device Management Security Controller support arm64: dts: ti: am654: Add secure proxy instance for main domain arm64: dts: ti: am654: Add uart nodes arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2 Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--arch/arm64/boot/dts/ti/k3-am65-main.dtsi51
-rw-r--r--arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi18
-rw-r--r--arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi46
-rw-r--r--arch/arm64/boot/dts/ti/k3-am65.dtsi54
-rw-r--r--arch/arm64/boot/dts/ti/k3-am654-base-board.dts5
5 files changed, 147 insertions, 27 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 2409344df4fa..adcd6341e40c 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -8,13 +8,13 @@
8&cbass_main { 8&cbass_main {
9 gic500: interrupt-controller@1800000 { 9 gic500: interrupt-controller@1800000 {
10 compatible = "arm,gic-v3"; 10 compatible = "arm,gic-v3";
11 #address-cells = <1>; 11 #address-cells = <2>;
12 #size-cells = <1>; 12 #size-cells = <2>;
13 ranges; 13 ranges;
14 #interrupt-cells = <3>; 14 #interrupt-cells = <3>;
15 interrupt-controller; 15 interrupt-controller;
16 reg = <0x01800000 0x10000>, /* GICD */ 16 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
17 <0x01880000 0x90000>; /* GICR */ 17 <0x00 0x01880000 0x00 0x90000>; /* GICR */
18 /* 18 /*
19 * vcpumntirq: 19 * vcpumntirq:
20 * virtual CPU interface maintenance interrupt 20 * virtual CPU interface maintenance interrupt
@@ -23,9 +23,50 @@
23 23
24 gic_its: gic-its@18200000 { 24 gic_its: gic-its@18200000 {
25 compatible = "arm,gic-v3-its"; 25 compatible = "arm,gic-v3-its";
26 reg = <0x01820000 0x10000>; 26 reg = <0x00 0x01820000 0x00 0x10000>;
27 msi-controller; 27 msi-controller;
28 #msi-cells = <1>; 28 #msi-cells = <1>;
29 }; 29 };
30 }; 30 };
31
32 secure_proxy_main: mailbox@32c00000 {
33 compatible = "ti,am654-secure-proxy";
34 #mbox-cells = <1>;
35 reg-names = "target_data", "rt", "scfg";
36 reg = <0x00 0x32c00000 0x00 0x100000>,
37 <0x00 0x32400000 0x00 0x100000>,
38 <0x00 0x32800000 0x00 0x100000>;
39 interrupt-names = "rx_011";
40 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
41 };
42
43 main_uart0: serial@2800000 {
44 compatible = "ti,am654-uart";
45 reg = <0x00 0x02800000 0x00 0x100>;
46 reg-shift = <2>;
47 reg-io-width = <4>;
48 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
49 clock-frequency = <48000000>;
50 current-speed = <115200>;
51 };
52
53 main_uart1: serial@2810000 {
54 compatible = "ti,am654-uart";
55 reg = <0x00 0x02810000 0x00 0x100>;
56 reg-shift = <2>;
57 reg-io-width = <4>;
58 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
59 clock-frequency = <48000000>;
60 current-speed = <115200>;
61 };
62
63 main_uart2: serial@2820000 {
64 compatible = "ti,am654-uart";
65 reg = <0x00 0x02820000 0x00 0x100>;
66 reg-shift = <2>;
67 reg-io-width = <4>;
68 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
69 clock-frequency = <48000000>;
70 current-speed = <115200>;
71 };
31}; 72};
diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
new file mode 100644
index 000000000000..8c611d16df44
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
@@ -0,0 +1,18 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for AM6 SoC Family MCU Domain peripherals
4 *
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
6 */
7
8&cbass_mcu {
9 mcu_uart0: serial@40a00000 {
10 compatible = "ti,am654-uart";
11 reg = <0x00 0x40a00000 0x00 0x100>;
12 reg-shift = <2>;
13 reg-io-width = <4>;
14 interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
15 clock-frequency = <96000000>;
16 current-speed = <115200>;
17 };
18};
diff --git a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
new file mode 100644
index 000000000000..affc3c309353
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
@@ -0,0 +1,46 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for AM6 SoC Family Wakeup Domain peripherals
4 *
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
6 */
7
8&cbass_wakeup {
9 dmsc: dmsc {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
12 #address-cells = <1>;
13 #size-cells = <1>;
14 ranges;
15
16 mbox-names = "rx", "tx";
17
18 mboxes= <&secure_proxy_main 11>,
19 <&secure_proxy_main 13>;
20
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <1>;
24 };
25
26 k3_clks: clocks {
27 compatible = "ti,k2g-sci-clk";
28 #clock-cells = <2>;
29 };
30
31 k3_reset: reset-controller {
32 compatible = "ti,sci-reset";
33 #reset-cells = <2>;
34 };
35 };
36
37 wkup_uart0: serial@42300000 {
38 compatible = "ti,am654-uart";
39 reg = <0x00 0x42300000 0x00 0x100>;
40 reg-shift = <2>;
41 reg-io-width = <4>;
42 interrupts = <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
43 clock-frequency = <48000000>;
44 current-speed = <115200>;
45 };
46};
diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi
index cede1fa0983c..3d4bf369d030 100644
--- a/arch/arm64/boot/dts/ti/k3-am65.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi
@@ -16,6 +16,14 @@
16 #address-cells = <2>; 16 #address-cells = <2>;
17 #size-cells = <2>; 17 #size-cells = <2>;
18 18
19 aliases {
20 serial0 = &wkup_uart0;
21 serial1 = &mcu_uart0;
22 serial2 = &main_uart0;
23 serial3 = &main_uart1;
24 serial4 = &main_uart2;
25 };
26
19 chosen { }; 27 chosen { };
20 28
21 firmware { 29 firmware {
@@ -46,38 +54,38 @@
46 54
47 cbass_main: interconnect@100000 { 55 cbass_main: interconnect@100000 {
48 compatible = "simple-bus"; 56 compatible = "simple-bus";
49 #address-cells = <1>; 57 #address-cells = <2>;
50 #size-cells = <1>; 58 #size-cells = <2>;
51 ranges = <0x00100000 0x00 0x00100000 0x00020000>, /* ctrl mmr */ 59 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
52 <0x00600000 0x00 0x00600000 0x00001100>, /* GPIO */ 60 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
53 <0x00900000 0x00 0x00900000 0x00012000>, /* serdes */ 61 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
54 <0x01000000 0x00 0x01000000 0x0af02400>, /* Most peripherals */ 62 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
55 <0x30800000 0x00 0x30800000 0x0bc00000>, /* MAIN NAVSS */ 63 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
56 /* MCUSS Range */ 64 /* MCUSS Range */
57 <0x28380000 0x00 0x28380000 0x03880000>, 65 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
58 <0x40200000 0x00 0x40200000 0x00900100>, 66 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
59 <0x42040000 0x00 0x42040000 0x03ac2400>, 67 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
60 <0x45100000 0x00 0x45100000 0x00c24000>, 68 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
61 <0x46000000 0x00 0x46000000 0x00200000>, 69 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
62 <0x47000000 0x00 0x47000000 0x00068400>; 70 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>;
63 71
64 cbass_mcu: interconnect@28380000 { 72 cbass_mcu: interconnect@28380000 {
65 compatible = "simple-bus"; 73 compatible = "simple-bus";
66 #address-cells = <1>; 74 #address-cells = <2>;
67 #size-cells = <1>; 75 #size-cells = <2>;
68 ranges = <0x28380000 0x28380000 0x03880000>, /* MCU NAVSS*/ 76 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
69 <0x40200000 0x40200000 0x00900100>, /* First peripheral window */ 77 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
70 <0x42040000 0x42040000 0x03ac2400>, /* WKUP */ 78 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
71 <0x45100000 0x45100000 0x00c24000>, /* MMRs, remaining NAVSS */ 79 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
72 <0x46000000 0x46000000 0x00200000>, /* CPSW */ 80 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
73 <0x47000000 0x47000000 0x00068400>; /* OSPI space 1 */ 81 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>; /* OSPI space 1 */
74 82
75 cbass_wakeup: interconnect@42040000 { 83 cbass_wakeup: interconnect@42040000 {
76 compatible = "simple-bus"; 84 compatible = "simple-bus";
77 #address-cells = <1>; 85 #address-cells = <1>;
78 #size-cells = <1>; 86 #size-cells = <1>;
79 /* WKUP Basic peripherals */ 87 /* WKUP Basic peripherals */
80 ranges = <0x42040000 0x42040000 0x03ac2400>; 88 ranges = <0x42040000 0x00 0x42040000 0x03ac2400>;
81 }; 89 };
82 }; 90 };
83 }; 91 };
@@ -85,3 +93,5 @@
85 93
86/* Now include the peripherals for each bus segments */ 94/* Now include the peripherals for each bus segments */
87#include "k3-am65-main.dtsi" 95#include "k3-am65-main.dtsi"
96#include "k3-am65-mcu.dtsi"
97#include "k3-am65-wakeup.dtsi"
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index af6956fdc13f..e146ac2ad781 100644
--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
@@ -34,3 +34,8 @@
34 }; 34 };
35 }; 35 };
36}; 36};
37
38&wkup_uart0 {
39 /* Wakeup UART is used by System firmware */
40 status = "disabled";
41};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-22 09:09:11 -0400