diff options
author | Eric Bernstein <eric.bernstein@amd.com> | 2017-11-24 17:51:34 -0500 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2017-12-14 10:57:50 -0500 |
commit | f23d558466cf14e58ec7f666a3af1a6708681bcc (patch) | |
tree | 10e80654be1d74f6147cf2064f250aa2cae46146 | |
parent | 043b19bdedf5d76d4a614f508baaf83aaf7c4b6e (diff) |
drm/amd/display: Move OPP mpc tree initialization to hw_init
Move OPP initialization of mpc tree parameters to hw_init function.
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 7 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 1 |
3 files changed, 3 insertions, 7 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 7ec87fcb22be..f0be2b872668 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | |||
@@ -782,6 +782,8 @@ static void dcn10_init_hw(struct dc *dc) | |||
782 | hubp->opp_id = 0xf; | 782 | hubp->opp_id = 0xf; |
783 | hubp->power_gated = false; | 783 | hubp->power_gated = false; |
784 | 784 | ||
785 | dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; | ||
786 | dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL; | ||
785 | dc->res_pool->opps[i]->mpcc_disconnect_pending[i] = true; | 787 | dc->res_pool->opps[i]->mpcc_disconnect_pending[i] = true; |
786 | pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; | 788 | pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; |
787 | 789 | ||
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c index 20d78cf46ab0..5f078868676c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | |||
@@ -330,18 +330,11 @@ void dcn10_opp_construct(struct dcn10_opp *oppn10, | |||
330 | const struct dcn10_opp_shift *opp_shift, | 330 | const struct dcn10_opp_shift *opp_shift, |
331 | const struct dcn10_opp_mask *opp_mask) | 331 | const struct dcn10_opp_mask *opp_mask) |
332 | { | 332 | { |
333 | int i; | ||
334 | 333 | ||
335 | oppn10->base.ctx = ctx; | 334 | oppn10->base.ctx = ctx; |
336 | oppn10->base.inst = inst; | 335 | oppn10->base.inst = inst; |
337 | oppn10->base.funcs = &dcn10_opp_funcs; | 336 | oppn10->base.funcs = &dcn10_opp_funcs; |
338 | 337 | ||
339 | oppn10->base.mpc_tree_params.opp_id = inst; | ||
340 | oppn10->base.mpc_tree_params.opp_list = NULL; | ||
341 | |||
342 | for (i = 0; i < MAX_PIPES; i++) | ||
343 | oppn10->base.mpcc_disconnect_pending[i] = false; | ||
344 | |||
345 | oppn10->regs = regs; | 338 | oppn10->regs = regs; |
346 | oppn10->opp_shift = opp_shift; | 339 | oppn10->opp_shift = opp_shift; |
347 | oppn10->opp_mask = opp_mask; | 340 | oppn10->opp_mask = opp_mask; |
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h index 42f2bb29a5fc..6da125de9507 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | |||
@@ -300,6 +300,7 @@ struct opp_funcs { | |||
300 | struct output_pixel_processor *opp, | 300 | struct output_pixel_processor *opp, |
301 | bool enable, | 301 | bool enable, |
302 | bool polarity); | 302 | bool polarity); |
303 | |||
303 | }; | 304 | }; |
304 | 305 | ||
305 | #endif | 306 | #endif |