diff options
author | Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> | 2018-04-27 18:21:54 -0400 |
---|---|---|
committer | Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | 2018-05-05 10:11:20 -0400 |
commit | f1e9a22ac3cff749077f40bf1a149aaaf587ae2d (patch) | |
tree | 8a3fc73fdf02a417f6638fde9d20196ab38847a2 | |
parent | 7ae90455bc865ab1c30fb4db53ac56ec32741ab9 (diff) |
drm: rcar-du: Add R8A77965 support
The R8A77965 (M3-N) SoC provides RGB, HDMI and LVDS output.
This platform is unusual in that the RGB is connected to DU3 leaving DU2
unpopulated. This is reflected by the channels_mask accordingly.
Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
-rw-r--r-- | drivers/gpu/drm/rcar-du/rcar_du_drv.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c index 2aa392b03e73..02aee6cb0e53 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c | |||
@@ -246,6 +246,34 @@ static const struct rcar_du_device_info rcar_du_r8a7796_info = { | |||
246 | .dpll_ch = BIT(1), | 246 | .dpll_ch = BIT(1), |
247 | }; | 247 | }; |
248 | 248 | ||
249 | static const struct rcar_du_device_info rcar_du_r8a77965_info = { | ||
250 | .gen = 3, | ||
251 | .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK | ||
252 | | RCAR_DU_FEATURE_EXT_CTRL_REGS | ||
253 | | RCAR_DU_FEATURE_VSP1_SOURCE, | ||
254 | .channels_mask = BIT(3) | BIT(1) | BIT(0), | ||
255 | .routes = { | ||
256 | /* | ||
257 | * R8A77965 has one RGB output, one LVDS output and one HDMI | ||
258 | * output. | ||
259 | */ | ||
260 | [RCAR_DU_OUTPUT_DPAD0] = { | ||
261 | .possible_crtcs = BIT(2), | ||
262 | .port = 0, | ||
263 | }, | ||
264 | [RCAR_DU_OUTPUT_HDMI0] = { | ||
265 | .possible_crtcs = BIT(1), | ||
266 | .port = 1, | ||
267 | }, | ||
268 | [RCAR_DU_OUTPUT_LVDS0] = { | ||
269 | .possible_crtcs = BIT(0), | ||
270 | .port = 2, | ||
271 | }, | ||
272 | }, | ||
273 | .num_lvds = 1, | ||
274 | .dpll_ch = BIT(1), | ||
275 | }; | ||
276 | |||
249 | static const struct rcar_du_device_info rcar_du_r8a77970_info = { | 277 | static const struct rcar_du_device_info rcar_du_r8a77970_info = { |
250 | .gen = 3, | 278 | .gen = 3, |
251 | .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK | 279 | .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK |
@@ -277,6 +305,7 @@ static const struct of_device_id rcar_du_of_table[] = { | |||
277 | { .compatible = "renesas,du-r8a7794", .data = &rcar_du_r8a7794_info }, | 305 | { .compatible = "renesas,du-r8a7794", .data = &rcar_du_r8a7794_info }, |
278 | { .compatible = "renesas,du-r8a7795", .data = &rcar_du_r8a7795_info }, | 306 | { .compatible = "renesas,du-r8a7795", .data = &rcar_du_r8a7795_info }, |
279 | { .compatible = "renesas,du-r8a7796", .data = &rcar_du_r8a7796_info }, | 307 | { .compatible = "renesas,du-r8a7796", .data = &rcar_du_r8a7796_info }, |
308 | { .compatible = "renesas,du-r8a77965", .data = &rcar_du_r8a77965_info }, | ||
280 | { .compatible = "renesas,du-r8a77970", .data = &rcar_du_r8a77970_info }, | 309 | { .compatible = "renesas,du-r8a77970", .data = &rcar_du_r8a77970_info }, |
281 | { } | 310 | { } |
282 | }; | 311 | }; |