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authorRussell King <rmk+kernel@arm.linux.org.uk>2014-08-05 05:27:25 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2014-08-05 05:27:25 -0400
commitf15bdfe4fb264ac30d9c176f898cbd52cfd1ffa9 (patch)
treed93b59190624c0df80854aff5078c588420c3516
parentc89c3a6acb847b03250a83cecae4f5c9ced2d960 (diff)
parentc70fbb01b11cecfa13d9e746f462617d3ac0e38c (diff)
Merge branch 'devel-stable' into for-next
Conflicts: arch/arm/kernel/perf_event_cpu.c
Diffstat
-rw-r--r--arch/arm/include/asm/memory.h4
-rw-r--r--arch/arm/include/asm/perf_event.h9
-rw-r--r--arch/arm/include/asm/pmu.h19
-rw-r--r--arch/arm/include/asm/uaccess.h2
-rw-r--r--arch/arm/kernel/perf_event.c13
-rw-r--r--arch/arm/kernel/perf_event_cpu.c13
-rw-r--r--arch/arm/kernel/perf_event_v6.c307
-rw-r--r--arch/arm/kernel/perf_event_v7.c967
-rw-r--r--arch/arm/kernel/perf_event_xscale.c121
-rw-r--r--arch/arm/oprofile/common.c14
10 files changed, 362 insertions, 1107 deletions
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 04ccf1c0a1af..e731018869a7 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -91,9 +91,7 @@
91 * of this define that was meant to. 91 * of this define that was meant to.
92 * Fortunately, there is no reference for this in noMMU mode, for now. 92 * Fortunately, there is no reference for this in noMMU mode, for now.
93 */ 93 */
94#ifndef TASK_SIZE 94#define TASK_SIZE UL(0xffffffff)
95#define TASK_SIZE (CONFIG_DRAM_SIZE)
96#endif
97 95
98#ifndef TASK_UNMAPPED_BASE 96#ifndef TASK_UNMAPPED_BASE
99#define TASK_UNMAPPED_BASE UL(0x00000000) 97#define TASK_UNMAPPED_BASE UL(0x00000000)
diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h
index 755877527cf9..c3a83691af8e 100644
--- a/arch/arm/include/asm/perf_event.h
+++ b/arch/arm/include/asm/perf_event.h
@@ -12,15 +12,6 @@
12#ifndef __ARM_PERF_EVENT_H__ 12#ifndef __ARM_PERF_EVENT_H__
13#define __ARM_PERF_EVENT_H__ 13#define __ARM_PERF_EVENT_H__
14 14
15/*
16 * The ARMv7 CPU PMU supports up to 32 event counters.
17 */
18#define ARMPMU_MAX_HWEVENTS 32
19
20#define HW_OP_UNSUPPORTED 0xFFFF
21#define C(_x) PERF_COUNT_HW_CACHE_##_x
22#define CACHE_OP_UNSUPPORTED 0xFFFF
23
24#ifdef CONFIG_HW_PERF_EVENTS 15#ifdef CONFIG_HW_PERF_EVENTS
25struct pt_regs; 16struct pt_regs;
26extern unsigned long perf_instruction_pointer(struct pt_regs *regs); 17extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index ae1919be8f98..0b648c541293 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -42,6 +42,25 @@ struct arm_pmu_platdata {
42 42
43#ifdef CONFIG_HW_PERF_EVENTS 43#ifdef CONFIG_HW_PERF_EVENTS
44 44
45/*
46 * The ARMv7 CPU PMU supports up to 32 event counters.
47 */
48#define ARMPMU_MAX_HWEVENTS 32
49
50#define HW_OP_UNSUPPORTED 0xFFFF
51#define C(_x) PERF_COUNT_HW_CACHE_##_x
52#define CACHE_OP_UNSUPPORTED 0xFFFF
53
54#define PERF_MAP_ALL_UNSUPPORTED \
55 [0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED
56
57#define PERF_CACHE_MAP_ALL_UNSUPPORTED \
58[0 ... C(MAX) - 1] = { \
59 [0 ... C(OP_MAX) - 1] = { \
60 [0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED, \
61 }, \
62}
63
45/* The events for a given PMU register set. */ 64/* The events for a given PMU register set. */
46struct pmu_hw_events { 65struct pmu_hw_events {
47 /* 66 /*
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
index 7057cf8b87d0..a4cd7af475e9 100644
--- a/arch/arm/include/asm/uaccess.h
+++ b/arch/arm/include/asm/uaccess.h
@@ -242,7 +242,7 @@ static inline void set_fs(mm_segment_t fs)
242#define access_ok(type,addr,size) (__range_ok(addr,size) == 0) 242#define access_ok(type,addr,size) (__range_ok(addr,size) == 0)
243 243
244#define user_addr_max() \ 244#define user_addr_max() \
245 (segment_eq(get_fs(), USER_DS) ? TASK_SIZE : ~0UL) 245 (segment_eq(get_fs(), KERNEL_DS) ? ~0UL : get_fs())
246 246
247/* 247/*
248 * The "__xxx" versions of the user access functions do not verify the 248 * The "__xxx" versions of the user access functions do not verify the
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index ae3e216a52c2..266cba46db3e 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -560,11 +560,16 @@ user_backtrace(struct frame_tail __user *tail,
560 struct perf_callchain_entry *entry) 560 struct perf_callchain_entry *entry)
561{ 561{
562 struct frame_tail buftail; 562 struct frame_tail buftail;
563 unsigned long err;
563 564
564 /* Also check accessibility of one struct frame_tail beyond */
565 if (!access_ok(VERIFY_READ, tail, sizeof(buftail))) 565 if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
566 return NULL; 566 return NULL;
567 if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail))) 567
568 pagefault_disable();
569 err = __copy_from_user_inatomic(&buftail, tail, sizeof(buftail));
570 pagefault_enable();
571
572 if (err)
568 return NULL; 573 return NULL;
569 574
570 perf_callchain_store(entry, buftail.lr); 575 perf_callchain_store(entry, buftail.lr);
@@ -590,6 +595,10 @@ perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
590 } 595 }
591 596
592 perf_callchain_store(entry, regs->ARM_pc); 597 perf_callchain_store(entry, regs->ARM_pc);
598
599 if (!current->mm)
600 return;
601
593 tail = (struct frame_tail __user *)regs->ARM_fp - 1; 602 tail = (struct frame_tail __user *)regs->ARM_fp - 1;
594 603
595 while ((entry->nr < PERF_MAX_STACK_DEPTH) && 604 while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c
index c02c2e8c877d..e6a6edbec613 100644
--- a/arch/arm/kernel/perf_event_cpu.c
+++ b/arch/arm/kernel/perf_event_cpu.c
@@ -233,14 +233,17 @@ static struct of_device_id cpu_pmu_of_device_ids[] = {
233 {.compatible = "arm,cortex-a7-pmu", .data = armv7_a7_pmu_init}, 233 {.compatible = "arm,cortex-a7-pmu", .data = armv7_a7_pmu_init},
234 {.compatible = "arm,cortex-a5-pmu", .data = armv7_a5_pmu_init}, 234 {.compatible = "arm,cortex-a5-pmu", .data = armv7_a5_pmu_init},
235 {.compatible = "arm,arm11mpcore-pmu", .data = armv6mpcore_pmu_init}, 235 {.compatible = "arm,arm11mpcore-pmu", .data = armv6mpcore_pmu_init},
236 {.compatible = "arm,arm1176-pmu", .data = armv6pmu_init}, 236 {.compatible = "arm,arm1176-pmu", .data = armv6_1176_pmu_init},
237 {.compatible = "arm,arm1136-pmu", .data = armv6pmu_init}, 237 {.compatible = "arm,arm1136-pmu", .data = armv6_1136_pmu_init},
238 {.compatible = "qcom,krait-pmu", .data = krait_pmu_init}, 238 {.compatible = "qcom,krait-pmu", .data = krait_pmu_init},
239 {}, 239 {},
240}; 240};
241 241
242static struct platform_device_id cpu_pmu_plat_device_ids[] = { 242static struct platform_device_id cpu_pmu_plat_device_ids[] = {
243 {.name = "arm-pmu"}, 243 {.name = "arm-pmu"},
244 {.name = "armv6-pmu"},
245 {.name = "armv7-pmu"},
246 {.name = "xscale-pmu"},
244 {}, 247 {},
245}; 248};
246 249
@@ -257,9 +260,13 @@ static int probe_current_pmu(struct arm_pmu *pmu)
257 switch (read_cpuid_part()) { 260 switch (read_cpuid_part()) {
258 /* ARM Ltd CPUs. */ 261 /* ARM Ltd CPUs. */
259 case ARM_CPU_PART_ARM1136: 262 case ARM_CPU_PART_ARM1136:
263 ret = armv6_1136_pmu_init(pmu);
264 break;
260 case ARM_CPU_PART_ARM1156: 265 case ARM_CPU_PART_ARM1156:
266 ret = armv6_1156_pmu_init(pmu);
267 break;
261 case ARM_CPU_PART_ARM1176: 268 case ARM_CPU_PART_ARM1176:
262 ret = armv6pmu_init(pmu); 269 ret = armv6_1176_pmu_init(pmu);
263 break; 270 break;
264 case ARM_CPU_PART_ARM11MPCORE: 271 case ARM_CPU_PART_ARM11MPCORE:
265 ret = armv6mpcore_pmu_init(pmu); 272 ret = armv6mpcore_pmu_init(pmu);
diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c
index 03664b0e8fa4..abfeb04f3213 100644
--- a/arch/arm/kernel/perf_event_v6.c
+++ b/arch/arm/kernel/perf_event_v6.c
@@ -65,13 +65,11 @@ enum armv6_counters {
65 * accesses/misses in hardware. 65 * accesses/misses in hardware.
66 */ 66 */
67static const unsigned armv6_perf_map[PERF_COUNT_HW_MAX] = { 67static const unsigned armv6_perf_map[PERF_COUNT_HW_MAX] = {
68 PERF_MAP_ALL_UNSUPPORTED,
68 [PERF_COUNT_HW_CPU_CYCLES] = ARMV6_PERFCTR_CPU_CYCLES, 69 [PERF_COUNT_HW_CPU_CYCLES] = ARMV6_PERFCTR_CPU_CYCLES,
69 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6_PERFCTR_INSTR_EXEC, 70 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6_PERFCTR_INSTR_EXEC,
70 [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
71 [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
72 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6_PERFCTR_BR_EXEC, 71 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6_PERFCTR_BR_EXEC,
73 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6_PERFCTR_BR_MISPREDICT, 72 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6_PERFCTR_BR_MISPREDICT,
74 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
75 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV6_PERFCTR_IBUF_STALL, 73 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV6_PERFCTR_IBUF_STALL,
76 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV6_PERFCTR_LSU_FULL_STALL, 74 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV6_PERFCTR_LSU_FULL_STALL,
77}; 75};
@@ -79,116 +77,31 @@ static const unsigned armv6_perf_map[PERF_COUNT_HW_MAX] = {
79static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 77static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
80 [PERF_COUNT_HW_CACHE_OP_MAX] 78 [PERF_COUNT_HW_CACHE_OP_MAX]
81 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 79 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
82 [C(L1D)] = { 80 PERF_CACHE_MAP_ALL_UNSUPPORTED,
83 /* 81
84 * The performance counters don't differentiate between read 82 /*
85 * and write accesses/misses so this isn't strictly correct, 83 * The performance counters don't differentiate between read and write
86 * but it's the best we can do. Writes and reads get 84 * accesses/misses so this isn't strictly correct, but it's the best we
87 * combined. 85 * can do. Writes and reads get combined.
88 */ 86 */
89 [C(OP_READ)] = { 87 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS,
90 [C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS, 88 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS,
91 [C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS, 89 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS,
92 }, 90 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS,
93 [C(OP_WRITE)] = { 91
94 [C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS, 92 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS,
95 [C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS, 93
96 }, 94 /*
97 [C(OP_PREFETCH)] = { 95 * The ARM performance counters can count micro DTLB misses, micro ITLB
98 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 96 * misses and main TLB misses. There isn't an event for TLB misses, so
99 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, 97 * use the micro misses here and if users want the main TLB misses they
100 }, 98 * can use a raw counter.
101 }, 99 */
102 [C(L1I)] = { 100 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS,
103 [C(OP_READ)] = { 101 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS,
104 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 102
105 [C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS, 103 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS,
106 }, 104 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS,
107 [C(OP_WRITE)] = {
108 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
109 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
110 },
111 [C(OP_PREFETCH)] = {
112 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
113 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
114 },
115 },
116 [C(LL)] = {
117 [C(OP_READ)] = {
118 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
119 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
120 },
121 [C(OP_WRITE)] = {
122 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
123 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
124 },
125 [C(OP_PREFETCH)] = {
126 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
127 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
128 },
129 },
130 [C(DTLB)] = {
131 /*
132 * The ARM performance counters can count micro DTLB misses,
133 * micro ITLB misses and main TLB misses. There isn't an event
134 * for TLB misses, so use the micro misses here and if users
135 * want the main TLB misses they can use a raw counter.
136 */
137 [C(OP_READ)] = {
138 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
139 [C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS,
140 },
141 [C(OP_WRITE)] = {
142 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
143 [C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS,
144 },
145 [C(OP_PREFETCH)] = {
146 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
147 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
148 },
149 },
150 [C(ITLB)] = {
151 [C(OP_READ)] = {
152 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
153 [C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS,
154 },
155 [C(OP_WRITE)] = {
156 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
157 [C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS,
158 },
159 [C(OP_PREFETCH)] = {
160 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
161 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
162 },
163 },
164 [C(BPU)] = {
165 [C(OP_READ)] = {
166 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
167 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
168 },
169 [C(OP_WRITE)] = {
170 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
171 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
172 },
173 [C(OP_PREFETCH)] = {
174 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
175 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
176 },
177 },
178 [C(NODE)] = {
179 [C(OP_READ)] = {
180 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
181 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
182 },
183 [C(OP_WRITE)] = {
184 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
185 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
186 },
187 [C(OP_PREFETCH)] = {
188 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
189 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
190 },
191 },
192}; 105};
193 106
194enum armv6mpcore_perf_types { 107enum armv6mpcore_perf_types {
@@ -220,13 +133,11 @@ enum armv6mpcore_perf_types {
220 * accesses/misses in hardware. 133 * accesses/misses in hardware.
221 */ 134 */
222static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = { 135static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = {
136 PERF_MAP_ALL_UNSUPPORTED,
223 [PERF_COUNT_HW_CPU_CYCLES] = ARMV6MPCORE_PERFCTR_CPU_CYCLES, 137 [PERF_COUNT_HW_CPU_CYCLES] = ARMV6MPCORE_PERFCTR_CPU_CYCLES,
224 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_INSTR_EXEC, 138 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_INSTR_EXEC,
225 [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
226 [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
227 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_BR_EXEC, 139 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_BR_EXEC,
228 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6MPCORE_PERFCTR_BR_MISPREDICT, 140 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6MPCORE_PERFCTR_BR_MISPREDICT,
229 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
230 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV6MPCORE_PERFCTR_IBUF_STALL, 141 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV6MPCORE_PERFCTR_IBUF_STALL,
231 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV6MPCORE_PERFCTR_LSU_FULL_STALL, 142 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV6MPCORE_PERFCTR_LSU_FULL_STALL,
232}; 143};
@@ -234,114 +145,26 @@ static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = {
234static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 145static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
235 [PERF_COUNT_HW_CACHE_OP_MAX] 146 [PERF_COUNT_HW_CACHE_OP_MAX]
236 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 147 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
237 [C(L1D)] = { 148 PERF_CACHE_MAP_ALL_UNSUPPORTED,
238 [C(OP_READ)] = { 149
239 [C(RESULT_ACCESS)] = 150 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS,
240 ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS, 151 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DCACHE_RDMISS,
241 [C(RESULT_MISS)] = 152 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS,
242 ARMV6MPCORE_PERFCTR_DCACHE_RDMISS, 153 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DCACHE_WRMISS,
243 }, 154
244 [C(OP_WRITE)] = { 155 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
245 [C(RESULT_ACCESS)] = 156
246 ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS, 157 /*
247 [C(RESULT_MISS)] = 158 * The ARM performance counters can count micro DTLB misses, micro ITLB
248 ARMV6MPCORE_PERFCTR_DCACHE_WRMISS, 159 * misses and main TLB misses. There isn't an event for TLB misses, so
249 }, 160 * use the micro misses here and if users want the main TLB misses they
250 [C(OP_PREFETCH)] = { 161 * can use a raw counter.
251 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 162 */
252 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, 163 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS,
253 }, 164 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS,
254 }, 165
255 [C(L1I)] = { 166 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ITLB_MISS,
256 [C(OP_READ)] = { 167 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ITLB_MISS,
257 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
258 [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
259 },
260 [C(OP_WRITE)] = {
261 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
262 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
263 },
264 [C(OP_PREFETCH)] = {
265 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
266 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
267 },
268 },
269 [C(LL)] = {
270 [C(OP_READ)] = {
271 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
272 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
273 },
274 [C(OP_WRITE)] = {
275 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
276 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
277 },
278 [C(OP_PREFETCH)] = {
279 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
280 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
281 },
282 },
283 [C(DTLB)] = {
284 /*
285 * The ARM performance counters can count micro DTLB misses,
286 * micro ITLB misses and main TLB misses. There isn't an event
287 * for TLB misses, so use the micro misses here and if users
288 * want the main TLB misses they can use a raw counter.
289 */
290 [C(OP_READ)] = {
291 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
292 [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS,
293 },
294 [C(OP_WRITE)] = {
295 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
296 [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS,
297 },
298 [C(OP_PREFETCH)] = {
299 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
300 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
301 },
302 },
303 [C(ITLB)] = {
304 [C(OP_READ)] = {
305 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
306 [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ITLB_MISS,
307 },
308 [C(OP_WRITE)] = {
309 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
310 [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ITLB_MISS,
311 },
312 [C(OP_PREFETCH)] = {
313 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
314 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
315 },
316 },
317 [C(BPU)] = {
318 [C(OP_READ)] = {
319 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
320 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
321 },
322 [C(OP_WRITE)] = {
323 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
324 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
325 },
326 [C(OP_PREFETCH)] = {
327 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
328 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
329 },
330 },
331 [C(NODE)] = {
332 [C(OP_READ)] = {
333 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
334 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
335 },
336 [C(OP_WRITE)] = {
337 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
338 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
339 },
340 [C(OP_PREFETCH)] = {
341 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
342 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
343 },
344 },
345}; 168};
346 169
347static inline unsigned long 170static inline unsigned long
@@ -653,9 +476,8 @@ static int armv6_map_event(struct perf_event *event)
653 &armv6_perf_cache_map, 0xFF); 476 &armv6_perf_cache_map, 0xFF);
654} 477}
655 478
656static int armv6pmu_init(struct arm_pmu *cpu_pmu) 479static void armv6pmu_init(struct arm_pmu *cpu_pmu)
657{ 480{
658 cpu_pmu->name = "v6";
659 cpu_pmu->handle_irq = armv6pmu_handle_irq; 481 cpu_pmu->handle_irq = armv6pmu_handle_irq;
660 cpu_pmu->enable = armv6pmu_enable_event; 482 cpu_pmu->enable = armv6pmu_enable_event;
661 cpu_pmu->disable = armv6pmu_disable_event; 483 cpu_pmu->disable = armv6pmu_disable_event;
@@ -667,7 +489,26 @@ static int armv6pmu_init(struct arm_pmu *cpu_pmu)
667 cpu_pmu->map_event = armv6_map_event; 489 cpu_pmu->map_event = armv6_map_event;
668 cpu_pmu->num_events = 3; 490 cpu_pmu->num_events = 3;
669 cpu_pmu->max_period = (1LLU << 32) - 1; 491 cpu_pmu->max_period = (1LLU << 32) - 1;
492}
493
494static int armv6_1136_pmu_init(struct arm_pmu *cpu_pmu)
495{
496 armv6pmu_init(cpu_pmu);
497 cpu_pmu->name = "armv6_1136";
498 return 0;
499}
670 500
501static int armv6_1156_pmu_init(struct arm_pmu *cpu_pmu)
502{
503 armv6pmu_init(cpu_pmu);
504 cpu_pmu->name = "armv6_1156";
505 return 0;
506}
507
508static int armv6_1176_pmu_init(struct arm_pmu *cpu_pmu)
509{
510 armv6pmu_init(cpu_pmu);
511 cpu_pmu->name = "armv6_1176";
671 return 0; 512 return 0;
672} 513}
673 514
@@ -687,7 +528,7 @@ static int armv6mpcore_map_event(struct perf_event *event)
687 528
688static int armv6mpcore_pmu_init(struct arm_pmu *cpu_pmu) 529static int armv6mpcore_pmu_init(struct arm_pmu *cpu_pmu)
689{ 530{
690 cpu_pmu->name = "v6mpcore"; 531 cpu_pmu->name = "armv6_11mpcore";
691 cpu_pmu->handle_irq = armv6pmu_handle_irq; 532 cpu_pmu->handle_irq = armv6pmu_handle_irq;
692 cpu_pmu->enable = armv6pmu_enable_event; 533 cpu_pmu->enable = armv6pmu_enable_event;
693 cpu_pmu->disable = armv6mpcore_pmu_disable_event; 534 cpu_pmu->disable = armv6mpcore_pmu_disable_event;
@@ -703,7 +544,17 @@ static int armv6mpcore_pmu_init(struct arm_pmu *cpu_pmu)
703 return 0; 544 return 0;
704} 545}
705#else 546#else
706static int armv6pmu_init(struct arm_pmu *cpu_pmu) 547static int armv6_1136_pmu_init(struct arm_pmu *cpu_pmu)
548{
549 return -ENODEV;
550}
551
552static int armv6_1156_pmu_init(struct arm_pmu *cpu_pmu)
553{
554 return -ENODEV;
555}
556
557static int armv6_1176_pmu_init(struct arm_pmu *cpu_pmu)
707{ 558{
708 return -ENODEV; 559 return -ENODEV;
709} 560}
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index 1d37568c547a..116758b77f93 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -148,137 +148,62 @@ enum krait_perf_types {
148 * accesses/misses in hardware. 148 * accesses/misses in hardware.
149 */ 149 */
150static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = { 150static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = {
151 PERF_MAP_ALL_UNSUPPORTED,
151 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 152 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
152 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 153 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
153 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 154 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
154 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 155 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
155 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, 156 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
156 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 157 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
157 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
158 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV7_A8_PERFCTR_STALL_ISIDE, 158 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV7_A8_PERFCTR_STALL_ISIDE,
159 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = HW_OP_UNSUPPORTED,
160}; 159};
161 160
162static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 161static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
163 [PERF_COUNT_HW_CACHE_OP_MAX] 162 [PERF_COUNT_HW_CACHE_OP_MAX]
164 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 163 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
165 [C(L1D)] = { 164 PERF_CACHE_MAP_ALL_UNSUPPORTED,
166 /* 165
167 * The performance counters don't differentiate between read 166 /*
168 * and write accesses/misses so this isn't strictly correct, 167 * The performance counters don't differentiate between read and write
169 * but it's the best we can do. Writes and reads get 168 * accesses/misses so this isn't strictly correct, but it's the best we
170 * combined. 169 * can do. Writes and reads get combined.
171 */ 170 */
172 [C(OP_READ)] = { 171 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
173 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 172 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
174 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 173 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
175 }, 174 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
176 [C(OP_WRITE)] = { 175
177 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 176 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,
178 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 177 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
179 }, 178
180 [C(OP_PREFETCH)] = { 179 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
181 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 180 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
182 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, 181 [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
183 }, 182 [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
184 }, 183
185 [C(L1I)] = { 184 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
186 [C(OP_READ)] = { 185 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
187 [C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS, 186
188 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, 187 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
189 }, 188 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
190 [C(OP_WRITE)] = { 189
191 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 190 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
192 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, 191 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
193 }, 192 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
194 [C(OP_PREFETCH)] = { 193 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
195 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
196 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
197 },
198 },
199 [C(LL)] = {
200 [C(OP_READ)] = {
201 [C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
202 [C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
203 },
204 [C(OP_WRITE)] = {
205 [C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
206 [C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
207 },
208 [C(OP_PREFETCH)] = {
209 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
210 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
211 },
212 },
213 [C(DTLB)] = {
214 [C(OP_READ)] = {
215 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
216 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
217 },
218 [C(OP_WRITE)] = {
219 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
220 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
221 },
222 [C(OP_PREFETCH)] = {
223 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
224 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
225 },
226 },
227 [C(ITLB)] = {
228 [C(OP_READ)] = {
229 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
230 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
231 },
232 [C(OP_WRITE)] = {
233 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
234 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
235 },
236 [C(OP_PREFETCH)] = {
237 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
238 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
239 },
240 },
241 [C(BPU)] = {
242 [C(OP_READ)] = {
243 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
244 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
245 },
246 [C(OP_WRITE)] = {
247 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
248 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
249 },
250 [C(OP_PREFETCH)] = {
251 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
252 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
253 },
254 },
255 [C(NODE)] = {
256 [C(OP_READ)] = {
257 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
258 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
259 },
260 [C(OP_WRITE)] = {
261 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
262 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
263 },
264 [C(OP_PREFETCH)] = {
265 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
266 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
267 },
268 },
269}; 194};
270 195
271/* 196/*
272 * Cortex-A9 HW events mapping 197 * Cortex-A9 HW events mapping
273 */ 198 */
274static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = { 199static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = {
200 PERF_MAP_ALL_UNSUPPORTED,
275 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 201 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
276 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_A9_PERFCTR_INSTR_CORE_RENAME, 202 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_A9_PERFCTR_INSTR_CORE_RENAME,
277 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 203 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
278 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 204 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
279 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, 205 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
280 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 206 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
281 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
282 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV7_A9_PERFCTR_STALL_ICACHE, 207 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV7_A9_PERFCTR_STALL_ICACHE,
283 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV7_A9_PERFCTR_STALL_DISPATCH, 208 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV7_A9_PERFCTR_STALL_DISPATCH,
284}; 209};
@@ -286,238 +211,83 @@ static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = {
286static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 211static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
287 [PERF_COUNT_HW_CACHE_OP_MAX] 212 [PERF_COUNT_HW_CACHE_OP_MAX]
288 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 213 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
289 [C(L1D)] = { 214 PERF_CACHE_MAP_ALL_UNSUPPORTED,
290 /* 215
291 * The performance counters don't differentiate between read 216 /*
292 * and write accesses/misses so this isn't strictly correct, 217 * The performance counters don't differentiate between read and write
293 * but it's the best we can do. Writes and reads get 218 * accesses/misses so this isn't strictly correct, but it's the best we
294 * combined. 219 * can do. Writes and reads get combined.
295 */ 220 */
296 [C(OP_READ)] = { 221 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
297 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 222 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
298 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 223 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
299 }, 224 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
300 [C(OP_WRITE)] = { 225
301 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 226 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
302 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 227
303 }, 228 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
304 [C(OP_PREFETCH)] = { 229 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
305 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 230
306 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, 231 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
307 }, 232 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
308 }, 233
309 [C(L1I)] = { 234 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
310 [C(OP_READ)] = { 235 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
311 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 236 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
312 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, 237 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
313 },
314 [C(OP_WRITE)] = {
315 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
316 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
317 },
318 [C(OP_PREFETCH)] = {
319 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
320 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
321 },
322 },
323 [C(LL)] = {
324 [C(OP_READ)] = {
325 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
326 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
327 },
328 [C(OP_WRITE)] = {
329 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
330 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
331 },
332 [C(OP_PREFETCH)] = {
333 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
334 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
335 },
336 },
337 [C(DTLB)] = {
338 [C(OP_READ)] = {
339 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
340 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
341 },
342 [C(OP_WRITE)] = {
343 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
344 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
345 },
346 [C(OP_PREFETCH)] = {
347 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
348 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
349 },
350 },
351 [C(ITLB)] = {
352 [C(OP_READ)] = {
353 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
354 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
355 },
356 [C(OP_WRITE)] = {
357 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
358 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
359 },
360 [C(OP_PREFETCH)] = {
361 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
362 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
363 },
364 },
365 [C(BPU)] = {
366 [C(OP_READ)] = {
367 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
368 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
369 },
370 [C(OP_WRITE)] = {
371 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
372 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
373 },
374 [C(OP_PREFETCH)] = {
375 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
376 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
377 },
378 },
379 [C(NODE)] = {
380 [C(OP_READ)] = {
381 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
382 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
383 },
384 [C(OP_WRITE)] = {
385 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
386 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
387 },
388 [C(OP_PREFETCH)] = {
389 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
390 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
391 },
392 },
393}; 238};
394 239
395/* 240/*
396 * Cortex-A5 HW events mapping 241 * Cortex-A5 HW events mapping
397 */ 242 */
398static const unsigned armv7_a5_perf_map[PERF_COUNT_HW_MAX] = { 243static const unsigned armv7_a5_perf_map[PERF_COUNT_HW_MAX] = {
244 PERF_MAP_ALL_UNSUPPORTED,
399 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 245 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
400 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 246 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
401 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 247 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
402 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 248 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
403 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, 249 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
404 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 250 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
405 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
406 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = HW_OP_UNSUPPORTED,
407 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = HW_OP_UNSUPPORTED,
408}; 251};
409 252
410static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 253static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
411 [PERF_COUNT_HW_CACHE_OP_MAX] 254 [PERF_COUNT_HW_CACHE_OP_MAX]
412 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 255 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
413 [C(L1D)] = { 256 PERF_CACHE_MAP_ALL_UNSUPPORTED,
414 [C(OP_READ)] = { 257
415 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 258 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
416 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 259 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
417 }, 260 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
418 [C(OP_WRITE)] = { 261 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
419 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 262 [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL,
420 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 263 [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP,
421 }, 264
422 [C(OP_PREFETCH)] = { 265 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
423 [C(RESULT_ACCESS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL, 266 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
424 [C(RESULT_MISS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP, 267 /*
425 }, 268 * The prefetch counters don't differentiate between the I side and the
426 }, 269 * D side.
427 [C(L1I)] = { 270 */
428 [C(OP_READ)] = { 271 [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL,
429 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, 272 [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP,
430 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, 273
431 }, 274 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
432 [C(OP_WRITE)] = { 275 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
433 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 276
434 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, 277 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
435 }, 278 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
436 /* 279
437 * The prefetch counters don't differentiate between the I 280 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
438 * side and the D side. 281 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
439 */ 282 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
440 [C(OP_PREFETCH)] = { 283 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
441 [C(RESULT_ACCESS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL,
442 [C(RESULT_MISS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP,
443 },
444 },
445 [C(LL)] = {
446 [C(OP_READ)] = {
447 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
448 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
449 },
450 [C(OP_WRITE)] = {
451 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
452 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
453 },
454 [C(OP_PREFETCH)] = {
455 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
456 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
457 },
458 },
459 [C(DTLB)] = {
460 [C(OP_READ)] = {
461 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
462 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
463 },
464 [C(OP_WRITE)] = {
465 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
466 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
467 },
468 [C(OP_PREFETCH)] = {
469 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
470 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
471 },
472 },
473 [C(ITLB)] = {
474 [C(OP_READ)] = {
475 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
476 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
477 },
478 [C(OP_WRITE)] = {
479 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
480 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
481 },
482 [C(OP_PREFETCH)] = {
483 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
484 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
485 },
486 },
487 [C(BPU)] = {
488 [C(OP_READ)] = {
489 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
490 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
491 },
492 [C(OP_WRITE)] = {
493 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
494 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
495 },
496 [C(OP_PREFETCH)] = {
497 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
498 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
499 },
500 },
501 [C(NODE)] = {
502 [C(OP_READ)] = {
503 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
504 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
505 },
506 [C(OP_WRITE)] = {
507 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
508 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
509 },
510 [C(OP_PREFETCH)] = {
511 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
512 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
513 },
514 },
515}; 284};
516 285
517/* 286/*
518 * Cortex-A15 HW events mapping 287 * Cortex-A15 HW events mapping
519 */ 288 */
520static const unsigned armv7_a15_perf_map[PERF_COUNT_HW_MAX] = { 289static const unsigned armv7_a15_perf_map[PERF_COUNT_HW_MAX] = {
290 PERF_MAP_ALL_UNSUPPORTED,
521 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 291 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
522 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 292 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
523 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 293 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
@@ -525,123 +295,48 @@ static const unsigned armv7_a15_perf_map[PERF_COUNT_HW_MAX] = {
525 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_A15_PERFCTR_PC_WRITE_SPEC, 295 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_A15_PERFCTR_PC_WRITE_SPEC,
526 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 296 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
527 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES, 297 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES,
528 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = HW_OP_UNSUPPORTED,
529 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = HW_OP_UNSUPPORTED,
530}; 298};
531 299
532static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 300static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
533 [PERF_COUNT_HW_CACHE_OP_MAX] 301 [PERF_COUNT_HW_CACHE_OP_MAX]
534 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 302 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
535 [C(L1D)] = { 303 PERF_CACHE_MAP_ALL_UNSUPPORTED,
536 [C(OP_READ)] = { 304
537 [C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ, 305 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ,
538 [C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ, 306 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ,
539 }, 307 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE,
540 [C(OP_WRITE)] = { 308 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE,
541 [C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE, 309
542 [C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE, 310 /*
543 }, 311 * Not all performance counters differentiate between read and write
544 [C(OP_PREFETCH)] = { 312 * accesses/misses so we're not always strictly correct, but it's the
545 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 313 * best we can do. Writes and reads get combined in these cases.
546 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, 314 */
547 }, 315 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
548 }, 316 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
549 [C(L1I)] = { 317
550 /* 318 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ,
551 * Not all performance counters differentiate between read 319 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ,
552 * and write accesses/misses so we're not always strictly 320 [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE,
553 * correct, but it's the best we can do. Writes and reads get 321 [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE,
554 * combined in these cases. 322
555 */ 323 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ,
556 [C(OP_READ)] = { 324 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE,
557 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, 325
558 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, 326 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
559 }, 327 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
560 [C(OP_WRITE)] = { 328
561 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 329 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
562 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, 330 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
563 }, 331 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
564 [C(OP_PREFETCH)] = { 332 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
565 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
566 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
567 },
568 },
569 [C(LL)] = {
570 [C(OP_READ)] = {
571 [C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ,
572 [C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ,
573 },
574 [C(OP_WRITE)] = {
575 [C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE,
576 [C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE,
577 },
578 [C(OP_PREFETCH)] = {
579 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
580 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
581 },
582 },
583 [C(DTLB)] = {
584 [C(OP_READ)] = {
585 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
586 [C(RESULT_MISS)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ,
587 },
588 [C(OP_WRITE)] = {
589 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
590 [C(RESULT_MISS)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE,
591 },
592 [C(OP_PREFETCH)] = {
593 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
594 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
595 },
596 },
597 [C(ITLB)] = {
598 [C(OP_READ)] = {
599 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
600 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
601 },
602 [C(OP_WRITE)] = {
603 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
604 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
605 },
606 [C(OP_PREFETCH)] = {
607 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
608 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
609 },
610 },
611 [C(BPU)] = {
612 [C(OP_READ)] = {
613 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
614 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
615 },
616 [C(OP_WRITE)] = {
617 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
618 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
619 },
620 [C(OP_PREFETCH)] = {
621 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
622 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
623 },
624 },
625 [C(NODE)] = {
626 [C(OP_READ)] = {
627 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
628 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
629 },
630 [C(OP_WRITE)] = {
631 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
632 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
633 },
634 [C(OP_PREFETCH)] = {
635 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
636 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
637 },
638 },
639}; 333};
640 334
641/* 335/*
642 * Cortex-A7 HW events mapping 336 * Cortex-A7 HW events mapping
643 */ 337 */
644static const unsigned armv7_a7_perf_map[PERF_COUNT_HW_MAX] = { 338static const unsigned armv7_a7_perf_map[PERF_COUNT_HW_MAX] = {
339 PERF_MAP_ALL_UNSUPPORTED,
645 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 340 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
646 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 341 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
647 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 342 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
@@ -649,123 +344,48 @@ static const unsigned armv7_a7_perf_map[PERF_COUNT_HW_MAX] = {
649 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, 344 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
650 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 345 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
651 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES, 346 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES,
652 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = HW_OP_UNSUPPORTED,
653 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = HW_OP_UNSUPPORTED,
654}; 347};
655 348
656static const unsigned armv7_a7_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 349static const unsigned armv7_a7_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
657 [PERF_COUNT_HW_CACHE_OP_MAX] 350 [PERF_COUNT_HW_CACHE_OP_MAX]
658 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 351 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
659 [C(L1D)] = { 352 PERF_CACHE_MAP_ALL_UNSUPPORTED,
660 /* 353
661 * The performance counters don't differentiate between read 354 /*
662 * and write accesses/misses so this isn't strictly correct, 355 * The performance counters don't differentiate between read and write
663 * but it's the best we can do. Writes and reads get 356 * accesses/misses so this isn't strictly correct, but it's the best we
664 * combined. 357 * can do. Writes and reads get combined.
665 */ 358 */
666 [C(OP_READ)] = { 359 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
667 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 360 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
668 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 361 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
669 }, 362 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
670 [C(OP_WRITE)] = { 363
671 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 364 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
672 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 365 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
673 }, 366
674 [C(OP_PREFETCH)] = { 367 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_CACHE_ACCESS,
675 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 368 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL,
676 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, 369 [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_CACHE_ACCESS,
677 }, 370 [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL,
678 }, 371
679 [C(L1I)] = { 372 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
680 [C(OP_READ)] = { 373 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
681 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, 374
682 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, 375 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
683 }, 376 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
684 [C(OP_WRITE)] = { 377
685 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 378 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
686 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, 379 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
687 }, 380 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
688 [C(OP_PREFETCH)] = { 381 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
689 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
690 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
691 },
692 },
693 [C(LL)] = {
694 [C(OP_READ)] = {
695 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_CACHE_ACCESS,
696 [C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL,
697 },
698 [C(OP_WRITE)] = {
699 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_CACHE_ACCESS,
700 [C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL,
701 },
702 [C(OP_PREFETCH)] = {
703 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
704 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
705 },
706 },
707 [C(DTLB)] = {
708 [C(OP_READ)] = {
709 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
710 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
711 },
712 [C(OP_WRITE)] = {
713 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
714 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
715 },
716 [C(OP_PREFETCH)] = {
717 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
718 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
719 },
720 },
721 [C(ITLB)] = {
722 [C(OP_READ)] = {
723 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
724 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
725 },
726 [C(OP_WRITE)] = {
727 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
728 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
729 },
730 [C(OP_PREFETCH)] = {
731 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
732 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
733 },
734 },
735 [C(BPU)] = {
736 [C(OP_READ)] = {
737 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
738 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
739 },
740 [C(OP_WRITE)] = {
741 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
742 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
743 },
744 [C(OP_PREFETCH)] = {
745 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
746 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
747 },
748 },
749 [C(NODE)] = {
750 [C(OP_READ)] = {
751 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
752 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
753 },
754 [C(OP_WRITE)] = {
755 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
756 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
757 },
758 [C(OP_PREFETCH)] = {
759 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
760 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
761 },
762 },
763}; 382};
764 383
765/* 384/*
766 * Cortex-A12 HW events mapping 385 * Cortex-A12 HW events mapping
767 */ 386 */
768static const unsigned armv7_a12_perf_map[PERF_COUNT_HW_MAX] = { 387static const unsigned armv7_a12_perf_map[PERF_COUNT_HW_MAX] = {
388 PERF_MAP_ALL_UNSUPPORTED,
769 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 389 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
770 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 390 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
771 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 391 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
@@ -773,138 +393,60 @@ static const unsigned armv7_a12_perf_map[PERF_COUNT_HW_MAX] = {
773 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_A12_PERFCTR_PC_WRITE_SPEC, 393 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_A12_PERFCTR_PC_WRITE_SPEC,
774 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 394 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
775 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES, 395 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES,
776 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = HW_OP_UNSUPPORTED,
777 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = HW_OP_UNSUPPORTED,
778}; 396};
779 397
780static const unsigned armv7_a12_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 398static const unsigned armv7_a12_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
781 [PERF_COUNT_HW_CACHE_OP_MAX] 399 [PERF_COUNT_HW_CACHE_OP_MAX]
782 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 400 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
783 [C(L1D)] = { 401 PERF_CACHE_MAP_ALL_UNSUPPORTED,
784 [C(OP_READ)] = { 402
785 [C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ, 403 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ,
786 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 404 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
787 }, 405 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE,
788 [C(OP_WRITE)] = { 406 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
789 [C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE, 407
790 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 408 /*
791 }, 409 * Not all performance counters differentiate between read and write
792 [C(OP_PREFETCH)] = { 410 * accesses/misses so we're not always strictly correct, but it's the
793 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 411 * best we can do. Writes and reads get combined in these cases.
794 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, 412 */
795 }, 413 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
796 }, 414 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
797 [C(L1I)] = { 415
798 /* 416 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ,
799 * Not all performance counters differentiate between read 417 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL,
800 * and write accesses/misses so we're not always strictly 418 [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE,
801 * correct, but it's the best we can do. Writes and reads get 419 [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL,
802 * combined in these cases. 420
803 */ 421 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
804 [C(OP_READ)] = { 422 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
805 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, 423 [C(DTLB)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV7_A12_PERFCTR_PF_TLB_REFILL,
806 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, 424
807 }, 425 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
808 [C(OP_WRITE)] = { 426 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
809 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 427
810 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, 428 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
811 }, 429 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
812 [C(OP_PREFETCH)] = { 430 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
813 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 431 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
814 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
815 },
816 },
817 [C(LL)] = {
818 [C(OP_READ)] = {
819 [C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ,
820 [C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL,
821 },
822 [C(OP_WRITE)] = {
823 [C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE,
824 [C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL,
825 },
826 [C(OP_PREFETCH)] = {
827 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
828 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
829 },
830 },
831 [C(DTLB)] = {
832 [C(OP_READ)] = {
833 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
834 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
835 },
836 [C(OP_WRITE)] = {
837 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
838 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
839 },
840 [C(OP_PREFETCH)] = {
841 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
842 [C(RESULT_MISS)] = ARMV7_A12_PERFCTR_PF_TLB_REFILL,
843 },
844 },
845 [C(ITLB)] = {
846 [C(OP_READ)] = {
847 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
848 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
849 },
850 [C(OP_WRITE)] = {
851 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
852 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
853 },
854 [C(OP_PREFETCH)] = {
855 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
856 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
857 },
858 },
859 [C(BPU)] = {
860 [C(OP_READ)] = {
861 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
862 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
863 },
864 [C(OP_WRITE)] = {
865 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
866 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
867 },
868 [C(OP_PREFETCH)] = {
869 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
870 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
871 },
872 },
873 [C(NODE)] = {
874 [C(OP_READ)] = {
875 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
876 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
877 },
878 [C(OP_WRITE)] = {
879 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
880 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
881 },
882 [C(OP_PREFETCH)] = {
883 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
884 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
885 },
886 },
887}; 432};
888 433
889/* 434/*
890 * Krait HW events mapping 435 * Krait HW events mapping
891 */ 436 */
892static const unsigned krait_perf_map[PERF_COUNT_HW_MAX] = { 437static const unsigned krait_perf_map[PERF_COUNT_HW_MAX] = {
438 PERF_MAP_ALL_UNSUPPORTED,
893 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 439 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
894 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 440 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
895 [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
896 [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
897 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, 441 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
898 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 442 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
899 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES, 443 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES,
900}; 444};
901 445
902static const unsigned krait_perf_map_no_branch[PERF_COUNT_HW_MAX] = { 446static const unsigned krait_perf_map_no_branch[PERF_COUNT_HW_MAX] = {
447 PERF_MAP_ALL_UNSUPPORTED,
903 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 448 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
904 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 449 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
905 [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
906 [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
907 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = HW_OP_UNSUPPORTED,
908 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 450 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
909 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES, 451 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES,
910}; 452};
@@ -912,110 +454,31 @@ static const unsigned krait_perf_map_no_branch[PERF_COUNT_HW_MAX] = {
912static const unsigned krait_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 454static const unsigned krait_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
913 [PERF_COUNT_HW_CACHE_OP_MAX] 455 [PERF_COUNT_HW_CACHE_OP_MAX]
914 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 456 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
915 [C(L1D)] = { 457 PERF_CACHE_MAP_ALL_UNSUPPORTED,
916 /* 458
917 * The performance counters don't differentiate between read 459 /*
918 * and write accesses/misses so this isn't strictly correct, 460 * The performance counters don't differentiate between read and write
919 * but it's the best we can do. Writes and reads get 461 * accesses/misses so this isn't strictly correct, but it's the best we
920 * combined. 462 * can do. Writes and reads get combined.
921 */ 463 */
922 [C(OP_READ)] = { 464 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
923 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 465 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
924 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 466 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
925 }, 467 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
926 [C(OP_WRITE)] = { 468
927 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 469 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ICACHE_ACCESS,
928 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 470 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = KRAIT_PERFCTR_L1_ICACHE_MISS,
929 }, 471
930 [C(OP_PREFETCH)] = { 472 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_DTLB_ACCESS,
931 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 473 [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_DTLB_ACCESS,
932 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, 474
933 }, 475 [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ITLB_ACCESS,
934 }, 476 [C(ITLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ITLB_ACCESS,
935 [C(L1I)] = { 477
936 [C(OP_READ)] = { 478 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
937 [C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ICACHE_ACCESS, 479 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
938 [C(RESULT_MISS)] = KRAIT_PERFCTR_L1_ICACHE_MISS, 480 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
939 }, 481 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
940 [C(OP_WRITE)] = {
941 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
942 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
943 },
944 [C(OP_PREFETCH)] = {
945 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
946 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
947 },
948 },
949 [C(LL)] = {
950 [C(OP_READ)] = {
951 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
952 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
953 },
954 [C(OP_WRITE)] = {
955 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
956 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
957 },
958 [C(OP_PREFETCH)] = {
959 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
960 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
961 },
962 },
963 [C(DTLB)] = {
964 [C(OP_READ)] = {
965 [C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_DTLB_ACCESS,
966 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
967 },
968 [C(OP_WRITE)] = {
969 [C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_DTLB_ACCESS,
970 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
971 },
972 [C(OP_PREFETCH)] = {
973 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
974 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
975 },
976 },
977 [C(ITLB)] = {
978 [C(OP_READ)] = {
979 [C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ITLB_ACCESS,
980 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
981 },
982 [C(OP_WRITE)] = {
983 [C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ITLB_ACCESS,
984 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
985 },
986 [C(OP_PREFETCH)] = {
987 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
988 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
989 },
990 },
991 [C(BPU)] = {
992 [C(OP_READ)] = {
993 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
994 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
995 },
996 [C(OP_WRITE)] = {
997 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
998 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
999 },
1000 [C(OP_PREFETCH)] = {
1001 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1002 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1003 },
1004 },
1005 [C(NODE)] = {
1006 [C(OP_READ)] = {
1007 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1008 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1009 },
1010 [C(OP_WRITE)] = {
1011 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1012 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1013 },
1014 [C(OP_PREFETCH)] = {
1015 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1016 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1017 },
1018 },
1019}; 482};
1020 483
1021/* 484/*
@@ -1545,7 +1008,7 @@ static u32 armv7_read_num_pmnc_events(void)
1545static int armv7_a8_pmu_init(struct arm_pmu *cpu_pmu) 1008static int armv7_a8_pmu_init(struct arm_pmu *cpu_pmu)
1546{ 1009{
1547 armv7pmu_init(cpu_pmu); 1010 armv7pmu_init(cpu_pmu);
1548 cpu_pmu->name = "ARMv7 Cortex-A8"; 1011 cpu_pmu->name = "armv7_cortex_a8";
1549 cpu_pmu->map_event = armv7_a8_map_event; 1012 cpu_pmu->map_event = armv7_a8_map_event;
1550 cpu_pmu->num_events = armv7_read_num_pmnc_events(); 1013 cpu_pmu->num_events = armv7_read_num_pmnc_events();
1551 return 0; 1014 return 0;
@@ -1554,7 +1017,7 @@ static int armv7_a8_pmu_init(struct arm_pmu *cpu_pmu)
1554static int armv7_a9_pmu_init(struct arm_pmu *cpu_pmu) 1017static int armv7_a9_pmu_init(struct arm_pmu *cpu_pmu)
1555{ 1018{
1556 armv7pmu_init(cpu_pmu); 1019 armv7pmu_init(cpu_pmu);
1557 cpu_pmu->name = "ARMv7 Cortex-A9"; 1020 cpu_pmu->name = "armv7_cortex_a9";
1558 cpu_pmu->map_event = armv7_a9_map_event; 1021 cpu_pmu->map_event = armv7_a9_map_event;
1559 cpu_pmu->num_events = armv7_read_num_pmnc_events(); 1022 cpu_pmu->num_events = armv7_read_num_pmnc_events();
1560 return 0; 1023 return 0;
@@ -1563,7 +1026,7 @@ static int armv7_a9_pmu_init(struct arm_pmu *cpu_pmu)
1563static int armv7_a5_pmu_init(struct arm_pmu *cpu_pmu) 1026static int armv7_a5_pmu_init(struct arm_pmu *cpu_pmu)
1564{ 1027{
1565 armv7pmu_init(cpu_pmu); 1028 armv7pmu_init(cpu_pmu);
1566 cpu_pmu->name = "ARMv7 Cortex-A5"; 1029 cpu_pmu->name = "armv7_cortex_a5";
1567 cpu_pmu->map_event = armv7_a5_map_event; 1030 cpu_pmu->map_event = armv7_a5_map_event;
1568 cpu_pmu->num_events = armv7_read_num_pmnc_events(); 1031 cpu_pmu->num_events = armv7_read_num_pmnc_events();
1569 return 0; 1032 return 0;
@@ -1572,7 +1035,7 @@ static int armv7_a5_pmu_init(struct arm_pmu *cpu_pmu)
1572static int armv7_a15_pmu_init(struct arm_pmu *cpu_pmu) 1035static int armv7_a15_pmu_init(struct arm_pmu *cpu_pmu)
1573{ 1036{
1574 armv7pmu_init(cpu_pmu); 1037 armv7pmu_init(cpu_pmu);
1575 cpu_pmu->name = "ARMv7 Cortex-A15"; 1038 cpu_pmu->name = "armv7_cortex_a15";
1576 cpu_pmu->map_event = armv7_a15_map_event; 1039 cpu_pmu->map_event = armv7_a15_map_event;
1577 cpu_pmu->num_events = armv7_read_num_pmnc_events(); 1040 cpu_pmu->num_events = armv7_read_num_pmnc_events();
1578 cpu_pmu->set_event_filter = armv7pmu_set_event_filter; 1041 cpu_pmu->set_event_filter = armv7pmu_set_event_filter;
@@ -1582,7 +1045,7 @@ static int armv7_a15_pmu_init(struct arm_pmu *cpu_pmu)
1582static int armv7_a7_pmu_init(struct arm_pmu *cpu_pmu) 1045static int armv7_a7_pmu_init(struct arm_pmu *cpu_pmu)
1583{ 1046{
1584 armv7pmu_init(cpu_pmu); 1047 armv7pmu_init(cpu_pmu);
1585 cpu_pmu->name = "ARMv7 Cortex-A7"; 1048 cpu_pmu->name = "armv7_cortex_a7";
1586 cpu_pmu->map_event = armv7_a7_map_event; 1049 cpu_pmu->map_event = armv7_a7_map_event;
1587 cpu_pmu->num_events = armv7_read_num_pmnc_events(); 1050 cpu_pmu->num_events = armv7_read_num_pmnc_events();
1588 cpu_pmu->set_event_filter = armv7pmu_set_event_filter; 1051 cpu_pmu->set_event_filter = armv7pmu_set_event_filter;
@@ -1592,7 +1055,7 @@ static int armv7_a7_pmu_init(struct arm_pmu *cpu_pmu)
1592static int armv7_a12_pmu_init(struct arm_pmu *cpu_pmu) 1055static int armv7_a12_pmu_init(struct arm_pmu *cpu_pmu)
1593{ 1056{
1594 armv7pmu_init(cpu_pmu); 1057 armv7pmu_init(cpu_pmu);
1595 cpu_pmu->name = "ARMv7 Cortex-A12"; 1058 cpu_pmu->name = "armv7_cortex_a12";
1596 cpu_pmu->map_event = armv7_a12_map_event; 1059 cpu_pmu->map_event = armv7_a12_map_event;
1597 cpu_pmu->num_events = armv7_read_num_pmnc_events(); 1060 cpu_pmu->num_events = armv7_read_num_pmnc_events();
1598 cpu_pmu->set_event_filter = armv7pmu_set_event_filter; 1061 cpu_pmu->set_event_filter = armv7pmu_set_event_filter;
@@ -1602,7 +1065,7 @@ static int armv7_a12_pmu_init(struct arm_pmu *cpu_pmu)
1602static int armv7_a17_pmu_init(struct arm_pmu *cpu_pmu) 1065static int armv7_a17_pmu_init(struct arm_pmu *cpu_pmu)
1603{ 1066{
1604 armv7_a12_pmu_init(cpu_pmu); 1067 armv7_a12_pmu_init(cpu_pmu);
1605 cpu_pmu->name = "ARMv7 Cortex-A17"; 1068 cpu_pmu->name = "armv7_cortex_a17";
1606 return 0; 1069 return 0;
1607} 1070}
1608 1071
@@ -1823,6 +1286,7 @@ static void krait_pmu_disable_event(struct perf_event *event)
1823 unsigned long flags; 1286 unsigned long flags;
1824 struct hw_perf_event *hwc = &event->hw; 1287 struct hw_perf_event *hwc = &event->hw;
1825 int idx = hwc->idx; 1288 int idx = hwc->idx;
1289 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
1826 struct pmu_hw_events *events = cpu_pmu->get_hw_events(); 1290 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
1827 1291
1828 /* Disable counter and interrupt */ 1292 /* Disable counter and interrupt */
@@ -1848,6 +1312,7 @@ static void krait_pmu_enable_event(struct perf_event *event)
1848 unsigned long flags; 1312 unsigned long flags;
1849 struct hw_perf_event *hwc = &event->hw; 1313 struct hw_perf_event *hwc = &event->hw;
1850 int idx = hwc->idx; 1314 int idx = hwc->idx;
1315 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
1851 struct pmu_hw_events *events = cpu_pmu->get_hw_events(); 1316 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
1852 1317
1853 /* 1318 /*
@@ -1981,7 +1446,7 @@ static void krait_pmu_clear_event_idx(struct pmu_hw_events *cpuc,
1981static int krait_pmu_init(struct arm_pmu *cpu_pmu) 1446static int krait_pmu_init(struct arm_pmu *cpu_pmu)
1982{ 1447{
1983 armv7pmu_init(cpu_pmu); 1448 armv7pmu_init(cpu_pmu);
1984 cpu_pmu->name = "ARMv7 Krait"; 1449 cpu_pmu->name = "armv7_krait";
1985 /* Some early versions of Krait don't support PC write events */ 1450 /* Some early versions of Krait don't support PC write events */
1986 if (of_property_read_bool(cpu_pmu->plat_device->dev.of_node, 1451 if (of_property_read_bool(cpu_pmu->plat_device->dev.of_node,
1987 "qcom,no-pc-write")) 1452 "qcom,no-pc-write"))
diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c
index 63990c42fac9..08da0af550b7 100644
--- a/arch/arm/kernel/perf_event_xscale.c
+++ b/arch/arm/kernel/perf_event_xscale.c
@@ -48,118 +48,31 @@ enum xscale_counters {
48}; 48};
49 49
50static const unsigned xscale_perf_map[PERF_COUNT_HW_MAX] = { 50static const unsigned xscale_perf_map[PERF_COUNT_HW_MAX] = {
51 PERF_MAP_ALL_UNSUPPORTED,
51 [PERF_COUNT_HW_CPU_CYCLES] = XSCALE_PERFCTR_CCNT, 52 [PERF_COUNT_HW_CPU_CYCLES] = XSCALE_PERFCTR_CCNT,
52 [PERF_COUNT_HW_INSTRUCTIONS] = XSCALE_PERFCTR_INSTRUCTION, 53 [PERF_COUNT_HW_INSTRUCTIONS] = XSCALE_PERFCTR_INSTRUCTION,
53 [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
54 [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
55 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = XSCALE_PERFCTR_BRANCH, 54 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = XSCALE_PERFCTR_BRANCH,
56 [PERF_COUNT_HW_BRANCH_MISSES] = XSCALE_PERFCTR_BRANCH_MISS, 55 [PERF_COUNT_HW_BRANCH_MISSES] = XSCALE_PERFCTR_BRANCH_MISS,
57 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
58 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = XSCALE_PERFCTR_ICACHE_NO_DELIVER, 56 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = XSCALE_PERFCTR_ICACHE_NO_DELIVER,
59 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = HW_OP_UNSUPPORTED,
60}; 57};
61 58
62static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 59static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
63 [PERF_COUNT_HW_CACHE_OP_MAX] 60 [PERF_COUNT_HW_CACHE_OP_MAX]
64 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 61 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
65 [C(L1D)] = { 62 PERF_CACHE_MAP_ALL_UNSUPPORTED,
66 [C(OP_READ)] = { 63
67 [C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS, 64 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS,
68 [C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS, 65 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS,
69 }, 66 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS,
70 [C(OP_WRITE)] = { 67 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS,
71 [C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS, 68
72 [C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS, 69 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = XSCALE_PERFCTR_ICACHE_MISS,
73 }, 70
74 [C(OP_PREFETCH)] = { 71 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = XSCALE_PERFCTR_DTLB_MISS,
75 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 72 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = XSCALE_PERFCTR_DTLB_MISS,
76 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, 73
77 }, 74 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = XSCALE_PERFCTR_ITLB_MISS,
78 }, 75 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = XSCALE_PERFCTR_ITLB_MISS,
79 [C(L1I)] = {
80 [C(OP_READ)] = {
81 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
82 [C(RESULT_MISS)] = XSCALE_PERFCTR_ICACHE_MISS,
83 },
84 [C(OP_WRITE)] = {
85 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
86 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
87 },
88 [C(OP_PREFETCH)] = {
89 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
90 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
91 },
92 },
93 [C(LL)] = {
94 [C(OP_READ)] = {
95 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
96 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
97 },
98 [C(OP_WRITE)] = {
99 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
100 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
101 },
102 [C(OP_PREFETCH)] = {
103 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
104 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
105 },
106 },
107 [C(DTLB)] = {
108 [C(OP_READ)] = {
109 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
110 [C(RESULT_MISS)] = XSCALE_PERFCTR_DTLB_MISS,
111 },
112 [C(OP_WRITE)] = {
113 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
114 [C(RESULT_MISS)] = XSCALE_PERFCTR_DTLB_MISS,
115 },
116 [C(OP_PREFETCH)] = {
117 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
118 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
119 },
120 },
121 [C(ITLB)] = {
122 [C(OP_READ)] = {
123 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
124 [C(RESULT_MISS)] = XSCALE_PERFCTR_ITLB_MISS,
125 },
126 [C(OP_WRITE)] = {
127 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
128 [C(RESULT_MISS)] = XSCALE_PERFCTR_ITLB_MISS,
129 },
130 [C(OP_PREFETCH)] = {
131 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
132 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
133 },
134 },
135 [C(BPU)] = {
136 [C(OP_READ)] = {
137 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
138 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
139 },
140 [C(OP_WRITE)] = {
141 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
142 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
143 },
144 [C(OP_PREFETCH)] = {
145 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
146 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
147 },
148 },
149 [C(NODE)] = {
150 [C(OP_READ)] = {
151 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
152 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
153 },
154 [C(OP_WRITE)] = {
155 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
156 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
157 },
158 [C(OP_PREFETCH)] = {
159 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
160 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
161 },
162 },
163}; 76};
164 77
165#define XSCALE_PMU_ENABLE 0x001 78#define XSCALE_PMU_ENABLE 0x001
@@ -442,7 +355,7 @@ static int xscale_map_event(struct perf_event *event)
442 355
443static int xscale1pmu_init(struct arm_pmu *cpu_pmu) 356static int xscale1pmu_init(struct arm_pmu *cpu_pmu)
444{ 357{
445 cpu_pmu->name = "xscale1"; 358 cpu_pmu->name = "armv5_xscale1";
446 cpu_pmu->handle_irq = xscale1pmu_handle_irq; 359 cpu_pmu->handle_irq = xscale1pmu_handle_irq;
447 cpu_pmu->enable = xscale1pmu_enable_event; 360 cpu_pmu->enable = xscale1pmu_enable_event;
448 cpu_pmu->disable = xscale1pmu_disable_event; 361 cpu_pmu->disable = xscale1pmu_disable_event;
@@ -812,7 +725,7 @@ static inline void xscale2pmu_write_counter(struct perf_event *event, u32 val)
812 725
813static int xscale2pmu_init(struct arm_pmu *cpu_pmu) 726static int xscale2pmu_init(struct arm_pmu *cpu_pmu)
814{ 727{
815 cpu_pmu->name = "xscale2"; 728 cpu_pmu->name = "armv5_xscale2";
816 cpu_pmu->handle_irq = xscale2pmu_handle_irq; 729 cpu_pmu->handle_irq = xscale2pmu_handle_irq;
817 cpu_pmu->enable = xscale2pmu_enable_event; 730 cpu_pmu->enable = xscale2pmu_enable_event;
818 cpu_pmu->disable = xscale2pmu_disable_event; 731 cpu_pmu->disable = xscale2pmu_disable_event;
diff --git a/arch/arm/oprofile/common.c b/arch/arm/oprofile/common.c
index e6a3c4c92163..cc649a1e46da 100644
--- a/arch/arm/oprofile/common.c
+++ b/arch/arm/oprofile/common.c
@@ -33,12 +33,14 @@ static struct op_perf_name {
33 char *perf_name; 33 char *perf_name;
34 char *op_name; 34 char *op_name;
35} op_perf_name_map[] = { 35} op_perf_name_map[] = {
36 { "xscale1", "arm/xscale1" }, 36 { "armv5_xscale1", "arm/xscale1" },
37 { "xscale1", "arm/xscale2" }, 37 { "armv5_xscale2", "arm/xscale2" },
38 { "v6", "arm/armv6" }, 38 { "armv6_1136", "arm/armv6" },
39 { "v6mpcore", "arm/mpcore" }, 39 { "armv6_1156", "arm/armv6" },
40 { "ARMv7 Cortex-A8", "arm/armv7" }, 40 { "armv6_1176", "arm/armv6" },
41 { "ARMv7 Cortex-A9", "arm/armv7-ca9" }, 41 { "armv6_11mpcore", "arm/mpcore" },
42 { "armv7_cortex_a8", "arm/armv7" },
43 { "armv7_cortex_a9", "arm/armv7-ca9" },
42}; 44};
43 45
44char *op_name_from_perf_id(void) 46char *op_name_from_perf_id(void)
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-19 10:44:29 -0400