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authorMichael Neuling <mikey@neuling.org>2018-09-13 01:33:47 -0400
committerMichael Ellerman <mpe@ellerman.id.au>2018-09-17 02:23:28 -0400
commitf14040bca89258b8a1c71e2112e430462172ce93 (patch)
treef7179ab15ba302b978937ad2a27018fc8fe5a410
parent11da3a7f84f19c26da6f86af878298694ede0804 (diff)
KVM: PPC: Book3S HV: Fix guest r11 corruption with POWER9 TM workarounds
When we come into the softpatch handler (0x1500), we use r11 to store the HSRR0 for later use by the denorm handler. We also use the softpatch handler for the TM workarounds for POWER9. Unfortunately, in kvmppc_interrupt_hv we later store r11 out to the vcpu assuming it's still what we got from userspace. This causes r11 to be corrupted in the VCPU and hence when we restore the guest, we get a corrupted r11. We've seen this when running TM tests inside guests on P9. This fixes the problem by only touching r11 in the denorm case. Fixes: 4bb3c7a020 ("KVM: PPC: Book3S HV: Work around transactional memory bugs in POWER9") Cc: <stable@vger.kernel.org> # 4.17+ Test-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Reviewed-by: Paul Mackerras <paulus@ozlabs.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
-rw-r--r--arch/powerpc/kernel/exceptions-64s.S4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index ea04dfb8c092..2d8fc8c9da7a 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -1314,9 +1314,7 @@ EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100)
1314 1314
1315#ifdef CONFIG_PPC_DENORMALISATION 1315#ifdef CONFIG_PPC_DENORMALISATION
1316 mfspr r10,SPRN_HSRR1 1316 mfspr r10,SPRN_HSRR1
1317 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
1318 andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */ 1317 andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */
1319 addi r11,r11,-4 /* HSRR0 is next instruction */
1320 bne+ denorm_assist 1318 bne+ denorm_assist
1321#endif 1319#endif
1322 1320
@@ -1382,6 +1380,8 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1382 */ 1380 */
1383 XVCPSGNDP32(32) 1381 XVCPSGNDP32(32)
1384denorm_done: 1382denorm_done:
1383 mfspr r11,SPRN_HSRR0
1384 subi r11,r11,4
1385 mtspr SPRN_HSRR0,r11 1385 mtspr SPRN_HSRR0,r11
1386 mtcrf 0x80,r9 1386 mtcrf 0x80,r9
1387 ld r9,PACA_EXGEN+EX_R9(r13) 1387 ld r9,PACA_EXGEN+EX_R9(r13)