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authorEric Bernstein <eric.bernstein@amd.com>2018-04-26 14:06:00 -0400
committerAlex Deucher <alexander.deucher@amd.com>2018-05-18 17:08:29 -0400
commitf0cd0a346dfd1df4b691fe38dafb51911392fbce (patch)
tree1fb15d20cd92ab8fd10f28c5175ef0ea984c8d43
parenta944744ba517256fcc9311e12c083563cbbe7c88 (diff)
drm/amd/display: DCN1 link encoder
Create DCN1 link encoder files and update AUX and HPD register access. Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c2
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn10/Makefile2
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c1362
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h330
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c43
5 files changed, 1716 insertions, 23 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 7c866a7d5e77..82cd1d6e6e59 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -11,8 +11,6 @@
11#include "dc_link_dp.h" 11#include "dc_link_dp.h"
12#include "dc_link_ddc.h" 12#include "dc_link_ddc.h"
13#include "dm_helpers.h" 13#include "dm_helpers.h"
14#include "dce/dce_link_encoder.h"
15#include "dce/dce_stream_encoder.h"
16#include "dpcd_defs.h" 14#include "dpcd_defs.h"
17 15
18enum dc_status core_link_read_dpcd( 16enum dc_status core_link_read_dpcd(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
index 5c69743a4b4f..84f52c63d95c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
@@ -26,7 +26,7 @@ DCN10 = dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \
26 dcn10_dpp.o dcn10_opp.o dcn10_optc.o \ 26 dcn10_dpp.o dcn10_opp.o dcn10_optc.o \
27 dcn10_hubp.o dcn10_mpc.o \ 27 dcn10_hubp.o dcn10_mpc.o \
28 dcn10_dpp_dscl.o dcn10_dpp_cm.o dcn10_cm_common.o \ 28 dcn10_dpp_dscl.o dcn10_dpp_cm.o dcn10_cm_common.o \
29 dcn10_hubbub.o dcn10_stream_encoder.o 29 dcn10_hubbub.o dcn10_stream_encoder.o dcn10_link_encoder.o
30 30
31AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10)) 31AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10))
32 32
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
new file mode 100644
index 000000000000..21fa40ac0786
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
@@ -0,0 +1,1362 @@
1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "reg_helper.h"
27
28#include "core_types.h"
29#include "link_encoder.h"
30#include "dcn10_link_encoder.h"
31#include "stream_encoder.h"
32#include "i2caux_interface.h"
33#include "dc_bios_types.h"
34
35#include "gpio_service_interface.h"
36
37#define CTX \
38 enc10->base.ctx
39#define DC_LOGGER \
40 enc10->base.ctx->logger
41
42#define REG(reg)\
43 (enc10->link_regs->reg)
44
45#undef FN
46#define FN(reg_name, field_name) \
47 enc10->link_shift->field_name, enc10->link_mask->field_name
48
49
50/*
51 * @brief
52 * Trigger Source Select
53 * ASIC-dependent, actual values for register programming
54 */
55#define DCN10_DIG_FE_SOURCE_SELECT_INVALID 0x0
56#define DCN10_DIG_FE_SOURCE_SELECT_DIGA 0x1
57#define DCN10_DIG_FE_SOURCE_SELECT_DIGB 0x2
58#define DCN10_DIG_FE_SOURCE_SELECT_DIGC 0x4
59#define DCN10_DIG_FE_SOURCE_SELECT_DIGD 0x08
60#define DCN10_DIG_FE_SOURCE_SELECT_DIGE 0x10
61#define DCN10_DIG_FE_SOURCE_SELECT_DIGF 0x20
62#define DCN10_DIG_FE_SOURCE_SELECT_DIGG 0x40
63
64enum {
65 DP_MST_UPDATE_MAX_RETRY = 50
66};
67
68
69
70static void aux_initialize(struct dcn10_link_encoder *enc10);
71
72
73static const struct link_encoder_funcs dcn10_lnk_enc_funcs = {
74 .validate_output_with_stream =
75 dcn10_link_encoder_validate_output_with_stream,
76 .hw_init = dcn10_link_encoder_hw_init,
77 .setup = dcn10_link_encoder_setup,
78 .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
79 .enable_dp_output = dcn10_link_encoder_enable_dp_output,
80 .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
81 .disable_output = dcn10_link_encoder_disable_output,
82 .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
83 .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
84 .update_mst_stream_allocation_table =
85 dcn10_link_encoder_update_mst_stream_allocation_table,
86 .psr_program_dp_dphy_fast_training =
87 dcn10_psr_program_dp_dphy_fast_training,
88 .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
89 .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
90 .enable_hpd = dcn10_link_encoder_enable_hpd,
91 .disable_hpd = dcn10_link_encoder_disable_hpd,
92 .is_dig_enabled = dcn10_is_dig_enabled,
93 .destroy = dcn10_link_encoder_destroy
94};
95
96static enum bp_result link_transmitter_control(
97 struct dcn10_link_encoder *enc10,
98 struct bp_transmitter_control *cntl)
99{
100 enum bp_result result;
101 struct dc_bios *bp = enc10->base.ctx->dc_bios;
102
103 result = bp->funcs->transmitter_control(bp, cntl);
104
105 return result;
106}
107
108static void enable_phy_bypass_mode(
109 struct dcn10_link_encoder *enc10,
110 bool enable)
111{
112 /* This register resides in DP back end block;
113 * transmitter is used for the offset
114 */
115 REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable);
116
117}
118
119static void disable_prbs_symbols(
120 struct dcn10_link_encoder *enc10,
121 bool disable)
122{
123 /* This register resides in DP back end block;
124 * transmitter is used for the offset
125 */
126 REG_UPDATE_4(DP_DPHY_CNTL,
127 DPHY_ATEST_SEL_LANE0, disable,
128 DPHY_ATEST_SEL_LANE1, disable,
129 DPHY_ATEST_SEL_LANE2, disable,
130 DPHY_ATEST_SEL_LANE3, disable);
131}
132
133static void disable_prbs_mode(
134 struct dcn10_link_encoder *enc10)
135{
136 REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0);
137}
138
139static void program_pattern_symbols(
140 struct dcn10_link_encoder *enc10,
141 uint16_t pattern_symbols[8])
142{
143 /* This register resides in DP back end block;
144 * transmitter is used for the offset
145 */
146 REG_SET_3(DP_DPHY_SYM0, 0,
147 DPHY_SYM1, pattern_symbols[0],
148 DPHY_SYM2, pattern_symbols[1],
149 DPHY_SYM3, pattern_symbols[2]);
150
151 /* This register resides in DP back end block;
152 * transmitter is used for the offset
153 */
154 REG_SET_3(DP_DPHY_SYM1, 0,
155 DPHY_SYM4, pattern_symbols[3],
156 DPHY_SYM5, pattern_symbols[4],
157 DPHY_SYM6, pattern_symbols[5]);
158
159 /* This register resides in DP back end block;
160 * transmitter is used for the offset
161 */
162 REG_SET_2(DP_DPHY_SYM2, 0,
163 DPHY_SYM7, pattern_symbols[6],
164 DPHY_SYM8, pattern_symbols[7]);
165}
166
167static void set_dp_phy_pattern_d102(
168 struct dcn10_link_encoder *enc10)
169{
170 /* Disable PHY Bypass mode to setup the test pattern */
171 enable_phy_bypass_mode(enc10, false);
172
173 /* For 10-bit PRBS or debug symbols
174 * please use the following sequence:
175 *
176 * Enable debug symbols on the lanes
177 */
178 disable_prbs_symbols(enc10, true);
179
180 /* Disable PRBS mode */
181 disable_prbs_mode(enc10);
182
183 /* Program debug symbols to be output */
184 {
185 uint16_t pattern_symbols[8] = {
186 0x2AA, 0x2AA, 0x2AA, 0x2AA,
187 0x2AA, 0x2AA, 0x2AA, 0x2AA
188 };
189
190 program_pattern_symbols(enc10, pattern_symbols);
191 }
192
193 /* Enable phy bypass mode to enable the test pattern */
194
195 enable_phy_bypass_mode(enc10, true);
196}
197
198static void set_link_training_complete(
199 struct dcn10_link_encoder *enc10,
200 bool complete)
201{
202 /* This register resides in DP back end block;
203 * transmitter is used for the offset
204 */
205 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete);
206
207}
208
209void dcn10_link_encoder_set_dp_phy_pattern_training_pattern(
210 struct link_encoder *enc,
211 uint32_t index)
212{
213 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
214 /* Write Training Pattern */
215
216 REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index);
217
218 /* Set HW Register Training Complete to false */
219
220 set_link_training_complete(enc10, false);
221
222 /* Disable PHY Bypass mode to output Training Pattern */
223
224 enable_phy_bypass_mode(enc10, false);
225
226 /* Disable PRBS mode */
227 disable_prbs_mode(enc10);
228}
229
230static void setup_panel_mode(
231 struct dcn10_link_encoder *enc10,
232 enum dp_panel_mode panel_mode)
233{
234 uint32_t value;
235
236 ASSERT(REG(DP_DPHY_INTERNAL_CTRL));
237 value = REG_READ(DP_DPHY_INTERNAL_CTRL);
238
239 switch (panel_mode) {
240 case DP_PANEL_MODE_EDP:
241 value = 0x1;
242 break;
243 case DP_PANEL_MODE_SPECIAL:
244 value = 0x11;
245 break;
246 default:
247 value = 0x0;
248 break;
249 }
250
251 REG_WRITE(DP_DPHY_INTERNAL_CTRL, value);
252}
253
254static void set_dp_phy_pattern_symbol_error(
255 struct dcn10_link_encoder *enc10)
256{
257 /* Disable PHY Bypass mode to setup the test pattern */
258 enable_phy_bypass_mode(enc10, false);
259
260 /* program correct panel mode*/
261 setup_panel_mode(enc10, DP_PANEL_MODE_DEFAULT);
262
263 /* A PRBS23 pattern is used for most DP electrical measurements. */
264
265 /* Enable PRBS symbols on the lanes */
266 disable_prbs_symbols(enc10, false);
267
268 /* For PRBS23 Set bit DPHY_PRBS_SEL=1 and Set bit DPHY_PRBS_EN=1 */
269 REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
270 DPHY_PRBS_SEL, 1,
271 DPHY_PRBS_EN, 1);
272
273 /* Enable phy bypass mode to enable the test pattern */
274 enable_phy_bypass_mode(enc10, true);
275}
276
277static void set_dp_phy_pattern_prbs7(
278 struct dcn10_link_encoder *enc10)
279{
280 /* Disable PHY Bypass mode to setup the test pattern */
281 enable_phy_bypass_mode(enc10, false);
282
283 /* A PRBS7 pattern is used for most DP electrical measurements. */
284
285 /* Enable PRBS symbols on the lanes */
286 disable_prbs_symbols(enc10, false);
287
288 /* For PRBS7 Set bit DPHY_PRBS_SEL=0 and Set bit DPHY_PRBS_EN=1 */
289 REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
290 DPHY_PRBS_SEL, 0,
291 DPHY_PRBS_EN, 1);
292
293 /* Enable phy bypass mode to enable the test pattern */
294 enable_phy_bypass_mode(enc10, true);
295}
296
297static void set_dp_phy_pattern_80bit_custom(
298 struct dcn10_link_encoder *enc10,
299 const uint8_t *pattern)
300{
301 /* Disable PHY Bypass mode to setup the test pattern */
302 enable_phy_bypass_mode(enc10, false);
303
304 /* Enable debug symbols on the lanes */
305
306 disable_prbs_symbols(enc10, true);
307
308 /* Enable PHY bypass mode to enable the test pattern */
309 /* TODO is it really needed ? */
310
311 enable_phy_bypass_mode(enc10, true);
312
313 /* Program 80 bit custom pattern */
314 {
315 uint16_t pattern_symbols[8];
316
317 pattern_symbols[0] =
318 ((pattern[1] & 0x03) << 8) | pattern[0];
319 pattern_symbols[1] =
320 ((pattern[2] & 0x0f) << 6) | ((pattern[1] >> 2) & 0x3f);
321 pattern_symbols[2] =
322 ((pattern[3] & 0x3f) << 4) | ((pattern[2] >> 4) & 0x0f);
323 pattern_symbols[3] =
324 (pattern[4] << 2) | ((pattern[3] >> 6) & 0x03);
325 pattern_symbols[4] =
326 ((pattern[6] & 0x03) << 8) | pattern[5];
327 pattern_symbols[5] =
328 ((pattern[7] & 0x0f) << 6) | ((pattern[6] >> 2) & 0x3f);
329 pattern_symbols[6] =
330 ((pattern[8] & 0x3f) << 4) | ((pattern[7] >> 4) & 0x0f);
331 pattern_symbols[7] =
332 (pattern[9] << 2) | ((pattern[8] >> 6) & 0x03);
333
334 program_pattern_symbols(enc10, pattern_symbols);
335 }
336
337 /* Enable phy bypass mode to enable the test pattern */
338
339 enable_phy_bypass_mode(enc10, true);
340}
341
342static void set_dp_phy_pattern_hbr2_compliance_cp2520_2(
343 struct dcn10_link_encoder *enc10,
344 unsigned int cp2520_pattern)
345{
346
347 /* previously there is a register DP_HBR2_EYE_PATTERN
348 * that is enabled to get the pattern.
349 * But it does not work with the latest spec change,
350 * so we are programming the following registers manually.
351 *
352 * The following settings have been confirmed
353 * by Nick Chorney and Sandra Liu
354 */
355
356 /* Disable PHY Bypass mode to setup the test pattern */
357
358 enable_phy_bypass_mode(enc10, false);
359
360 /* Setup DIG encoder in DP SST mode */
361 enc10->base.funcs->setup(&enc10->base, SIGNAL_TYPE_DISPLAY_PORT);
362
363 /* ensure normal panel mode. */
364 setup_panel_mode(enc10, DP_PANEL_MODE_DEFAULT);
365
366 /* no vbid after BS (SR)
367 * DP_LINK_FRAMING_CNTL changed history Sandra Liu
368 * 11000260 / 11000104 / 110000FC
369 */
370 REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
371 DP_IDLE_BS_INTERVAL, 0xFC,
372 DP_VBID_DISABLE, 1,
373 DP_VID_ENHANCED_FRAME_MODE, 1);
374
375 /* swap every BS with SR */
376 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0);
377
378 /* select cp2520 patterns */
379 if (REG(DP_DPHY_HBR2_PATTERN_CONTROL))
380 REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL,
381 DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern);
382 else
383 /* pre-DCE11 can only generate CP2520 pattern 2 */
384 ASSERT(cp2520_pattern == 2);
385
386 /* set link training complete */
387 set_link_training_complete(enc10, true);
388
389 /* disable video stream */
390 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
391
392 /* Disable PHY Bypass mode to setup the test pattern */
393 enable_phy_bypass_mode(enc10, false);
394}
395
396static void set_dp_phy_pattern_passthrough_mode(
397 struct dcn10_link_encoder *enc10,
398 enum dp_panel_mode panel_mode)
399{
400 /* program correct panel mode */
401 setup_panel_mode(enc10, panel_mode);
402
403 /* restore LINK_FRAMING_CNTL and DPHY_SCRAMBLER_BS_COUNT
404 * in case we were doing HBR2 compliance pattern before
405 */
406 REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
407 DP_IDLE_BS_INTERVAL, 0x2000,
408 DP_VBID_DISABLE, 0,
409 DP_VID_ENHANCED_FRAME_MODE, 1);
410
411 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF);
412
413 /* set link training complete */
414 set_link_training_complete(enc10, true);
415
416 /* Disable PHY Bypass mode to setup the test pattern */
417 enable_phy_bypass_mode(enc10, false);
418
419 /* Disable PRBS mode */
420 disable_prbs_mode(enc10);
421}
422
423/* return value is bit-vector */
424static uint8_t get_frontend_source(
425 enum engine_id engine)
426{
427 switch (engine) {
428 case ENGINE_ID_DIGA:
429 return DCN10_DIG_FE_SOURCE_SELECT_DIGA;
430 case ENGINE_ID_DIGB:
431 return DCN10_DIG_FE_SOURCE_SELECT_DIGB;
432 case ENGINE_ID_DIGC:
433 return DCN10_DIG_FE_SOURCE_SELECT_DIGC;
434 case ENGINE_ID_DIGD:
435 return DCN10_DIG_FE_SOURCE_SELECT_DIGD;
436 case ENGINE_ID_DIGE:
437 return DCN10_DIG_FE_SOURCE_SELECT_DIGE;
438 case ENGINE_ID_DIGF:
439 return DCN10_DIG_FE_SOURCE_SELECT_DIGF;
440 case ENGINE_ID_DIGG:
441 return DCN10_DIG_FE_SOURCE_SELECT_DIGG;
442 default:
443 ASSERT_CRITICAL(false);
444 return DCN10_DIG_FE_SOURCE_SELECT_INVALID;
445 }
446}
447
448static void configure_encoder(
449 struct dcn10_link_encoder *enc10,
450 const struct dc_link_settings *link_settings)
451{
452 /* set number of lanes */
453
454 REG_SET(DP_CONFIG, 0,
455 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE);
456
457 /* setup scrambler */
458 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1);
459}
460
461void dcn10_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
462 bool exit_link_training_required)
463{
464 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
465
466 if (exit_link_training_required)
467 REG_UPDATE(DP_DPHY_FAST_TRAINING,
468 DPHY_RX_FAST_TRAINING_CAPABLE, 1);
469 else {
470 REG_UPDATE(DP_DPHY_FAST_TRAINING,
471 DPHY_RX_FAST_TRAINING_CAPABLE, 0);
472 /*In DCE 11, we are able to pre-program a Force SR register
473 * to be able to trigger SR symbol after 5 idle patterns
474 * transmitted. Upon PSR Exit, DMCU can trigger
475 * DPHY_LOAD_BS_COUNT_START = 1. Upon writing 1 to
476 * DPHY_LOAD_BS_COUNT_START and the internal counter
477 * reaches DPHY_LOAD_BS_COUNT, the next BS symbol will be
478 * replaced by SR symbol once.
479 */
480
481 REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5);
482 }
483}
484
485void dcn10_psr_program_secondary_packet(struct link_encoder *enc,
486 unsigned int sdp_transmit_line_num_deadline)
487{
488 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
489
490 REG_UPDATE_2(DP_SEC_CNTL1,
491 DP_SEC_GSP0_LINE_NUM, sdp_transmit_line_num_deadline,
492 DP_SEC_GSP0_PRIORITY, 1);
493}
494
495bool dcn10_is_dig_enabled(struct link_encoder *enc)
496{
497 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
498 uint32_t value;
499
500 REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value);
501 return value;
502}
503
504static void link_encoder_disable(struct dcn10_link_encoder *enc10)
505{
506 /* reset training pattern */
507 REG_SET(DP_DPHY_TRAINING_PATTERN_SEL, 0,
508 DPHY_TRAINING_PATTERN_SEL, 0);
509
510 /* reset training complete */
511 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0);
512
513 /* reset panel mode */
514 setup_panel_mode(enc10, DP_PANEL_MODE_DEFAULT);
515}
516
517static void hpd_initialize(
518 struct dcn10_link_encoder *enc10)
519{
520 /* Associate HPD with DIG_BE */
521 enum hpd_source_id hpd_source = enc10->base.hpd_source;
522
523 REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source);
524}
525
526bool dcn10_link_encoder_validate_dvi_output(
527 const struct dcn10_link_encoder *enc10,
528 enum signal_type connector_signal,
529 enum signal_type signal,
530 const struct dc_crtc_timing *crtc_timing)
531{
532 uint32_t max_pixel_clock = TMDS_MAX_PIXEL_CLOCK;
533
534 if (signal == SIGNAL_TYPE_DVI_DUAL_LINK)
535 max_pixel_clock *= 2;
536
537 /* This handles the case of HDMI downgrade to DVI we don't want to
538 * we don't want to cap the pixel clock if the DDI is not DVI.
539 */
540 if (connector_signal != SIGNAL_TYPE_DVI_DUAL_LINK &&
541 connector_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
542 max_pixel_clock = enc10->base.features.max_hdmi_pixel_clock;
543
544 /* DVI only support RGB pixel encoding */
545 if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB)
546 return false;
547
548 /*connect DVI via adpater's HDMI connector*/
549 if ((connector_signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
550 connector_signal == SIGNAL_TYPE_HDMI_TYPE_A) &&
551 signal != SIGNAL_TYPE_HDMI_TYPE_A &&
552 crtc_timing->pix_clk_khz > TMDS_MAX_PIXEL_CLOCK)
553 return false;
554 if (crtc_timing->pix_clk_khz < TMDS_MIN_PIXEL_CLOCK)
555 return false;
556
557 if (crtc_timing->pix_clk_khz > max_pixel_clock)
558 return false;
559
560 /* DVI supports 6/8bpp single-link and 10/16bpp dual-link */
561 switch (crtc_timing->display_color_depth) {
562 case COLOR_DEPTH_666:
563 case COLOR_DEPTH_888:
564 break;
565 case COLOR_DEPTH_101010:
566 case COLOR_DEPTH_161616:
567 if (signal != SIGNAL_TYPE_DVI_DUAL_LINK)
568 return false;
569 break;
570 default:
571 return false;
572 }
573
574 return true;
575}
576
577static bool dcn10_link_encoder_validate_hdmi_output(
578 const struct dcn10_link_encoder *enc10,
579 const struct dc_crtc_timing *crtc_timing,
580 int adjusted_pix_clk_khz)
581{
582 enum dc_color_depth max_deep_color =
583 enc10->base.features.max_hdmi_deep_color;
584
585 if (max_deep_color < crtc_timing->display_color_depth)
586 return false;
587
588 if (crtc_timing->display_color_depth < COLOR_DEPTH_888)
589 return false;
590 if (adjusted_pix_clk_khz < TMDS_MIN_PIXEL_CLOCK)
591 return false;
592
593 if ((adjusted_pix_clk_khz == 0) ||
594 (adjusted_pix_clk_khz > enc10->base.features.max_hdmi_pixel_clock))
595 return false;
596
597 /* DCE11 HW does not support 420 */
598 if (!enc10->base.features.ycbcr420_supported &&
599 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
600 return false;
601
602 if (!enc10->base.features.flags.bits.HDMI_6GB_EN &&
603 adjusted_pix_clk_khz >= 300000)
604 return false;
605 return true;
606}
607
608bool dcn10_link_encoder_validate_dp_output(
609 const struct dcn10_link_encoder *enc10,
610 const struct dc_crtc_timing *crtc_timing)
611{
612 /* default RGB only */
613 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
614 return true;
615
616 if (enc10->base.features.flags.bits.IS_YCBCR_CAPABLE)
617 return true;
618
619 /* for DCE 8.x or later DP Y-only feature,
620 * we need ASIC cap + FeatureSupportDPYonly, not support 666
621 */
622 if (crtc_timing->flags.Y_ONLY &&
623 enc10->base.features.flags.bits.IS_YCBCR_CAPABLE &&
624 crtc_timing->display_color_depth != COLOR_DEPTH_666)
625 return true;
626
627 return false;
628}
629
630void dcn10_link_encoder_construct(
631 struct dcn10_link_encoder *enc10,
632 const struct encoder_init_data *init_data,
633 const struct encoder_feature_support *enc_features,
634 const struct dcn10_link_enc_registers *link_regs,
635 const struct dcn10_link_enc_aux_registers *aux_regs,
636 const struct dcn10_link_enc_hpd_registers *hpd_regs,
637 const struct dcn10_link_enc_shift *link_shift,
638 const struct dcn10_link_enc_mask *link_mask)
639{
640 struct bp_encoder_cap_info bp_cap_info = {0};
641 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
642 enum bp_result result = BP_RESULT_OK;
643
644 enc10->base.funcs = &dcn10_lnk_enc_funcs;
645 enc10->base.ctx = init_data->ctx;
646 enc10->base.id = init_data->encoder;
647
648 enc10->base.hpd_source = init_data->hpd_source;
649 enc10->base.connector = init_data->connector;
650
651 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
652
653 enc10->base.features = *enc_features;
654
655 enc10->base.transmitter = init_data->transmitter;
656
657 /* set the flag to indicate whether driver poll the I2C data pin
658 * while doing the DP sink detect
659 */
660
661/* if (dal_adapter_service_is_feature_supported(as,
662 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
663 enc10->base.features.flags.bits.
664 DP_SINK_DETECT_POLL_DATA_PIN = true;*/
665
666 enc10->base.output_signals =
667 SIGNAL_TYPE_DVI_SINGLE_LINK |
668 SIGNAL_TYPE_DVI_DUAL_LINK |
669 SIGNAL_TYPE_LVDS |
670 SIGNAL_TYPE_DISPLAY_PORT |
671 SIGNAL_TYPE_DISPLAY_PORT_MST |
672 SIGNAL_TYPE_EDP |
673 SIGNAL_TYPE_HDMI_TYPE_A;
674
675 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
676 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
677 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
678 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
679 * Prefer DIG assignment is decided by board design.
680 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
681 * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
682 * By this, adding DIGG should not hurt DCE 8.0.
683 * This will let DCE 8.1 share DCE 8.0 as much as possible
684 */
685
686 enc10->link_regs = link_regs;
687 enc10->aux_regs = aux_regs;
688 enc10->hpd_regs = hpd_regs;
689 enc10->link_shift = link_shift;
690 enc10->link_mask = link_mask;
691
692 switch (enc10->base.transmitter) {
693 case TRANSMITTER_UNIPHY_A:
694 enc10->base.preferred_engine = ENGINE_ID_DIGA;
695 break;
696 case TRANSMITTER_UNIPHY_B:
697 enc10->base.preferred_engine = ENGINE_ID_DIGB;
698 break;
699 case TRANSMITTER_UNIPHY_C:
700 enc10->base.preferred_engine = ENGINE_ID_DIGC;
701 break;
702 case TRANSMITTER_UNIPHY_D:
703 enc10->base.preferred_engine = ENGINE_ID_DIGD;
704 break;
705 case TRANSMITTER_UNIPHY_E:
706 enc10->base.preferred_engine = ENGINE_ID_DIGE;
707 break;
708 case TRANSMITTER_UNIPHY_F:
709 enc10->base.preferred_engine = ENGINE_ID_DIGF;
710 break;
711 case TRANSMITTER_UNIPHY_G:
712 enc10->base.preferred_engine = ENGINE_ID_DIGG;
713 break;
714 default:
715 ASSERT_CRITICAL(false);
716 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
717 }
718
719 /* default to one to mirror Windows behavior */
720 enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
721
722 result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
723 enc10->base.id, &bp_cap_info);
724
725 /* Override features with DCE-specific values */
726 if (result == BP_RESULT_OK) {
727 enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
728 bp_cap_info.DP_HBR2_EN;
729 enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
730 bp_cap_info.DP_HBR3_EN;
731 enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
732 } else {
733 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
734 __func__,
735 result);
736 }
737}
738
739bool dcn10_link_encoder_validate_output_with_stream(
740 struct link_encoder *enc,
741 const struct dc_stream_state *stream)
742{
743 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
744 bool is_valid;
745
746 switch (stream->signal) {
747 case SIGNAL_TYPE_DVI_SINGLE_LINK:
748 case SIGNAL_TYPE_DVI_DUAL_LINK:
749 is_valid = dcn10_link_encoder_validate_dvi_output(
750 enc10,
751 stream->sink->link->connector_signal,
752 stream->signal,
753 &stream->timing);
754 break;
755 case SIGNAL_TYPE_HDMI_TYPE_A:
756 is_valid = dcn10_link_encoder_validate_hdmi_output(
757 enc10,
758 &stream->timing,
759 stream->phy_pix_clk);
760 break;
761 case SIGNAL_TYPE_DISPLAY_PORT:
762 case SIGNAL_TYPE_DISPLAY_PORT_MST:
763 is_valid = dcn10_link_encoder_validate_dp_output(
764 enc10, &stream->timing);
765 break;
766 case SIGNAL_TYPE_EDP:
767 is_valid = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ? true : false;
768 break;
769 case SIGNAL_TYPE_VIRTUAL:
770 is_valid = true;
771 break;
772 default:
773 is_valid = false;
774 break;
775 }
776
777 return is_valid;
778}
779
780void dcn10_link_encoder_hw_init(
781 struct link_encoder *enc)
782{
783 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
784 struct bp_transmitter_control cntl = { 0 };
785 enum bp_result result;
786
787 cntl.action = TRANSMITTER_CONTROL_INIT;
788 cntl.engine_id = ENGINE_ID_UNKNOWN;
789 cntl.transmitter = enc10->base.transmitter;
790 cntl.connector_obj_id = enc10->base.connector;
791 cntl.lanes_number = LANE_COUNT_FOUR;
792 cntl.coherent = false;
793 cntl.hpd_sel = enc10->base.hpd_source;
794
795 if (enc10->base.connector.id == CONNECTOR_ID_EDP)
796 cntl.signal = SIGNAL_TYPE_EDP;
797
798 result = link_transmitter_control(enc10, &cntl);
799
800 if (result != BP_RESULT_OK) {
801 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
802 __func__);
803 BREAK_TO_DEBUGGER();
804 return;
805 }
806
807 if (enc10->base.connector.id == CONNECTOR_ID_LVDS) {
808 cntl.action = TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS;
809
810 result = link_transmitter_control(enc10, &cntl);
811
812 ASSERT(result == BP_RESULT_OK);
813
814 }
815 aux_initialize(enc10);
816
817 /* reinitialize HPD.
818 * hpd_initialize() will pass DIG_FE id to HW context.
819 * All other routine within HW context will use fe_engine_offset
820 * as DIG_FE id even caller pass DIG_FE id.
821 * So this routine must be called first.
822 */
823 hpd_initialize(enc10);
824}
825
826void dcn10_link_encoder_destroy(struct link_encoder **enc)
827{
828 kfree(TO_DCN10_LINK_ENC(*enc));
829 *enc = NULL;
830}
831
832void dcn10_link_encoder_setup(
833 struct link_encoder *enc,
834 enum signal_type signal)
835{
836 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
837
838 switch (signal) {
839 case SIGNAL_TYPE_EDP:
840 case SIGNAL_TYPE_DISPLAY_PORT:
841 /* DP SST */
842 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0);
843 break;
844 case SIGNAL_TYPE_LVDS:
845 /* LVDS */
846 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1);
847 break;
848 case SIGNAL_TYPE_DVI_SINGLE_LINK:
849 case SIGNAL_TYPE_DVI_DUAL_LINK:
850 /* TMDS-DVI */
851 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2);
852 break;
853 case SIGNAL_TYPE_HDMI_TYPE_A:
854 /* TMDS-HDMI */
855 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3);
856 break;
857 case SIGNAL_TYPE_DISPLAY_PORT_MST:
858 /* DP MST */
859 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5);
860 break;
861 default:
862 ASSERT_CRITICAL(false);
863 /* invalid mode ! */
864 break;
865 }
866
867}
868
869/* TODO: still need depth or just pass in adjusted pixel clock? */
870void dcn10_link_encoder_enable_tmds_output(
871 struct link_encoder *enc,
872 enum clock_source_id clock_source,
873 enum dc_color_depth color_depth,
874 enum signal_type signal,
875 uint32_t pixel_clock)
876{
877 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
878 struct bp_transmitter_control cntl = { 0 };
879 enum bp_result result;
880
881 /* Enable the PHY */
882
883 cntl.action = TRANSMITTER_CONTROL_ENABLE;
884 cntl.engine_id = enc->preferred_engine;
885 cntl.transmitter = enc10->base.transmitter;
886 cntl.pll_id = clock_source;
887 cntl.signal = signal;
888 if (cntl.signal == SIGNAL_TYPE_DVI_DUAL_LINK)
889 cntl.lanes_number = 8;
890 else
891 cntl.lanes_number = 4;
892
893 cntl.hpd_sel = enc10->base.hpd_source;
894
895 cntl.pixel_clock = pixel_clock;
896 cntl.color_depth = color_depth;
897
898 result = link_transmitter_control(enc10, &cntl);
899
900 if (result != BP_RESULT_OK) {
901 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
902 __func__);
903 BREAK_TO_DEBUGGER();
904 }
905}
906
907/* enables DP PHY output */
908void dcn10_link_encoder_enable_dp_output(
909 struct link_encoder *enc,
910 const struct dc_link_settings *link_settings,
911 enum clock_source_id clock_source)
912{
913 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
914 struct bp_transmitter_control cntl = { 0 };
915 enum bp_result result;
916
917 /* Enable the PHY */
918
919 /* number_of_lanes is used for pixel clock adjust,
920 * but it's not passed to asic_control.
921 * We need to set number of lanes manually.
922 */
923 configure_encoder(enc10, link_settings);
924
925 cntl.action = TRANSMITTER_CONTROL_ENABLE;
926 cntl.engine_id = enc->preferred_engine;
927 cntl.transmitter = enc10->base.transmitter;
928 cntl.pll_id = clock_source;
929 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT;
930 cntl.lanes_number = link_settings->lane_count;
931 cntl.hpd_sel = enc10->base.hpd_source;
932 cntl.pixel_clock = link_settings->link_rate
933 * LINK_RATE_REF_FREQ_IN_KHZ;
934 /* TODO: check if undefined works */
935 cntl.color_depth = COLOR_DEPTH_UNDEFINED;
936
937 result = link_transmitter_control(enc10, &cntl);
938
939 if (result != BP_RESULT_OK) {
940 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
941 __func__);
942 BREAK_TO_DEBUGGER();
943 }
944}
945
946/* enables DP PHY output in MST mode */
947void dcn10_link_encoder_enable_dp_mst_output(
948 struct link_encoder *enc,
949 const struct dc_link_settings *link_settings,
950 enum clock_source_id clock_source)
951{
952 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
953 struct bp_transmitter_control cntl = { 0 };
954 enum bp_result result;
955
956 /* Enable the PHY */
957
958 /* number_of_lanes is used for pixel clock adjust,
959 * but it's not passed to asic_control.
960 * We need to set number of lanes manually.
961 */
962 configure_encoder(enc10, link_settings);
963
964 cntl.action = TRANSMITTER_CONTROL_ENABLE;
965 cntl.engine_id = ENGINE_ID_UNKNOWN;
966 cntl.transmitter = enc10->base.transmitter;
967 cntl.pll_id = clock_source;
968 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
969 cntl.lanes_number = link_settings->lane_count;
970 cntl.hpd_sel = enc10->base.hpd_source;
971 cntl.pixel_clock = link_settings->link_rate
972 * LINK_RATE_REF_FREQ_IN_KHZ;
973 /* TODO: check if undefined works */
974 cntl.color_depth = COLOR_DEPTH_UNDEFINED;
975
976 result = link_transmitter_control(enc10, &cntl);
977
978 if (result != BP_RESULT_OK) {
979 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
980 __func__);
981 BREAK_TO_DEBUGGER();
982 }
983}
984/*
985 * @brief
986 * Disable transmitter and its encoder
987 */
988void dcn10_link_encoder_disable_output(
989 struct link_encoder *enc,
990 enum signal_type signal)
991{
992 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
993 struct bp_transmitter_control cntl = { 0 };
994 enum bp_result result;
995
996 if (!dcn10_is_dig_enabled(enc)) {
997 /* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */
998 return;
999 }
1000 /* Power-down RX and disable GPU PHY should be paired.
1001 * Disabling PHY without powering down RX may cause
1002 * symbol lock loss, on which we will get DP Sink interrupt.
1003 */
1004
1005 /* There is a case for the DP active dongles
1006 * where we want to disable the PHY but keep RX powered,
1007 * for those we need to ignore DP Sink interrupt
1008 * by checking lane count that has been set
1009 * on the last do_enable_output().
1010 */
1011
1012 /* disable transmitter */
1013 cntl.action = TRANSMITTER_CONTROL_DISABLE;
1014 cntl.transmitter = enc10->base.transmitter;
1015 cntl.hpd_sel = enc10->base.hpd_source;
1016 cntl.signal = signal;
1017 cntl.connector_obj_id = enc10->base.connector;
1018
1019 result = link_transmitter_control(enc10, &cntl);
1020
1021 if (result != BP_RESULT_OK) {
1022 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1023 __func__);
1024 BREAK_TO_DEBUGGER();
1025 return;
1026 }
1027
1028 /* disable encoder */
1029 if (dc_is_dp_signal(signal))
1030 link_encoder_disable(enc10);
1031}
1032
1033void dcn10_link_encoder_dp_set_lane_settings(
1034 struct link_encoder *enc,
1035 const struct link_training_settings *link_settings)
1036{
1037 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1038 union dpcd_training_lane_set training_lane_set = { { 0 } };
1039 int32_t lane = 0;
1040 struct bp_transmitter_control cntl = { 0 };
1041
1042 if (!link_settings) {
1043 BREAK_TO_DEBUGGER();
1044 return;
1045 }
1046
1047 cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS;
1048 cntl.transmitter = enc10->base.transmitter;
1049 cntl.connector_obj_id = enc10->base.connector;
1050 cntl.lanes_number = link_settings->link_settings.lane_count;
1051 cntl.hpd_sel = enc10->base.hpd_source;
1052 cntl.pixel_clock = link_settings->link_settings.link_rate *
1053 LINK_RATE_REF_FREQ_IN_KHZ;
1054
1055 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) {
1056 /* translate lane settings */
1057
1058 training_lane_set.bits.VOLTAGE_SWING_SET =
1059 link_settings->lane_settings[lane].VOLTAGE_SWING;
1060 training_lane_set.bits.PRE_EMPHASIS_SET =
1061 link_settings->lane_settings[lane].PRE_EMPHASIS;
1062
1063 /* post cursor 2 setting only applies to HBR2 link rate */
1064 if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) {
1065 /* this is passed to VBIOS
1066 * to program post cursor 2 level
1067 */
1068 training_lane_set.bits.POST_CURSOR2_SET =
1069 link_settings->lane_settings[lane].POST_CURSOR2;
1070 }
1071
1072 cntl.lane_select = lane;
1073 cntl.lane_settings = training_lane_set.raw;
1074
1075 /* call VBIOS table to set voltage swing and pre-emphasis */
1076 link_transmitter_control(enc10, &cntl);
1077 }
1078}
1079
1080/* set DP PHY test and training patterns */
1081void dcn10_link_encoder_dp_set_phy_pattern(
1082 struct link_encoder *enc,
1083 const struct encoder_set_dp_phy_pattern_param *param)
1084{
1085 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1086
1087 switch (param->dp_phy_pattern) {
1088 case DP_TEST_PATTERN_TRAINING_PATTERN1:
1089 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 0);
1090 break;
1091 case DP_TEST_PATTERN_TRAINING_PATTERN2:
1092 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 1);
1093 break;
1094 case DP_TEST_PATTERN_TRAINING_PATTERN3:
1095 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 2);
1096 break;
1097 case DP_TEST_PATTERN_TRAINING_PATTERN4:
1098 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 3);
1099 break;
1100 case DP_TEST_PATTERN_D102:
1101 set_dp_phy_pattern_d102(enc10);
1102 break;
1103 case DP_TEST_PATTERN_SYMBOL_ERROR:
1104 set_dp_phy_pattern_symbol_error(enc10);
1105 break;
1106 case DP_TEST_PATTERN_PRBS7:
1107 set_dp_phy_pattern_prbs7(enc10);
1108 break;
1109 case DP_TEST_PATTERN_80BIT_CUSTOM:
1110 set_dp_phy_pattern_80bit_custom(
1111 enc10, param->custom_pattern);
1112 break;
1113 case DP_TEST_PATTERN_CP2520_1:
1114 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, 1);
1115 break;
1116 case DP_TEST_PATTERN_CP2520_2:
1117 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, 2);
1118 break;
1119 case DP_TEST_PATTERN_CP2520_3:
1120 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, 3);
1121 break;
1122 case DP_TEST_PATTERN_VIDEO_MODE: {
1123 set_dp_phy_pattern_passthrough_mode(
1124 enc10, param->dp_panel_mode);
1125 break;
1126 }
1127
1128 default:
1129 /* invalid phy pattern */
1130 ASSERT_CRITICAL(false);
1131 break;
1132 }
1133}
1134
1135static void fill_stream_allocation_row_info(
1136 const struct link_mst_stream_allocation *stream_allocation,
1137 uint32_t *src,
1138 uint32_t *slots)
1139{
1140 const struct stream_encoder *stream_enc = stream_allocation->stream_enc;
1141
1142 if (stream_enc) {
1143 *src = stream_enc->id;
1144 *slots = stream_allocation->slot_count;
1145 } else {
1146 *src = 0;
1147 *slots = 0;
1148 }
1149}
1150
1151/* programs DP MST VC payload allocation */
1152void dcn10_link_encoder_update_mst_stream_allocation_table(
1153 struct link_encoder *enc,
1154 const struct link_mst_stream_allocation_table *table)
1155{
1156 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1157 uint32_t value0 = 0;
1158 uint32_t value1 = 0;
1159 uint32_t value2 = 0;
1160 uint32_t slots = 0;
1161 uint32_t src = 0;
1162 uint32_t retries = 0;
1163
1164 /* For CZ, there are only 3 pipes. So Virtual channel is up 3.*/
1165
1166 /* --- Set MSE Stream Attribute -
1167 * Setup VC Payload Table on Tx Side,
1168 * Issue allocation change trigger
1169 * to commit payload on both tx and rx side
1170 */
1171
1172 /* we should clean-up table each time */
1173
1174 if (table->stream_count >= 1) {
1175 fill_stream_allocation_row_info(
1176 &table->stream_allocations[0],
1177 &src,
1178 &slots);
1179 } else {
1180 src = 0;
1181 slots = 0;
1182 }
1183
1184 REG_UPDATE_2(DP_MSE_SAT0,
1185 DP_MSE_SAT_SRC0, src,
1186 DP_MSE_SAT_SLOT_COUNT0, slots);
1187
1188 if (table->stream_count >= 2) {
1189 fill_stream_allocation_row_info(
1190 &table->stream_allocations[1],
1191 &src,
1192 &slots);
1193 } else {
1194 src = 0;
1195 slots = 0;
1196 }
1197
1198 REG_UPDATE_2(DP_MSE_SAT0,
1199 DP_MSE_SAT_SRC1, src,
1200 DP_MSE_SAT_SLOT_COUNT1, slots);
1201
1202 if (table->stream_count >= 3) {
1203 fill_stream_allocation_row_info(
1204 &table->stream_allocations[2],
1205 &src,
1206 &slots);
1207 } else {
1208 src = 0;
1209 slots = 0;
1210 }
1211
1212 REG_UPDATE_2(DP_MSE_SAT1,
1213 DP_MSE_SAT_SRC2, src,
1214 DP_MSE_SAT_SLOT_COUNT2, slots);
1215
1216 if (table->stream_count >= 4) {
1217 fill_stream_allocation_row_info(
1218 &table->stream_allocations[3],
1219 &src,
1220 &slots);
1221 } else {
1222 src = 0;
1223 slots = 0;
1224 }
1225
1226 REG_UPDATE_2(DP_MSE_SAT1,
1227 DP_MSE_SAT_SRC3, src,
1228 DP_MSE_SAT_SLOT_COUNT3, slots);
1229
1230 /* --- wait for transaction finish */
1231
1232 /* send allocation change trigger (ACT) ?
1233 * this step first sends the ACT,
1234 * then double buffers the SAT into the hardware
1235 * making the new allocation active on the DP MST mode link
1236 */
1237
1238 /* DP_MSE_SAT_UPDATE:
1239 * 0 - No Action
1240 * 1 - Update SAT with trigger
1241 * 2 - Update SAT without trigger
1242 */
1243 REG_UPDATE(DP_MSE_SAT_UPDATE,
1244 DP_MSE_SAT_UPDATE, 1);
1245
1246 /* wait for update to complete
1247 * (i.e. DP_MSE_SAT_UPDATE field is reset to 0)
1248 * then wait for the transmission
1249 * of at least 16 MTP headers on immediate local link.
1250 * i.e. DP_MSE_16_MTP_KEEPOUT field (read only) is reset to 0
1251 * a value of 1 indicates that DP MST mode
1252 * is in the 16 MTP keepout region after a VC has been added.
1253 * MST stream bandwidth (VC rate) can be configured
1254 * after this bit is cleared
1255 */
1256 do {
1257 udelay(10);
1258
1259 value0 = REG_READ(DP_MSE_SAT_UPDATE);
1260
1261 REG_GET(DP_MSE_SAT_UPDATE,
1262 DP_MSE_SAT_UPDATE, &value1);
1263
1264 REG_GET(DP_MSE_SAT_UPDATE,
1265 DP_MSE_16_MTP_KEEPOUT, &value2);
1266
1267 /* bit field DP_MSE_SAT_UPDATE is set to 1 already */
1268 if (!value1 && !value2)
1269 break;
1270 ++retries;
1271 } while (retries < DP_MST_UPDATE_MAX_RETRY);
1272}
1273
1274void dcn10_link_encoder_connect_dig_be_to_fe(
1275 struct link_encoder *enc,
1276 enum engine_id engine,
1277 bool connect)
1278{
1279 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1280 uint32_t field;
1281
1282 if (engine != ENGINE_ID_UNKNOWN) {
1283
1284 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field);
1285
1286 if (connect)
1287 field |= get_frontend_source(engine);
1288 else
1289 field &= ~get_frontend_source(engine);
1290
1291 REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field);
1292 }
1293}
1294
1295
1296#define HPD_REG(reg)\
1297 (enc10->hpd_regs->reg)
1298
1299#define HPD_REG_READ(reg_name) \
1300 dm_read_reg(CTX, HPD_REG(reg_name))
1301
1302#define HPD_REG_UPDATE_N(reg_name, n, ...) \
1303 generic_reg_update_ex(CTX, \
1304 HPD_REG(reg_name), \
1305 HPD_REG_READ(reg_name), \
1306 n, __VA_ARGS__)
1307
1308#define HPD_REG_UPDATE(reg_name, field, val) \
1309 HPD_REG_UPDATE_N(reg_name, 1, \
1310 FN(reg_name, field), val)
1311
1312void dcn10_link_encoder_enable_hpd(struct link_encoder *enc)
1313{
1314 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1315
1316 HPD_REG_UPDATE(DC_HPD_CONTROL,
1317 DC_HPD_EN, 1);
1318}
1319
1320void dcn10_link_encoder_disable_hpd(struct link_encoder *enc)
1321{
1322 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1323
1324 HPD_REG_UPDATE(DC_HPD_CONTROL,
1325 DC_HPD_EN, 0);
1326}
1327
1328
1329#define AUX_REG(reg)\
1330 (enc10->aux_regs->reg)
1331
1332#define AUX_REG_READ(reg_name) \
1333 dm_read_reg(CTX, AUX_REG(reg_name))
1334
1335#define AUX_REG_UPDATE_N(reg_name, n, ...) \
1336 generic_reg_update_ex(CTX, \
1337 AUX_REG(reg_name), \
1338 AUX_REG_READ(reg_name), \
1339 n, __VA_ARGS__)
1340
1341#define AUX_REG_UPDATE(reg_name, field, val) \
1342 AUX_REG_UPDATE_N(reg_name, 1, \
1343 FN(reg_name, field), val)
1344
1345#define AUX_REG_UPDATE_2(reg, f1, v1, f2, v2) \
1346 AUX_REG_UPDATE_N(reg, 2,\
1347 FN(reg, f1), v1,\
1348 FN(reg, f2), v2)
1349
1350static void aux_initialize(
1351 struct dcn10_link_encoder *enc10)
1352{
1353 enum hpd_source_id hpd_source = enc10->base.hpd_source;
1354
1355 AUX_REG_UPDATE_2(AUX_CONTROL,
1356 AUX_HPD_SEL, hpd_source,
1357 AUX_LS_READ_EN, 0);
1358
1359 /* 1/4 window (the maximum allowed) */
1360 AUX_REG_UPDATE(AUX_DPHY_RX_CONTROL0,
1361 AUX_RX_RECEIVE_WINDOW, 1);
1362}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
new file mode 100644
index 000000000000..2a97cdb2cfbb
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
@@ -0,0 +1,330 @@
1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DC_LINK_ENCODER__DCN10_H__
27#define __DC_LINK_ENCODER__DCN10_H__
28
29#include "link_encoder.h"
30
31#define TO_DCN10_LINK_ENC(link_encoder)\
32 container_of(link_encoder, struct dcn10_link_encoder, base)
33
34
35#define AUX_REG_LIST(id)\
36 SRI(AUX_CONTROL, DP_AUX, id), \
37 SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id)
38
39#define HPD_REG_LIST(id)\
40 SRI(DC_HPD_CONTROL, HPD, id)
41
42#define LE_DCN_COMMON_REG_LIST(id) \
43 SRI(DIG_BE_CNTL, DIG, id), \
44 SRI(DIG_BE_EN_CNTL, DIG, id), \
45 SRI(DP_CONFIG, DP, id), \
46 SRI(DP_DPHY_CNTL, DP, id), \
47 SRI(DP_DPHY_PRBS_CNTL, DP, id), \
48 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
49 SRI(DP_DPHY_SYM0, DP, id), \
50 SRI(DP_DPHY_SYM1, DP, id), \
51 SRI(DP_DPHY_SYM2, DP, id), \
52 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
53 SRI(DP_LINK_CNTL, DP, id), \
54 SRI(DP_LINK_FRAMING_CNTL, DP, id), \
55 SRI(DP_MSE_SAT0, DP, id), \
56 SRI(DP_MSE_SAT1, DP, id), \
57 SRI(DP_MSE_SAT2, DP, id), \
58 SRI(DP_MSE_SAT_UPDATE, DP, id), \
59 SRI(DP_SEC_CNTL, DP, id), \
60 SRI(DP_VID_STREAM_CNTL, DP, id), \
61 SRI(DP_DPHY_FAST_TRAINING, DP, id), \
62 SRI(DP_SEC_CNTL1, DP, id), \
63 SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
64 SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
65 SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)
66
67#define LE_DCN10_REG_LIST(id)\
68 LE_DCN_COMMON_REG_LIST(id)
69
70struct dcn10_link_enc_aux_registers {
71 uint32_t AUX_CONTROL;
72 uint32_t AUX_DPHY_RX_CONTROL0;
73};
74
75struct dcn10_link_enc_hpd_registers {
76 uint32_t DC_HPD_CONTROL;
77};
78
79struct dcn10_link_enc_registers {
80 uint32_t DIG_BE_CNTL;
81 uint32_t DIG_BE_EN_CNTL;
82 uint32_t DP_CONFIG;
83 uint32_t DP_DPHY_CNTL;
84 uint32_t DP_DPHY_INTERNAL_CTRL;
85 uint32_t DP_DPHY_PRBS_CNTL;
86 uint32_t DP_DPHY_SCRAM_CNTL;
87 uint32_t DP_DPHY_SYM0;
88 uint32_t DP_DPHY_SYM1;
89 uint32_t DP_DPHY_SYM2;
90 uint32_t DP_DPHY_TRAINING_PATTERN_SEL;
91 uint32_t DP_LINK_CNTL;
92 uint32_t DP_LINK_FRAMING_CNTL;
93 uint32_t DP_MSE_SAT0;
94 uint32_t DP_MSE_SAT1;
95 uint32_t DP_MSE_SAT2;
96 uint32_t DP_MSE_SAT_UPDATE;
97 uint32_t DP_SEC_CNTL;
98 uint32_t DP_VID_STREAM_CNTL;
99 uint32_t DP_DPHY_FAST_TRAINING;
100 uint32_t DP_DPHY_BS_SR_SWAP_CNTL;
101 uint32_t DP_DPHY_HBR2_PATTERN_CONTROL;
102 uint32_t DP_SEC_CNTL1;
103};
104
105#define LE_SF(reg_name, field_name, post_fix)\
106 .field_name = reg_name ## __ ## field_name ## post_fix
107
108#define LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh)\
109 LE_SF(DIG0_DIG_BE_EN_CNTL, DIG_ENABLE, mask_sh),\
110 LE_SF(DIG0_DIG_BE_CNTL, DIG_HPD_SELECT, mask_sh),\
111 LE_SF(DIG0_DIG_BE_CNTL, DIG_MODE, mask_sh),\
112 LE_SF(DIG0_DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, mask_sh),\
113 LE_SF(DP0_DP_DPHY_CNTL, DPHY_BYPASS, mask_sh),\
114 LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE0, mask_sh),\
115 LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE1, mask_sh),\
116 LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE2, mask_sh),\
117 LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE3, mask_sh),\
118 LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, mask_sh),\
119 LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_SEL, mask_sh),\
120 LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM1, mask_sh),\
121 LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM2, mask_sh),\
122 LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM3, mask_sh),\
123 LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM4, mask_sh),\
124 LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM5, mask_sh),\
125 LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM6, mask_sh),\
126 LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM7, mask_sh),\
127 LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM8, mask_sh),\
128 LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, mask_sh),\
129 LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, mask_sh),\
130 LE_SF(DP0_DP_DPHY_FAST_TRAINING, DPHY_RX_FAST_TRAINING_CAPABLE, mask_sh),\
131 LE_SF(DP0_DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, mask_sh),\
132 LE_SF(DP0_DP_DPHY_TRAINING_PATTERN_SEL, DPHY_TRAINING_PATTERN_SEL, mask_sh),\
133 LE_SF(DP0_DP_DPHY_HBR2_PATTERN_CONTROL, DP_DPHY_HBR2_PATTERN_CONTROL, mask_sh),\
134 LE_SF(DP0_DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, mask_sh),\
135 LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_IDLE_BS_INTERVAL, mask_sh),\
136 LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VBID_DISABLE, mask_sh),\
137 LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VID_ENHANCED_FRAME_MODE, mask_sh),\
138 LE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
139 LE_SF(DP0_DP_CONFIG, DP_UDI_LANES, mask_sh),\
140 LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_LINE_NUM, mask_sh),\
141 LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_PRIORITY, mask_sh),\
142 LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC0, mask_sh),\
143 LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC1, mask_sh),\
144 LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT0, mask_sh),\
145 LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT1, mask_sh),\
146 LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC2, mask_sh),\
147 LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC3, mask_sh),\
148 LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT2, mask_sh),\
149 LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT3, mask_sh),\
150 LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_SAT_UPDATE, mask_sh),\
151 LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_16_MTP_KEEPOUT, mask_sh),\
152 LE_SF(DP_AUX0_AUX_CONTROL, AUX_HPD_SEL, mask_sh),\
153 LE_SF(DP_AUX0_AUX_CONTROL, AUX_LS_READ_EN, mask_sh),\
154 LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW, mask_sh),\
155 LE_SF(HPD0_DC_HPD_CONTROL, DC_HPD_EN, mask_sh)
156
157#define DCN_LINK_ENCODER_REG_FIELD_LIST(type) \
158 type DIG_ENABLE;\
159 type DIG_HPD_SELECT;\
160 type DIG_MODE;\
161 type DIG_FE_SOURCE_SELECT;\
162 type DPHY_BYPASS;\
163 type DPHY_ATEST_SEL_LANE0;\
164 type DPHY_ATEST_SEL_LANE1;\
165 type DPHY_ATEST_SEL_LANE2;\
166 type DPHY_ATEST_SEL_LANE3;\
167 type DPHY_PRBS_EN;\
168 type DPHY_PRBS_SEL;\
169 type DPHY_SYM1;\
170 type DPHY_SYM2;\
171 type DPHY_SYM3;\
172 type DPHY_SYM4;\
173 type DPHY_SYM5;\
174 type DPHY_SYM6;\
175 type DPHY_SYM7;\
176 type DPHY_SYM8;\
177 type DPHY_SCRAMBLER_BS_COUNT;\
178 type DPHY_SCRAMBLER_ADVANCE;\
179 type DPHY_RX_FAST_TRAINING_CAPABLE;\
180 type DPHY_LOAD_BS_COUNT;\
181 type DPHY_TRAINING_PATTERN_SEL;\
182 type DP_DPHY_HBR2_PATTERN_CONTROL;\
183 type DP_LINK_TRAINING_COMPLETE;\
184 type DP_IDLE_BS_INTERVAL;\
185 type DP_VBID_DISABLE;\
186 type DP_VID_ENHANCED_FRAME_MODE;\
187 type DP_VID_STREAM_ENABLE;\
188 type DP_UDI_LANES;\
189 type DP_SEC_GSP0_LINE_NUM;\
190 type DP_SEC_GSP0_PRIORITY;\
191 type DP_MSE_SAT_SRC0;\
192 type DP_MSE_SAT_SRC1;\
193 type DP_MSE_SAT_SRC2;\
194 type DP_MSE_SAT_SRC3;\
195 type DP_MSE_SAT_SLOT_COUNT0;\
196 type DP_MSE_SAT_SLOT_COUNT1;\
197 type DP_MSE_SAT_SLOT_COUNT2;\
198 type DP_MSE_SAT_SLOT_COUNT3;\
199 type DP_MSE_SAT_UPDATE;\
200 type DP_MSE_16_MTP_KEEPOUT;\
201 type AUX_HPD_SEL;\
202 type AUX_LS_READ_EN;\
203 type AUX_RX_RECEIVE_WINDOW;\
204 type DC_HPD_EN
205
206struct dcn10_link_enc_shift {
207 DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
208};
209
210struct dcn10_link_enc_mask {
211 DCN_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
212};
213
214struct dcn10_link_encoder {
215 struct link_encoder base;
216 const struct dcn10_link_enc_registers *link_regs;
217 const struct dcn10_link_enc_aux_registers *aux_regs;
218 const struct dcn10_link_enc_hpd_registers *hpd_regs;
219 const struct dcn10_link_enc_shift *link_shift;
220 const struct dcn10_link_enc_mask *link_mask;
221};
222
223
224void dcn10_link_encoder_construct(
225 struct dcn10_link_encoder *enc10,
226 const struct encoder_init_data *init_data,
227 const struct encoder_feature_support *enc_features,
228 const struct dcn10_link_enc_registers *link_regs,
229 const struct dcn10_link_enc_aux_registers *aux_regs,
230 const struct dcn10_link_enc_hpd_registers *hpd_regs,
231 const struct dcn10_link_enc_shift *link_shift,
232 const struct dcn10_link_enc_mask *link_mask);
233
234bool dcn10_link_encoder_validate_dvi_output(
235 const struct dcn10_link_encoder *enc10,
236 enum signal_type connector_signal,
237 enum signal_type signal,
238 const struct dc_crtc_timing *crtc_timing);
239
240bool dcn10_link_encoder_validate_rgb_output(
241 const struct dcn10_link_encoder *enc10,
242 const struct dc_crtc_timing *crtc_timing);
243
244bool dcn10_link_encoder_validate_dp_output(
245 const struct dcn10_link_encoder *enc10,
246 const struct dc_crtc_timing *crtc_timing);
247
248bool dcn10_link_encoder_validate_wireless_output(
249 const struct dcn10_link_encoder *enc10,
250 const struct dc_crtc_timing *crtc_timing);
251
252bool dcn10_link_encoder_validate_output_with_stream(
253 struct link_encoder *enc,
254 const struct dc_stream_state *stream);
255
256/****************** HW programming ************************/
257
258/* initialize HW */ /* why do we initialze aux in here? */
259void dcn10_link_encoder_hw_init(struct link_encoder *enc);
260
261void dcn10_link_encoder_destroy(struct link_encoder **enc);
262
263/* program DIG_MODE in DIG_BE */
264/* TODO can this be combined with enable_output? */
265void dcn10_link_encoder_setup(
266 struct link_encoder *enc,
267 enum signal_type signal);
268
269/* enables TMDS PHY output */
270/* TODO: still need depth or just pass in adjusted pixel clock? */
271void dcn10_link_encoder_enable_tmds_output(
272 struct link_encoder *enc,
273 enum clock_source_id clock_source,
274 enum dc_color_depth color_depth,
275 enum signal_type signal,
276 uint32_t pixel_clock);
277
278/* enables DP PHY output */
279void dcn10_link_encoder_enable_dp_output(
280 struct link_encoder *enc,
281 const struct dc_link_settings *link_settings,
282 enum clock_source_id clock_source);
283
284/* enables DP PHY output in MST mode */
285void dcn10_link_encoder_enable_dp_mst_output(
286 struct link_encoder *enc,
287 const struct dc_link_settings *link_settings,
288 enum clock_source_id clock_source);
289
290/* disable PHY output */
291void dcn10_link_encoder_disable_output(
292 struct link_encoder *enc,
293 enum signal_type signal);
294
295/* set DP lane settings */
296void dcn10_link_encoder_dp_set_lane_settings(
297 struct link_encoder *enc,
298 const struct link_training_settings *link_settings);
299
300void dcn10_link_encoder_dp_set_phy_pattern(
301 struct link_encoder *enc,
302 const struct encoder_set_dp_phy_pattern_param *param);
303
304/* programs DP MST VC payload allocation */
305void dcn10_link_encoder_update_mst_stream_allocation_table(
306 struct link_encoder *enc,
307 const struct link_mst_stream_allocation_table *table);
308
309void dcn10_link_encoder_connect_dig_be_to_fe(
310 struct link_encoder *enc,
311 enum engine_id engine,
312 bool connect);
313
314void dcn10_link_encoder_set_dp_phy_pattern_training_pattern(
315 struct link_encoder *enc,
316 uint32_t index);
317
318void dcn10_link_encoder_enable_hpd(struct link_encoder *enc);
319
320void dcn10_link_encoder_disable_hpd(struct link_encoder *enc);
321
322void dcn10_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
323 bool exit_link_training_required);
324
325void dcn10_psr_program_secondary_packet(struct link_encoder *enc,
326 unsigned int sdp_transmit_line_num_deadline);
327
328bool dcn10_is_dig_enabled(struct link_encoder *enc);
329
330#endif /* __DC_LINK_ENCODER__DCN10_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index ace2e03dced4..df5cb2d1d164 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -38,7 +38,7 @@
38#include "dcn10/dcn10_hw_sequencer.h" 38#include "dcn10/dcn10_hw_sequencer.h"
39#include "dce110/dce110_hw_sequencer.h" 39#include "dce110/dce110_hw_sequencer.h"
40#include "dcn10/dcn10_opp.h" 40#include "dcn10/dcn10_opp.h"
41#include "dce/dce_link_encoder.h" 41#include "dcn10/dcn10_link_encoder.h"
42#include "dcn10/dcn10_stream_encoder.h" 42#include "dcn10/dcn10_stream_encoder.h"
43#include "dce/dce_clocks.h" 43#include "dce/dce_clocks.h"
44#include "dce/dce_clock_source.h" 44#include "dce/dce_clock_source.h"
@@ -214,13 +214,11 @@ static const struct dce_aduio_mask audio_mask = {
214 AUX_REG_LIST(id)\ 214 AUX_REG_LIST(id)\
215} 215}
216 216
217static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 217static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
218 aux_regs(0), 218 aux_regs(0),
219 aux_regs(1), 219 aux_regs(1),
220 aux_regs(2), 220 aux_regs(2),
221 aux_regs(3), 221 aux_regs(3)
222 aux_regs(4),
223 aux_regs(5)
224}; 222};
225 223
226#define hpd_regs(id)\ 224#define hpd_regs(id)\
@@ -228,13 +226,11 @@ static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
228 HPD_REG_LIST(id)\ 226 HPD_REG_LIST(id)\
229} 227}
230 228
231static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 229static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
232 hpd_regs(0), 230 hpd_regs(0),
233 hpd_regs(1), 231 hpd_regs(1),
234 hpd_regs(2), 232 hpd_regs(2),
235 hpd_regs(3), 233 hpd_regs(3)
236 hpd_regs(4),
237 hpd_regs(5)
238}; 234};
239 235
240#define link_regs(id)\ 236#define link_regs(id)\
@@ -243,14 +239,19 @@ static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
243 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 239 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
244} 240}
245 241
246static const struct dce110_link_enc_registers link_enc_regs[] = { 242static const struct dcn10_link_enc_registers link_enc_regs[] = {
247 link_regs(0), 243 link_regs(0),
248 link_regs(1), 244 link_regs(1),
249 link_regs(2), 245 link_regs(2),
250 link_regs(3), 246 link_regs(3)
251 link_regs(4), 247};
252 link_regs(5), 248
253 link_regs(6), 249static const struct dcn10_link_enc_shift le_shift = {
250 LINK_ENCODER_MASK_SH_LIST_DCN10(__SHIFT)
251};
252
253static const struct dcn10_link_enc_mask le_mask = {
254 LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK)
254}; 255};
255 256
256#define ipp_regs(id)\ 257#define ipp_regs(id)\
@@ -583,20 +584,22 @@ static const struct encoder_feature_support link_enc_feature = {
583struct link_encoder *dcn10_link_encoder_create( 584struct link_encoder *dcn10_link_encoder_create(
584 const struct encoder_init_data *enc_init_data) 585 const struct encoder_init_data *enc_init_data)
585{ 586{
586 struct dce110_link_encoder *enc110 = 587 struct dcn10_link_encoder *enc10 =
587 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 588 kzalloc(sizeof(struct dcn10_link_encoder), GFP_KERNEL);
588 589
589 if (!enc110) 590 if (!enc10)
590 return NULL; 591 return NULL;
591 592
592 dce110_link_encoder_construct(enc110, 593 dcn10_link_encoder_construct(enc10,
593 enc_init_data, 594 enc_init_data,
594 &link_enc_feature, 595 &link_enc_feature,
595 &link_enc_regs[enc_init_data->transmitter], 596 &link_enc_regs[enc_init_data->transmitter],
596 &link_enc_aux_regs[enc_init_data->channel - 1], 597 &link_enc_aux_regs[enc_init_data->channel - 1],
597 &link_enc_hpd_regs[enc_init_data->hpd_source]); 598 &link_enc_hpd_regs[enc_init_data->hpd_source],
599 &le_shift,
600 &le_mask);
598 601
599 return &enc110->base; 602 return &enc10->base;
600} 603}
601 604
602struct clock_source *dcn10_clock_source_create( 605struct clock_source *dcn10_clock_source_create(
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 04:54:31 -0400