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authorDanilo Cesar Lemes de Paula <danilo.cesar@collabora.co.uk>2015-11-25 12:07:55 -0500
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-12-15 04:22:26 -0500
commitf03d8ede7a901d2425da5c21a91f6a76fe16b47f (patch)
tree7f6416f78a7913f069b9628dd4c069814b1b3284
parent51bce5bc38bdb79c0f7ab33f1fe91a68ef1afa77 (diff)
drm/doc: Convert to markdown
DRM Docbook is now Markdown ready. This means its doc is able to use markdown text on it. * Documentation/DocBook/drm.tmpl: Contains a table duplicated from drivers/gpu/drm/i915/i915_reg.h. This is not needed anymore * drivers/gpu/drm/drm_modeset_lock.c: had a code example that used to look pretty bad on html. Fixed by using proper code markup. * drivers/gpu/drm/drm_prime.c: Remove spaces between lines to make a proper markup list. * drivers/gpu/drm/i915/i915_reg.h: Altought pandoc supports tables, it doesn't support table cell spanning. But we can use fixed-width for those special cases. * include/drm/drm_vma_manager.h: Another code example that should be proper indented with four spaces. v2 (Daniel): Adjust name to gpu.xml due to rename. v3 (Daniel): Split out the actual enabling in the Makefile - this way we can merge the conversion, while just keeping the enabling in a drm-private tree. Signed-off-by: Danilo Cesar Lemes de Paula <danilo.cesar@collabora.co.uk> (v1) Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: Jonathan Corbet <corbet@lwn.net> Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: Stephan Mueller <smueller@chronox.de> Cc: Michal Marek <mmarek@suse.cz> Cc: linux-kernel@vger.kernel.org Cc: linux-doc@vger.kernel.org Cc: intel-gfx <intel-gfx@lists.freedesktop.org> Cc: dri-devel <dri-devel@lists.freedesktop.org> Acked-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1448471279-19748-2-git-send-email-daniel.vetter@ffwll.ch
-rw-r--r--Documentation/DocBook/gpu.tmpl86
-rw-r--r--drivers/gpu/drm/drm_modes.c12
-rw-r--r--drivers/gpu/drm/drm_modeset_lock.c14
-rw-r--r--drivers/gpu/drm/drm_prime.c16
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h48
5 files changed, 42 insertions, 134 deletions
diff --git a/Documentation/DocBook/gpu.tmpl b/Documentation/DocBook/gpu.tmpl
index c66d6412f573..a27bdf9eaab5 100644
--- a/Documentation/DocBook/gpu.tmpl
+++ b/Documentation/DocBook/gpu.tmpl
@@ -3570,92 +3570,6 @@ int num_ioctls;</synopsis>
3570 <sect2> 3570 <sect2>
3571 <title>DPIO</title> 3571 <title>DPIO</title>
3572!Pdrivers/gpu/drm/i915/i915_reg.h DPIO 3572!Pdrivers/gpu/drm/i915/i915_reg.h DPIO
3573 <table id="dpiox2">
3574 <title>Dual channel PHY (VLV/CHV/BXT)</title>
3575 <tgroup cols="8">
3576 <colspec colname="c0" />
3577 <colspec colname="c1" />
3578 <colspec colname="c2" />
3579 <colspec colname="c3" />
3580 <colspec colname="c4" />
3581 <colspec colname="c5" />
3582 <colspec colname="c6" />
3583 <colspec colname="c7" />
3584 <spanspec spanname="ch0" namest="c0" nameend="c3" />
3585 <spanspec spanname="ch1" namest="c4" nameend="c7" />
3586 <spanspec spanname="ch0pcs01" namest="c0" nameend="c1" />
3587 <spanspec spanname="ch0pcs23" namest="c2" nameend="c3" />
3588 <spanspec spanname="ch1pcs01" namest="c4" nameend="c5" />
3589 <spanspec spanname="ch1pcs23" namest="c6" nameend="c7" />
3590 <thead>
3591 <row>
3592 <entry spanname="ch0">CH0</entry>
3593 <entry spanname="ch1">CH1</entry>
3594 </row>
3595 </thead>
3596 <tbody valign="top" align="center">
3597 <row>
3598 <entry spanname="ch0">CMN/PLL/REF</entry>
3599 <entry spanname="ch1">CMN/PLL/REF</entry>
3600 </row>
3601 <row>
3602 <entry spanname="ch0pcs01">PCS01</entry>
3603 <entry spanname="ch0pcs23">PCS23</entry>
3604 <entry spanname="ch1pcs01">PCS01</entry>
3605 <entry spanname="ch1pcs23">PCS23</entry>
3606 </row>
3607 <row>
3608 <entry>TX0</entry>
3609 <entry>TX1</entry>
3610 <entry>TX2</entry>
3611 <entry>TX3</entry>
3612 <entry>TX0</entry>
3613 <entry>TX1</entry>
3614 <entry>TX2</entry>
3615 <entry>TX3</entry>
3616 </row>
3617 <row>
3618 <entry spanname="ch0">DDI0</entry>
3619 <entry spanname="ch1">DDI1</entry>
3620 </row>
3621 </tbody>
3622 </tgroup>
3623 </table>
3624 <table id="dpiox1">
3625 <title>Single channel PHY (CHV/BXT)</title>
3626 <tgroup cols="4">
3627 <colspec colname="c0" />
3628 <colspec colname="c1" />
3629 <colspec colname="c2" />
3630 <colspec colname="c3" />
3631 <spanspec spanname="ch0" namest="c0" nameend="c3" />
3632 <spanspec spanname="ch0pcs01" namest="c0" nameend="c1" />
3633 <spanspec spanname="ch0pcs23" namest="c2" nameend="c3" />
3634 <thead>
3635 <row>
3636 <entry spanname="ch0">CH0</entry>
3637 </row>
3638 </thead>
3639 <tbody valign="top" align="center">
3640 <row>
3641 <entry spanname="ch0">CMN/PLL/REF</entry>
3642 </row>
3643 <row>
3644 <entry spanname="ch0pcs01">PCS01</entry>
3645 <entry spanname="ch0pcs23">PCS23</entry>
3646 </row>
3647 <row>
3648 <entry>TX0</entry>
3649 <entry>TX1</entry>
3650 <entry>TX2</entry>
3651 <entry>TX3</entry>
3652 </row>
3653 <row>
3654 <entry spanname="ch0">DDI2</entry>
3655 </row>
3656 </tbody>
3657 </tgroup>
3658 </table>
3659 </sect2> 3573 </sect2>
3660 3574
3661 <sect2> 3575 <sect2>
diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index 5a8a78d5e960..20775c05235a 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -553,10 +553,10 @@ EXPORT_SYMBOL(drm_gtf_mode_complex);
553 * drivers/video/fbmon.c 553 * drivers/video/fbmon.c
554 * 554 *
555 * Standard GTF parameters: 555 * Standard GTF parameters:
556 * M = 600 556 * M = 600
557 * C = 40 557 * C = 40
558 * K = 128 558 * K = 128
559 * J = 20 559 * J = 20
560 * 560 *
561 * Returns: 561 * Returns:
562 * The modeline based on the GTF algorithm stored in a drm_display_mode object. 562 * The modeline based on the GTF algorithm stored in a drm_display_mode object.
@@ -1244,7 +1244,7 @@ EXPORT_SYMBOL(drm_mode_connector_list_update);
1244 * This uses the same parameters as the fb modedb.c, except for an extra 1244 * This uses the same parameters as the fb modedb.c, except for an extra
1245 * force-enable, force-enable-digital and force-disable bit at the end: 1245 * force-enable, force-enable-digital and force-disable bit at the end:
1246 * 1246 *
1247 * <xres>x<yres>[M][R][-<bpp>][@<refresh>][i][m][eDd] 1247 * <xres>x<yres>[M][R][-<bpp>][@<refresh>][i][m][eDd]
1248 * 1248 *
1249 * The intermediate drm_cmdline_mode structure is required to store additional 1249 * The intermediate drm_cmdline_mode structure is required to store additional
1250 * options from the command line modline like the force-enable/disable flag. 1250 * options from the command line modline like the force-enable/disable flag.
@@ -1523,4 +1523,4 @@ int drm_mode_convert_umode(struct drm_display_mode *out,
1523 1523
1524out: 1524out:
1525 return ret; 1525 return ret;
1526} \ No newline at end of file 1526}
diff --git a/drivers/gpu/drm/drm_modeset_lock.c b/drivers/gpu/drm/drm_modeset_lock.c
index c2f5971146ba..e3a4adf03e7b 100644
--- a/drivers/gpu/drm/drm_modeset_lock.c
+++ b/drivers/gpu/drm/drm_modeset_lock.c
@@ -40,17 +40,15 @@
40 * The basic usage pattern is to: 40 * The basic usage pattern is to:
41 * 41 *
42 * drm_modeset_acquire_init(&ctx) 42 * drm_modeset_acquire_init(&ctx)
43 * retry: 43 * retry:
44 * foreach (lock in random_ordered_set_of_locks) { 44 * foreach (lock in random_ordered_set_of_locks) {
45 * ret = drm_modeset_lock(lock, &ctx) 45 * ret = drm_modeset_lock(lock, &ctx)
46 * if (ret == -EDEADLK) { 46 * if (ret == -EDEADLK) {
47 * drm_modeset_backoff(&ctx); 47 * drm_modeset_backoff(&ctx);
48 * goto retry; 48 * goto retry;
49 * } 49 * }
50 * } 50 * }
51 *
52 * ... do stuff ... 51 * ... do stuff ...
53 *
54 * drm_modeset_drop_locks(&ctx); 52 * drm_modeset_drop_locks(&ctx);
55 * drm_modeset_acquire_fini(&ctx); 53 * drm_modeset_acquire_fini(&ctx);
56 */ 54 */
diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
index 9f935f55d74c..27aa7183b20b 100644
--- a/drivers/gpu/drm/drm_prime.c
+++ b/drivers/gpu/drm/drm_prime.c
@@ -313,19 +313,15 @@ static const struct dma_buf_ops drm_gem_prime_dmabuf_ops = {
313 * 313 *
314 * Export callbacks: 314 * Export callbacks:
315 * 315 *
316 * - @gem_prime_pin (optional): prepare a GEM object for exporting 316 * * @gem_prime_pin (optional): prepare a GEM object for exporting
317 * 317 * * @gem_prime_get_sg_table: provide a scatter/gather table of pinned pages
318 * - @gem_prime_get_sg_table: provide a scatter/gather table of pinned pages 318 * * @gem_prime_vmap: vmap a buffer exported by your driver
319 * 319 * * @gem_prime_vunmap: vunmap a buffer exported by your driver
320 * - @gem_prime_vmap: vmap a buffer exported by your driver 320 * * @gem_prime_mmap (optional): mmap a buffer exported by your driver
321 *
322 * - @gem_prime_vunmap: vunmap a buffer exported by your driver
323 *
324 * - @gem_prime_mmap (optional): mmap a buffer exported by your driver
325 * 321 *
326 * Import callback: 322 * Import callback:
327 * 323 *
328 * - @gem_prime_import_sg_table (import): produce a GEM object from another 324 * * @gem_prime_import_sg_table (import): produce a GEM object from another
329 * driver's scatter/gather table 325 * driver's scatter/gather table
330 */ 326 */
331 327
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 206b213a74e1..1dae5ac3e0b1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -855,31 +855,31 @@ enum skl_disp_power_wells {
855 * 855 *
856 * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is 856 * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is
857 * digital port D (CHV) or port A (BXT). 857 * digital port D (CHV) or port A (BXT).
858 */
859/*
860 * Dual channel PHY (VLV/CHV/BXT)
861 * ---------------------------------
862 * | CH0 | CH1 |
863 * | CMN/PLL/REF | CMN/PLL/REF |
864 * |---------------|---------------| Display PHY
865 * | PCS01 | PCS23 | PCS01 | PCS23 |
866 * |-------|-------|-------|-------|
867 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|
868 * ---------------------------------
869 * | DDI0 | DDI1 | DP/HDMI ports
870 * ---------------------------------
871 * 858 *
872 * Single channel PHY (CHV/BXT) 859 *
873 * ----------------- 860 * Dual channel PHY (VLV/CHV/BXT)
874 * | CH0 | 861 * ---------------------------------
875 * | CMN/PLL/REF | 862 * | CH0 | CH1 |
876 * |---------------| Display PHY 863 * | CMN/PLL/REF | CMN/PLL/REF |
877 * | PCS01 | PCS23 | 864 * |---------------|---------------| Display PHY
878 * |-------|-------| 865 * | PCS01 | PCS23 | PCS01 | PCS23 |
879 * |TX0|TX1|TX2|TX3| 866 * |-------|-------|-------|-------|
880 * ----------------- 867 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|
881 * | DDI2 | DP/HDMI port 868 * ---------------------------------
882 * ----------------- 869 * | DDI0 | DDI1 | DP/HDMI ports
870 * ---------------------------------
871 *
872 * Single channel PHY (CHV/BXT)
873 * -----------------
874 * | CH0 |
875 * | CMN/PLL/REF |
876 * |---------------| Display PHY
877 * | PCS01 | PCS23 |
878 * |-------|-------|
879 * |TX0|TX1|TX2|TX3|
880 * -----------------
881 * | DDI2 | DP/HDMI port
882 * -----------------
883 */ 883 */
884#define DPIO_DEVFN 0 884#define DPIO_DEVFN 0
885 885