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authorArnd Bergmann <arnd@arndb.de>2018-03-27 07:28:10 -0400
committerArnd Bergmann <arnd@arndb.de>2018-03-27 07:28:10 -0400
commitf02e0468c4ddca24f904766a048ce135071ae80f (patch)
tree0bcee5b95c6f37997380bafceb69cb9b815b8a57
parentd45357e40e0f70ebef15abb62d2a5e22fcdb02ea (diff)
parentca565be2b526a731d02a2fbff96fb0572567ea55 (diff)
Merge tag 'renesas-arm64-dt-for-v4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Pull "Renesas ARM64 Based SoC DT Updates for v4.17" from Simon Horman: * R-Car Gen3 boards and SoCs - Make phy-mode of EtherAVB a board-specific property. The SoC DTs file now uses "rgmii" and boards override this with "rgmii-txid" as appropriate. Previously "rgmii-txid" was used in SoC DTs but this did not describe that more sophiticated functionality is a board rather than SoC property. * Condor board with R-Car V3H (r8a77980) SoC - Initial upstream support * Condor board with R-Car V3H (r8a77980) SoC - Initial upstream support * R-Car D3 (r8a77995) - Add I2C nodes and then describing the PCA9654 I/O expander connected to the I2C0 bus. * Eagle board with R-Car V3M (r8a77970) SoC - Enable PFC support for configuring SCIF0 pins This uses PFC support added to the V3M DT - Describe EtherAVB PHY IRQ This uses support for GPIO added to the V3M DT - Enable I2C0 support Sergei Shtylyov says "The I2C0 bus is populated by ON Semiconductor PCA9653 I/O expander and Analog Devices ADV7511W HDMI transmitter (but we're only describing the former chip now)." * R-Car V3M (r8a77970) SoCs - Add PFC support - Describe GPIO devices - Describe I2C devices - Srt subnodes of root node alphabetically to eas future maintence overhead * Draak board with R-Car D3 (r8a77995) SoC - Enable SDHI2 Wolfram Sang says "The single SDHI controller is connected to eMMC." - Enable DU Kieran Bingham says "Enable the DU, providing only the VGA output for now." * R-Car D3 (r8a77995) and V3M (r8a77970) SoCs - Move nodes which have no reg property out of bus By deffinition the bus only has hardware with an address on the bus - Remove non-existing STBE region from EtherAVB Stream Buffer for EtherAVB-IF (STBE) is not present on these SoCs * R-Car D3 (r8a77995) SoC - Add FCPV, VSP and DU support Kieran Bingham says "The r8a77995-d3 platform supports 3 VSP instances. One VSPBS can be used as a dual-input image blender, while two VSPD instances can be utilised as part of a display (DU) pipeline. Add support for these, along with their required FCPV nodes." * Salvator-X and Salvator-XS boards with R-Car Gen3 SoCs - Add GPIO extender This is a basis for follow-up work to configure the GPIOs of the extender * Salvator-X and Salvator-XS board with R-Car M3-N (r8a77965) SoC - Initial upstream support * R-Car H3 (r8a7795) and M3-W (r8a7796) SoCs - Add OPPs table for cpu devices This, along with recently upstreamed Z and Z2 clock support allows use of CPUFreq with both A57 and A53 CPUs. - Add thermal cooling management Allows the use of CPUFreq as a cooling device on A57 CPUs - Correct register size of thermal node Niklas Söderlund says "To be able to read fused calibration values from hardware the size of the register resource of TSC1 needs to be incremented to cover one more register which holds the information if the calibration values have been fused or not. Instead of increasing TSC1 size to the value from the datasheet update all TSC's size to the smallest granularity of the address decoder circuitry" - Fix register mappings on VSPs Kieran Bingham says "The VSPD includes a CLUT on RPF2. Ensure that the register space is mapped correctly to support this." * R-Car H3 (r8a7795) SoC - Move SCIF node into alphabetical order to ease future maintenance overhead - Add IPMMU-PV1 device node This resolves an oversight when IPMMU nodes were added to the H3 DT. All IPMMU devices should now be described in DT. - Add missing SYS-DMAC2 dmas Geert Uytterhoeven says "On R-Car H3, on-chip peripheral modules that can make use of DMA are wired to either SYS-DMAC0 only, or to both SYS-DMAC1 and SYS-DMAC2. Add the missing DMA properties pointing to SYS-DMAC2 for HSCIF[0-2], SCIF[0125], and I2C[0-2]. These were initially left out because early firmware versions prohibited using SYS-DMAC2. This restriction has been lifted in IPL and Secure Monitor Rev1.0.6 (released on Feb 25, 2016)." * tag 'renesas-arm64-dt-for-v4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (69 commits) arm64: dts: renesas: v3msk: add SCIF0 pins arm64: dts: renesas: r8a7795: Add missing SYS-DMAC2 dmas arm64: dts: renesas: r8a7795: Add IPMMU-PV1 device node arm64: dts: renesas: r8a77970: sort subnodes of root node alphabetically arm64: dts: renesas: eagle: add I2C0 support arm64: dts: renesas: r8a77970: add I2C support arm64: dts: renesas: r8a77965-salvator-xs: Add SoC name to file header arm64: dts: renesas: r8a77965: Add EtherAVB device node arm64: dts: renesas: r8a77970: Set EtherAVB phy mode to "rgmii" arm64: dts: renesas: r8a77995: Set EtherAVB phy mode to "rgmii" arm64: dts: renesas: r8a7795: Set EtherAVB phy mode to "rgmii" arm64: dts: renesas: r8a7796: Set EtherAVB phy mode to "rgmii" arm64: dts: renesas: v3msk: Override EtherAVB phy-mode arm64: dts: renesas: eagle: Override EtherAVB phy-mode arm64: dts: renesas: draak: Override EtherAVB phy-mode arm64: dts: renesas: ulcb: Override EtherAVB phy-mode arm64: dts: renesas: salvator-common: Override EtherAVB phy-mode arm64: dts: renesas: r8a77965: Add INTC-EX device node arm64: dts: renesas: r8a77965: Add IIC-DVFS device node arm64: dts: renesas: Add support for Salvator-XS with R-Car M3-N ...
Diffstat
-rw-r--r--arch/arm64/Kconfig.platforms12
-rw-r--r--arch/arm64/boot/dts/renesas/Makefile2
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi3
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795.dtsi194
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7796.dtsi130
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts21
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts21
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77965.dtsi878
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77970-eagle.dts33
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts11
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77970.dtsi218
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77980-condor.dts58
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77980.dtsi385
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77995-draak.dts124
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77995.dtsi193
-rw-r--r--arch/arm64/boot/dts/renesas/salvator-common.dtsi8
-rw-r--r--arch/arm64/boot/dts/renesas/ulcb.dtsi1
17 files changed, 2216 insertions, 76 deletions
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index fbedbd8f619a..2b1535cdeb7c 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -190,12 +190,24 @@ config ARCH_R8A7796
190 help 190 help
191 This enables support for the Renesas R-Car M3-W SoC. 191 This enables support for the Renesas R-Car M3-W SoC.
192 192
193config ARCH_R8A77965
194 bool "Renesas R-Car M3-N SoC Platform"
195 depends on ARCH_RENESAS
196 help
197 This enables support for the Renesas R-Car M3-N SoC.
198
193config ARCH_R8A77970 199config ARCH_R8A77970
194 bool "Renesas R-Car V3M SoC Platform" 200 bool "Renesas R-Car V3M SoC Platform"
195 depends on ARCH_RENESAS 201 depends on ARCH_RENESAS
196 help 202 help
197 This enables support for the Renesas R-Car V3M SoC. 203 This enables support for the Renesas R-Car V3M SoC.
198 204
205config ARCH_R8A77980
206 bool "Renesas R-Car V3H SoC Platform"
207 depends on ARCH_RENESAS
208 help
209 This enables support for the Renesas R-Car V3H SoC.
210
199config ARCH_R8A77995 211config ARCH_R8A77995
200 bool "Renesas R-Car D3 SoC Platform" 212 bool "Renesas R-Car D3 SoC Platform"
201 depends on ARCH_RENESAS 213 depends on ARCH_RENESAS
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 2186d0193b73..5ede06000ea4 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -7,5 +7,7 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-h3ulcb-kf.dtb
7dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb 7dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb
8dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb 8dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb
9dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb 9dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
10dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb
10dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb 11dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb
12dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb
11dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb 13dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
index 26769a11a190..f9acd125d687 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
@@ -23,6 +23,7 @@
23 23
24 /delete-node/ mmu@febe0000; 24 /delete-node/ mmu@febe0000;
25 /delete-node/ mmu@fe980000; 25 /delete-node/ mmu@fe980000;
26 /delete-node/ mmu@fd950000;
26 /delete-node/ mmu@fd960000; 27 /delete-node/ mmu@fd960000;
27 /delete-node/ mmu@fd970000; 28 /delete-node/ mmu@fd970000;
28 29
@@ -80,7 +81,7 @@
80 81
81 vspd3: vsp@fea38000 { 82 vspd3: vsp@fea38000 {
82 compatible = "renesas,vsp2"; 83 compatible = "renesas,vsp2";
83 reg = <0 0xfea38000 0 0x4000>; 84 reg = <0 0xfea38000 0 0x8000>;
84 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 85 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
85 clocks = <&cpg CPG_MOD 620>; 86 clocks = <&cpg CPG_MOD 620>;
86 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 87 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index d12df6f2ff09..1d5e3ac0231c 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -41,6 +41,9 @@
41 power-domains = <&sysc R8A7795_PD_CA57_CPU0>; 41 power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
42 next-level-cache = <&L2_CA57>; 42 next-level-cache = <&L2_CA57>;
43 enable-method = "psci"; 43 enable-method = "psci";
44 clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
45 operating-points-v2 = <&cluster0_opp>;
46 #cooling-cells = <2>;
44 }; 47 };
45 48
46 a57_1: cpu@1 { 49 a57_1: cpu@1 {
@@ -50,6 +53,9 @@
50 power-domains = <&sysc R8A7795_PD_CA57_CPU1>; 53 power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
51 next-level-cache = <&L2_CA57>; 54 next-level-cache = <&L2_CA57>;
52 enable-method = "psci"; 55 enable-method = "psci";
56 clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
57 operating-points-v2 = <&cluster0_opp>;
58 #cooling-cells = <2>;
53 }; 59 };
54 60
55 a57_2: cpu@2 { 61 a57_2: cpu@2 {
@@ -59,6 +65,9 @@
59 power-domains = <&sysc R8A7795_PD_CA57_CPU2>; 65 power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
60 next-level-cache = <&L2_CA57>; 66 next-level-cache = <&L2_CA57>;
61 enable-method = "psci"; 67 enable-method = "psci";
68 clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
69 operating-points-v2 = <&cluster0_opp>;
70 #cooling-cells = <2>;
62 }; 71 };
63 72
64 a57_3: cpu@3 { 73 a57_3: cpu@3 {
@@ -68,6 +77,9 @@
68 power-domains = <&sysc R8A7795_PD_CA57_CPU3>; 77 power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
69 next-level-cache = <&L2_CA57>; 78 next-level-cache = <&L2_CA57>;
70 enable-method = "psci"; 79 enable-method = "psci";
80 clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
81 operating-points-v2 = <&cluster0_opp>;
82 #cooling-cells = <2>;
71 }; 83 };
72 84
73 a53_0: cpu@100 { 85 a53_0: cpu@100 {
@@ -77,6 +89,8 @@
77 power-domains = <&sysc R8A7795_PD_CA53_CPU0>; 89 power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
78 next-level-cache = <&L2_CA53>; 90 next-level-cache = <&L2_CA53>;
79 enable-method = "psci"; 91 enable-method = "psci";
92 clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
93 operating-points-v2 = <&cluster1_opp>;
80 }; 94 };
81 95
82 a53_1: cpu@101 { 96 a53_1: cpu@101 {
@@ -86,6 +100,8 @@
86 power-domains = <&sysc R8A7795_PD_CA53_CPU1>; 100 power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
87 next-level-cache = <&L2_CA53>; 101 next-level-cache = <&L2_CA53>;
88 enable-method = "psci"; 102 enable-method = "psci";
103 clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
104 operating-points-v2 = <&cluster1_opp>;
89 }; 105 };
90 106
91 a53_2: cpu@102 { 107 a53_2: cpu@102 {
@@ -95,6 +111,8 @@
95 power-domains = <&sysc R8A7795_PD_CA53_CPU2>; 111 power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
96 next-level-cache = <&L2_CA53>; 112 next-level-cache = <&L2_CA53>;
97 enable-method = "psci"; 113 enable-method = "psci";
114 clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
115 operating-points-v2 = <&cluster1_opp>;
98 }; 116 };
99 117
100 a53_3: cpu@103 { 118 a53_3: cpu@103 {
@@ -104,6 +122,8 @@
104 power-domains = <&sysc R8A7795_PD_CA53_CPU3>; 122 power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
105 next-level-cache = <&L2_CA53>; 123 next-level-cache = <&L2_CA53>;
106 enable-method = "psci"; 124 enable-method = "psci";
125 clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
126 operating-points-v2 = <&cluster1_opp>;
107 }; 127 };
108 128
109 L2_CA57: cache-controller-0 { 129 L2_CA57: cache-controller-0 {
@@ -165,11 +185,59 @@
165 clock-frequency = <0>; 185 clock-frequency = <0>;
166 }; 186 };
167 187
168 /* External SCIF clock - to be overridden by boards that provide it */ 188 cluster0_opp: opp_table0 {
169 scif_clk: scif { 189 compatible = "operating-points-v2";
170 compatible = "fixed-clock"; 190 opp-shared;
171 #clock-cells = <0>; 191
172 clock-frequency = <0>; 192 opp-500000000 {
193 opp-hz = /bits/ 64 <500000000>;
194 opp-microvolt = <830000>;
195 clock-latency-ns = <300000>;
196 };
197 opp-1000000000 {
198 opp-hz = /bits/ 64 <1000000000>;
199 opp-microvolt = <830000>;
200 clock-latency-ns = <300000>;
201 };
202 opp-1500000000 {
203 opp-hz = /bits/ 64 <1500000000>;
204 opp-microvolt = <830000>;
205 clock-latency-ns = <300000>;
206 opp-suspend;
207 };
208 opp-1600000000 {
209 opp-hz = /bits/ 64 <1600000000>;
210 opp-microvolt = <900000>;
211 clock-latency-ns = <300000>;
212 turbo-mode;
213 };
214 opp-1700000000 {
215 opp-hz = /bits/ 64 <1700000000>;
216 opp-microvolt = <960000>;
217 clock-latency-ns = <300000>;
218 turbo-mode;
219 };
220 };
221
222 cluster1_opp: opp_table1 {
223 compatible = "operating-points-v2";
224 opp-shared;
225
226 opp-800000000 {
227 opp-hz = /bits/ 64 <800000000>;
228 opp-microvolt = <820000>;
229 clock-latency-ns = <300000>;
230 };
231 opp-1000000000 {
232 opp-hz = /bits/ 64 <1000000000>;
233 opp-microvolt = <820000>;
234 clock-latency-ns = <300000>;
235 };
236 opp-1200000000 {
237 opp-hz = /bits/ 64 <1200000000>;
238 opp-microvolt = <820000>;
239 clock-latency-ns = <300000>;
240 };
173 }; 241 };
174 242
175 /* External PCIe clock - can be overridden by the board */ 243 /* External PCIe clock - can be overridden by the board */
@@ -208,6 +276,13 @@
208 method = "smc"; 276 method = "smc";
209 }; 277 };
210 278
279 /* External SCIF clock - to be overridden by boards that provide it */
280 scif_clk: scif {
281 compatible = "fixed-clock";
282 #clock-cells = <0>;
283 clock-frequency = <0>;
284 };
285
211 soc: soc { 286 soc: soc {
212 compatible = "simple-bus"; 287 compatible = "simple-bus";
213 interrupt-parent = <&gic>; 288 interrupt-parent = <&gic>;
@@ -470,6 +545,15 @@
470 status = "disabled"; 545 status = "disabled";
471 }; 546 };
472 547
548 ipmmu_pv1: mmu@fd950000 {
549 compatible = "renesas,ipmmu-r8a7795";
550 reg = <0 0xfd950000 0 0x1000>;
551 renesas,ipmmu-main = <&ipmmu_mm 7>;
552 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
553 #iommu-cells = <1>;
554 status = "disabled";
555 };
556
473 ipmmu_pv2: mmu@fd960000 { 557 ipmmu_pv2: mmu@fd960000 {
474 compatible = "renesas,ipmmu-r8a7795"; 558 compatible = "renesas,ipmmu-r8a7795";
475 reg = <0 0xfd960000 0 0x1000>; 559 reg = <0 0xfd960000 0 0x1000>;
@@ -798,7 +882,7 @@
798 clocks = <&cpg CPG_MOD 812>; 882 clocks = <&cpg CPG_MOD 812>;
799 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 883 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
800 resets = <&cpg 812>; 884 resets = <&cpg 812>;
801 phy-mode = "rgmii-txid"; 885 phy-mode = "rgmii";
802 iommus = <&ipmmu_ds0 16>; 886 iommus = <&ipmmu_ds0 16>;
803 #address-cells = <1>; 887 #address-cells = <1>;
804 #size-cells = <0>; 888 #size-cells = <0>;
@@ -992,8 +1076,9 @@
992 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1076 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
993 <&scif_clk>; 1077 <&scif_clk>;
994 clock-names = "fck", "brg_int", "scif_clk"; 1078 clock-names = "fck", "brg_int", "scif_clk";
995 dmas = <&dmac1 0x31>, <&dmac1 0x30>; 1079 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
996 dma-names = "tx", "rx"; 1080 <&dmac2 0x31>, <&dmac2 0x30>;
1081 dma-names = "tx", "rx", "tx", "rx";
997 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1082 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
998 resets = <&cpg 520>; 1083 resets = <&cpg 520>;
999 status = "disabled"; 1084 status = "disabled";
@@ -1009,8 +1094,9 @@
1009 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1094 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
1010 <&scif_clk>; 1095 <&scif_clk>;
1011 clock-names = "fck", "brg_int", "scif_clk"; 1096 clock-names = "fck", "brg_int", "scif_clk";
1012 dmas = <&dmac1 0x33>, <&dmac1 0x32>; 1097 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
1013 dma-names = "tx", "rx"; 1098 <&dmac2 0x33>, <&dmac2 0x32>;
1099 dma-names = "tx", "rx", "tx", "rx";
1014 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1100 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1015 resets = <&cpg 519>; 1101 resets = <&cpg 519>;
1016 status = "disabled"; 1102 status = "disabled";
@@ -1026,8 +1112,9 @@
1026 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1112 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
1027 <&scif_clk>; 1113 <&scif_clk>;
1028 clock-names = "fck", "brg_int", "scif_clk"; 1114 clock-names = "fck", "brg_int", "scif_clk";
1029 dmas = <&dmac1 0x35>, <&dmac1 0x34>; 1115 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
1030 dma-names = "tx", "rx"; 1116 <&dmac2 0x35>, <&dmac2 0x34>;
1117 dma-names = "tx", "rx", "tx", "rx";
1031 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1118 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1032 resets = <&cpg 518>; 1119 resets = <&cpg 518>;
1033 status = "disabled"; 1120 status = "disabled";
@@ -1138,8 +1225,9 @@
1138 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1225 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
1139 <&scif_clk>; 1226 <&scif_clk>;
1140 clock-names = "fck", "brg_int", "scif_clk"; 1227 clock-names = "fck", "brg_int", "scif_clk";
1141 dmas = <&dmac1 0x51>, <&dmac1 0x50>; 1228 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1142 dma-names = "tx", "rx"; 1229 <&dmac2 0x51>, <&dmac2 0x50>;
1230 dma-names = "tx", "rx", "tx", "rx";
1143 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1231 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1144 resets = <&cpg 207>; 1232 resets = <&cpg 207>;
1145 status = "disabled"; 1233 status = "disabled";
@@ -1154,8 +1242,9 @@
1154 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1242 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
1155 <&scif_clk>; 1243 <&scif_clk>;
1156 clock-names = "fck", "brg_int", "scif_clk"; 1244 clock-names = "fck", "brg_int", "scif_clk";
1157 dmas = <&dmac1 0x53>, <&dmac1 0x52>; 1245 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1158 dma-names = "tx", "rx"; 1246 <&dmac2 0x53>, <&dmac2 0x52>;
1247 dma-names = "tx", "rx", "tx", "rx";
1159 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1248 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1160 resets = <&cpg 206>; 1249 resets = <&cpg 206>;
1161 status = "disabled"; 1250 status = "disabled";
@@ -1170,8 +1259,9 @@
1170 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1259 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
1171 <&scif_clk>; 1260 <&scif_clk>;
1172 clock-names = "fck", "brg_int", "scif_clk"; 1261 clock-names = "fck", "brg_int", "scif_clk";
1173 dmas = <&dmac1 0x13>, <&dmac1 0x12>; 1262 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1174 dma-names = "tx", "rx"; 1263 <&dmac2 0x13>, <&dmac2 0x12>;
1264 dma-names = "tx", "rx", "tx", "rx";
1175 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1265 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1176 resets = <&cpg 310>; 1266 resets = <&cpg 310>;
1177 status = "disabled"; 1267 status = "disabled";
@@ -1218,8 +1308,9 @@
1218 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1308 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
1219 <&scif_clk>; 1309 <&scif_clk>;
1220 clock-names = "fck", "brg_int", "scif_clk"; 1310 clock-names = "fck", "brg_int", "scif_clk";
1221 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>; 1311 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1222 dma-names = "tx", "rx"; 1312 <&dmac2 0x5b>, <&dmac2 0x5a>;
1313 dma-names = "tx", "rx", "tx", "rx";
1223 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1314 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1224 resets = <&cpg 202>; 1315 resets = <&cpg 202>;
1225 status = "disabled"; 1316 status = "disabled";
@@ -1251,8 +1342,9 @@
1251 clocks = <&cpg CPG_MOD 931>; 1342 clocks = <&cpg CPG_MOD 931>;
1252 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1343 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1253 resets = <&cpg 931>; 1344 resets = <&cpg 931>;
1254 dmas = <&dmac1 0x91>, <&dmac1 0x90>; 1345 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
1255 dma-names = "tx", "rx"; 1346 <&dmac2 0x91>, <&dmac2 0x90>;
1347 dma-names = "tx", "rx", "tx", "rx";
1256 i2c-scl-internal-delay-ns = <110>; 1348 i2c-scl-internal-delay-ns = <110>;
1257 status = "disabled"; 1349 status = "disabled";
1258 }; 1350 };
@@ -1267,8 +1359,9 @@
1267 clocks = <&cpg CPG_MOD 930>; 1359 clocks = <&cpg CPG_MOD 930>;
1268 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1360 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1269 resets = <&cpg 930>; 1361 resets = <&cpg 930>;
1270 dmas = <&dmac1 0x93>, <&dmac1 0x92>; 1362 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
1271 dma-names = "tx", "rx"; 1363 <&dmac2 0x93>, <&dmac2 0x92>;
1364 dma-names = "tx", "rx", "tx", "rx";
1272 i2c-scl-internal-delay-ns = <6>; 1365 i2c-scl-internal-delay-ns = <6>;
1273 status = "disabled"; 1366 status = "disabled";
1274 }; 1367 };
@@ -1283,8 +1376,9 @@
1283 clocks = <&cpg CPG_MOD 929>; 1376 clocks = <&cpg CPG_MOD 929>;
1284 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1377 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1285 resets = <&cpg 929>; 1378 resets = <&cpg 929>;
1286 dmas = <&dmac1 0x95>, <&dmac1 0x94>; 1379 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
1287 dma-names = "tx", "rx"; 1380 <&dmac2 0x95>, <&dmac2 0x94>;
1381 dma-names = "tx", "rx", "tx", "rx";
1288 i2c-scl-internal-delay-ns = <6>; 1382 i2c-scl-internal-delay-ns = <6>;
1289 status = "disabled"; 1383 status = "disabled";
1290 }; 1384 };
@@ -2143,7 +2237,7 @@
2143 2237
2144 vspd0: vsp@fea20000 { 2238 vspd0: vsp@fea20000 {
2145 compatible = "renesas,vsp2"; 2239 compatible = "renesas,vsp2";
2146 reg = <0 0xfea20000 0 0x4000>; 2240 reg = <0 0xfea20000 0 0x8000>;
2147 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 2241 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
2148 clocks = <&cpg CPG_MOD 623>; 2242 clocks = <&cpg CPG_MOD 623>;
2149 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2243 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -2163,7 +2257,7 @@
2163 2257
2164 vspd1: vsp@fea28000 { 2258 vspd1: vsp@fea28000 {
2165 compatible = "renesas,vsp2"; 2259 compatible = "renesas,vsp2";
2166 reg = <0 0xfea28000 0 0x4000>; 2260 reg = <0 0xfea28000 0 0x8000>;
2167 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 2261 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
2168 clocks = <&cpg CPG_MOD 622>; 2262 clocks = <&cpg CPG_MOD 622>;
2169 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2263 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -2183,7 +2277,7 @@
2183 2277
2184 vspd2: vsp@fea30000 { 2278 vspd2: vsp@fea30000 {
2185 compatible = "renesas,vsp2"; 2279 compatible = "renesas,vsp2";
2186 reg = <0 0xfea30000 0 0x4000>; 2280 reg = <0 0xfea30000 0 0x8000>;
2187 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 2281 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
2188 clocks = <&cpg CPG_MOD 621>; 2282 clocks = <&cpg CPG_MOD 621>;
2189 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2283 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -2320,9 +2414,9 @@
2320 2414
2321 tsc: thermal@e6198000 { 2415 tsc: thermal@e6198000 {
2322 compatible = "renesas,r8a7795-thermal"; 2416 compatible = "renesas,r8a7795-thermal";
2323 reg = <0 0xe6198000 0 0x68>, 2417 reg = <0 0xe6198000 0 0x100>,
2324 <0 0xe61a0000 0 0x5c>, 2418 <0 0xe61a0000 0 0x100>,
2325 <0 0xe61a8000 0 0x5c>; 2419 <0 0xe61a8000 0 0x100>;
2326 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 2420 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
2327 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 2421 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
2328 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 2422 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
@@ -2357,12 +2451,24 @@
2357 thermal-sensors = <&tsc 0>; 2451 thermal-sensors = <&tsc 0>;
2358 2452
2359 trips { 2453 trips {
2454 sensor1_passive: sensor1-passive {
2455 temperature = <95000>;
2456 hysteresis = <2000>;
2457 type = "passive";
2458 };
2360 sensor1_crit: sensor1-crit { 2459 sensor1_crit: sensor1-crit {
2361 temperature = <120000>; 2460 temperature = <120000>;
2362 hysteresis = <2000>; 2461 hysteresis = <2000>;
2363 type = "critical"; 2462 type = "critical";
2364 }; 2463 };
2365 }; 2464 };
2465
2466 cooling-maps {
2467 map0 {
2468 trip = <&sensor1_passive>;
2469 cooling-device = <&a57_0 4 4>;
2470 };
2471 };
2366 }; 2472 };
2367 2473
2368 sensor_thermal2: sensor-thermal2 { 2474 sensor_thermal2: sensor-thermal2 {
@@ -2371,12 +2477,24 @@
2371 thermal-sensors = <&tsc 1>; 2477 thermal-sensors = <&tsc 1>;
2372 2478
2373 trips { 2479 trips {
2480 sensor2_passive: sensor2-passive {
2481 temperature = <95000>;
2482 hysteresis = <2000>;
2483 type = "passive";
2484 };
2374 sensor2_crit: sensor2-crit { 2485 sensor2_crit: sensor2-crit {
2375 temperature = <120000>; 2486 temperature = <120000>;
2376 hysteresis = <2000>; 2487 hysteresis = <2000>;
2377 type = "critical"; 2488 type = "critical";
2378 }; 2489 };
2379 }; 2490 };
2491
2492 cooling-maps {
2493 map0 {
2494 trip = <&sensor2_passive>;
2495 cooling-device = <&a57_0 4 4>;
2496 };
2497 };
2380 }; 2498 };
2381 2499
2382 sensor_thermal3: sensor-thermal3 { 2500 sensor_thermal3: sensor-thermal3 {
@@ -2385,12 +2503,24 @@
2385 thermal-sensors = <&tsc 2>; 2503 thermal-sensors = <&tsc 2>;
2386 2504
2387 trips { 2505 trips {
2506 sensor3_passive: sensor3-passive {
2507 temperature = <95000>;
2508 hysteresis = <2000>;
2509 type = "passive";
2510 };
2388 sensor3_crit: sensor3-crit { 2511 sensor3_crit: sensor3-crit {
2389 temperature = <120000>; 2512 temperature = <120000>;
2390 hysteresis = <2000>; 2513 hysteresis = <2000>;
2391 type = "critical"; 2514 type = "critical";
2392 }; 2515 };
2393 }; 2516 };
2517
2518 cooling-maps {
2519 map0 {
2520 trip = <&sensor3_passive>;
2521 cooling-device = <&a57_0 4 4>;
2522 };
2523 };
2394 }; 2524 };
2395 }; 2525 };
2396 2526
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index c5192d513d7d..556eb8e45499 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -71,6 +71,9 @@
71 power-domains = <&sysc R8A7796_PD_CA57_CPU0>; 71 power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
72 next-level-cache = <&L2_CA57>; 72 next-level-cache = <&L2_CA57>;
73 enable-method = "psci"; 73 enable-method = "psci";
74 clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
75 operating-points-v2 = <&cluster0_opp>;
76 #cooling-cells = <2>;
74 }; 77 };
75 78
76 a57_1: cpu@1 { 79 a57_1: cpu@1 {
@@ -80,6 +83,9 @@
80 power-domains = <&sysc R8A7796_PD_CA57_CPU1>; 83 power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
81 next-level-cache = <&L2_CA57>; 84 next-level-cache = <&L2_CA57>;
82 enable-method = "psci"; 85 enable-method = "psci";
86 clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
87 operating-points-v2 = <&cluster0_opp>;
88 #cooling-cells = <2>;
83 }; 89 };
84 90
85 a53_0: cpu@100 { 91 a53_0: cpu@100 {
@@ -89,6 +95,8 @@
89 power-domains = <&sysc R8A7796_PD_CA53_CPU0>; 95 power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
90 next-level-cache = <&L2_CA53>; 96 next-level-cache = <&L2_CA53>;
91 enable-method = "psci"; 97 enable-method = "psci";
98 clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
99 operating-points-v2 = <&cluster1_opp>;
92 }; 100 };
93 101
94 a53_1: cpu@101 { 102 a53_1: cpu@101 {
@@ -98,6 +106,8 @@
98 power-domains = <&sysc R8A7796_PD_CA53_CPU1>; 106 power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
99 next-level-cache = <&L2_CA53>; 107 next-level-cache = <&L2_CA53>;
100 enable-method = "psci"; 108 enable-method = "psci";
109 clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
110 operating-points-v2 = <&cluster1_opp>;
101 }; 111 };
102 112
103 a53_2: cpu@102 { 113 a53_2: cpu@102 {
@@ -107,6 +117,8 @@
107 power-domains = <&sysc R8A7796_PD_CA53_CPU2>; 117 power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
108 next-level-cache = <&L2_CA53>; 118 next-level-cache = <&L2_CA53>;
109 enable-method = "psci"; 119 enable-method = "psci";
120 clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
121 operating-points-v2 = <&cluster1_opp>;
110 }; 122 };
111 123
112 a53_3: cpu@103 { 124 a53_3: cpu@103 {
@@ -116,6 +128,8 @@
116 power-domains = <&sysc R8A7796_PD_CA53_CPU3>; 128 power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
117 next-level-cache = <&L2_CA53>; 129 next-level-cache = <&L2_CA53>;
118 enable-method = "psci"; 130 enable-method = "psci";
131 clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
132 operating-points-v2 = <&cluster1_opp>;
119 }; 133 };
120 134
121 L2_CA57: cache-controller-0 { 135 L2_CA57: cache-controller-0 {
@@ -147,6 +161,72 @@
147 clock-frequency = <0>; 161 clock-frequency = <0>;
148 }; 162 };
149 163
164 cluster0_opp: opp_table0 {
165 compatible = "operating-points-v2";
166 opp-shared;
167
168 opp-500000000 {
169 opp-hz = /bits/ 64 <500000000>;
170 opp-microvolt = <820000>;
171 clock-latency-ns = <300000>;
172 };
173 opp-1000000000 {
174 opp-hz = /bits/ 64 <1000000000>;
175 opp-microvolt = <820000>;
176 clock-latency-ns = <300000>;
177 };
178 opp-1500000000 {
179 opp-hz = /bits/ 64 <1500000000>;
180 opp-microvolt = <820000>;
181 clock-latency-ns = <300000>;
182 };
183 opp-1600000000 {
184 opp-hz = /bits/ 64 <1600000000>;
185 opp-microvolt = <900000>;
186 clock-latency-ns = <300000>;
187 turbo-mode;
188 };
189 opp-1700000000 {
190 opp-hz = /bits/ 64 <1700000000>;
191 opp-microvolt = <900000>;
192 clock-latency-ns = <300000>;
193 turbo-mode;
194 };
195 opp-1800000000 {
196 opp-hz = /bits/ 64 <1800000000>;
197 opp-microvolt = <960000>;
198 clock-latency-ns = <300000>;
199 turbo-mode;
200 };
201 };
202
203 cluster1_opp: opp_table1 {
204 compatible = "operating-points-v2";
205 opp-shared;
206
207 opp-800000000 {
208 opp-hz = /bits/ 64 <800000000>;
209 opp-microvolt = <820000>;
210 clock-latency-ns = <300000>;
211 };
212 opp-1000000000 {
213 opp-hz = /bits/ 64 <1000000000>;
214 opp-microvolt = <820000>;
215 clock-latency-ns = <300000>;
216 };
217 opp-1200000000 {
218 opp-hz = /bits/ 64 <1200000000>;
219 opp-microvolt = <820000>;
220 clock-latency-ns = <300000>;
221 };
222 opp-1300000000 {
223 opp-hz = /bits/ 64 <1300000000>;
224 opp-microvolt = <820000>;
225 clock-latency-ns = <300000>;
226 turbo-mode;
227 };
228 };
229
150 /* External PCIe clock - can be overridden by the board */ 230 /* External PCIe clock - can be overridden by the board */
151 pcie_bus_clk: pcie_bus { 231 pcie_bus_clk: pcie_bus {
152 compatible = "fixed-clock"; 232 compatible = "fixed-clock";
@@ -894,7 +974,7 @@
894 clocks = <&cpg CPG_MOD 812>; 974 clocks = <&cpg CPG_MOD 812>;
895 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 975 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
896 resets = <&cpg 812>; 976 resets = <&cpg 812>;
897 phy-mode = "rgmii-txid"; 977 phy-mode = "rgmii";
898 iommus = <&ipmmu_ds0 16>; 978 iommus = <&ipmmu_ds0 16>;
899 #address-cells = <1>; 979 #address-cells = <1>;
900 #size-cells = <0>; 980 #size-cells = <0>;
@@ -1561,9 +1641,9 @@
1561 1641
1562 tsc: thermal@e6198000 { 1642 tsc: thermal@e6198000 {
1563 compatible = "renesas,r8a7796-thermal"; 1643 compatible = "renesas,r8a7796-thermal";
1564 reg = <0 0xe6198000 0 0x68>, 1644 reg = <0 0xe6198000 0 0x100>,
1565 <0 0xe61a0000 0 0x5c>, 1645 <0 0xe61a0000 0 0x100>,
1566 <0 0xe61a8000 0 0x5c>; 1646 <0 0xe61a8000 0 0x100>;
1567 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 1647 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
1568 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 1648 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
1569 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1649 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
@@ -1839,7 +1919,7 @@
1839 1919
1840 vspd0: vsp@fea20000 { 1920 vspd0: vsp@fea20000 {
1841 compatible = "renesas,vsp2"; 1921 compatible = "renesas,vsp2";
1842 reg = <0 0xfea20000 0 0x4000>; 1922 reg = <0 0xfea20000 0 0x8000>;
1843 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1923 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
1844 clocks = <&cpg CPG_MOD 623>; 1924 clocks = <&cpg CPG_MOD 623>;
1845 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1925 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -1859,7 +1939,7 @@
1859 1939
1860 vspd1: vsp@fea28000 { 1940 vspd1: vsp@fea28000 {
1861 compatible = "renesas,vsp2"; 1941 compatible = "renesas,vsp2";
1862 reg = <0 0xfea28000 0 0x4000>; 1942 reg = <0 0xfea28000 0 0x8000>;
1863 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1943 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
1864 clocks = <&cpg CPG_MOD 622>; 1944 clocks = <&cpg CPG_MOD 622>;
1865 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1945 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -1879,7 +1959,7 @@
1879 1959
1880 vspd2: vsp@fea30000 { 1960 vspd2: vsp@fea30000 {
1881 compatible = "renesas,vsp2"; 1961 compatible = "renesas,vsp2";
1882 reg = <0 0xfea30000 0 0x4000>; 1962 reg = <0 0xfea30000 0 0x8000>;
1883 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 1963 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
1884 clocks = <&cpg CPG_MOD 621>; 1964 clocks = <&cpg CPG_MOD 621>;
1885 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1965 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -1998,12 +2078,24 @@
1998 thermal-sensors = <&tsc 0>; 2078 thermal-sensors = <&tsc 0>;
1999 2079
2000 trips { 2080 trips {
2081 sensor1_passive: sensor1-passive {
2082 temperature = <95000>;
2083 hysteresis = <2000>;
2084 type = "passive";
2085 };
2001 sensor1_crit: sensor1-crit { 2086 sensor1_crit: sensor1-crit {
2002 temperature = <120000>; 2087 temperature = <120000>;
2003 hysteresis = <2000>; 2088 hysteresis = <2000>;
2004 type = "critical"; 2089 type = "critical";
2005 }; 2090 };
2006 }; 2091 };
2092
2093 cooling-maps {
2094 map0 {
2095 trip = <&sensor1_passive>;
2096 cooling-device = <&a57_0 5 5>;
2097 };
2098 };
2007 }; 2099 };
2008 2100
2009 sensor_thermal2: sensor-thermal2 { 2101 sensor_thermal2: sensor-thermal2 {
@@ -2012,12 +2104,24 @@
2012 thermal-sensors = <&tsc 1>; 2104 thermal-sensors = <&tsc 1>;
2013 2105
2014 trips { 2106 trips {
2107 sensor2_passive: sensor2-passive {
2108 temperature = <95000>;
2109 hysteresis = <2000>;
2110 type = "passive";
2111 };
2015 sensor2_crit: sensor2-crit { 2112 sensor2_crit: sensor2-crit {
2016 temperature = <120000>; 2113 temperature = <120000>;
2017 hysteresis = <2000>; 2114 hysteresis = <2000>;
2018 type = "critical"; 2115 type = "critical";
2019 }; 2116 };
2020 }; 2117 };
2118
2119 cooling-maps {
2120 map0 {
2121 trip = <&sensor2_passive>;
2122 cooling-device = <&a57_0 5 5>;
2123 };
2124 };
2021 }; 2125 };
2022 2126
2023 sensor_thermal3: sensor-thermal3 { 2127 sensor_thermal3: sensor-thermal3 {
@@ -2026,12 +2130,24 @@
2026 thermal-sensors = <&tsc 2>; 2130 thermal-sensors = <&tsc 2>;
2027 2131
2028 trips { 2132 trips {
2133 sensor3_passive: sensor3-passive {
2134 temperature = <95000>;
2135 hysteresis = <2000>;
2136 type = "passive";
2137 };
2029 sensor3_crit: sensor3-crit { 2138 sensor3_crit: sensor3-crit {
2030 temperature = <120000>; 2139 temperature = <120000>;
2031 hysteresis = <2000>; 2140 hysteresis = <2000>;
2032 type = "critical"; 2141 type = "critical";
2033 }; 2142 };
2034 }; 2143 };
2144
2145 cooling-maps {
2146 map0 {
2147 trip = <&sensor3_passive>;
2148 cooling-device = <&a57_0 5 5>;
2149 };
2150 };
2035 }; 2151 };
2036 }; 2152 };
2037 2153
diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts
new file mode 100644
index 000000000000..75d890d91df9
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts
@@ -0,0 +1,21 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the Salvator-X board with R-Car M3-N
4 *
5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
6 */
7
8/dts-v1/;
9#include "r8a77965.dtsi"
10#include "salvator-x.dtsi"
11
12/ {
13 model = "Renesas Salvator-X board based on r8a77965";
14 compatible = "renesas,salvator-x", "renesas,r8a77965";
15
16 memory@48000000 {
17 device_type = "memory";
18 /* first 128MB is reserved for secure area. */
19 reg = <0x0 0x48000000 0x0 0x78000000>;
20 };
21};
diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
new file mode 100644
index 000000000000..a83a00deed9e
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
@@ -0,0 +1,21 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the Salvator-X 2nd version board with R-Car M3-N
4 *
5 * Copyright (C) 2017 Renesas Electronics Corp.
6 */
7
8/dts-v1/;
9#include "r8a77965.dtsi"
10#include "salvator-xs.dtsi"
11
12/ {
13 model = "Renesas Salvator-X 2nd version board based on r8a77965";
14 compatible = "renesas,salvator-xs", "renesas,r8a77965";
15
16 memory@48000000 {
17 device_type = "memory";
18 /* first 128MB is reserved for secure area. */
19 reg = <0x0 0x48000000 0x0 0x78000000>;
20 };
21};
diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
new file mode 100644
index 000000000000..f0871fcdd984
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -0,0 +1,878 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a77965 SoC
4 *
5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
6 *
7 * Based on r8a7796.dtsi
8 * Copyright (C) 2016 Renesas Electronics Corp.
9 */
10
11#include <dt-bindings/clock/renesas-cpg-mssr.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13
14#define CPG_AUDIO_CLK_I 10
15
16/ {
17 compatible = "renesas,r8a77965";
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 aliases {
22 i2c7 = &i2c_dvfs;
23 };
24
25 psci {
26 compatible = "arm,psci-1.0", "arm,psci-0.2";
27 method = "smc";
28 };
29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 a57_0: cpu@0 {
35 compatible = "arm,cortex-a57", "arm,armv8";
36 reg = <0x0>;
37 device_type = "cpu";
38 power-domains = <&sysc 0>;
39 next-level-cache = <&L2_CA57>;
40 enable-method = "psci";
41 };
42
43 a57_1: cpu@1 {
44 compatible = "arm,cortex-a57","arm,armv8";
45 reg = <0x1>;
46 device_type = "cpu";
47 power-domains = <&sysc 1>;
48 next-level-cache = <&L2_CA57>;
49 enable-method = "psci";
50 };
51
52 L2_CA57: cache-controller-0 {
53 compatible = "cache";
54 power-domains = <&sysc 12>;
55 cache-unified;
56 cache-level = <2>;
57 };
58 };
59
60 extal_clk: extal {
61 compatible = "fixed-clock";
62 #clock-cells = <0>;
63 /* This value must be overridden by the board */
64 clock-frequency = <0>;
65 };
66
67 extalr_clk: extalr {
68 compatible = "fixed-clock";
69 #clock-cells = <0>;
70 /* This value must be overridden by the board */
71 clock-frequency = <0>;
72 };
73
74 /*
75 * The external audio clocks are configured as 0 Hz fixed frequency
76 * clocks by default.
77 * Boards that provide audio clocks should override them.
78 */
79 audio_clk_a: audio_clk_a {
80 compatible = "fixed-clock";
81 #clock-cells = <0>;
82 clock-frequency = <0>;
83 };
84
85 audio_clk_b: audio_clk_b {
86 compatible = "fixed-clock";
87 #clock-cells = <0>;
88 clock-frequency = <0>;
89 };
90
91 audio_clk_c: audio_clk_c {
92 compatible = "fixed-clock";
93 #clock-cells = <0>;
94 clock-frequency = <0>;
95 };
96
97 /* External CAN clock - to be overridden by boards that provide it */
98 can_clk: can {
99 compatible = "fixed-clock";
100 #clock-cells = <0>;
101 clock-frequency = <0>;
102 };
103
104 /* External SCIF clock - to be overridden by boards that provide it */
105 scif_clk: scif {
106 compatible = "fixed-clock";
107 #clock-cells = <0>;
108 clock-frequency = <0>;
109 };
110
111 /* External PCIe clock - can be overridden by the board */
112 pcie_bus_clk: pcie_bus {
113 compatible = "fixed-clock";
114 #clock-cells = <0>;
115 clock-frequency = <0>;
116 };
117
118 /* External USB clocks - can be overridden by the board */
119 usb3s0_clk: usb3s0 {
120 compatible = "fixed-clock";
121 #clock-cells = <0>;
122 clock-frequency = <0>;
123 };
124
125 usb_extal_clk: usb_extal {
126 compatible = "fixed-clock";
127 #clock-cells = <0>;
128 clock-frequency = <0>;
129 };
130
131 timer {
132 compatible = "arm,armv8-timer";
133 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
134 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
135 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
136 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
137 };
138
139 pmu_a57 {
140 compatible = "arm,cortex-a57-pmu";
141 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
142 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
143 interrupt-affinity = <&a57_0>,
144 <&a57_1>;
145 };
146
147 soc {
148 compatible = "simple-bus";
149 interrupt-parent = <&gic>;
150 #address-cells = <2>;
151 #size-cells = <2>;
152 ranges;
153
154 gic: interrupt-controller@f1010000 {
155 compatible = "arm,gic-400";
156 #interrupt-cells = <3>;
157 #address-cells = <0>;
158 interrupt-controller;
159 reg = <0x0 0xf1010000 0 0x1000>,
160 <0x0 0xf1020000 0 0x20000>,
161 <0x0 0xf1040000 0 0x20000>,
162 <0x0 0xf1060000 0 0x20000>;
163 interrupts = <GIC_PPI 9
164 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
165 clocks = <&cpg CPG_MOD 408>;
166 clock-names = "clk";
167 power-domains = <&sysc 32>;
168 resets = <&cpg 408>;
169 };
170
171 pfc: pin-controller@e6060000 {
172 compatible = "renesas,pfc-r8a77965";
173 reg = <0 0xe6060000 0 0x50c>;
174 };
175
176 cpg: clock-controller@e6150000 {
177 compatible = "renesas,r8a77965-cpg-mssr";
178 reg = <0 0xe6150000 0 0x1000>;
179 clocks = <&extal_clk>, <&extalr_clk>;
180 clock-names = "extal", "extalr";
181 #clock-cells = <2>;
182 #power-domain-cells = <0>;
183 #reset-cells = <1>;
184 };
185
186 rst: reset-controller@e6160000 {
187 compatible = "renesas,r8a77965-rst";
188 reg = <0 0xe6160000 0 0x0200>;
189 };
190
191 prr: chipid@fff00044 {
192 compatible = "renesas,prr";
193 reg = <0 0xfff00044 0 4>;
194 };
195
196 sysc: system-controller@e6180000 {
197 compatible = "renesas,r8a77965-sysc";
198 reg = <0 0xe6180000 0 0x0400>;
199 #power-domain-cells = <1>;
200 };
201
202 gpio0: gpio@e6050000 {
203 compatible = "renesas,gpio-r8a77965",
204 "renesas,rcar-gen3-gpio";
205 reg = <0 0xe6050000 0 0x50>;
206 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
207 #gpio-cells = <2>;
208 gpio-controller;
209 gpio-ranges = <&pfc 0 0 16>;
210 #interrupt-cells = <2>;
211 interrupt-controller;
212 clocks = <&cpg CPG_MOD 912>;
213 power-domains = <&sysc 32>;
214 resets = <&cpg 912>;
215 };
216
217 gpio1: gpio@e6051000 {
218 compatible = "renesas,gpio-r8a77965",
219 "renesas,rcar-gen3-gpio";
220 reg = <0 0xe6051000 0 0x50>;
221 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
222 #gpio-cells = <2>;
223 gpio-controller;
224 gpio-ranges = <&pfc 0 32 29>;
225 #interrupt-cells = <2>;
226 interrupt-controller;
227 clocks = <&cpg CPG_MOD 911>;
228 power-domains = <&sysc 32>;
229 resets = <&cpg 911>;
230 };
231
232 gpio2: gpio@e6052000 {
233 compatible = "renesas,gpio-r8a77965",
234 "renesas,rcar-gen3-gpio";
235 reg = <0 0xe6052000 0 0x50>;
236 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
237 #gpio-cells = <2>;
238 gpio-controller;
239 gpio-ranges = <&pfc 0 64 15>;
240 #interrupt-cells = <2>;
241 interrupt-controller;
242 clocks = <&cpg CPG_MOD 910>;
243 power-domains = <&sysc 32>;
244 resets = <&cpg 910>;
245 };
246
247 gpio3: gpio@e6053000 {
248 compatible = "renesas,gpio-r8a77965",
249 "renesas,rcar-gen3-gpio";
250 reg = <0 0xe6053000 0 0x50>;
251 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
252 #gpio-cells = <2>;
253 gpio-controller;
254 gpio-ranges = <&pfc 0 96 16>;
255 #interrupt-cells = <2>;
256 interrupt-controller;
257 clocks = <&cpg CPG_MOD 909>;
258 power-domains = <&sysc 32>;
259 resets = <&cpg 909>;
260 };
261
262 gpio4: gpio@e6054000 {
263 compatible = "renesas,gpio-r8a77965",
264 "renesas,rcar-gen3-gpio";
265 reg = <0 0xe6054000 0 0x50>;
266 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
267 #gpio-cells = <2>;
268 gpio-controller;
269 gpio-ranges = <&pfc 0 128 18>;
270 #interrupt-cells = <2>;
271 interrupt-controller;
272 clocks = <&cpg CPG_MOD 908>;
273 power-domains = <&sysc 32>;
274 resets = <&cpg 908>;
275 };
276
277 gpio5: gpio@e6055000 {
278 compatible = "renesas,gpio-r8a77965",
279 "renesas,rcar-gen3-gpio";
280 reg = <0 0xe6055000 0 0x50>;
281 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
282 #gpio-cells = <2>;
283 gpio-controller;
284 gpio-ranges = <&pfc 0 160 26>;
285 #interrupt-cells = <2>;
286 interrupt-controller;
287 clocks = <&cpg CPG_MOD 907>;
288 power-domains = <&sysc 32>;
289 resets = <&cpg 907>;
290 };
291
292 gpio6: gpio@e6055400 {
293 compatible = "renesas,gpio-r8a77965",
294 "renesas,rcar-gen3-gpio";
295 reg = <0 0xe6055400 0 0x50>;
296 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
297 #gpio-cells = <2>;
298 gpio-controller;
299 gpio-ranges = <&pfc 0 192 32>;
300 #interrupt-cells = <2>;
301 interrupt-controller;
302 clocks = <&cpg CPG_MOD 906>;
303 power-domains = <&sysc 32>;
304 resets = <&cpg 906>;
305 };
306
307 gpio7: gpio@e6055800 {
308 compatible = "renesas,gpio-r8a77965",
309 "renesas,rcar-gen3-gpio";
310 reg = <0 0xe6055800 0 0x50>;
311 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
312 #gpio-cells = <2>;
313 gpio-controller;
314 gpio-ranges = <&pfc 0 224 4>;
315 #interrupt-cells = <2>;
316 interrupt-controller;
317 clocks = <&cpg CPG_MOD 905>;
318 power-domains = <&sysc 32>;
319 resets = <&cpg 905>;
320 };
321
322 intc_ex: interrupt-controller@e61c0000 {
323 compatible = "renesas,intc-ex-r8a77965", "renesas,irqc";
324 #interrupt-cells = <2>;
325 interrupt-controller;
326 reg = <0 0xe61c0000 0 0x200>;
327 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
328 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
329 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
330 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
331 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
332 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&cpg CPG_MOD 407>;
334 power-domains = <&sysc 32>;
335 resets = <&cpg 407>;
336 };
337
338 dmac0: dma-controller@e6700000 {
339 compatible = "renesas,dmac-r8a77965",
340 "renesas,rcar-dmac";
341 reg = <0 0xe6700000 0 0x10000>;
342 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
343 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
344 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
345 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
346 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
347 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
348 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
349 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
350 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
351 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
352 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
353 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
354 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
355 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
356 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
357 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
358 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
359 interrupt-names = "error",
360 "ch0", "ch1", "ch2", "ch3",
361 "ch4", "ch5", "ch6", "ch7",
362 "ch8", "ch9", "ch10", "ch11",
363 "ch12", "ch13", "ch14", "ch15";
364 clocks = <&cpg CPG_MOD 219>;
365 clock-names = "fck";
366 power-domains = <&sysc 32>;
367 resets = <&cpg 219>;
368 #dma-cells = <1>;
369 dma-channels = <16>;
370 };
371
372 dmac1: dma-controller@e7300000 {
373 compatible = "renesas,dmac-r8a77965",
374 "renesas,rcar-dmac";
375 reg = <0 0xe7300000 0 0x10000>;
376 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
377 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
378 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
379 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
380 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
381 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
382 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
383 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
384 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
385 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
386 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
387 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
388 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
389 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
390 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
391 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
392 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
393 interrupt-names = "error",
394 "ch0", "ch1", "ch2", "ch3",
395 "ch4", "ch5", "ch6", "ch7",
396 "ch8", "ch9", "ch10", "ch11",
397 "ch12", "ch13", "ch14", "ch15";
398 clocks = <&cpg CPG_MOD 218>;
399 clock-names = "fck";
400 power-domains = <&sysc 32>;
401 resets = <&cpg 218>;
402 #dma-cells = <1>;
403 dma-channels = <16>;
404 };
405
406 dmac2: dma-controller@e7310000 {
407 compatible = "renesas,dmac-r8a77965",
408 "renesas,rcar-dmac";
409 reg = <0 0xe7310000 0 0x10000>;
410 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
411 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
412 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
413 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
414 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
415 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
416 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
417 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
418 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
419 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
420 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
421 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
422 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
423 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
424 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
425 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
426 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
427 interrupt-names = "error",
428 "ch0", "ch1", "ch2", "ch3",
429 "ch4", "ch5", "ch6", "ch7",
430 "ch8", "ch9", "ch10", "ch11",
431 "ch12", "ch13", "ch14", "ch15";
432 clocks = <&cpg CPG_MOD 217>;
433 clock-names = "fck";
434 power-domains = <&sysc 32>;
435 resets = <&cpg 217>;
436 #dma-cells = <1>;
437 dma-channels = <16>;
438 };
439
440 scif0: serial@e6e60000 {
441 compatible = "renesas,scif-r8a77965",
442 "renesas,rcar-gen3-scif", "renesas,scif";
443 reg = <0 0xe6e60000 0 64>;
444 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&cpg CPG_MOD 207>,
446 <&cpg CPG_CORE 20>,
447 <&scif_clk>;
448 clock-names = "fck", "brg_int", "scif_clk";
449 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
450 <&dmac2 0x51>, <&dmac2 0x50>;
451 dma-names = "tx", "rx", "tx", "rx";
452 power-domains = <&sysc 32>;
453 resets = <&cpg 207>;
454 status = "disabled";
455 };
456
457 scif1: serial@e6e68000 {
458 compatible = "renesas,scif-r8a77965",
459 "renesas,rcar-gen3-scif", "renesas,scif";
460 reg = <0 0xe6e68000 0 64>;
461 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&cpg CPG_MOD 206>,
463 <&cpg CPG_CORE 20>,
464 <&scif_clk>;
465 clock-names = "fck", "brg_int", "scif_clk";
466 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
467 <&dmac2 0x53>, <&dmac2 0x52>;
468 dma-names = "tx", "rx", "tx", "rx";
469 power-domains = <&sysc 32>;
470 resets = <&cpg 206>;
471 status = "disabled";
472 };
473
474 scif2: serial@e6e88000 {
475 compatible = "renesas,scif-r8a77965",
476 "renesas,rcar-gen3-scif", "renesas,scif";
477 reg = <0 0xe6e88000 0 64>;
478 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&cpg CPG_MOD 310>,
480 <&cpg CPG_CORE 20>,
481 <&scif_clk>;
482 clock-names = "fck", "brg_int", "scif_clk";
483 power-domains = <&sysc 32>;
484 resets = <&cpg 310>;
485 status = "disabled";
486 };
487
488 scif3: serial@e6c50000 {
489 compatible = "renesas,scif-r8a77965",
490 "renesas,rcar-gen3-scif", "renesas,scif";
491 reg = <0 0xe6c50000 0 64>;
492 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
493 clocks = <&cpg CPG_MOD 204>,
494 <&cpg CPG_CORE 20>,
495 <&scif_clk>;
496 clock-names = "fck", "brg_int", "scif_clk";
497 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
498 dma-names = "tx", "rx";
499 power-domains = <&sysc 32>;
500 resets = <&cpg 204>;
501 status = "disabled";
502 };
503
504 scif4: serial@e6c40000 {
505 compatible = "renesas,scif-r8a77965",
506 "renesas,rcar-gen3-scif", "renesas,scif";
507 reg = <0 0xe6c40000 0 64>;
508 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
509 clocks = <&cpg CPG_MOD 203>,
510 <&cpg CPG_CORE 20>,
511 <&scif_clk>;
512 clock-names = "fck", "brg_int", "scif_clk";
513 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
514 dma-names = "tx", "rx";
515 power-domains = <&sysc 32>;
516 resets = <&cpg 203>;
517 status = "disabled";
518 };
519
520 scif5: serial@e6f30000 {
521 compatible = "renesas,scif-r8a77965",
522 "renesas,rcar-gen3-scif", "renesas,scif";
523 reg = <0 0xe6f30000 0 64>;
524 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&cpg CPG_MOD 202>,
526 <&cpg CPG_CORE 20>,
527 <&scif_clk>;
528 clock-names = "fck", "brg_int", "scif_clk";
529 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
530 <&dmac2 0x5b>, <&dmac2 0x5a>;
531 dma-names = "tx", "rx", "tx", "rx";
532 power-domains = <&sysc 32>;
533 resets = <&cpg 202>;
534 status = "disabled";
535 };
536
537 avb: ethernet@e6800000 {
538 compatible = "renesas,etheravb-r8a77965",
539 "renesas,etheravb-rcar-gen3";
540 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
541 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
542 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
543 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
544 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
545 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
546 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
547 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
548 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
549 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
550 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
551 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
552 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
553 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
554 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
555 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
556 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
558 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
559 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
560 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
564 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
566 interrupt-names = "ch0", "ch1", "ch2", "ch3",
567 "ch4", "ch5", "ch6", "ch7",
568 "ch8", "ch9", "ch10", "ch11",
569 "ch12", "ch13", "ch14", "ch15",
570 "ch16", "ch17", "ch18", "ch19",
571 "ch20", "ch21", "ch22", "ch23",
572 "ch24";
573 clocks = <&cpg CPG_MOD 812>;
574 power-domains = <&sysc 32>;
575 resets = <&cpg 812>;
576 phy-mode = "rgmii";
577 #address-cells = <1>;
578 #size-cells = <0>;
579 status = "disabled";
580 };
581
582 csi20: csi2@fea80000 {
583 reg = <0 0xfea80000 0 0x10000>;
584 /* placeholder */
585
586 ports {
587 #address-cells = <1>;
588 #size-cells = <0>;
589 };
590 };
591
592 csi40: csi2@feaa0000 {
593 reg = <0 0xfeaa0000 0 0x10000>;
594 /* placeholder */
595
596 ports {
597 #address-cells = <1>;
598 #size-cells = <0>;
599 };
600 };
601
602 vin0: video@e6ef0000 {
603 reg = <0 0xe6ef0000 0 0x1000>;
604 /* placeholder */
605 };
606
607 vin1: video@e6ef1000 {
608 reg = <0 0xe6ef1000 0 0x1000>;
609 /* placeholder */
610 };
611
612 vin2: video@e6ef2000 {
613 reg = <0 0xe6ef2000 0 0x1000>;
614 /* placeholder */
615 };
616
617 vin3: video@e6ef3000 {
618 reg = <0 0xe6ef3000 0 0x1000>;
619 /* placeholder */
620 };
621
622 vin4: video@e6ef4000 {
623 reg = <0 0xe6ef4000 0 0x1000>;
624 /* placeholder */
625 };
626
627 vin5: video@e6ef5000 {
628 reg = <0 0xe6ef5000 0 0x1000>;
629 /* placeholder */
630 };
631
632 vin6: video@e6ef6000 {
633 reg = <0 0xe6ef6000 0 0x1000>;
634 /* placeholder */
635 };
636
637 vin7: video@e6ef7000 {
638 reg = <0 0xe6ef7000 0 0x1000>;
639 /* placeholder */
640 };
641
642 ohci0: usb@ee080000 {
643 reg = <0 0xee080000 0 0x100>;
644 /* placeholder */
645 };
646
647 ehci0: usb@ee080100 {
648 reg = <0 0xee080100 0 0x100>;
649 /* placeholder */
650 };
651
652 usb2_phy0: usb-phy@ee080200 {
653 reg = <0 0xee080200 0 0x700>;
654 /* placeholder */
655 };
656
657 usb2_phy1: usb-phy@ee0a0200 {
658 reg = <0 0xee0a0200 0 0x700>;
659 /* placeholder */
660 };
661
662 ohci1: usb@ee0a0000 {
663 reg = <0 0xee0a0000 0 0x100>;
664 /* placeholder */
665 };
666
667 ehci1: usb@ee0a0100 {
668 reg = <0 0xee0a0100 0 0x100>;
669 /* placeholder */
670 };
671
672 i2c0: i2c@e6500000 {
673 reg = <0 0xe6500000 0 0x40>;
674 /* placeholder */
675 };
676
677 i2c1: i2c@e6508000 {
678 reg = <0 0xe6508000 0 0x40>;
679 /* placeholder */
680 };
681
682 i2c2: i2c@e6510000 {
683 #address-cells = <1>;
684 #size-cells = <0>;
685
686 reg = <0 0xe6510000 0 0x40>;
687 /* placeholder */
688 };
689
690 i2c3: i2c@e66d0000 {
691 reg = <0 0xe66d0000 0 0x40>;
692 /* placeholder */
693 };
694
695 i2c4: i2c@e66d8000 {
696 #address-cells = <1>;
697 #size-cells = <0>;
698
699 reg = <0 0xe66d8000 0 0x40>;
700 /* placeholder */
701 };
702
703 i2c5: i2c@e66e0000 {
704 reg = <0 0xe66e0000 0 0x40>;
705 /* placeholder */
706 };
707
708 i2c6: i2c@e66e8000 {
709 reg = <0 0xe66e8000 0 0x40>;
710 /* placeholder */
711 };
712
713 i2c_dvfs: i2c@e60b0000 {
714 #address-cells = <1>;
715 #size-cells = <0>;
716 compatible = "renesas,iic-r8a77965",
717 "renesas,rcar-gen3-iic",
718 "renesas,rmobile-iic";
719 reg = <0 0xe60b0000 0 0x425>;
720 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&cpg CPG_MOD 926>;
722 power-domains = <&sysc 32>;
723 resets = <&cpg 926>;
724 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
725 dma-names = "tx", "rx";
726 status = "disabled";
727 };
728
729 pwm0: pwm@e6e30000 {
730 reg = <0 0xe6e30000 0 8>;
731 /* placeholder */
732 };
733
734 pwm1: pwm@e6e31000 {
735 reg = <0 0xe6e31000 0 8>;
736 #pwm-cells = <2>;
737 /* placeholder */
738 };
739
740 pwm2: pwm@e6e32000 {
741 reg = <0 0xe6e32000 0 8>;
742 /* placeholder */
743 };
744
745 pwm3: pwm@e6e33000 {
746 reg = <0 0xe6e33000 0 8>;
747 /* placeholder */
748 };
749
750 pwm4: pwm@e6e34000 {
751 reg = <0 0xe6e34000 0 8>;
752 /* placeholder */
753 };
754
755 pwm5: pwm@e6e35000 {
756 reg = <0 0xe6e35000 0 8>;
757 /* placeholder */
758 };
759
760 pwm6: pwm@e6e36000 {
761 reg = <0 0xe6e36000 0 8>;
762 /* placeholder */
763 };
764
765 du: display@feb00000 {
766 reg = <0 0xfeb00000 0 0x80000>,
767 <0 0xfeb90000 0 0x14>;
768 /* placeholder */
769
770 ports {
771 #address-cells = <1>;
772 #size-cells = <0>;
773
774 port@0 {
775 reg = <0>;
776 du_out_rgb: endpoint {
777 };
778 };
779 port@1 {
780 reg = <1>;
781 du_out_hdmi0: endpoint {
782 };
783 };
784 port@2 {
785 reg = <2>;
786 du_out_lvds0: endpoint {
787 };
788 };
789 };
790 };
791
792 hsusb: usb@e6590000 {
793 reg = <0 0xe6590000 0 0x100>;
794 /* placeholder */
795 };
796
797 pciec0: pcie@fe000000 {
798 reg = <0 0xfe000000 0 0x80000>;
799 /* placeholder */
800 };
801
802 pciec1: pcie@ee800000 {
803 reg = <0 0xee800000 0 0x80000>;
804 /* placeholder */
805 };
806
807 rcar_sound: sound@ec500000 {
808 reg = <0 0xec500000 0 0x1000>, /* SCU */
809 <0 0xec5a0000 0 0x100>, /* ADG */
810 <0 0xec540000 0 0x1000>, /* SSIU */
811 <0 0xec541000 0 0x280>, /* SSI */
812 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
813 /* placeholder */
814
815 rcar_sound,dvc {
816 dvc0: dvc-0 {
817 };
818 dvc1: dvc-1 {
819 };
820 };
821
822 rcar_sound,src {
823 src0: src-0 {
824 };
825 src1: src-1 {
826 };
827 };
828
829 rcar_sound,ssi {
830 ssi0: ssi-0 {
831 };
832 ssi1: ssi-1 {
833 };
834 };
835 };
836
837 sdhi0: sd@ee100000 {
838 reg = <0 0xee100000 0 0x2000>;
839 /* placeholder */
840 };
841
842 sdhi1: sd@ee120000 {
843 reg = <0 0xee120000 0 0x2000>;
844 /* placeholder */
845 };
846
847 sdhi2: sd@ee140000 {
848 reg = <0 0xee140000 0 0x2000>;
849 /* placeholder */
850 };
851
852 sdhi3: sd@ee160000 {
853 reg = <0 0xee160000 0 0x2000>;
854 /* placeholder */
855 };
856
857 usb3_phy0: usb-phy@e65ee000 {
858 reg = <0 0xe65ee000 0 0x90>;
859 #phy-cells = <0>;
860 /* placeholder */
861 };
862
863 usb3_peri0: usb@ee020000 {
864 reg = <0 0xee020000 0 0x400>;
865 /* placeholder */
866 };
867
868 xhci0: usb@ee000000 {
869 reg = <0 0xee000000 0 0xc00>;
870 /* placeholder */
871 };
872
873 wdt0: watchdog@e6020000 {
874 reg = <0 0xe6020000 0 0x0c>;
875 /* placeholder */
876 };
877 };
878};
diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
index 8fe5c193e049..3c5f598c9766 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
@@ -36,11 +36,14 @@
36&avb { 36&avb {
37 renesas,no-ether-link; 37 renesas,no-ether-link;
38 phy-handle = <&phy0>; 38 phy-handle = <&phy0>;
39 phy-mode = "rgmii-id";
39 status = "okay"; 40 status = "okay";
40 41
41 phy0: ethernet-phy@0 { 42 phy0: ethernet-phy@0 {
42 rxc-skew-ps = <1500>; 43 rxc-skew-ps = <1500>;
43 reg = <0>; 44 reg = <0>;
45 interrupt-parent = <&gpio1>;
46 interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
44 }; 47 };
45}; 48};
46 49
@@ -52,11 +55,41 @@
52 clock-frequency = <32768>; 55 clock-frequency = <32768>;
53}; 56};
54 57
58&i2c0 {
59 pinctrl-0 = <&i2c0_pins>;
60 pinctrl-names = "default";
61
62 status = "okay";
63 clock-frequency = <400000>;
64
65 io_expander: gpio@20 {
66 compatible = "onnn,pca9654";
67 reg = <0x20>;
68 gpio-controller;
69 #gpio-cells = <2>;
70 };
71};
72
73&pfc {
74 i2c0_pins: i2c0 {
75 groups = "i2c0";
76 function = "i2c0";
77 };
78
79 scif0_pins: scif0 {
80 groups = "scif0_data";
81 function = "scif0";
82 };
83};
84
55&rwdt { 85&rwdt {
56 timeout-sec = <60>; 86 timeout-sec = <60>;
57 status = "okay"; 87 status = "okay";
58}; 88};
59 89
60&scif0 { 90&scif0 {
91 pinctrl-0 = <&scif0_pins>;
92 pinctrl-names = "default";
93
61 status = "okay"; 94 status = "okay";
62}; 95};
diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
index 8624ca87d6b2..a8ceeac77992 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
@@ -34,6 +34,7 @@
34&avb { 34&avb {
35 renesas,no-ether-link; 35 renesas,no-ether-link;
36 phy-handle = <&phy0>; 36 phy-handle = <&phy0>;
37 phy-mode = "rgmii-id";
37 status = "okay"; 38 status = "okay";
38 39
39 phy0: ethernet-phy@0 { 40 phy0: ethernet-phy@0 {
@@ -50,6 +51,16 @@
50 clock-frequency = <32768>; 51 clock-frequency = <32768>;
51}; 52};
52 53
54&pfc {
55 scif0_pins: scif0 {
56 groups = "scif0_data";
57 function = "scif0";
58 };
59};
60
53&scif0 { 61&scif0 {
62 pinctrl-0 = <&scif0_pins>;
63 pinctrl-names = "default";
64
54 status = "okay"; 65 status = "okay";
55}; 66};
diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
index c35a117fc447..c6db8ea43906 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -19,9 +19,12 @@
19 #address-cells = <2>; 19 #address-cells = <2>;
20 #size-cells = <2>; 20 #size-cells = <2>;
21 21
22 psci { 22 aliases {
23 compatible = "arm,psci-1.0", "arm,psci-0.2"; 23 i2c0 = &i2c0;
24 method = "smc"; 24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 i2c3 = &i2c3;
27 i2c4 = &i2c4;
25 }; 28 };
26 29
27 cpus { 30 cpus {
@@ -60,6 +63,11 @@
60 clock-frequency = <0>; 63 clock-frequency = <0>;
61 }; 64 };
62 65
66 psci {
67 compatible = "arm,psci-1.0", "arm,psci-0.2";
68 method = "smc";
69 };
70
63 /* External SCIF clock - to be overridden by boards that provide it */ 71 /* External SCIF clock - to be overridden by boards that provide it */
64 scif_clk: scif { 72 scif_clk: scif {
65 compatible = "fixed-clock"; 73 compatible = "fixed-clock";
@@ -92,18 +100,6 @@
92 resets = <&cpg 408>; 100 resets = <&cpg 408>;
93 }; 101 };
94 102
95 timer {
96 compatible = "arm,armv8-timer";
97 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
98 IRQ_TYPE_LEVEL_LOW)>,
99 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
100 IRQ_TYPE_LEVEL_LOW)>,
101 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
102 IRQ_TYPE_LEVEL_LOW)>,
103 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
104 IRQ_TYPE_LEVEL_LOW)>;
105 };
106
107 rwdt: watchdog@e6020000 { 103 rwdt: watchdog@e6020000 {
108 compatible = "renesas,r8a77970-wdt", 104 compatible = "renesas,r8a77970-wdt",
109 "renesas,rcar-gen3-wdt"; 105 "renesas,rcar-gen3-wdt";
@@ -178,6 +174,101 @@
178 #iommu-cells = <1>; 174 #iommu-cells = <1>;
179 }; 175 };
180 176
177 pfc: pin-controller@e6060000 {
178 compatible = "renesas,pfc-r8a77970";
179 reg = <0 0xe6060000 0 0x504>;
180 };
181
182 gpio0: gpio@e6050000 {
183 compatible = "renesas,gpio-r8a77970",
184 "renesas,rcar-gen3-gpio";
185 reg = <0 0xe6050000 0 0x50>;
186 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
187 #gpio-cells = <2>;
188 gpio-controller;
189 gpio-ranges = <&pfc 0 0 22>;
190 #interrupt-cells = <2>;
191 interrupt-controller;
192 clocks = <&cpg CPG_MOD 912>;
193 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
194 resets = <&cpg 912>;
195 };
196
197 gpio1: gpio@e6051000 {
198 compatible = "renesas,gpio-r8a77970",
199 "renesas,rcar-gen3-gpio";
200 reg = <0 0xe6051000 0 0x50>;
201 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
202 #gpio-cells = <2>;
203 gpio-controller;
204 gpio-ranges = <&pfc 0 32 28>;
205 #interrupt-cells = <2>;
206 interrupt-controller;
207 clocks = <&cpg CPG_MOD 911>;
208 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
209 resets = <&cpg 911>;
210 };
211
212 gpio2: gpio@e6052000 {
213 compatible = "renesas,gpio-r8a77970",
214 "renesas,rcar-gen3-gpio";
215 reg = <0 0xe6052000 0 0x50>;
216 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
217 #gpio-cells = <2>;
218 gpio-controller;
219 gpio-ranges = <&pfc 0 64 17>;
220 #interrupt-cells = <2>;
221 interrupt-controller;
222 clocks = <&cpg CPG_MOD 910>;
223 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
224 resets = <&cpg 910>;
225 };
226
227 gpio3: gpio@e6053000 {
228 compatible = "renesas,gpio-r8a77970",
229 "renesas,rcar-gen3-gpio";
230 reg = <0 0xe6053000 0 0x50>;
231 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
232 #gpio-cells = <2>;
233 gpio-controller;
234 gpio-ranges = <&pfc 0 96 17>;
235 #interrupt-cells = <2>;
236 interrupt-controller;
237 clocks = <&cpg CPG_MOD 909>;
238 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
239 resets = <&cpg 909>;
240 };
241
242 gpio4: gpio@e6054000 {
243 compatible = "renesas,gpio-r8a77970",
244 "renesas,rcar-gen3-gpio";
245 reg = <0 0xe6054000 0 0x50>;
246 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
247 #gpio-cells = <2>;
248 gpio-controller;
249 gpio-ranges = <&pfc 0 128 6>;
250 #interrupt-cells = <2>;
251 interrupt-controller;
252 clocks = <&cpg CPG_MOD 908>;
253 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
254 resets = <&cpg 908>;
255 };
256
257 gpio5: gpio@e6055000 {
258 compatible = "renesas,gpio-r8a77970",
259 "renesas,rcar-gen3-gpio";
260 reg = <0 0xe6055000 0 0x50>;
261 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
262 #gpio-cells = <2>;
263 gpio-controller;
264 gpio-ranges = <&pfc 0 160 15>;
265 #interrupt-cells = <2>;
266 interrupt-controller;
267 clocks = <&cpg CPG_MOD 907>;
268 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
269 resets = <&cpg 907>;
270 };
271
181 intc_ex: interrupt-controller@e61c0000 { 272 intc_ex: interrupt-controller@e61c0000 {
182 compatible = "renesas,intc-ex-r8a77970", "renesas,irqc"; 273 compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
183 #interrupt-cells = <2>; 274 #interrupt-cells = <2>;
@@ -255,6 +346,91 @@
255 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; 346 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
256 }; 347 };
257 348
349 i2c0: i2c@e6500000 {
350 compatible = "renesas,i2c-r8a77970",
351 "renesas,rcar-gen3-i2c";
352 reg = <0 0xe6500000 0 0x40>;
353 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&cpg CPG_MOD 931>;
355 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
356 resets = <&cpg 931>;
357 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
358 <&dmac2 0x91>, <&dmac2 0x90>;
359 dma-names = "tx", "rx", "tx", "rx";
360 i2c-scl-internal-delay-ns = <6>;
361 #address-cells = <1>;
362 #size-cells = <0>;
363 status = "disabled";
364 };
365
366 i2c1: i2c@e6508000 {
367 compatible = "renesas,i2c-r8a77970",
368 "renesas,rcar-gen3-i2c";
369 reg = <0 0xe6508000 0 0x40>;
370 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&cpg CPG_MOD 930>;
372 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
373 resets = <&cpg 930>;
374 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
375 <&dmac2 0x93>, <&dmac2 0x92>;
376 dma-names = "tx", "rx", "tx", "rx";
377 i2c-scl-internal-delay-ns = <6>;
378 #address-cells = <1>;
379 #size-cells = <0>;
380 status = "disabled";
381 };
382
383 i2c2: i2c@e6510000 {
384 compatible = "renesas,i2c-r8a77970",
385 "renesas,rcar-gen3-i2c";
386 reg = <0 0xe6510000 0 0x40>;
387 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&cpg CPG_MOD 929>;
389 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
390 resets = <&cpg 929>;
391 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
392 <&dmac2 0x95>, <&dmac2 0x94>;
393 dma-names = "tx", "rx", "tx", "rx";
394 i2c-scl-internal-delay-ns = <6>;
395 #address-cells = <1>;
396 #size-cells = <0>;
397 status = "disabled";
398 };
399
400 i2c3: i2c@e66d0000 {
401 compatible = "renesas,i2c-r8a77970",
402 "renesas,rcar-gen3-i2c";
403 reg = <0 0xe66d0000 0 0x40>;
404 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&cpg CPG_MOD 928>;
406 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
407 resets = <&cpg 928>;
408 dmas = <&dmac1 0x97>, <&dmac1 0x96>,
409 <&dmac2 0x97>, <&dmac2 0x96>;
410 dma-names = "tx", "rx", "tx", "rx";
411 i2c-scl-internal-delay-ns = <6>;
412 #address-cells = <1>;
413 #size-cells = <0>;
414 status = "disabled";
415 };
416
417 i2c4: i2c@e66d8000 {
418 compatible = "renesas,i2c-r8a77970",
419 "renesas,rcar-gen3-i2c";
420 reg = <0 0xe66d8000 0 0x40>;
421 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&cpg CPG_MOD 927>;
423 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
424 resets = <&cpg 927>;
425 dmas = <&dmac1 0x99>, <&dmac1 0x98>,
426 <&dmac2 0x99>, <&dmac2 0x98>;
427 dma-names = "tx", "rx", "tx", "rx";
428 i2c-scl-internal-delay-ns = <6>;
429 #address-cells = <1>;
430 #size-cells = <0>;
431 status = "disabled";
432 };
433
258 hscif0: serial@e6540000 { 434 hscif0: serial@e6540000 {
259 compatible = "renesas,hscif-r8a77970", 435 compatible = "renesas,hscif-r8a77970",
260 "renesas,rcar-gen3-hscif", 436 "renesas,rcar-gen3-hscif",
@@ -400,7 +576,7 @@
400 avb: ethernet@e6800000 { 576 avb: ethernet@e6800000 {
401 compatible = "renesas,etheravb-r8a77970", 577 compatible = "renesas,etheravb-r8a77970",
402 "renesas,etheravb-rcar-gen3"; 578 "renesas,etheravb-rcar-gen3";
403 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; 579 reg = <0 0xe6800000 0 0x800>;
404 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 580 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
@@ -436,10 +612,18 @@
436 clocks = <&cpg CPG_MOD 812>; 612 clocks = <&cpg CPG_MOD 812>;
437 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 613 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
438 resets = <&cpg 812>; 614 resets = <&cpg 812>;
439 phy-mode = "rgmii-id"; 615 phy-mode = "rgmii";
440 iommus = <&ipmmu_rt 3>; 616 iommus = <&ipmmu_rt 3>;
441 #address-cells = <1>; 617 #address-cells = <1>;
442 #size-cells = <0>; 618 #size-cells = <0>;
443 }; 619 };
444 }; 620 };
621
622 timer {
623 compatible = "arm,armv8-timer";
624 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
625 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
626 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
627 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
628 };
445}; 629};
diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
new file mode 100644
index 000000000000..06cf6845765a
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -0,0 +1,58 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the Condor board
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 */
8
9/dts-v1/;
10#include "r8a77980.dtsi"
11
12/ {
13 model = "Renesas Condor board based on r8a77980";
14 compatible = "renesas,condor", "renesas,r8a77980";
15
16 aliases {
17 serial0 = &scif0;
18 ethernet0 = &avb;
19 };
20
21 chosen {
22 stdout-path = "serial0:115200n8";
23 };
24
25 memory@48000000 {
26 device_type = "memory";
27 /* first 128MB is reserved for secure area. */
28 reg = <0 0x48000000 0 0x78000000>;
29 };
30};
31
32&avb {
33 phy-mode = "rgmii-id";
34 phy-handle = <&phy0>;
35 renesas,no-ether-link;
36 status = "okay";
37
38 phy0: ethernet-phy@0 {
39 rxc-skew-ps = <1500>;
40 reg = <0>;
41 };
42};
43
44&extal_clk {
45 clock-frequency = <16666666>;
46};
47
48&extalr_clk {
49 clock-frequency = <32768>;
50};
51
52&scif0 {
53 status = "okay";
54};
55
56&scif_clk {
57 clock-frequency = <14745600>;
58};
diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
new file mode 100644
index 000000000000..03845fd74996
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -0,0 +1,385 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a77980 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 */
8
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/clock/renesas-cpg-mssr.h>
12
13/ {
14 compatible = "renesas,r8a77980";
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 a53_0: cpu@0 {
23 device_type = "cpu";
24 compatible = "arm,cortex-a53", "arm,armv8";
25 reg = <0>;
26 clocks = <&cpg CPG_CORE 0>;
27 power-domains = <&sysc 5>;
28 next-level-cache = <&L2_CA53>;
29 enable-method = "psci";
30 };
31
32 L2_CA53: cache-controller {
33 compatible = "cache";
34 power-domains = <&sysc 21>;
35 cache-unified;
36 cache-level = <2>;
37 };
38 };
39
40 extal_clk: extal {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 /* This value must be overridden by the board */
44 clock-frequency = <0>;
45 };
46
47 extalr_clk: extalr {
48 compatible = "fixed-clock";
49 #clock-cells = <0>;
50 /* This value must be overridden by the board */
51 clock-frequency = <0>;
52 };
53
54 psci {
55 compatible = "arm,psci-1.0", "arm,psci-0.2";
56 method = "smc";
57 };
58
59 /* External SCIF clock - to be overridden by boards that provide it */
60 scif_clk: scif {
61 compatible = "fixed-clock";
62 #clock-cells = <0>;
63 clock-frequency = <0>;
64 };
65
66 soc {
67 compatible = "simple-bus";
68 interrupt-parent = <&gic>;
69
70 #address-cells = <2>;
71 #size-cells = <2>;
72 ranges;
73
74 cpg: clock-controller@e6150000 {
75 compatible = "renesas,r8a77980-cpg-mssr";
76 reg = <0 0xe6150000 0 0x1000>;
77 clocks = <&extal_clk>, <&extalr_clk>;
78 clock-names = "extal", "extalr";
79 #clock-cells = <2>;
80 #power-domain-cells = <0>;
81 #reset-cells = <1>;
82 };
83
84 rst: reset-controller@e6160000 {
85 compatible = "renesas,r8a77980-rst";
86 reg = <0 0xe6160000 0 0x200>;
87 };
88
89 sysc: system-controller@e6180000 {
90 compatible = "renesas,r8a77980-sysc";
91 reg = <0 0xe6180000 0 0x440>;
92 #power-domain-cells = <1>;
93 };
94
95 hscif0: serial@e6540000 {
96 compatible = "renesas,hscif-r8a77980",
97 "renesas,rcar-gen3-hscif",
98 "renesas,hscif";
99 reg = <0 0xe6540000 0 0x60>;
100 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
101 clocks = <&cpg CPG_MOD 520>,
102 <&cpg CPG_CORE 19>,
103 <&scif_clk>;
104 clock-names = "fck", "brg_int", "scif_clk";
105 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
106 <&dmac2 0x31>, <&dmac2 0x30>;
107 dma-names = "tx", "rx", "tx", "rx";
108 power-domains = <&sysc 32>;
109 resets = <&cpg 520>;
110 status = "disabled";
111 };
112
113 hscif1: serial@e6550000 {
114 compatible = "renesas,hscif-r8a77980",
115 "renesas,rcar-gen3-hscif",
116 "renesas,hscif";
117 reg = <0 0xe6550000 0 0x60>;
118 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
119 clocks = <&cpg CPG_MOD 519>,
120 <&cpg CPG_CORE 19>,
121 <&scif_clk>;
122 clock-names = "fck", "brg_int", "scif_clk";
123 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
124 <&dmac2 0x33>, <&dmac2 0x32>;
125 dma-names = "tx", "rx", "tx", "rx";
126 power-domains = <&sysc 32>;
127 resets = <&cpg 519>;
128 status = "disabled";
129 };
130
131 hscif2: serial@e6560000 {
132 compatible = "renesas,hscif-r8a77980",
133 "renesas,rcar-gen3-hscif",
134 "renesas,hscif";
135 reg = <0 0xe6560000 0 0x60>;
136 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
137 clocks = <&cpg CPG_MOD 518>,
138 <&cpg CPG_CORE 19>,
139 <&scif_clk>;
140 clock-names = "fck", "brg_int", "scif_clk";
141 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
142 <&dmac2 0x35>, <&dmac2 0x34>;
143 dma-names = "tx", "rx", "tx", "rx";
144 power-domains = <&sysc 32>;
145 resets = <&cpg 518>;
146 status = "disabled";
147 };
148
149 hscif3: serial@e66a0000 {
150 compatible = "renesas,hscif-r8a77980",
151 "renesas,rcar-gen3-hscif",
152 "renesas,hscif";
153 reg = <0 0xe66a0000 0 0x60>;
154 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
155 clocks = <&cpg CPG_MOD 517>,
156 <&cpg CPG_CORE 19>,
157 <&scif_clk>;
158 clock-names = "fck", "brg_int", "scif_clk";
159 dmas = <&dmac1 0x37>, <&dmac1 0x36>,
160 <&dmac2 0x37>, <&dmac2 0x36>;
161 dma-names = "tx", "rx", "tx", "rx";
162 power-domains = <&sysc 32>;
163 resets = <&cpg 517>;
164 status = "disabled";
165 };
166
167 avb: ethernet@e6800000 {
168 compatible = "renesas,etheravb-r8a77980",
169 "renesas,etheravb-rcar-gen3";
170 reg = <0 0xe6800000 0 0x800>;
171 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
189 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
190 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
191 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
196 interrupt-names = "ch0", "ch1", "ch2", "ch3",
197 "ch4", "ch5", "ch6", "ch7",
198 "ch8", "ch9", "ch10", "ch11",
199 "ch12", "ch13", "ch14", "ch15",
200 "ch16", "ch17", "ch18", "ch19",
201 "ch20", "ch21", "ch22", "ch23",
202 "ch24";
203 clocks = <&cpg CPG_MOD 812>;
204 power-domains = <&sysc 32>;
205 resets = <&cpg 812>;
206 phy-mode = "rgmii";
207 #address-cells = <1>;
208 #size-cells = <0>;
209 };
210
211 scif0: serial@e6e60000 {
212 compatible = "renesas,scif-r8a77980",
213 "renesas,rcar-gen3-scif",
214 "renesas,scif";
215 reg = <0 0xe6e60000 0 0x40>;
216 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&cpg CPG_MOD 207>,
218 <&cpg CPG_CORE 19>,
219 <&scif_clk>;
220 clock-names = "fck", "brg_int", "scif_clk";
221 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
222 <&dmac2 0x51>, <&dmac2 0x50>;
223 dma-names = "tx", "rx", "tx", "rx";
224 power-domains = <&sysc 32>;
225 resets = <&cpg 207>;
226 status = "disabled";
227 };
228
229 scif1: serial@e6e68000 {
230 compatible = "renesas,scif-r8a77980",
231 "renesas,rcar-gen3-scif",
232 "renesas,scif";
233 reg = <0 0xe6e68000 0 0x40>;
234 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
235 clocks = <&cpg CPG_MOD 206>,
236 <&cpg CPG_CORE 19>,
237 <&scif_clk>;
238 clock-names = "fck", "brg_int", "scif_clk";
239 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
240 <&dmac2 0x53>, <&dmac2 0x52>;
241 dma-names = "tx", "rx", "tx", "rx";
242 power-domains = <&sysc 32>;
243 resets = <&cpg 206>;
244 status = "disabled";
245 };
246
247 scif3: serial@e6c50000 {
248 compatible = "renesas,scif-r8a77980",
249 "renesas,rcar-gen3-scif",
250 "renesas,scif";
251 reg = <0 0xe6c50000 0 0x40>;
252 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&cpg CPG_MOD 204>,
254 <&cpg CPG_CORE 19>,
255 <&scif_clk>;
256 clock-names = "fck", "brg_int", "scif_clk";
257 dmas = <&dmac1 0x57>, <&dmac1 0x56>,
258 <&dmac2 0x57>, <&dmac2 0x56>;
259 dma-names = "tx", "rx", "tx", "rx";
260 power-domains = <&sysc 32>;
261 resets = <&cpg 204>;
262 status = "disabled";
263 };
264
265 scif4: serial@e6c40000 {
266 compatible = "renesas,scif-r8a77980",
267 "renesas,rcar-gen3-scif",
268 "renesas,scif";
269 reg = <0 0xe6c40000 0 0x40>;
270 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&cpg CPG_MOD 203>,
272 <&cpg CPG_CORE 19>,
273 <&scif_clk>;
274 clock-names = "fck", "brg_int", "scif_clk";
275 dmas = <&dmac1 0x59>, <&dmac1 0x58>,
276 <&dmac2 0x59>, <&dmac2 0x58>;
277 dma-names = "tx", "rx", "tx", "rx";
278 power-domains = <&sysc 32>;
279 resets = <&cpg 203>;
280 status = "disabled";
281 };
282
283 dmac1: dma-controller@e7300000 {
284 compatible = "renesas,dmac-r8a77980",
285 "renesas,rcar-dmac";
286 reg = <0 0xe7300000 0 0x10000>;
287 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
288 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
289 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
290 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
291 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
292 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
293 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
294 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
295 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
296 GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH
297 GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH
298 GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH
299 GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH
300 GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH
301 GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH
302 GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH
303 GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
304 interrupt-names = "error",
305 "ch0", "ch1", "ch2", "ch3",
306 "ch4", "ch5", "ch6", "ch7",
307 "ch8", "ch9", "ch10", "ch11",
308 "ch12", "ch13", "ch14", "ch15";
309 clocks = <&cpg CPG_MOD 218>;
310 clock-names = "fck";
311 power-domains = <&sysc 32>;
312 resets = <&cpg 218>;
313 #dma-cells = <1>;
314 dma-channels = <16>;
315 };
316
317 dmac2: dma-controller@e7310000 {
318 compatible = "renesas,dmac-r8a77980",
319 "renesas,rcar-dmac";
320 reg = <0 0xe7310000 0 0x10000>;
321 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
322 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
323 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
324 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
325 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
326 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
327 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
328 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
329 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH
330 GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH
331 GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH
332 GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH
333 GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH
334 GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH
335 GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH
336 GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH
337 GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
338 interrupt-names = "error",
339 "ch0", "ch1", "ch2", "ch3",
340 "ch4", "ch5", "ch6", "ch7",
341 "ch8", "ch9", "ch10", "ch11",
342 "ch12", "ch13", "ch14", "ch15";
343 clocks = <&cpg CPG_MOD 217>;
344 clock-names = "fck";
345 power-domains = <&sysc 32>;
346 resets = <&cpg 217>;
347 #dma-cells = <1>;
348 dma-channels = <16>;
349 };
350
351 gic: interrupt-controller@f1010000 {
352 compatible = "arm,gic-400";
353 #interrupt-cells = <3>;
354 #address-cells = <0>;
355 interrupt-controller;
356 reg = <0x0 0xf1010000 0 0x1000>,
357 <0x0 0xf1020000 0 0x20000>,
358 <0x0 0xf1040000 0 0x20000>,
359 <0x0 0xf1060000 0 0x20000>;
360 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
361 IRQ_TYPE_LEVEL_HIGH)>;
362 clocks = <&cpg CPG_MOD 408>;
363 clock-names = "clk";
364 power-domains = <&sysc 32>;
365 resets = <&cpg 408>;
366 };
367
368 prr: chipid@fff00044 {
369 compatible = "renesas,prr";
370 reg = <0 0xfff00044 0 4>;
371 };
372 };
373
374 timer {
375 compatible = "arm,armv8-timer";
376 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
377 IRQ_TYPE_LEVEL_LOW)>,
378 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
379 IRQ_TYPE_LEVEL_LOW)>,
380 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
381 IRQ_TYPE_LEVEL_LOW)>,
382 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
383 IRQ_TYPE_LEVEL_LOW)>;
384 };
385};
diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
index 09de73b11db8..d03f19414028 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
@@ -27,11 +27,61 @@
27 stdout-path = "serial0:115200n8"; 27 stdout-path = "serial0:115200n8";
28 }; 28 };
29 29
30 vga {
31 compatible = "vga-connector";
32
33 port {
34 vga_in: endpoint {
35 remote-endpoint = <&adv7123_out>;
36 };
37 };
38 };
39
40 vga-encoder {
41 compatible = "adi,adv7123";
42
43 ports {
44 #address-cells = <1>;
45 #size-cells = <0>;
46
47 port@0 {
48 reg = <0>;
49 adv7123_in: endpoint {
50 remote-endpoint = <&du_out_rgb>;
51 };
52 };
53 port@1 {
54 reg = <1>;
55 adv7123_out: endpoint {
56 remote-endpoint = <&vga_in>;
57 };
58 };
59 };
60 };
61
30 memory@48000000 { 62 memory@48000000 {
31 device_type = "memory"; 63 device_type = "memory";
32 /* first 128MB is reserved for secure area. */ 64 /* first 128MB is reserved for secure area. */
33 reg = <0x0 0x48000000 0x0 0x18000000>; 65 reg = <0x0 0x48000000 0x0 0x18000000>;
34 }; 66 };
67
68 reg_1p8v: regulator0 {
69 compatible = "regulator-fixed";
70 regulator-name = "fixed-1.8V";
71 regulator-min-microvolt = <1800000>;
72 regulator-max-microvolt = <1800000>;
73 regulator-boot-on;
74 regulator-always-on;
75 };
76
77 reg_3p3v: regulator1 {
78 compatible = "regulator-fixed";
79 regulator-name = "fixed-3.3V";
80 regulator-min-microvolt = <3300000>;
81 regulator-max-microvolt = <3300000>;
82 regulator-boot-on;
83 regulator-always-on;
84 };
35}; 85};
36 86
37&extal_clk { 87&extal_clk {
@@ -46,6 +96,21 @@
46 }; 96 };
47 }; 97 };
48 98
99 du_pins: du {
100 groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
101 function = "du";
102 };
103
104 i2c0_pins: i2c0 {
105 groups = "i2c0";
106 function = "i2c0";
107 };
108
109 i2c1_pins: i2c1 {
110 groups = "i2c1";
111 function = "i2c1";
112 };
113
49 pwm0_pins: pwm0 { 114 pwm0_pins: pwm0 {
50 groups = "pwm0_c"; 115 groups = "pwm0_c";
51 function = "pwm0"; 116 function = "pwm0";
@@ -61,12 +126,56 @@
61 function = "scif2"; 126 function = "scif2";
62 }; 127 };
63 128
129 sdhi2_pins: sd2 {
130 groups = "mmc_data8", "mmc_ctrl";
131 function = "mmc";
132 power-source = <1800>;
133 };
134
135 sdhi2_pins_uhs: sd2_uhs {
136 groups = "mmc_data8", "mmc_ctrl";
137 function = "mmc";
138 power-source = <1800>;
139 };
140
64 usb0_pins: usb0 { 141 usb0_pins: usb0 {
65 groups = "usb0"; 142 groups = "usb0";
66 function = "usb0"; 143 function = "usb0";
67 }; 144 };
68}; 145};
69 146
147&i2c0 {
148 pinctrl-0 = <&i2c0_pins>;
149 pinctrl-names = "default";
150 status = "okay";
151
152 eeprom@50 {
153 compatible = "rohm,br24t01", "atmel,24c01";
154 reg = <0x50>;
155 pagesize = <8>;
156 };
157};
158
159&i2c1 {
160 pinctrl-0 = <&i2c1_pins>;
161 pinctrl-names = "default";
162 status = "okay";
163};
164
165&du {
166 pinctrl-0 = <&du_pins>;
167 pinctrl-names = "default";
168 status = "okay";
169
170 ports {
171 port@0 {
172 endpoint {
173 remote-endpoint = <&adv7123_in>;
174 };
175 };
176 };
177};
178
70&ehci0 { 179&ehci0 {
71 status = "okay"; 180 status = "okay";
72}; 181};
@@ -80,6 +189,7 @@
80 pinctrl-names = "default"; 189 pinctrl-names = "default";
81 renesas,no-ether-link; 190 renesas,no-ether-link;
82 phy-handle = <&phy0>; 191 phy-handle = <&phy0>;
192 phy-mode = "rgmii-txid";
83 status = "okay"; 193 status = "okay";
84 194
85 phy0: ethernet-phy@0 { 195 phy0: ethernet-phy@0 {
@@ -97,6 +207,20 @@
97 status = "okay"; 207 status = "okay";
98}; 208};
99 209
210&sdhi2 {
211 /* used for on-board eMMC */
212 pinctrl-0 = <&sdhi2_pins>;
213 pinctrl-1 = <&sdhi2_pins_uhs>;
214 pinctrl-names = "default", "state_uhs";
215
216 vmmc-supply = <&reg_3p3v>;
217 vqmmc-supply = <&reg_1p8v>;
218 bus-width = <8>;
219 mmc-hs200-1_8v;
220 non-removable;
221 status = "okay";
222};
223
100&usb2_phy0 { 224&usb2_phy0 {
101 pinctrl-0 = <&usb0_pins>; 225 pinctrl-0 = <&usb0_pins>;
102 pinctrl-names = "default"; 226 pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index cff42cd1a6c8..82aed7ee984c 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -58,6 +58,11 @@
58 clock-frequency = <0>; 58 clock-frequency = <0>;
59 }; 59 };
60 60
61 pmu_a53 {
62 compatible = "arm,cortex-a53-pmu";
63 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
64 };
65
61 scif_clk: scif { 66 scif_clk: scif {
62 compatible = "fixed-clock"; 67 compatible = "fixed-clock";
63 #clock-cells = <0>; 68 #clock-cells = <0>;
@@ -88,18 +93,6 @@
88 resets = <&cpg 408>; 93 resets = <&cpg 408>;
89 }; 94 };
90 95
91 timer {
92 compatible = "arm,armv8-timer";
93 interrupts = <GIC_PPI 13
94 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
95 <GIC_PPI 14
96 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
97 <GIC_PPI 11
98 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
99 <GIC_PPI 10
100 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
101 };
102
103 rwdt: watchdog@e6020000 { 96 rwdt: watchdog@e6020000 {
104 compatible = "renesas,r8a77995-wdt", 97 compatible = "renesas,r8a77995-wdt",
105 "renesas,rcar-gen3-wdt"; 98 "renesas,rcar-gen3-wdt";
@@ -110,11 +103,6 @@
110 status = "disabled"; 103 status = "disabled";
111 }; 104 };
112 105
113 pmu_a53 {
114 compatible = "arm,cortex-a53-pmu";
115 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
116 };
117
118 ipmmu_vi0: mmu@febd0000 { 106 ipmmu_vi0: mmu@febd0000 {
119 compatible = "renesas,ipmmu-r8a77995"; 107 compatible = "renesas,ipmmu-r8a77995";
120 reg = <0 0xfebd0000 0 0x1000>; 108 reg = <0 0xfebd0000 0 0x1000>;
@@ -488,7 +476,7 @@
488 avb: ethernet@e6800000 { 476 avb: ethernet@e6800000 {
489 compatible = "renesas,etheravb-r8a77995", 477 compatible = "renesas,etheravb-r8a77995",
490 "renesas,etheravb-rcar-gen3"; 478 "renesas,etheravb-rcar-gen3";
491 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; 479 reg = <0 0xe6800000 0 0x800>;
492 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 480 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
@@ -524,7 +512,7 @@
524 clocks = <&cpg CPG_MOD 812>; 512 clocks = <&cpg CPG_MOD 812>;
525 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 513 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
526 resets = <&cpg 812>; 514 resets = <&cpg 812>;
527 phy-mode = "rgmii-txid"; 515 phy-mode = "rgmii";
528 iommus = <&ipmmu_ds0 16>; 516 iommus = <&ipmmu_ds0 16>;
529 #address-cells = <1>; 517 #address-cells = <1>;
530 #size-cells = <0>; 518 #size-cells = <0>;
@@ -548,6 +536,73 @@
548 status = "disabled"; 536 status = "disabled";
549 }; 537 };
550 538
539 i2c0: i2c@e6500000 {
540 #address-cells = <1>;
541 #size-cells = <0>;
542 compatible = "renesas,i2c-r8a77995",
543 "renesas,rcar-gen3-i2c";
544 reg = <0 0xe6500000 0 0x40>;
545 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
546 clocks = <&cpg CPG_MOD 931>;
547 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
548 resets = <&cpg 931>;
549 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
550 <&dmac2 0x91>, <&dmac2 0x90>;
551 dma-names = "tx", "rx", "tx", "rx";
552 i2c-scl-internal-delay-ns = <6>;
553 status = "disabled";
554 };
555
556 i2c1: i2c@e6508000 {
557 #address-cells = <1>;
558 #size-cells = <0>;
559 compatible = "renesas,i2c-r8a77995",
560 "renesas,rcar-gen3-i2c";
561 reg = <0 0xe6508000 0 0x40>;
562 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
563 clocks = <&cpg CPG_MOD 930>;
564 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
565 resets = <&cpg 930>;
566 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
567 <&dmac2 0x93>, <&dmac2 0x92>;
568 dma-names = "tx", "rx", "tx", "rx";
569 i2c-scl-internal-delay-ns = <6>;
570 status = "disabled";
571 };
572
573 i2c2: i2c@e6510000 {
574 #address-cells = <1>;
575 #size-cells = <0>;
576 compatible = "renesas,i2c-r8a77995",
577 "renesas,rcar-gen3-i2c";
578 reg = <0 0xe6510000 0 0x40>;
579 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
580 clocks = <&cpg CPG_MOD 929>;
581 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
582 resets = <&cpg 929>;
583 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
584 <&dmac2 0x95>, <&dmac2 0x94>;
585 dma-names = "tx", "rx", "tx", "rx";
586 i2c-scl-internal-delay-ns = <6>;
587 status = "disabled";
588 };
589
590 i2c3: i2c@e66d0000 {
591 #address-cells = <1>;
592 #size-cells = <0>;
593 compatible = "renesas,i2c-r8a77995",
594 "renesas,rcar-gen3-i2c";
595 reg = <0 0xe66d0000 0 0x40>;
596 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
597 clocks = <&cpg CPG_MOD 928>;
598 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
599 resets = <&cpg 928>;
600 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
601 dma-names = "tx", "rx";
602 i2c-scl-internal-delay-ns = <6>;
603 status = "disabled";
604 };
605
551 pwm0: pwm@e6e30000 { 606 pwm0: pwm@e6e30000 {
552 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; 607 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
553 reg = <0 0xe6e30000 0 0x8>; 608 reg = <0 0xe6e30000 0 0x8>;
@@ -636,5 +691,105 @@
636 #phy-cells = <0>; 691 #phy-cells = <0>;
637 status = "disabled"; 692 status = "disabled";
638 }; 693 };
694
695 vspbs: vsp@fe960000 {
696 compatible = "renesas,vsp2";
697 reg = <0 0xfe960000 0 0x8000>;
698 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
699 clocks = <&cpg CPG_MOD 627>;
700 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
701 resets = <&cpg 627>;
702 renesas,fcp = <&fcpvb0>;
703 };
704
705 fcpvb0: fcp@fe96f000 {
706 compatible = "renesas,fcpv";
707 reg = <0 0xfe96f000 0 0x200>;
708 clocks = <&cpg CPG_MOD 607>;
709 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
710 resets = <&cpg 607>;
711 iommus = <&ipmmu_vp0 5>;
712 };
713
714 vspd0: vsp@fea20000 {
715 compatible = "renesas,vsp2";
716 reg = <0 0xfea20000 0 0x8000>;
717 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
718 clocks = <&cpg CPG_MOD 623>;
719 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
720 resets = <&cpg 623>;
721 renesas,fcp = <&fcpvd0>;
722 };
723
724 fcpvd0: fcp@fea27000 {
725 compatible = "renesas,fcpv";
726 reg = <0 0xfea27000 0 0x200>;
727 clocks = <&cpg CPG_MOD 603>;
728 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
729 resets = <&cpg 603>;
730 iommus = <&ipmmu_vi0 8>;
731 };
732
733 vspd1: vsp@fea28000 {
734 compatible = "renesas,vsp2";
735 reg = <0 0xfea28000 0 0x8000>;
736 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&cpg CPG_MOD 622>;
738 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
739 resets = <&cpg 622>;
740 renesas,fcp = <&fcpvd1>;
741 };
742
743 fcpvd1: fcp@fea2f000 {
744 compatible = "renesas,fcpv";
745 reg = <0 0xfea2f000 0 0x200>;
746 clocks = <&cpg CPG_MOD 602>;
747 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
748 resets = <&cpg 602>;
749 iommus = <&ipmmu_vi0 9>;
750 };
751
752 du: display@feb00000 {
753 compatible = "renesas,du-r8a77995";
754 reg = <0 0xfeb00000 0 0x80000>;
755 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
756 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
757 clocks = <&cpg CPG_MOD 724>,
758 <&cpg CPG_MOD 723>;
759 clock-names = "du.0", "du.1";
760 vsps = <&vspd0 0 &vspd1 0>;
761 status = "disabled";
762
763 ports {
764 #address-cells = <1>;
765 #size-cells = <0>;
766
767 port@0 {
768 reg = <0>;
769 du_out_rgb: endpoint {
770 };
771 };
772
773 port@1 {
774 reg = <1>;
775 du_out_lvds0: endpoint {
776 };
777 };
778
779 port@2 {
780 reg = <2>;
781 du_out_lvds1: endpoint {
782 };
783 };
784 };
785 };
786 };
787
788 timer {
789 compatible = "arm,armv8-timer";
790 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
791 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
792 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
793 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
639 }; 794 };
640}; 795};
diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
index c3fafb6025b3..2a7f36abd2dd 100644
--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
@@ -256,6 +256,7 @@
256 pinctrl-0 = <&avb_pins>; 256 pinctrl-0 = <&avb_pins>;
257 pinctrl-names = "default"; 257 pinctrl-names = "default";
258 phy-handle = <&phy0>; 258 phy-handle = <&phy0>;
259 phy-mode = "rgmii-txid";
259 status = "okay"; 260 status = "okay";
260 261
261 phy0: ethernet-phy@0 { 262 phy0: ethernet-phy@0 {
@@ -338,6 +339,13 @@
338&i2c4 { 339&i2c4 {
339 status = "okay"; 340 status = "okay";
340 341
342 pca9654: gpio@20 {
343 compatible = "onnn,pca9654";
344 reg = <0x20>;
345 gpio-controller;
346 #gpio-cells = <2>;
347 };
348
341 csa_vdd: adc@7c { 349 csa_vdd: adc@7c {
342 compatible = "maxim,max9611"; 350 compatible = "maxim,max9611";
343 reg = <0x7c>; 351 reg = <0x7c>;
diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi
index 3e7a6b94e9f8..6f814845f8b6 100644
--- a/arch/arm64/boot/dts/renesas/ulcb.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi
@@ -146,6 +146,7 @@
146 pinctrl-0 = <&avb_pins>; 146 pinctrl-0 = <&avb_pins>;
147 pinctrl-names = "default"; 147 pinctrl-names = "default";
148 phy-handle = <&phy0>; 148 phy-handle = <&phy0>;
149 phy-mode = "rgmii-txid";
149 status = "okay"; 150 status = "okay";
150 151
151 phy0: ethernet-phy@0 { 152 phy0: ethernet-phy@0 {
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-22 11:22:54 -0400