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authorLinus Torvalds <torvalds@linux-foundation.org>2018-02-02 17:22:53 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2018-02-02 17:22:53 -0500
commitef991796be0e65b644fe60198bd1112830eff173 (patch)
treefcefb8bd7f8ba7d8dcde31ae37f703f05cb131a9
parentbf644990a796bd72d6f3977f3307169919a23f85 (diff)
parent02e389e63e3523828fc3832f27e0341885f60f6f (diff)
Merge tag 'pinctrl-v4.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v4.16 kernel cycle. Like with GPIO it is actually a bit calm this time. Core changes: - After lengthy discussions and partly due to my ignorance, we have merged a patch making pinctrl_force_default() and pinctrl_force_sleep() reprogram the states into the hardware of any hogged pins, even if they are already in the desired state. This only apply to hogged pins since groups of pins owned by drivers need to be managed by each driver, lest they could not do things like runtime PM and put pins to sleeping state even if the system as a whole is not in sleep. New drivers: - New driver for the Microsemi Ocelot SoC. This is used in ethernet switches. - The X-Powers AXP209 GPIO driver was extended to also deal with pin control and moved over from the GPIO subsystem. This circuit is a mixed-mode integrated circuit which is part of AllWinner designs. - New subdriver for the Qualcomm MSM8998 SoC, core of a high end mobile devices (phones) chipset. - New subdriver for the ST Microelectronics STM32MP157 MPU and STM32F769 MCU from the STM32 family. - New subdriver for the MediaTek MT7622 SoC. This is used for routers, repeater, gateways and such network infrastructure. - New subdriver for the NXP (former Freescale) i.MX 6ULL. This SoC has multimedia features and target "smart devices", I guess in-car entertainment, in-flight entertainment, industrial control panels etc. General improvements: - Incremental improvements on the SH-PFC subdrivers for things like the CAN bus. - Enable the glitch filter on Baytrail GPIOs used for interrupts. - Proper handling of pins to GPIO ranges on the Semtec SX150X - An IRQ setup ordering fix on MCP23S08. - A good set of janitorial coding style fixes" * tag 'pinctrl-v4.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (102 commits) pinctrl: mcp23s08: fix irq setup order pinctrl: Forward declare struct device pinctrl: sunxi: Use of_clk_get_parent_count() instead of open coding pinctrl: stm32: add STM32F769 MCU support pinctrl: sx150x: Add a static gpio/pinctrl pin range mapping pinctrl: sx150x: Register pinctrl before adding the gpiochip pinctrl: sx150x: Unregister the pinctrl on release pinctrl: ingenic: Remove redundant dev_err call in ingenic_pinctrl_probe() pinctrl: sprd: Use seq_putc() in sprd_pinconf_group_dbg_show() pinctrl: pinmux: Use seq_putc() in pinmux_pins_show() pinctrl: abx500: Use seq_putc() in abx500_gpio_dbg_show() pinctrl: mediatek: mt7622: align error handling of mtk_hw_get_value call pinctrl: mediatek: mt7622: fix potential uninitialized value being returned pinctrl: uniphier: refactor drive strength get/set functions pinctrl: imx7ulp: constify struct imx_cfg_params_decode pinctrl: imx: constify struct imx_pinctrl_soc_info pinctrl: imx7d: simplify imx7d_pinctrl_probe pinctrl: imx: use struct imx_pinctrl_soc_info as a const pinctrl: sunxi-pinctrl: fix pin funtion can not be match correctly. pinctrl: qcom: Add msm8998 pinctrl driver ...
Diffstat
-rw-r--r--Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt3
-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.txt3
-rw-r--r--Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt39
-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt351
-rw-r--r--Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt193
-rw-r--r--Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt1
-rw-r--r--Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.txt27
-rw-r--r--Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt2
-rw-r--r--MAINTAINERS11
-rw-r--r--drivers/gpio/gpio-uniphier.c2
-rw-r--r--drivers/gpio/gpiolib-acpi.c75
-rw-r--r--drivers/pinctrl/Kconfig15
-rw-r--r--drivers/pinctrl/Makefile3
-rw-r--r--drivers/pinctrl/core.c24
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx.c81
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx.h13
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx25.c2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx35.c2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx50.c2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx51.c2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx53.c2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx6dl.c2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx6q.c2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx6sl.c2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx6sx.c2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx6ul.c52
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx7d.c10
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx7ulp.c7
-rw-r--r--drivers/pinctrl/freescale/pinctrl-vf610.c5
-rw-r--r--drivers/pinctrl/intel/pinctrl-baytrail.c6
-rw-r--r--drivers/pinctrl/intel/pinctrl-cannonlake.c65
-rw-r--r--drivers/pinctrl/intel/pinctrl-cherryview.c59
-rw-r--r--drivers/pinctrl/intel/pinctrl-intel.c179
-rw-r--r--drivers/pinctrl/intel/pinctrl-intel.h3
-rw-r--r--drivers/pinctrl/intel/pinctrl-merrifield.c7
-rw-r--r--drivers/pinctrl/mediatek/Kconfig15
-rw-r--r--drivers/pinctrl/mediatek/Makefile3
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mt7622.c1597
-rw-r--r--drivers/pinctrl/meson/Kconfig9
-rw-r--r--drivers/pinctrl/meson/Makefile2
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c118
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h62
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson-axg.c975
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson.h1
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-armada-37xx.c4
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-mvebu.c5
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-abx500.c10
-rw-r--r--drivers/pinctrl/pinctrl-adi2.c13
-rw-r--r--drivers/pinctrl/pinctrl-at91-pio4.c4
-rw-r--r--drivers/pinctrl/pinctrl-at91.c4
-rw-r--r--drivers/pinctrl/pinctrl-axp209.c4
-rw-r--r--drivers/pinctrl/pinctrl-gemini.c84
-rw-r--r--drivers/pinctrl/pinctrl-ingenic.c4
-rw-r--r--drivers/pinctrl/pinctrl-mcp23s08.c54
-rw-r--r--drivers/pinctrl/pinctrl-ocelot.c511
-rw-r--r--drivers/pinctrl/pinctrl-palmas.c4
-rw-r--r--drivers/pinctrl/pinctrl-rockchip.c31
-rw-r--r--drivers/pinctrl/pinctrl-single.c10
-rw-r--r--drivers/pinctrl/pinctrl-sx150x.c40
-rw-r--r--drivers/pinctrl/pinctrl-tz1090-pdc.c9
-rw-r--r--drivers/pinctrl/pinctrl-tz1090.c9
-rw-r--r--drivers/pinctrl/pinctrl-utils.c4
-rw-r--r--drivers/pinctrl/pinctrl-xway.c10
-rw-r--r--drivers/pinctrl/pinmux.c4
-rw-r--r--drivers/pinctrl/pxa/pinctrl-pxa2xx.c4
-rw-r--r--drivers/pinctrl/qcom/Kconfig8
-rw-r--r--drivers/pinctrl/qcom/Makefile1
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm.c5
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm8998.c1590
-rw-r--r--drivers/pinctrl/samsung/Kconfig1
-rw-r--r--drivers/pinctrl/samsung/pinctrl-exynos-arm.c33
-rw-r--r--drivers/pinctrl/samsung/pinctrl-exynos-arm64.c33
-rw-r--r--drivers/pinctrl/samsung/pinctrl-exynos.c33
-rw-r--r--drivers/pinctrl/samsung/pinctrl-exynos.h6
-rw-r--r--drivers/pinctrl/samsung/pinctrl-exynos5440.c21
-rw-r--r--drivers/pinctrl/samsung/pinctrl-s3c24xx.c23
-rw-r--r--drivers/pinctrl/samsung/pinctrl-s3c64xx.c27
-rw-r--r--drivers/pinctrl/samsung/pinctrl-samsung.c37
-rw-r--r--drivers/pinctrl/samsung/pinctrl-samsung.h6
-rw-r--r--drivers/pinctrl/sh-pfc/Kconfig5
-rw-r--r--drivers/pinctrl/sh-pfc/Makefile1
-rw-r--r--drivers/pinctrl/sh-pfc/core.c6
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7791.c62
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7794.c473
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c2
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7795.c193
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7796.c66
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a77970.c2329
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a77995.c88
-rw-r--r--drivers/pinctrl/sh-pfc/sh_pfc.h17
-rw-r--r--drivers/pinctrl/spear/pinctrl-plgpio.c8
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear.c4
-rw-r--r--drivers/pinctrl/sprd/pinctrl-sprd.c2
-rw-r--r--drivers/pinctrl/stm32/Kconfig12
-rw-r--r--drivers/pinctrl/stm32/Makefile2
-rw-r--r--drivers/pinctrl/stm32/pinctrl-stm32.c3
-rw-r--r--drivers/pinctrl/stm32/pinctrl-stm32.h3
-rw-r--r--drivers/pinctrl/stm32/pinctrl-stm32f429.c3
-rw-r--r--drivers/pinctrl/stm32/pinctrl-stm32f469.c6
-rw-r--r--drivers/pinctrl/stm32/pinctrl-stm32f746.c3
-rw-r--r--drivers/pinctrl/stm32/pinctrl-stm32f769.c1827
-rw-r--r--drivers/pinctrl/stm32/pinctrl-stm32h743.c6
-rw-r--r--drivers/pinctrl/stm32/pinctrl-stm32mp157.c2188
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c2
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sunxi.c7
-rw-r--r--drivers/pinctrl/tegra/pinctrl-tegra.c9
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier-core.c176
-rw-r--r--drivers/pinctrl/vt8500/pinctrl-vt8500.c4
-rw-r--r--drivers/pinctrl/vt8500/pinctrl-wm8505.c4
-rw-r--r--drivers/pinctrl/vt8500/pinctrl-wm8650.c4
-rw-r--r--drivers/pinctrl/vt8500/pinctrl-wm8750.c4
-rw-r--r--drivers/pinctrl/vt8500/pinctrl-wm8850.c4
-rw-r--r--include/dt-bindings/gpio/meson-axg-gpio.h116
-rw-r--r--include/dt-bindings/pinctrl/stm32-pinfunc.h6
-rw-r--r--include/linux/pinctrl/devinfo.h2
115 files changed, 13578 insertions, 751 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt
index d857b67fab72..4346ff2dd8e6 100644
--- a/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt
@@ -17,6 +17,9 @@ and generic pin config nodes.
17 17
18Supported configurations: 18Supported configurations:
19- skew-delay is supported on the Ethernet pins 19- skew-delay is supported on the Ethernet pins
20- drive-strength with 4, 8, 12 or 16 mA as argument is supported for
21 entire groups on the groups "idegrp", "gmii_gmac0_grp", "gmii_gmac1_grp"
22 and "pcigrp".
20 23
21Example: 24Example:
22 25
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.txt
index a81bbf37ed66..7ca4f6118d9a 100644
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.txt
@@ -4,7 +4,8 @@ Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
4and usage. 4and usage.
5 5
6Required properties: 6Required properties:
7- compatible: "fsl,imx6ul-iomuxc" 7- compatible: "fsl,imx6ul-iomuxc" for main IOMUX controller or
8 "fsl,imx6ull-iomuxc-snvs" for i.MX 6ULL's SNVS IOMUX controller.
8- fsl,pins: each entry consists of 6 integers and represents the mux and config 9- fsl,pins: each entry consists of 6 integers and represents the mux and config
9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val 10 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
10 input_val> are specified using a PIN_FUNC_ID macro, which can be found in 11 input_val> are specified using a PIN_FUNC_ID macro, which can be found in
diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
new file mode 100644
index 000000000000..24a210e0c59a
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
@@ -0,0 +1,39 @@
1Microsemi Ocelot pin controller Device Tree Bindings
2----------------------------------------------------
3
4Required properties:
5 - compatible : Should be "mscc,ocelot-pinctrl"
6 - reg : Address and length of the register set for the device
7 - gpio-controller : Indicates this device is a GPIO controller
8 - #gpio-cells : Must be 2.
9 The first cell is the pin number and the
10 second cell specifies GPIO flags, as defined in
11 <dt-bindings/gpio/gpio.h>.
12 - gpio-ranges : Range of pins managed by the GPIO controller.
13
14
15The ocelot-pinctrl driver uses the generic pin multiplexing and generic pin
16configuration documented in pinctrl-bindings.txt.
17
18The following generic properties are supported:
19 - function
20 - pins
21
22Example:
23 gpio: pinctrl@71070034 {
24 compatible = "mscc,ocelot-pinctrl";
25 reg = <0x71070034 0x28>;
26 gpio-controller;
27 #gpio-cells = <2>;
28 gpio-ranges = <&gpio 0 0 22>;
29
30 uart_pins: uart-pins {
31 pins = "GPIO_6", "GPIO_7";
32 function = "uart";
33 };
34
35 uart2_pins: uart2-pins {
36 pins = "GPIO_12", "GPIO_13";
37 function = "uart2";
38 };
39 };
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt
new file mode 100644
index 000000000000..f18ed99f6e14
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt
@@ -0,0 +1,351 @@
1== MediaTek MT7622 pinctrl controller ==
2
3Required properties for the root node:
4 - compatible: Should be one of the following
5 "mediatek,mt7622-pinctrl" for MT7622 SoC
6 - reg: offset and length of the pinctrl space
7
8 - gpio-controller: Marks the device node as a GPIO controller.
9 - #gpio-cells: Should be two. The first cell is the pin number and the
10 second is the GPIO flags.
11
12Please refer to pinctrl-bindings.txt in this directory for details of the
13common pinctrl bindings used by client devices, including the meaning of the
14phrase "pin configuration node".
15
16MT7622 pin configuration nodes act as a container for an arbitrary number of
17subnodes. Each of these subnodes represents some desired configuration for a
18pin, a group, or a list of pins or groups. This configuration can include the
19mux function to select on those pin(s)/group(s), and various pin configuration
20parameters, such as pull-up, slew rate, etc.
21
22We support 2 types of configuration nodes. Those nodes can be either pinmux
23nodes or pinconf nodes. Each configuration node can consist of multiple nodes
24describing the pinmux and pinconf options.
25
26The name of each subnode doesn't matter as long as it is unique; all subnodes
27should be enumerated and processed purely based on their content.
28
29== pinmux nodes content ==
30
31The following generic properties as defined in pinctrl-bindings.txt are valid
32to specify in a pinmux subnode:
33
34Required properties are:
35 - groups: An array of strings. Each string contains the name of a group.
36 Valid values for these names are listed below.
37 - function: A string containing the name of the function to mux to the
38 group. Valid values for function names are listed below.
39
40== pinconf nodes content ==
41
42The following generic properties as defined in pinctrl-bindings.txt are valid
43to specify in a pinconf subnode:
44
45Required properties are:
46 - pins: An array of strings. Each string contains the name of a pin.
47 Valid values for these names are listed below.
48 - groups: An array of strings. Each string contains the name of a group.
49 Valid values for these names are listed below.
50
51Optional properies are:
52 bias-disable, bias-pull, bias-pull-down, input-enable,
53 input-schmitt-enable, input-schmitt-disable, output-enable
54 output-low, output-high, drive-strength, slew-rate
55
56 Valid arguments for 'slew-rate' are '0' for no slew rate controlled and '1' for
57 slower slew rate respectively.
58 Valid arguments for 'drive-strength', 4, 8, 12, or 16 in mA.
59
60The following specific properties as defined are valid to specify in a pinconf
61subnode:
62
63Optional properties are:
64 - mediatek,tdsel: An integer describing the steps for output level shifter duty
65 cycle when asserted (high pulse width adjustment). Valid arguments are from 0
66 to 15.
67 - mediatek,rdsel: An integer describing the steps for input level shifter duty
68 cycle when asserted (high pulse width adjustment). Valid arguments are from 0
69 to 63.
70
71== Valid values for pins, function and groups on MT7622 ==
72
73Valid values for pins are:
74pins can be referenced via the pin names as the below table shown and the
75related physical number is also put ahead of those names which helps cross
76references to pins between groups to know whether pins assignment conflict
77happens among devices try to acquire those available pins.
78
79 Pin #: Valid values for pins
80 -----------------------------
81 PIN 0: "GPIO_A"
82 PIN 1: "I2S1_IN"
83 PIN 2: "I2S1_OUT"
84 PIN 3: "I2S_BCLK"
85 PIN 4: "I2S_WS"
86 PIN 5: "I2S_MCLK"
87 PIN 6: "TXD0"
88 PIN 7: "RXD0"
89 PIN 8: "SPI_WP"
90 PIN 9: "SPI_HOLD"
91 PIN 10: "SPI_CLK"
92 PIN 11: "SPI_MOSI"
93 PIN 12: "SPI_MISO"
94 PIN 13: "SPI_CS"
95 PIN 14: "I2C_SDA"
96 PIN 15: "I2C_SCL"
97 PIN 16: "I2S2_IN"
98 PIN 17: "I2S3_IN"
99 PIN 18: "I2S4_IN"
100 PIN 19: "I2S2_OUT"
101 PIN 20: "I2S3_OUT"
102 PIN 21: "I2S4_OUT"
103 PIN 22: "GPIO_B"
104 PIN 23: "MDC"
105 PIN 24: "MDIO"
106 PIN 25: "G2_TXD0"
107 PIN 26: "G2_TXD1"
108 PIN 27: "G2_TXD2"
109 PIN 28: "G2_TXD3"
110 PIN 29: "G2_TXEN"
111 PIN 30: "G2_TXC"
112 PIN 31: "G2_RXD0"
113 PIN 32: "G2_RXD1"
114 PIN 33: "G2_RXD2"
115 PIN 34: "G2_RXD3"
116 PIN 35: "G2_RXDV"
117 PIN 36: "G2_RXC"
118 PIN 37: "NCEB"
119 PIN 38: "NWEB"
120 PIN 39: "NREB"
121 PIN 40: "NDL4"
122 PIN 41: "NDL5"
123 PIN 42: "NDL6"
124 PIN 43: "NDL7"
125 PIN 44: "NRB"
126 PIN 45: "NCLE"
127 PIN 46: "NALE"
128 PIN 47: "NDL0"
129 PIN 48: "NDL1"
130 PIN 49: "NDL2"
131 PIN 50: "NDL3"
132 PIN 51: "MDI_TP_P0"
133 PIN 52: "MDI_TN_P0"
134 PIN 53: "MDI_RP_P0"
135 PIN 54: "MDI_RN_P0"
136 PIN 55: "MDI_TP_P1"
137 PIN 56: "MDI_TN_P1"
138 PIN 57: "MDI_RP_P1"
139 PIN 58: "MDI_RN_P1"
140 PIN 59: "MDI_RP_P2"
141 PIN 60: "MDI_RN_P2"
142 PIN 61: "MDI_TP_P2"
143 PIN 62: "MDI_TN_P2"
144 PIN 63: "MDI_TP_P3"
145 PIN 64: "MDI_TN_P3"
146 PIN 65: "MDI_RP_P3"
147 PIN 66: "MDI_RN_P3"
148 PIN 67: "MDI_RP_P4"
149 PIN 68: "MDI_RN_P4"
150 PIN 69: "MDI_TP_P4"
151 PIN 70: "MDI_TN_P4"
152 PIN 71: "PMIC_SCL"
153 PIN 72: "PMIC_SDA"
154 PIN 73: "SPIC1_CLK"
155 PIN 74: "SPIC1_MOSI"
156 PIN 75: "SPIC1_MISO"
157 PIN 76: "SPIC1_CS"
158 PIN 77: "GPIO_D"
159 PIN 78: "WATCHDOG"
160 PIN 79: "RTS3_N"
161 PIN 80: "CTS3_N"
162 PIN 81: "TXD3"
163 PIN 82: "RXD3"
164 PIN 83: "PERST0_N"
165 PIN 84: "PERST1_N"
166 PIN 85: "WLED_N"
167 PIN 86: "EPHY_LED0_N"
168 PIN 87: "AUXIN0"
169 PIN 88: "AUXIN1"
170 PIN 89: "AUXIN2"
171 PIN 90: "AUXIN3"
172 PIN 91: "TXD4"
173 PIN 92: "RXD4"
174 PIN 93: "RTS4_N"
175 PIN 94: "CST4_N"
176 PIN 95: "PWM1"
177 PIN 96: "PWM2"
178 PIN 97: "PWM3"
179 PIN 98: "PWM4"
180 PIN 99: "PWM5"
181 PIN 100: "PWM6"
182 PIN 101: "PWM7"
183 PIN 102: "GPIO_E"
184
185Valid values for function are:
186 "emmc", "eth", "i2c", "i2s", "ir", "led", "flash", "pcie",
187 "pmic", "pwm", "sd", "spi", "tdm", "uart", "watchdog"
188
189Valid values for groups are:
190additional data is put followingly with valid value allowing us to know which
191applicable function and which relevant pins (in pin#) are able applied for that
192group.
193
194 Valid value function pins (in pin#)
195 -------------------------------------------------------------------------
196 "emmc" "emmc" 40, 41, 42, 43, 44, 45,
197 47, 48, 49, 50
198 "emmc_rst" "emmc" 37
199 "esw" "eth" 51, 52, 53, 54, 55, 56,
200 57, 58, 59, 60, 61, 62,
201 63, 64, 65, 66, 67, 68,
202 69, 70
203 "esw_p0_p1" "eth" 51, 52, 53, 54, 55, 56,
204 57, 58
205 "esw_p2_p3_p4" "eth" 59, 60, 61, 62, 63, 64,
206 65, 66, 67, 68, 69, 70
207 "rgmii_via_esw" "eth" 59, 60, 61, 62, 63, 64,
208 65, 66, 67, 68, 69, 70
209 "rgmii_via_gmac1" "eth" 59, 60, 61, 62, 63, 64,
210 65, 66, 67, 68, 69, 70
211 "rgmii_via_gmac2" "eth" 25, 26, 27, 28, 29, 30,
212 31, 32, 33, 34, 35, 36
213 "mdc_mdio" "eth" 23, 24
214 "i2c0" "i2c" 14, 15
215 "i2c1_0" "i2c" 55, 56
216 "i2c1_1" "i2c" 73, 74
217 "i2c1_2" "i2c" 87, 88
218 "i2c2_0" "i2c" 57, 58
219 "i2c2_1" "i2c" 75, 76
220 "i2c2_2" "i2c" 89, 90
221 "i2s_in_mclk_bclk_ws" "i2s" 3, 4, 5
222 "i2s1_in_data" "i2s" 1
223 "i2s2_in_data" "i2s" 16
224 "i2s3_in_data" "i2s" 17
225 "i2s4_in_data" "i2s" 18
226 "i2s_out_mclk_bclk_ws" "i2s" 3, 4, 5
227 "i2s1_out_data" "i2s" 2
228 "i2s2_out_data" "i2s" 19
229 "i2s3_out_data" "i2s" 20
230 "i2s4_out_data" "i2s" 21
231 "ir_0_tx" "ir" 16
232 "ir_1_tx" "ir" 59
233 "ir_2_tx" "ir" 99
234 "ir_0_rx" "ir" 17
235 "ir_1_rx" "ir" 60
236 "ir_2_rx" "ir" 100
237 "ephy_leds" "led" 86, 91, 92, 93, 94
238 "ephy0_led" "led" 86
239 "ephy1_led" "led" 91
240 "ephy2_led" "led" 92
241 "ephy3_led" "led" 93
242 "ephy4_led" "led" 94
243 "wled" "led" 85
244 "par_nand" "flash" 37, 38, 39, 40, 41, 42,
245 43, 44, 45, 46, 47, 48,
246 49, 50
247 "snfi" "flash" 8, 9, 10, 11, 12, 13
248 "spi_nor" "flash" 8, 9, 10, 11, 12, 13
249 "pcie0_0_waken" "pcie" 14
250 "pcie0_1_waken" "pcie" 79
251 "pcie1_0_waken" "pcie" 14
252 "pcie0_0_clkreq" "pcie" 15
253 "pcie0_1_clkreq" "pcie" 80
254 "pcie1_0_clkreq" "pcie" 15
255 "pcie0_pad_perst" "pcie" 83
256 "pcie1_pad_perst" "pcie" 84
257 "pmic_bus" "pmic" 71, 72
258 "pwm_ch1_0" "pwm" 51
259 "pwm_ch1_1" "pwm" 73
260 "pwm_ch1_2" "pwm" 95
261 "pwm_ch2_0" "pwm" 52
262 "pwm_ch2_1" "pwm" 74
263 "pwm_ch2_2" "pwm" 96
264 "pwm_ch3_0" "pwm" 53
265 "pwm_ch3_1" "pwm" 75
266 "pwm_ch3_2" "pwm" 97
267 "pwm_ch4_0" "pwm" 54
268 "pwm_ch4_1" "pwm" 67
269 "pwm_ch4_2" "pwm" 76
270 "pwm_ch4_3" "pwm" 98
271 "pwm_ch5_0" "pwm" 68
272 "pwm_ch5_1" "pwm" 77
273 "pwm_ch5_2" "pwm" 99
274 "pwm_ch6_0" "pwm" 69
275 "pwm_ch6_1" "pwm" 78
276 "pwm_ch6_2" "pwm" 81
277 "pwm_ch6_3" "pwm" 100
278 "pwm_ch7_0" "pwm" 70
279 "pwm_ch7_1" "pwm" 82
280 "pwm_ch7_2" "pwm" 101
281 "sd_0" "sd" 16, 17, 18, 19, 20, 21
282 "sd_1" "sd" 25, 26, 27, 28, 29, 30
283 "spic0_0" "spi" 63, 64, 65, 66
284 "spic0_1" "spi" 79, 80, 81, 82
285 "spic1_0" "spi" 67, 68, 69, 70
286 "spic1_1" "spi" 73, 74, 75, 76
287 "spic2_0_wp_hold" "spi" 8, 9
288 "spic2_0" "spi" 10, 11, 12, 13
289 "tdm_0_out_mclk_bclk_ws" "tdm" 8, 9, 10
290 "tdm_0_in_mclk_bclk_ws" "tdm" 11, 12, 13
291 "tdm_0_out_data" "tdm" 20
292 "tdm_0_in_data" "tdm" 21
293 "tdm_1_out_mclk_bclk_ws" "tdm" 57, 58, 59
294 "tdm_1_in_mclk_bclk_ws" "tdm" 60, 61, 62
295 "tdm_1_out_data" "tdm" 55
296 "tdm_1_in_data" "tdm" 56
297 "uart0_0_tx_rx" "uart" 6, 7
298 "uart1_0_tx_rx" "uart" 55, 56
299 "uart1_0_rts_cts" "uart" 57, 58
300 "uart1_1_tx_rx" "uart" 73, 74
301 "uart1_1_rts_cts" "uart" 75, 76
302 "uart2_0_tx_rx" "uart" 3, 4
303 "uart2_0_rts_cts" "uart" 1, 2
304 "uart2_1_tx_rx" "uart" 51, 52
305 "uart2_1_rts_cts" "uart" 53, 54
306 "uart2_2_tx_rx" "uart" 59, 60
307 "uart2_2_rts_cts" "uart" 61, 62
308 "uart2_3_tx_rx" "uart" 95, 96
309 "uart3_0_tx_rx" "uart" 57, 58
310 "uart3_1_tx_rx" "uart" 81, 82
311 "uart3_1_rts_cts" "uart" 79, 80
312 "uart4_0_tx_rx" "uart" 61, 62
313 "uart4_1_tx_rx" "uart" 91, 92
314 "uart4_1_rts_cts" "uart" 93, 94
315 "uart4_2_tx_rx" "uart" 97, 98
316 "uart4_2_rts_cts" "uart" 95, 96
317 "watchdog" "watchdog" 78
318
319Example:
320
321 pio: pinctrl@10211000 {
322 compatible = "mediatek,mt7622-pinctrl";
323 reg = <0 0x10211000 0 0x1000>;
324 gpio-controller;
325 #gpio-cells = <2>;
326
327 pinctrl_eth_default: eth-default {
328 mux-mdio {
329 groups = "mdc_mdio";
330 function = "eth";
331 drive-strength = <12>;
332 };
333
334 mux-gmac2 {
335 groups = "gmac2";
336 function = "eth";
337 drive-strength = <12>;
338 };
339
340 mux-esw {
341 groups = "esw";
342 function = "eth";
343 drive-strength = <8>;
344 };
345
346 conf-mdio {
347 pins = "MDC";
348 bias-pull-up;
349 };
350 };
351 };
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt
new file mode 100644
index 000000000000..e70c79bbbc5b
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt
@@ -0,0 +1,193 @@
1Qualcomm MSM8998 TLMM block
2
3This binding describes the Top Level Mode Multiplexer block found in the
4MSM8998 platform.
5
6- compatible:
7 Usage: required
8 Value type: <string>
9 Definition: must be "qcom,msm8998-pinctrl"
10
11- reg:
12 Usage: required
13 Value type: <prop-encoded-array>
14 Definition: the base address and size of the TLMM register space.
15
16- interrupts:
17 Usage: required
18 Value type: <prop-encoded-array>
19 Definition: should specify the TLMM summary IRQ.
20
21- interrupt-controller:
22 Usage: required
23 Value type: <none>
24 Definition: identifies this node as an interrupt controller
25
26- #interrupt-cells:
27 Usage: required
28 Value type: <u32>
29 Definition: must be 2. Specifying the pin number and flags, as defined
30 in <dt-bindings/interrupt-controller/irq.h>
31
32- gpio-controller:
33 Usage: required
34 Value type: <none>
35 Definition: identifies this node as a gpio controller
36
37- #gpio-cells:
38 Usage: required
39 Value type: <u32>
40 Definition: must be 2. Specifying the pin number and flags, as defined
41 in <dt-bindings/gpio/gpio.h>
42
43Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
44a general description of GPIO and interrupt bindings.
45
46Please refer to pinctrl-bindings.txt in this directory for details of the
47common pinctrl bindings used by client devices, including the meaning of the
48phrase "pin configuration node".
49
50The pin configuration nodes act as a container for an arbitrary number of
51subnodes. Each of these subnodes represents some desired configuration for a
52pin, a group, or a list of pins or groups. This configuration can include the
53mux function to select on those pin(s)/group(s), and various pin configuration
54parameters, such as pull-up, drive strength, etc.
55
56
57PIN CONFIGURATION NODES:
58
59The name of each subnode is not important; all subnodes should be enumerated
60and processed purely based on their content.
61
62Each subnode only affects those parameters that are explicitly listed. In
63other words, a subnode that lists a mux function but no pin configuration
64parameters implies no information about any pin configuration parameters.
65Similarly, a pin subnode that describes a pullup parameter implies no
66information about e.g. the mux function.
67
68
69The following generic properties as defined in pinctrl-bindings.txt are valid
70to specify in a pin configuration subnode:
71
72- pins:
73 Usage: required
74 Value type: <string-array>
75 Definition: List of gpio pins affected by the properties specified in
76 this subnode.
77
78 Valid pins are:
79 gpio0-gpio149
80 Supports mux, bias and drive-strength
81
82 sdc2_clk, sdc2_cmd, sdc2_data
83 Supports bias and drive-strength
84
85 ufs_reset
86 Supports bias and drive-strength
87
88- function:
89 Usage: required
90 Value type: <string>
91 Definition: Specify the alternative function to be configured for the
92 specified pins. Functions are only valid for gpio pins.
93 Valid values are:
94
95 gpio, adsp_ext, agera_pll, atest_char, atest_gpsadc0,
96 atest_gpsadc1, atest_tsens, atest_tsens2, atest_usb1,
97 atest_usb10, atest_usb11, atest_usb12, atest_usb13,
98 audio_ref, bimc_dte0, bimc_dte1, blsp10_spi, blsp10_spi_a,
99 blsp10_spi_b, blsp11_i2c, blsp1_spi, blsp1_spi_a,
100 blsp1_spi_b, blsp2_spi, blsp9_spi, blsp_i2c1, blsp_i2c2,
101 blsp_i2c3, blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7,
102 blsp_i2c8, blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12,
103 blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5,
104 blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10,
105 blsp_spi11, blsp_spi12, blsp_uart1_a, blsp_uart1_b,
106 blsp_uart2_a, blsp_uart2_b, blsp_uart3_a, blsp_uart3_b,
107 blsp_uart7_a, blsp_uart7_b, blsp_uart8, blsp_uart8_a,
108 blsp_uart8_b, blsp_uart9_a, blsp_uart9_b, blsp_uim1_a,
109 blsp_uim1_b, blsp_uim2_a, blsp_uim2_b, blsp_uim3_a,
110 blsp_uim3_b, blsp_uim7_a, blsp_uim7_b, blsp_uim8_a,
111 blsp_uim8_b, blsp_uim9_a, blsp_uim9_b, bt_reset,
112 btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0,
113 cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng,
114 cri_trng0, cri_trng1, dbg_out, ddr_bist, edp_hot, edp_lcd,
115 gcc_gp1_a, gcc_gp1_b, gcc_gp2_a, gcc_gp2_b, gcc_gp3_a,
116 gcc_gp3_b, hdmi_cec, hdmi_ddc, hdmi_hot, hdmi_rcv,
117 isense_dbg, jitter_bist, ldo_en, ldo_update, lpass_slimbus,
118 m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
119 mdp_vsync3, mdp_vsync_a, mdp_vsync_b, modem_tsync, mss_lte,
120 nav_dr, nav_pps, pa_indicator, pci_e0, phase_flag,
121 pll_bypassnl, pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc,
122 pwr_crypto, pwr_modem, pwr_nav, qdss_cti0_a, qdss_cti0_b,
123 qdss_cti1_a, qdss_cti1_b, qdss, qlink_enable,
124 qlink_request, qua_mi2s, sd_card, sd_write, sdc40, sdc41,
125 sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu,
126 spkr_i2s, ssbi1, ssc_irq, ter_mi2s, tgu_ch0, tgu_ch1,
127 tsense_pwm1, tsense_pwm2, tsif1_clk, tsif1_data, tsif1_en,
128 tsif1_error, tsif1_sync, tsif2_clk, tsif2_data, tsif2_en,
129 tsif2_error, tsif2_sync, uim1_clk, uim1_data, uim1_present,
130 uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,
131 uim_batt, usb_phy, vfr_1, vsense_clkout, vsense_data0,
132 vsense_data1, vsense_mode, wlan1_adc0, wlan1_adc1,
133 wlan2_adc0, wlan2_adc1,
134
135- bias-disable:
136 Usage: optional
137 Value type: <none>
138 Definition: The specified pins should be configued as no pull.
139
140- bias-pull-down:
141 Usage: optional
142 Value type: <none>
143 Definition: The specified pins should be configued as pull down.
144
145- bias-pull-up:
146 Usage: optional
147 Value type: <none>
148 Definition: The specified pins should be configued as pull up.
149
150- output-high:
151 Usage: optional
152 Value type: <none>
153 Definition: The specified pins are configured in output mode, driven
154 high.
155 Not valid for sdc pins.
156
157- output-low:
158 Usage: optional
159 Value type: <none>
160 Definition: The specified pins are configured in output mode, driven
161 low.
162 Not valid for sdc pins.
163
164- drive-strength:
165 Usage: optional
166 Value type: <u32>
167 Definition: Selects the drive strength for the specified pins, in mA.
168 Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
169
170Example:
171
172 tlmm: pinctrl@03400000 {
173 compatible = "qcom,msm8998-pinctrl";
174 reg = <0x03400000 0xc00000>;
175 interrupts = <0 208 0>;
176 gpio-controller;
177 #gpio-cells = <2>;
178 interrupt-controller;
179 #interrupt-cells = <2>;
180
181 uart_console_active: uart_console_active {
182 mux {
183 pins = "gpio4", "gpio5";
184 function = "blsp_uart8_a";
185 };
186
187 config {
188 pins = "gpio4", "gpio5";
189 drive-strength = <2>;
190 bias-disable;
191 };
192 };
193 };
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
index 9b4f8041c36a..bb1790e0b176 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -24,6 +24,7 @@ Required Properties:
24 - "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller. 24 - "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
25 - "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller. 25 - "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller.
26 - "renesas,pfc-r8a7796": for R8A7796 (R-Car M3-W) compatible pin-controller. 26 - "renesas,pfc-r8a7796": for R8A7796 (R-Car M3-W) compatible pin-controller.
27 - "renesas,pfc-r8a77970": for R8A77970 (R-Car V3M) compatible pin-controller.
27 - "renesas,pfc-r8a77995": for R8A77995 (R-Car D3) compatible pin-controller. 28 - "renesas,pfc-r8a77995": for R8A77995 (R-Car D3) compatible pin-controller.
28 - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller. 29 - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
29 30
diff --git a/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.txt
new file mode 100644
index 000000000000..8173b12138ad
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.txt
@@ -0,0 +1,27 @@
1UniPhier SoCs pin controller
2
3Required properties:
4- compatible: should be one of the following:
5 "socionext,uniphier-ld4-pinctrl" - for LD4 SoC
6 "socionext,uniphier-pro4-pinctrl" - for Pro4 SoC
7 "socionext,uniphier-sld8-pinctrl" - for sLD8 SoC
8 "socionext,uniphier-pro5-pinctrl" - for Pro5 SoC
9 "socionext,uniphier-pxs2-pinctrl" - for PXs2 SoC
10 "socionext,uniphier-ld6b-pinctrl" - for LD6b SoC
11 "socionext,uniphier-ld11-pinctrl" - for LD11 SoC
12 "socionext,uniphier-ld20-pinctrl" - for LD20 SoC
13 "socionext,uniphier-pxs3-pinctrl" - for PXs3 SoC
14
15Note:
16The UniPhier pinctrl should be a subnode of a "syscon" compatible node.
17
18Example:
19 soc-glue@5f800000 {
20 compatible = "socionext,uniphier-pro4-soc-glue",
21 "simple-mfd", "syscon";
22 reg = <0x5f800000 0x2000>;
23
24 pinctrl: pinctrl {
25 compatible = "socionext,uniphier-pro4-pinctrl";
26 };
27 };
diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
index 58c2a4c229db..2c46f30b62c5 100644
--- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
@@ -12,6 +12,8 @@ Required properies:
12 "st,stm32f469-pinctrl" 12 "st,stm32f469-pinctrl"
13 "st,stm32f746-pinctrl" 13 "st,stm32f746-pinctrl"
14 "st,stm32h743-pinctrl" 14 "st,stm32h743-pinctrl"
15 "st,stm32mp157-pinctrl"
16 "st,stm32mp157-z-pinctrl"
15 - #address-cells: The value of this property must be 1 17 - #address-cells: The value of this property must be 1
16 - #size-cells : The value of this property must be 1 18 - #size-cells : The value of this property must be 1
17 - ranges : defines mapping between pin controller node (parent) to 19 - ranges : defines mapping between pin controller node (parent) to
diff --git a/MAINTAINERS b/MAINTAINERS
index 1dc846d0add6..cd0e9c763bd8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2086,6 +2086,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
2086T: git git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier.git 2086T: git git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier.git
2087S: Maintained 2087S: Maintained
2088F: Documentation/devicetree/bindings/gpio/gpio-uniphier.txt 2088F: Documentation/devicetree/bindings/gpio/gpio-uniphier.txt
2089F: Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.txt
2089F: arch/arm/boot/dts/uniphier* 2090F: arch/arm/boot/dts/uniphier*
2090F: arch/arm/include/asm/hardware/cache-uniphier.h 2091F: arch/arm/include/asm/hardware/cache-uniphier.h
2091F: arch/arm/mach-uniphier/ 2092F: arch/arm/mach-uniphier/
@@ -10875,6 +10876,16 @@ M: Heikki Krogerus <heikki.krogerus@linux.intel.com>
10875S: Maintained 10876S: Maintained
10876F: drivers/pinctrl/intel/ 10877F: drivers/pinctrl/intel/
10877 10878
10879PIN CONTROLLER - MEDIATEK
10880M: Sean Wang <sean.wang@mediatek.com>
10881L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
10882S: Maintained
10883F: Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
10884F: Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt
10885F: drivers/pinctrl/mediatek/pinctrl-mtk-common.*
10886F: drivers/pinctrl/mediatek/pinctrl-mt2701.c
10887F: drivers/pinctrl/mediatek/pinctrl-mt7622.c
10888
10878PIN CONTROLLER - QUALCOMM 10889PIN CONTROLLER - QUALCOMM
10879M: Bjorn Andersson <bjorn.andersson@linaro.org> 10890M: Bjorn Andersson <bjorn.andersson@linaro.org>
10880S: Maintained 10891S: Maintained
diff --git a/drivers/gpio/gpio-uniphier.c b/drivers/gpio/gpio-uniphier.c
index 016d7427ebfa..761d8279abca 100644
--- a/drivers/gpio/gpio-uniphier.c
+++ b/drivers/gpio/gpio-uniphier.c
@@ -505,4 +505,4 @@ module_platform_driver(uniphier_gpio_driver);
505 505
506MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>"); 506MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
507MODULE_DESCRIPTION("UniPhier GPIO driver"); 507MODULE_DESCRIPTION("UniPhier GPIO driver");
508MODULE_LICENSE("GPL"); 508MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpio/gpiolib-acpi.c b/drivers/gpio/gpiolib-acpi.c
index 0ecffd172a80..e2232cbcec8b 100644
--- a/drivers/gpio/gpiolib-acpi.c
+++ b/drivers/gpio/gpiolib-acpi.c
@@ -58,58 +58,6 @@ static int acpi_gpiochip_find(struct gpio_chip *gc, void *data)
58 return ACPI_HANDLE(gc->parent) == data; 58 return ACPI_HANDLE(gc->parent) == data;
59} 59}
60 60
61#ifdef CONFIG_PINCTRL
62/**
63 * acpi_gpiochip_pin_to_gpio_offset() - translates ACPI GPIO to Linux GPIO
64 * @gdev: GPIO device
65 * @pin: ACPI GPIO pin number from GpioIo/GpioInt resource
66 *
67 * Function takes ACPI GpioIo/GpioInt pin number as a parameter and
68 * translates it to a corresponding offset suitable to be passed to a
69 * GPIO controller driver.
70 *
71 * Typically the returned offset is same as @pin, but if the GPIO
72 * controller uses pin controller and the mapping is not contiguous the
73 * offset might be different.
74 */
75static int acpi_gpiochip_pin_to_gpio_offset(struct gpio_device *gdev, int pin)
76{
77 struct gpio_pin_range *pin_range;
78
79 /* If there are no ranges in this chip, use 1:1 mapping */
80 if (list_empty(&gdev->pin_ranges))
81 return pin;
82
83 list_for_each_entry(pin_range, &gdev->pin_ranges, node) {
84 const struct pinctrl_gpio_range *range = &pin_range->range;
85 int i;
86
87 if (range->pins) {
88 for (i = 0; i < range->npins; i++) {
89 if (range->pins[i] == pin)
90 return range->base + i - gdev->base;
91 }
92 } else {
93 if (pin >= range->pin_base &&
94 pin < range->pin_base + range->npins) {
95 unsigned gpio_base;
96
97 gpio_base = range->base - gdev->base;
98 return gpio_base + pin - range->pin_base;
99 }
100 }
101 }
102
103 return -EINVAL;
104}
105#else
106static inline int acpi_gpiochip_pin_to_gpio_offset(struct gpio_device *gdev,
107 int pin)
108{
109 return pin;
110}
111#endif
112
113/** 61/**
114 * acpi_get_gpiod() - Translate ACPI GPIO pin to GPIO descriptor usable with GPIO API 62 * acpi_get_gpiod() - Translate ACPI GPIO pin to GPIO descriptor usable with GPIO API
115 * @path: ACPI GPIO controller full path name, (e.g. "\\_SB.GPO1") 63 * @path: ACPI GPIO controller full path name, (e.g. "\\_SB.GPO1")
@@ -125,7 +73,6 @@ static struct gpio_desc *acpi_get_gpiod(char *path, int pin)
125 struct gpio_chip *chip; 73 struct gpio_chip *chip;
126 acpi_handle handle; 74 acpi_handle handle;
127 acpi_status status; 75 acpi_status status;
128 int offset;
129 76
130 status = acpi_get_handle(NULL, path, &handle); 77 status = acpi_get_handle(NULL, path, &handle);
131 if (ACPI_FAILURE(status)) 78 if (ACPI_FAILURE(status))
@@ -135,11 +82,7 @@ static struct gpio_desc *acpi_get_gpiod(char *path, int pin)
135 if (!chip) 82 if (!chip)
136 return ERR_PTR(-EPROBE_DEFER); 83 return ERR_PTR(-EPROBE_DEFER);
137 84
138 offset = acpi_gpiochip_pin_to_gpio_offset(chip->gpiodev, pin); 85 return gpiochip_get_desc(chip, pin);
139 if (offset < 0)
140 return ERR_PTR(offset);
141
142 return gpiochip_get_desc(chip, offset);
143} 86}
144 87
145static irqreturn_t acpi_gpio_irq_handler(int irq, void *data) 88static irqreturn_t acpi_gpio_irq_handler(int irq, void *data)
@@ -216,10 +159,6 @@ static acpi_status acpi_gpiochip_request_interrupt(struct acpi_resource *ares,
216 if (!handler) 159 if (!handler)
217 return AE_OK; 160 return AE_OK;
218 161
219 pin = acpi_gpiochip_pin_to_gpio_offset(chip->gpiodev, pin);
220 if (pin < 0)
221 return AE_BAD_PARAMETER;
222
223 desc = gpiochip_request_own_desc(chip, pin, "ACPI:Event"); 162 desc = gpiochip_request_own_desc(chip, pin, "ACPI:Event");
224 if (IS_ERR(desc)) { 163 if (IS_ERR(desc)) {
225 dev_err(chip->parent, "Failed to request GPIO\n"); 164 dev_err(chip->parent, "Failed to request GPIO\n");
@@ -871,12 +810,6 @@ acpi_gpio_adr_space_handler(u32 function, acpi_physical_address address,
871 struct gpio_desc *desc; 810 struct gpio_desc *desc;
872 bool found; 811 bool found;
873 812
874 pin = acpi_gpiochip_pin_to_gpio_offset(chip->gpiodev, pin);
875 if (pin < 0) {
876 status = AE_BAD_PARAMETER;
877 goto out;
878 }
879
880 mutex_lock(&achip->conn_lock); 813 mutex_lock(&achip->conn_lock);
881 814
882 found = false; 815 found = false;
@@ -1009,11 +942,7 @@ static struct gpio_desc *acpi_gpiochip_parse_own_gpio(
1009 if (ret < 0) 942 if (ret < 0)
1010 return ERR_PTR(ret); 943 return ERR_PTR(ret);
1011 944
1012 ret = acpi_gpiochip_pin_to_gpio_offset(chip->gpiodev, gpios[0]); 945 desc = gpiochip_get_desc(chip, gpios[0]);
1013 if (ret < 0)
1014 return ERR_PTR(ret);
1015
1016 desc = gpiochip_get_desc(chip, ret);
1017 if (IS_ERR(desc)) 946 if (IS_ERR(desc))
1018 return desc; 947 return desc;
1019 948
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index ce126955212c..0f254b35c378 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -66,6 +66,10 @@ config PINCTRL_AS3722
66config PINCTRL_AXP209 66config PINCTRL_AXP209
67 tristate "X-Powers AXP209 PMIC pinctrl and GPIO Support" 67 tristate "X-Powers AXP209 PMIC pinctrl and GPIO Support"
68 depends on MFD_AXP20X 68 depends on MFD_AXP20X
69 depends on OF
70 select PINMUX
71 select GENERIC_PINCONF
72 select GPIOLIB
69 help 73 help
70 AXP PMICs provides multiple GPIOs that can be muxed for different 74 AXP PMICs provides multiple GPIOs that can be muxed for different
71 functions. This driver bundles a pinctrl driver to select the function 75 functions. This driver bundles a pinctrl driver to select the function
@@ -353,6 +357,17 @@ config PINCTRL_RK805
353 help 357 help
354 This selects the pinctrl driver for RK805. 358 This selects the pinctrl driver for RK805.
355 359
360config PINCTRL_OCELOT
361 bool "Pinctrl driver for the Microsemi Ocelot SoCs"
362 default y
363 depends on OF
364 depends on MSCC_OCELOT || COMPILE_TEST
365 select GPIOLIB
366 select GENERIC_PINCONF
367 select GENERIC_PINCTRL_GROUPS
368 select GENERIC_PINMUX_FUNCTIONS
369 select REGMAP_MMIO
370
356source "drivers/pinctrl/aspeed/Kconfig" 371source "drivers/pinctrl/aspeed/Kconfig"
357source "drivers/pinctrl/bcm/Kconfig" 372source "drivers/pinctrl/bcm/Kconfig"
358source "drivers/pinctrl/berlin/Kconfig" 373source "drivers/pinctrl/berlin/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 4777f1595ce2..d3692633e9ed 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
46obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o 46obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o
47obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o 47obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o
48obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o 48obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o
49obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o
49 50
50obj-$(CONFIG_ARCH_ASPEED) += aspeed/ 51obj-$(CONFIG_ARCH_ASPEED) += aspeed/
51obj-y += bcm/ 52obj-y += bcm/
@@ -65,5 +66,5 @@ obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/
65obj-y += ti/ 66obj-y += ti/
66obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ 67obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
67obj-$(CONFIG_ARCH_VT8500) += vt8500/ 68obj-$(CONFIG_ARCH_VT8500) += vt8500/
68obj-$(CONFIG_PINCTRL_MTK) += mediatek/ 69obj-y += mediatek/
69obj-$(CONFIG_PINCTRL_ZX) += zte/ 70obj-$(CONFIG_PINCTRL_ZX) += zte/
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index 4c8d5b23e4d0..2c0dbfcff3e6 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -1189,19 +1189,16 @@ struct pinctrl_state *pinctrl_lookup_state(struct pinctrl *p,
1189EXPORT_SYMBOL_GPL(pinctrl_lookup_state); 1189EXPORT_SYMBOL_GPL(pinctrl_lookup_state);
1190 1190
1191/** 1191/**
1192 * pinctrl_select_state() - select/activate/program a pinctrl state to HW 1192 * pinctrl_commit_state() - select/activate/program a pinctrl state to HW
1193 * @p: the pinctrl handle for the device that requests configuration 1193 * @p: the pinctrl handle for the device that requests configuration
1194 * @state: the state handle to select/activate/program 1194 * @state: the state handle to select/activate/program
1195 */ 1195 */
1196int pinctrl_select_state(struct pinctrl *p, struct pinctrl_state *state) 1196static int pinctrl_commit_state(struct pinctrl *p, struct pinctrl_state *state)
1197{ 1197{
1198 struct pinctrl_setting *setting, *setting2; 1198 struct pinctrl_setting *setting, *setting2;
1199 struct pinctrl_state *old_state = p->state; 1199 struct pinctrl_state *old_state = p->state;
1200 int ret; 1200 int ret;
1201 1201
1202 if (p->state == state)
1203 return 0;
1204
1205 if (p->state) { 1202 if (p->state) {
1206 /* 1203 /*
1207 * For each pinmux setting in the old state, forget SW's record 1204 * For each pinmux setting in the old state, forget SW's record
@@ -1265,6 +1262,19 @@ unapply_new_state:
1265 1262
1266 return ret; 1263 return ret;
1267} 1264}
1265
1266/**
1267 * pinctrl_select_state() - select/activate/program a pinctrl state to HW
1268 * @p: the pinctrl handle for the device that requests configuration
1269 * @state: the state handle to select/activate/program
1270 */
1271int pinctrl_select_state(struct pinctrl *p, struct pinctrl_state *state)
1272{
1273 if (p->state == state)
1274 return 0;
1275
1276 return pinctrl_commit_state(p, state);
1277}
1268EXPORT_SYMBOL_GPL(pinctrl_select_state); 1278EXPORT_SYMBOL_GPL(pinctrl_select_state);
1269 1279
1270static void devm_pinctrl_release(struct device *dev, void *res) 1280static void devm_pinctrl_release(struct device *dev, void *res)
@@ -1430,7 +1440,7 @@ void pinctrl_unregister_map(const struct pinctrl_map *map)
1430int pinctrl_force_sleep(struct pinctrl_dev *pctldev) 1440int pinctrl_force_sleep(struct pinctrl_dev *pctldev)
1431{ 1441{
1432 if (!IS_ERR(pctldev->p) && !IS_ERR(pctldev->hog_sleep)) 1442 if (!IS_ERR(pctldev->p) && !IS_ERR(pctldev->hog_sleep))
1433 return pinctrl_select_state(pctldev->p, pctldev->hog_sleep); 1443 return pinctrl_commit_state(pctldev->p, pctldev->hog_sleep);
1434 return 0; 1444 return 0;
1435} 1445}
1436EXPORT_SYMBOL_GPL(pinctrl_force_sleep); 1446EXPORT_SYMBOL_GPL(pinctrl_force_sleep);
@@ -1442,7 +1452,7 @@ EXPORT_SYMBOL_GPL(pinctrl_force_sleep);
1442int pinctrl_force_default(struct pinctrl_dev *pctldev) 1452int pinctrl_force_default(struct pinctrl_dev *pctldev)
1443{ 1453{
1444 if (!IS_ERR(pctldev->p) && !IS_ERR(pctldev->hog_default)) 1454 if (!IS_ERR(pctldev->p) && !IS_ERR(pctldev->hog_default))
1445 return pinctrl_select_state(pctldev->p, pctldev->hog_default); 1455 return pinctrl_commit_state(pctldev->p, pctldev->hog_default);
1446 return 0; 1456 return 0;
1447} 1457}
1448EXPORT_SYMBOL_GPL(pinctrl_force_default); 1458EXPORT_SYMBOL_GPL(pinctrl_force_default);
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
index 6e472691d8ee..24aaddd760a0 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -62,7 +62,6 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
62 struct pinctrl_map **map, unsigned *num_maps) 62 struct pinctrl_map **map, unsigned *num_maps)
63{ 63{
64 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 64 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
65 struct imx_pinctrl_soc_info *info = ipctl->info;
66 const struct group_desc *grp; 65 const struct group_desc *grp;
67 struct pinctrl_map *new_map; 66 struct pinctrl_map *new_map;
68 struct device_node *parent; 67 struct device_node *parent;
@@ -75,7 +74,7 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
75 */ 74 */
76 grp = imx_pinctrl_find_group_by_name(pctldev, np->name); 75 grp = imx_pinctrl_find_group_by_name(pctldev, np->name);
77 if (!grp) { 76 if (!grp) {
78 dev_err(info->dev, "unable to find group for node %s\n", 77 dev_err(ipctl->dev, "unable to find group for node %s\n",
79 np->name); 78 np->name);
80 return -EINVAL; 79 return -EINVAL;
81 } 80 }
@@ -146,7 +145,7 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
146 unsigned group) 145 unsigned group)
147{ 146{
148 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 147 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
149 struct imx_pinctrl_soc_info *info = ipctl->info; 148 const struct imx_pinctrl_soc_info *info = ipctl->info;
150 const struct imx_pin_reg *pin_reg; 149 const struct imx_pin_reg *pin_reg;
151 unsigned int npins, pin_id; 150 unsigned int npins, pin_id;
152 int i; 151 int i;
@@ -174,7 +173,7 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
174 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; 173 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
175 174
176 pin_id = pin->pin; 175 pin_id = pin->pin;
177 pin_reg = &info->pin_regs[pin_id]; 176 pin_reg = &ipctl->pin_regs[pin_id];
178 177
179 if (pin_reg->mux_reg == -1) { 178 if (pin_reg->mux_reg == -1) {
180 dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n", 179 dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n",
@@ -255,8 +254,8 @@ static u32 imx_pinconf_decode_generic_config(struct imx_pinctrl *ipctl,
255 unsigned long *configs, 254 unsigned long *configs,
256 unsigned int num_configs) 255 unsigned int num_configs)
257{ 256{
258 struct imx_pinctrl_soc_info *info = ipctl->info; 257 const struct imx_pinctrl_soc_info *info = ipctl->info;
259 struct imx_cfg_params_decode *decode; 258 const struct imx_cfg_params_decode *decode;
260 enum pin_config_param param; 259 enum pin_config_param param;
261 u32 raw_config = 0; 260 u32 raw_config = 0;
262 u32 param_val; 261 u32 param_val;
@@ -289,7 +288,7 @@ static u32 imx_pinconf_decode_generic_config(struct imx_pinctrl *ipctl,
289static u32 imx_pinconf_parse_generic_config(struct device_node *np, 288static u32 imx_pinconf_parse_generic_config(struct device_node *np,
290 struct imx_pinctrl *ipctl) 289 struct imx_pinctrl *ipctl)
291{ 290{
292 struct imx_pinctrl_soc_info *info = ipctl->info; 291 const struct imx_pinctrl_soc_info *info = ipctl->info;
293 struct pinctrl_dev *pctl = ipctl->pctl; 292 struct pinctrl_dev *pctl = ipctl->pctl;
294 unsigned int num_configs; 293 unsigned int num_configs;
295 unsigned long *configs; 294 unsigned long *configs;
@@ -310,11 +309,11 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev,
310 unsigned pin_id, unsigned long *config) 309 unsigned pin_id, unsigned long *config)
311{ 310{
312 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 311 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
313 struct imx_pinctrl_soc_info *info = ipctl->info; 312 const struct imx_pinctrl_soc_info *info = ipctl->info;
314 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; 313 const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
315 314
316 if (pin_reg->conf_reg == -1) { 315 if (pin_reg->conf_reg == -1) {
317 dev_err(info->dev, "Pin(%s) does not support config function\n", 316 dev_err(ipctl->dev, "Pin(%s) does not support config function\n",
318 info->pins[pin_id].name); 317 info->pins[pin_id].name);
319 return -EINVAL; 318 return -EINVAL;
320 } 319 }
@@ -332,12 +331,12 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev,
332 unsigned num_configs) 331 unsigned num_configs)
333{ 332{
334 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 333 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
335 struct imx_pinctrl_soc_info *info = ipctl->info; 334 const struct imx_pinctrl_soc_info *info = ipctl->info;
336 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; 335 const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
337 int i; 336 int i;
338 337
339 if (pin_reg->conf_reg == -1) { 338 if (pin_reg->conf_reg == -1) {
340 dev_err(info->dev, "Pin(%s) does not support config function\n", 339 dev_err(ipctl->dev, "Pin(%s) does not support config function\n",
341 info->pins[pin_id].name); 340 info->pins[pin_id].name);
342 return -EINVAL; 341 return -EINVAL;
343 } 342 }
@@ -368,8 +367,7 @@ static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
368 struct seq_file *s, unsigned pin_id) 367 struct seq_file *s, unsigned pin_id)
369{ 368{
370 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 369 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
371 struct imx_pinctrl_soc_info *info = ipctl->info; 370 const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
372 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
373 unsigned long config; 371 unsigned long config;
374 372
375 if (!pin_reg || pin_reg->conf_reg == -1) { 373 if (!pin_reg || pin_reg->conf_reg == -1) {
@@ -427,13 +425,13 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
427 struct imx_pinctrl *ipctl, 425 struct imx_pinctrl *ipctl,
428 u32 index) 426 u32 index)
429{ 427{
430 struct imx_pinctrl_soc_info *info = ipctl->info; 428 const struct imx_pinctrl_soc_info *info = ipctl->info;
431 int size, pin_size; 429 int size, pin_size;
432 const __be32 *list; 430 const __be32 *list;
433 int i; 431 int i;
434 u32 config; 432 u32 config;
435 433
436 dev_dbg(info->dev, "group(%d): %s\n", index, np->name); 434 dev_dbg(ipctl->dev, "group(%d): %s\n", index, np->name);
437 435
438 if (info->flags & SHARE_MUX_CONF_REG) 436 if (info->flags & SHARE_MUX_CONF_REG)
439 pin_size = SHARE_FSL_PIN_SIZE; 437 pin_size = SHARE_FSL_PIN_SIZE;
@@ -460,7 +458,7 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
460 if (!list) { 458 if (!list) {
461 list = of_get_property(np, "pinmux", &size); 459 list = of_get_property(np, "pinmux", &size);
462 if (!list) { 460 if (!list) {
463 dev_err(info->dev, 461 dev_err(ipctl->dev,
464 "no fsl,pins and pins property in node %pOF\n", np); 462 "no fsl,pins and pins property in node %pOF\n", np);
465 return -EINVAL; 463 return -EINVAL;
466 } 464 }
@@ -468,7 +466,7 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
468 466
469 /* we do not check return since it's safe node passed down */ 467 /* we do not check return since it's safe node passed down */
470 if (!size || size % pin_size) { 468 if (!size || size % pin_size) {
471 dev_err(info->dev, "Invalid fsl,pins or pins property in node %pOF\n", np); 469 dev_err(ipctl->dev, "Invalid fsl,pins or pins property in node %pOF\n", np);
472 return -EINVAL; 470 return -EINVAL;
473 } 471 }
474 472
@@ -476,9 +474,9 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
476 config = imx_pinconf_parse_generic_config(np, ipctl); 474 config = imx_pinconf_parse_generic_config(np, ipctl);
477 475
478 grp->num_pins = size / pin_size; 476 grp->num_pins = size / pin_size;
479 grp->data = devm_kzalloc(info->dev, grp->num_pins * 477 grp->data = devm_kzalloc(ipctl->dev, grp->num_pins *
480 sizeof(struct imx_pin), GFP_KERNEL); 478 sizeof(struct imx_pin), GFP_KERNEL);
481 grp->pins = devm_kzalloc(info->dev, grp->num_pins * 479 grp->pins = devm_kzalloc(ipctl->dev, grp->num_pins *
482 sizeof(unsigned int), GFP_KERNEL); 480 sizeof(unsigned int), GFP_KERNEL);
483 if (!grp->pins || !grp->data) 481 if (!grp->pins || !grp->data)
484 return -ENOMEM; 482 return -ENOMEM;
@@ -502,7 +500,7 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
502 } 500 }
503 501
504 pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4; 502 pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
505 pin_reg = &info->pin_regs[pin_id]; 503 pin_reg = &ipctl->pin_regs[pin_id];
506 pin->pin = pin_id; 504 pin->pin = pin_id;
507 grp->pins[i] = pin_id; 505 grp->pins[i] = pin_id;
508 pin_reg->mux_reg = mux_reg; 506 pin_reg->mux_reg = mux_reg;
@@ -524,7 +522,7 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
524 pin->config = config & ~IMX_PAD_SION; 522 pin->config = config & ~IMX_PAD_SION;
525 } 523 }
526 524
527 dev_dbg(info->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name, 525 dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name,
528 pin->mux_mode, pin->config); 526 pin->mux_mode, pin->config);
529 } 527 }
530 528
@@ -536,13 +534,12 @@ static int imx_pinctrl_parse_functions(struct device_node *np,
536 u32 index) 534 u32 index)
537{ 535{
538 struct pinctrl_dev *pctl = ipctl->pctl; 536 struct pinctrl_dev *pctl = ipctl->pctl;
539 struct imx_pinctrl_soc_info *info = ipctl->info;
540 struct device_node *child; 537 struct device_node *child;
541 struct function_desc *func; 538 struct function_desc *func;
542 struct group_desc *grp; 539 struct group_desc *grp;
543 u32 i = 0; 540 u32 i = 0;
544 541
545 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); 542 dev_dbg(pctl->dev, "parse function(%d): %s\n", index, np->name);
546 543
547 func = pinmux_generic_get_function(pctl, index); 544 func = pinmux_generic_get_function(pctl, index);
548 if (!func) 545 if (!func)
@@ -552,10 +549,10 @@ static int imx_pinctrl_parse_functions(struct device_node *np,
552 func->name = np->name; 549 func->name = np->name;
553 func->num_group_names = of_get_child_count(np); 550 func->num_group_names = of_get_child_count(np);
554 if (func->num_group_names == 0) { 551 if (func->num_group_names == 0) {
555 dev_err(info->dev, "no groups defined in %pOF\n", np); 552 dev_err(ipctl->dev, "no groups defined in %pOF\n", np);
556 return -EINVAL; 553 return -EINVAL;
557 } 554 }
558 func->group_names = devm_kcalloc(info->dev, func->num_group_names, 555 func->group_names = devm_kcalloc(ipctl->dev, func->num_group_names,
559 sizeof(char *), GFP_KERNEL); 556 sizeof(char *), GFP_KERNEL);
560 if (!func->group_names) 557 if (!func->group_names)
561 return -ENOMEM; 558 return -ENOMEM;
@@ -563,15 +560,15 @@ static int imx_pinctrl_parse_functions(struct device_node *np,
563 for_each_child_of_node(np, child) { 560 for_each_child_of_node(np, child) {
564 func->group_names[i] = child->name; 561 func->group_names[i] = child->name;
565 562
566 grp = devm_kzalloc(info->dev, sizeof(struct group_desc), 563 grp = devm_kzalloc(ipctl->dev, sizeof(struct group_desc),
567 GFP_KERNEL); 564 GFP_KERNEL);
568 if (!grp) 565 if (!grp)
569 return -ENOMEM; 566 return -ENOMEM;
570 567
571 mutex_lock(&info->mutex); 568 mutex_lock(&ipctl->mutex);
572 radix_tree_insert(&pctl->pin_group_tree, 569 radix_tree_insert(&pctl->pin_group_tree,
573 info->group_index++, grp); 570 ipctl->group_index++, grp);
574 mutex_unlock(&info->mutex); 571 mutex_unlock(&ipctl->mutex);
575 572
576 imx_pinctrl_parse_groups(child, grp, ipctl, i++); 573 imx_pinctrl_parse_groups(child, grp, ipctl, i++);
577 } 574 }
@@ -608,7 +605,6 @@ static int imx_pinctrl_probe_dt(struct platform_device *pdev,
608 struct device_node *np = pdev->dev.of_node; 605 struct device_node *np = pdev->dev.of_node;
609 struct device_node *child; 606 struct device_node *child;
610 struct pinctrl_dev *pctl = ipctl->pctl; 607 struct pinctrl_dev *pctl = ipctl->pctl;
611 struct imx_pinctrl_soc_info *info = ipctl->info;
612 u32 nfuncs = 0; 608 u32 nfuncs = 0;
613 u32 i = 0; 609 u32 i = 0;
614 bool flat_funcs; 610 bool flat_funcs;
@@ -635,13 +631,13 @@ static int imx_pinctrl_probe_dt(struct platform_device *pdev,
635 if (!function) 631 if (!function)
636 return -ENOMEM; 632 return -ENOMEM;
637 633
638 mutex_lock(&info->mutex); 634 mutex_lock(&ipctl->mutex);
639 radix_tree_insert(&pctl->pin_function_tree, i, function); 635 radix_tree_insert(&pctl->pin_function_tree, i, function);
640 mutex_unlock(&info->mutex); 636 mutex_unlock(&ipctl->mutex);
641 } 637 }
642 pctl->num_functions = nfuncs; 638 pctl->num_functions = nfuncs;
643 639
644 info->group_index = 0; 640 ipctl->group_index = 0;
645 if (flat_funcs) { 641 if (flat_funcs) {
646 pctl->num_groups = of_get_child_count(np); 642 pctl->num_groups = of_get_child_count(np);
647 } else { 643 } else {
@@ -672,7 +668,7 @@ static void imx_free_resources(struct imx_pinctrl *ipctl)
672} 668}
673 669
674int imx_pinctrl_probe(struct platform_device *pdev, 670int imx_pinctrl_probe(struct platform_device *pdev,
675 struct imx_pinctrl_soc_info *info) 671 const struct imx_pinctrl_soc_info *info)
676{ 672{
677 struct regmap_config config = { .name = "gpr" }; 673 struct regmap_config config = { .name = "gpr" };
678 struct device_node *dev_np = pdev->dev.of_node; 674 struct device_node *dev_np = pdev->dev.of_node;
@@ -687,7 +683,6 @@ int imx_pinctrl_probe(struct platform_device *pdev,
687 dev_err(&pdev->dev, "wrong pinctrl info\n"); 683 dev_err(&pdev->dev, "wrong pinctrl info\n");
688 return -EINVAL; 684 return -EINVAL;
689 } 685 }
690 info->dev = &pdev->dev;
691 686
692 if (info->gpr_compatible) { 687 if (info->gpr_compatible) {
693 gpr = syscon_regmap_lookup_by_compatible(info->gpr_compatible); 688 gpr = syscon_regmap_lookup_by_compatible(info->gpr_compatible);
@@ -700,14 +695,14 @@ int imx_pinctrl_probe(struct platform_device *pdev,
700 if (!ipctl) 695 if (!ipctl)
701 return -ENOMEM; 696 return -ENOMEM;
702 697
703 info->pin_regs = devm_kmalloc(&pdev->dev, sizeof(*info->pin_regs) * 698 ipctl->pin_regs = devm_kmalloc(&pdev->dev, sizeof(*ipctl->pin_regs) *
704 info->npins, GFP_KERNEL); 699 info->npins, GFP_KERNEL);
705 if (!info->pin_regs) 700 if (!ipctl->pin_regs)
706 return -ENOMEM; 701 return -ENOMEM;
707 702
708 for (i = 0; i < info->npins; i++) { 703 for (i = 0; i < info->npins; i++) {
709 info->pin_regs[i].mux_reg = -1; 704 ipctl->pin_regs[i].mux_reg = -1;
710 info->pin_regs[i].conf_reg = -1; 705 ipctl->pin_regs[i].conf_reg = -1;
711 } 706 }
712 707
713 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 708 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -751,10 +746,10 @@ int imx_pinctrl_probe(struct platform_device *pdev,
751 /* platform specific callback */ 746 /* platform specific callback */
752 imx_pmx_ops.gpio_set_direction = info->gpio_set_direction; 747 imx_pmx_ops.gpio_set_direction = info->gpio_set_direction;
753 748
754 mutex_init(&info->mutex); 749 mutex_init(&ipctl->mutex);
755 750
756 ipctl->info = info; 751 ipctl->info = info;
757 ipctl->dev = info->dev; 752 ipctl->dev = &pdev->dev;
758 platform_set_drvdata(pdev, ipctl); 753 platform_set_drvdata(pdev, ipctl);
759 ret = devm_pinctrl_register_and_init(&pdev->dev, 754 ret = devm_pinctrl_register_and_init(&pdev->dev,
760 imx_pinctrl_desc, ipctl, 755 imx_pinctrl_desc, ipctl,
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h
index 5aa22b52c1d4..038e8c0e5b96 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -58,14 +58,10 @@ struct imx_cfg_params_decode {
58}; 58};
59 59
60struct imx_pinctrl_soc_info { 60struct imx_pinctrl_soc_info {
61 struct device *dev;
62 const struct pinctrl_pin_desc *pins; 61 const struct pinctrl_pin_desc *pins;
63 unsigned int npins; 62 unsigned int npins;
64 struct imx_pin_reg *pin_regs;
65 unsigned int group_index;
66 unsigned int flags; 63 unsigned int flags;
67 const char *gpr_compatible; 64 const char *gpr_compatible;
68 struct mutex mutex;
69 65
70 /* MUX_MODE shift and mask in case SHARE_MUX_CONF_REG */ 66 /* MUX_MODE shift and mask in case SHARE_MUX_CONF_REG */
71 unsigned int mux_mask; 67 unsigned int mux_mask;
@@ -75,7 +71,7 @@ struct imx_pinctrl_soc_info {
75 bool generic_pinconf; 71 bool generic_pinconf;
76 const struct pinconf_generic_params *custom_params; 72 const struct pinconf_generic_params *custom_params;
77 unsigned int num_custom_params; 73 unsigned int num_custom_params;
78 struct imx_cfg_params_decode *decodes; 74 const struct imx_cfg_params_decode *decodes;
79 unsigned int num_decodes; 75 unsigned int num_decodes;
80 void (*fixup)(unsigned long *configs, unsigned int num_configs, 76 void (*fixup)(unsigned long *configs, unsigned int num_configs,
81 u32 *raw_config); 77 u32 *raw_config);
@@ -95,7 +91,10 @@ struct imx_pinctrl {
95 struct pinctrl_dev *pctl; 91 struct pinctrl_dev *pctl;
96 void __iomem *base; 92 void __iomem *base;
97 void __iomem *input_sel_base; 93 void __iomem *input_sel_base;
98 struct imx_pinctrl_soc_info *info; 94 const struct imx_pinctrl_soc_info *info;
95 struct imx_pin_reg *pin_regs;
96 unsigned int group_index;
97 struct mutex mutex;
99}; 98};
100 99
101#define IMX_CFG_PARAMS_DECODE(p, m, o) \ 100#define IMX_CFG_PARAMS_DECODE(p, m, o) \
@@ -117,5 +116,5 @@ struct imx_pinctrl {
117#define IOMUXC_CONFIG_SION (0x1 << 4) 116#define IOMUXC_CONFIG_SION (0x1 << 4)
118 117
119int imx_pinctrl_probe(struct platform_device *pdev, 118int imx_pinctrl_probe(struct platform_device *pdev,
120 struct imx_pinctrl_soc_info *info); 119 const struct imx_pinctrl_soc_info *info);
121#endif /* __DRIVERS_PINCTRL_IMX_H */ 120#endif /* __DRIVERS_PINCTRL_IMX_H */
diff --git a/drivers/pinctrl/freescale/pinctrl-imx25.c b/drivers/pinctrl/freescale/pinctrl-imx25.c
index d7367fabe712..db6d9d1382f9 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx25.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx25.c
@@ -309,7 +309,7 @@ static const struct pinctrl_pin_desc imx25_pinctrl_pads[] = {
309 IMX_PINCTRL_PIN(MX25_PAD_BOOT_MODE1), 309 IMX_PINCTRL_PIN(MX25_PAD_BOOT_MODE1),
310}; 310};
311 311
312static struct imx_pinctrl_soc_info imx25_pinctrl_info = { 312static const struct imx_pinctrl_soc_info imx25_pinctrl_info = {
313 .pins = imx25_pinctrl_pads, 313 .pins = imx25_pinctrl_pads,
314 .npins = ARRAY_SIZE(imx25_pinctrl_pads), 314 .npins = ARRAY_SIZE(imx25_pinctrl_pads),
315}; 315};
diff --git a/drivers/pinctrl/freescale/pinctrl-imx35.c b/drivers/pinctrl/freescale/pinctrl-imx35.c
index 6315ba6af431..6927946ae4b5 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx35.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx35.c
@@ -999,7 +999,7 @@ static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = {
999 IMX_PINCTRL_PIN(MX35_PAD_TEST_MODE), 999 IMX_PINCTRL_PIN(MX35_PAD_TEST_MODE),
1000}; 1000};
1001 1001
1002static struct imx_pinctrl_soc_info imx35_pinctrl_info = { 1002static const struct imx_pinctrl_soc_info imx35_pinctrl_info = {
1003 .pins = imx35_pinctrl_pads, 1003 .pins = imx35_pinctrl_pads,
1004 .npins = ARRAY_SIZE(imx35_pinctrl_pads), 1004 .npins = ARRAY_SIZE(imx35_pinctrl_pads),
1005}; 1005};
diff --git a/drivers/pinctrl/freescale/pinctrl-imx50.c b/drivers/pinctrl/freescale/pinctrl-imx50.c
index 8e3a17df5c5d..eb349b97290f 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx50.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx50.c
@@ -385,7 +385,7 @@ static const struct pinctrl_pin_desc imx50_pinctrl_pads[] = {
385 IMX_PINCTRL_PIN(MX50_PAD_EIM_CRE), 385 IMX_PINCTRL_PIN(MX50_PAD_EIM_CRE),
386}; 386};
387 387
388static struct imx_pinctrl_soc_info imx50_pinctrl_info = { 388static const struct imx_pinctrl_soc_info imx50_pinctrl_info = {
389 .pins = imx50_pinctrl_pads, 389 .pins = imx50_pinctrl_pads,
390 .npins = ARRAY_SIZE(imx50_pinctrl_pads), 390 .npins = ARRAY_SIZE(imx50_pinctrl_pads),
391 .gpr_compatible = "fsl,imx50-iomuxc-gpr", 391 .gpr_compatible = "fsl,imx50-iomuxc-gpr",
diff --git a/drivers/pinctrl/freescale/pinctrl-imx51.c b/drivers/pinctrl/freescale/pinctrl-imx51.c
index eeac64ba2709..49acd991b5fb 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx51.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx51.c
@@ -762,7 +762,7 @@ static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = {
762 IMX_PINCTRL_PIN(MX51_PAD_CSI1_MCLK), 762 IMX_PINCTRL_PIN(MX51_PAD_CSI1_MCLK),
763}; 763};
764 764
765static struct imx_pinctrl_soc_info imx51_pinctrl_info = { 765static const struct imx_pinctrl_soc_info imx51_pinctrl_info = {
766 .pins = imx51_pinctrl_pads, 766 .pins = imx51_pinctrl_pads,
767 .npins = ARRAY_SIZE(imx51_pinctrl_pads), 767 .npins = ARRAY_SIZE(imx51_pinctrl_pads),
768}; 768};
diff --git a/drivers/pinctrl/freescale/pinctrl-imx53.c b/drivers/pinctrl/freescale/pinctrl-imx53.c
index 46a9572f3473..6dd0c60eaea4 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx53.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx53.c
@@ -448,7 +448,7 @@ static const struct pinctrl_pin_desc imx53_pinctrl_pads[] = {
448 IMX_PINCTRL_PIN(MX53_PAD_GPIO_18), 448 IMX_PINCTRL_PIN(MX53_PAD_GPIO_18),
449}; 449};
450 450
451static struct imx_pinctrl_soc_info imx53_pinctrl_info = { 451static const struct imx_pinctrl_soc_info imx53_pinctrl_info = {
452 .pins = imx53_pinctrl_pads, 452 .pins = imx53_pinctrl_pads,
453 .npins = ARRAY_SIZE(imx53_pinctrl_pads), 453 .npins = ARRAY_SIZE(imx53_pinctrl_pads),
454 .gpr_compatible = "fsl,imx53-iomuxc-gpr", 454 .gpr_compatible = "fsl,imx53-iomuxc-gpr",
diff --git a/drivers/pinctrl/freescale/pinctrl-imx6dl.c b/drivers/pinctrl/freescale/pinctrl-imx6dl.c
index 3f25ca5867cc..91b85fc01de8 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx6dl.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6dl.c
@@ -457,7 +457,7 @@ static const struct pinctrl_pin_desc imx6dl_pinctrl_pads[] = {
457 IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT7), 457 IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT7),
458}; 458};
459 459
460static struct imx_pinctrl_soc_info imx6dl_pinctrl_info = { 460static const struct imx_pinctrl_soc_info imx6dl_pinctrl_info = {
461 .pins = imx6dl_pinctrl_pads, 461 .pins = imx6dl_pinctrl_pads,
462 .npins = ARRAY_SIZE(imx6dl_pinctrl_pads), 462 .npins = ARRAY_SIZE(imx6dl_pinctrl_pads),
463 .gpr_compatible = "fsl,imx6q-iomuxc-gpr", 463 .gpr_compatible = "fsl,imx6q-iomuxc-gpr",
diff --git a/drivers/pinctrl/freescale/pinctrl-imx6q.c b/drivers/pinctrl/freescale/pinctrl-imx6q.c
index d61651c40458..5f653d69d0f5 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx6q.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6q.c
@@ -460,7 +460,7 @@ static const struct pinctrl_pin_desc imx6q_pinctrl_pads[] = {
460 IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT3), 460 IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT3),
461}; 461};
462 462
463static struct imx_pinctrl_soc_info imx6q_pinctrl_info = { 463static const struct imx_pinctrl_soc_info imx6q_pinctrl_info = {
464 .pins = imx6q_pinctrl_pads, 464 .pins = imx6q_pinctrl_pads,
465 .npins = ARRAY_SIZE(imx6q_pinctrl_pads), 465 .npins = ARRAY_SIZE(imx6q_pinctrl_pads),
466 .gpr_compatible = "fsl,imx6q-iomuxc-gpr", 466 .gpr_compatible = "fsl,imx6q-iomuxc-gpr",
diff --git a/drivers/pinctrl/freescale/pinctrl-imx6sl.c b/drivers/pinctrl/freescale/pinctrl-imx6sl.c
index d023f6b00623..1167dc273c04 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx6sl.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6sl.c
@@ -363,7 +363,7 @@ static const struct pinctrl_pin_desc imx6sl_pinctrl_pads[] = {
363 IMX_PINCTRL_PIN(MX6SL_PAD_WDOG_B), 363 IMX_PINCTRL_PIN(MX6SL_PAD_WDOG_B),
364}; 364};
365 365
366static struct imx_pinctrl_soc_info imx6sl_pinctrl_info = { 366static const struct imx_pinctrl_soc_info imx6sl_pinctrl_info = {
367 .pins = imx6sl_pinctrl_pads, 367 .pins = imx6sl_pinctrl_pads,
368 .npins = ARRAY_SIZE(imx6sl_pinctrl_pads), 368 .npins = ARRAY_SIZE(imx6sl_pinctrl_pads),
369 .gpr_compatible = "fsl,imx6sl-iomuxc-gpr", 369 .gpr_compatible = "fsl,imx6sl-iomuxc-gpr",
diff --git a/drivers/pinctrl/freescale/pinctrl-imx6sx.c b/drivers/pinctrl/freescale/pinctrl-imx6sx.c
index 898b781701e6..15ea56c75f68 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx6sx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6sx.c
@@ -367,7 +367,7 @@ static const struct pinctrl_pin_desc imx6sx_pinctrl_pads[] = {
367 IMX_PINCTRL_PIN(MX6SX_PAD_USB_H_STROBE), 367 IMX_PINCTRL_PIN(MX6SX_PAD_USB_H_STROBE),
368}; 368};
369 369
370static struct imx_pinctrl_soc_info imx6sx_pinctrl_info = { 370static const struct imx_pinctrl_soc_info imx6sx_pinctrl_info = {
371 .pins = imx6sx_pinctrl_pads, 371 .pins = imx6sx_pinctrl_pads,
372 .npins = ARRAY_SIZE(imx6sx_pinctrl_pads), 372 .npins = ARRAY_SIZE(imx6sx_pinctrl_pads),
373 .gpr_compatible = "fsl,imx6sx-iomuxc-gpr", 373 .gpr_compatible = "fsl,imx6sx-iomuxc-gpr",
diff --git a/drivers/pinctrl/freescale/pinctrl-imx6ul.c b/drivers/pinctrl/freescale/pinctrl-imx6ul.c
index 1aeb840aae1d..4580717ade19 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx6ul.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6ul.c
@@ -150,6 +150,21 @@ enum imx6ul_pads {
150 MX6UL_PAD_CSI_DATA07 = 128, 150 MX6UL_PAD_CSI_DATA07 = 128,
151}; 151};
152 152
153enum imx6ull_lpsr_pads {
154 MX6ULL_PAD_BOOT_MODE0 = 0,
155 MX6ULL_PAD_BOOT_MODE1 = 1,
156 MX6ULL_PAD_SNVS_TAMPER0 = 2,
157 MX6ULL_PAD_SNVS_TAMPER1 = 3,
158 MX6ULL_PAD_SNVS_TAMPER2 = 4,
159 MX6ULL_PAD_SNVS_TAMPER3 = 5,
160 MX6ULL_PAD_SNVS_TAMPER4 = 6,
161 MX6ULL_PAD_SNVS_TAMPER5 = 7,
162 MX6ULL_PAD_SNVS_TAMPER6 = 8,
163 MX6ULL_PAD_SNVS_TAMPER7 = 9,
164 MX6ULL_PAD_SNVS_TAMPER8 = 10,
165 MX6ULL_PAD_SNVS_TAMPER9 = 11,
166};
167
153/* Pad names for the pinmux subsystem */ 168/* Pad names for the pinmux subsystem */
154static const struct pinctrl_pin_desc imx6ul_pinctrl_pads[] = { 169static const struct pinctrl_pin_desc imx6ul_pinctrl_pads[] = {
155 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE0), 170 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE0),
@@ -283,20 +298,49 @@ static const struct pinctrl_pin_desc imx6ul_pinctrl_pads[] = {
283 IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA07), 298 IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA07),
284}; 299};
285 300
286static struct imx_pinctrl_soc_info imx6ul_pinctrl_info = { 301/* pad for i.MX6ULL lpsr pinmux */
302static const struct pinctrl_pin_desc imx6ull_snvs_pinctrl_pads[] = {
303 IMX_PINCTRL_PIN(MX6ULL_PAD_BOOT_MODE0),
304 IMX_PINCTRL_PIN(MX6ULL_PAD_BOOT_MODE1),
305 IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER0),
306 IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER1),
307 IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER2),
308 IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER3),
309 IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER4),
310 IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER5),
311 IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER6),
312 IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER7),
313 IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER8),
314 IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER9),
315};
316
317static const struct imx_pinctrl_soc_info imx6ul_pinctrl_info = {
287 .pins = imx6ul_pinctrl_pads, 318 .pins = imx6ul_pinctrl_pads,
288 .npins = ARRAY_SIZE(imx6ul_pinctrl_pads), 319 .npins = ARRAY_SIZE(imx6ul_pinctrl_pads),
289 .gpr_compatible = "fsl,imx6ul-iomuxc-gpr", 320 .gpr_compatible = "fsl,imx6ul-iomuxc-gpr",
290}; 321};
291 322
292static struct of_device_id imx6ul_pinctrl_of_match[] = { 323static const struct imx_pinctrl_soc_info imx6ull_snvs_pinctrl_info = {
293 { .compatible = "fsl,imx6ul-iomuxc", }, 324 .pins = imx6ull_snvs_pinctrl_pads,
325 .npins = ARRAY_SIZE(imx6ull_snvs_pinctrl_pads),
326 .flags = ZERO_OFFSET_VALID,
327};
328
329static const struct of_device_id imx6ul_pinctrl_of_match[] = {
330 { .compatible = "fsl,imx6ul-iomuxc", .data = &imx6ul_pinctrl_info, },
331 { .compatible = "fsl,imx6ull-iomuxc-snvs", .data = &imx6ull_snvs_pinctrl_info, },
294 { /* sentinel */ } 332 { /* sentinel */ }
295}; 333};
296 334
297static int imx6ul_pinctrl_probe(struct platform_device *pdev) 335static int imx6ul_pinctrl_probe(struct platform_device *pdev)
298{ 336{
299 return imx_pinctrl_probe(pdev, &imx6ul_pinctrl_info); 337 const struct imx_pinctrl_soc_info *pinctrl_info;
338
339 pinctrl_info = of_device_get_match_data(&pdev->dev);
340 if (!pinctrl_info)
341 return -ENODEV;
342
343 return imx_pinctrl_probe(pdev, pinctrl_info);
300} 344}
301 345
302static struct platform_driver imx6ul_pinctrl_driver = { 346static struct platform_driver imx6ul_pinctrl_driver = {
diff --git a/drivers/pinctrl/freescale/pinctrl-imx7d.c b/drivers/pinctrl/freescale/pinctrl-imx7d.c
index 754159ee7b1e..0b0a2f33b06a 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx7d.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx7d.c
@@ -378,16 +378,12 @@ static const struct of_device_id imx7d_pinctrl_of_match[] = {
378 378
379static int imx7d_pinctrl_probe(struct platform_device *pdev) 379static int imx7d_pinctrl_probe(struct platform_device *pdev)
380{ 380{
381 const struct of_device_id *match; 381 const struct imx_pinctrl_soc_info *pinctrl_info;
382 struct imx_pinctrl_soc_info *pinctrl_info;
383 382
384 match = of_match_device(imx7d_pinctrl_of_match, &pdev->dev); 383 pinctrl_info = of_device_get_match_data(&pdev->dev);
385 384 if (!pinctrl_info)
386 if (!match)
387 return -ENODEV; 385 return -ENODEV;
388 386
389 pinctrl_info = (struct imx_pinctrl_soc_info *) match->data;
390
391 return imx_pinctrl_probe(pdev, pinctrl_info); 387 return imx_pinctrl_probe(pdev, pinctrl_info);
392} 388}
393 389
diff --git a/drivers/pinctrl/freescale/pinctrl-imx7ulp.c b/drivers/pinctrl/freescale/pinctrl-imx7ulp.c
index b7bebb292f37..f363e45fd246 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx7ulp.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx7ulp.c
@@ -266,7 +266,7 @@ static const struct pinctrl_pin_desc imx7ulp_pinctrl_pads[] = {
266#define BP_MUX_MODE 8 266#define BP_MUX_MODE 8
267#define BM_PULL_ENABLED BIT(1) 267#define BM_PULL_ENABLED BIT(1)
268 268
269struct imx_cfg_params_decode imx7ulp_cfg_decodes[] = { 269static const struct imx_cfg_params_decode imx7ulp_cfg_decodes[] = {
270 IMX_CFG_PARAMS_DECODE(PIN_CONFIG_DRIVE_STRENGTH, BIT(6), 6), 270 IMX_CFG_PARAMS_DECODE(PIN_CONFIG_DRIVE_STRENGTH, BIT(6), 6),
271 IMX_CFG_PARAMS_DECODE(PIN_CONFIG_DRIVE_PUSH_PULL, BIT(5), 5), 271 IMX_CFG_PARAMS_DECODE(PIN_CONFIG_DRIVE_PUSH_PULL, BIT(5), 5),
272 IMX_CFG_PARAMS_DECODE(PIN_CONFIG_SLEW_RATE, BIT(2), 2), 272 IMX_CFG_PARAMS_DECODE(PIN_CONFIG_SLEW_RATE, BIT(2), 2),
@@ -307,11 +307,10 @@ static int imx7ulp_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
307 unsigned offset, bool input) 307 unsigned offset, bool input)
308{ 308{
309 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 309 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
310 struct imx_pinctrl_soc_info *info = ipctl->info;
311 const struct imx_pin_reg *pin_reg; 310 const struct imx_pin_reg *pin_reg;
312 u32 reg; 311 u32 reg;
313 312
314 pin_reg = &info->pin_regs[offset]; 313 pin_reg = &ipctl->pin_regs[offset];
315 if (pin_reg->mux_reg == -1) 314 if (pin_reg->mux_reg == -1)
316 return -EINVAL; 315 return -EINVAL;
317 316
@@ -325,7 +324,7 @@ static int imx7ulp_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
325 return 0; 324 return 0;
326} 325}
327 326
328static struct imx_pinctrl_soc_info imx7ulp_pinctrl_info = { 327static const struct imx_pinctrl_soc_info imx7ulp_pinctrl_info = {
329 .pins = imx7ulp_pinctrl_pads, 328 .pins = imx7ulp_pinctrl_pads,
330 .npins = ARRAY_SIZE(imx7ulp_pinctrl_pads), 329 .npins = ARRAY_SIZE(imx7ulp_pinctrl_pads),
331 .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG, 330 .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG,
diff --git a/drivers/pinctrl/freescale/pinctrl-vf610.c b/drivers/pinctrl/freescale/pinctrl-vf610.c
index ac18bb6d6d5e..c078f859ae15 100644
--- a/drivers/pinctrl/freescale/pinctrl-vf610.c
+++ b/drivers/pinctrl/freescale/pinctrl-vf610.c
@@ -300,11 +300,10 @@ static int vf610_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
300 unsigned offset, bool input) 300 unsigned offset, bool input)
301{ 301{
302 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 302 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
303 struct imx_pinctrl_soc_info *info = ipctl->info;
304 const struct imx_pin_reg *pin_reg; 303 const struct imx_pin_reg *pin_reg;
305 u32 reg; 304 u32 reg;
306 305
307 pin_reg = &info->pin_regs[offset]; 306 pin_reg = &ipctl->pin_regs[offset];
308 if (pin_reg->mux_reg == -1) 307 if (pin_reg->mux_reg == -1)
309 return -EINVAL; 308 return -EINVAL;
310 309
@@ -319,7 +318,7 @@ static int vf610_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
319 return 0; 318 return 0;
320} 319}
321 320
322static struct imx_pinctrl_soc_info vf610_pinctrl_info = { 321static const struct imx_pinctrl_soc_info vf610_pinctrl_info = {
323 .pins = vf610_pinctrl_pads, 322 .pins = vf610_pinctrl_pads,
324 .npins = ARRAY_SIZE(vf610_pinctrl_pads), 323 .npins = ARRAY_SIZE(vf610_pinctrl_pads),
325 .flags = SHARE_MUX_CONF_REG | ZERO_OFFSET_VALID, 324 .flags = SHARE_MUX_CONF_REG | ZERO_OFFSET_VALID,
diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c
index 9c1ca29c60b7..6b52ea1440a6 100644
--- a/drivers/pinctrl/intel/pinctrl-baytrail.c
+++ b/drivers/pinctrl/intel/pinctrl-baytrail.c
@@ -46,6 +46,9 @@
46#define BYT_TRIG_POS BIT(25) 46#define BYT_TRIG_POS BIT(25)
47#define BYT_TRIG_LVL BIT(24) 47#define BYT_TRIG_LVL BIT(24)
48#define BYT_DEBOUNCE_EN BIT(20) 48#define BYT_DEBOUNCE_EN BIT(20)
49#define BYT_GLITCH_FILTER_EN BIT(19)
50#define BYT_GLITCH_F_SLOW_CLK BIT(17)
51#define BYT_GLITCH_F_FAST_CLK BIT(16)
49#define BYT_PULL_STR_SHIFT 9 52#define BYT_PULL_STR_SHIFT 9
50#define BYT_PULL_STR_MASK (3 << BYT_PULL_STR_SHIFT) 53#define BYT_PULL_STR_MASK (3 << BYT_PULL_STR_SHIFT)
51#define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT) 54#define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT)
@@ -1579,6 +1582,9 @@ static int byt_irq_type(struct irq_data *d, unsigned int type)
1579 */ 1582 */
1580 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG | 1583 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
1581 BYT_TRIG_LVL); 1584 BYT_TRIG_LVL);
1585 /* Enable glitch filtering */
1586 value |= BYT_GLITCH_FILTER_EN | BYT_GLITCH_F_SLOW_CLK |
1587 BYT_GLITCH_F_FAST_CLK;
1582 1588
1583 writel(value, reg); 1589 writel(value, reg);
1584 1590
diff --git a/drivers/pinctrl/intel/pinctrl-cannonlake.c b/drivers/pinctrl/intel/pinctrl-cannonlake.c
index e130599be571..6243e7d95e7e 100644
--- a/drivers/pinctrl/intel/pinctrl-cannonlake.c
+++ b/drivers/pinctrl/intel/pinctrl-cannonlake.c
@@ -23,13 +23,16 @@
23#define CNL_HOSTSW_OWN 0x0b0 23#define CNL_HOSTSW_OWN 0x0b0
24#define CNL_GPI_IE 0x120 24#define CNL_GPI_IE 0x120
25 25
26#define CNL_GPP(r, s, e) \ 26#define CNL_GPP(r, s, e, g) \
27 { \ 27 { \
28 .reg_num = (r), \ 28 .reg_num = (r), \
29 .base = (s), \ 29 .base = (s), \
30 .size = ((e) - (s) + 1), \ 30 .size = ((e) - (s) + 1), \
31 .gpio_base = (g), \
31 } 32 }
32 33
34#define CNL_NO_GPIO -1
35
33#define CNL_COMMUNITY(b, s, e, g) \ 36#define CNL_COMMUNITY(b, s, e, g) \
34 { \ 37 { \
35 .barno = (b), \ 38 .barno = (b), \
@@ -363,32 +366,32 @@ static const struct pinctrl_pin_desc cnlh_pins[] = {
363}; 366};
364 367
365static const struct intel_padgroup cnlh_community0_gpps[] = { 368static const struct intel_padgroup cnlh_community0_gpps[] = {
366 CNL_GPP(0, 0, 24), /* GPP_A */ 369 CNL_GPP(0, 0, 24, 0), /* GPP_A */
367 CNL_GPP(1, 25, 50), /* GPP_B */ 370 CNL_GPP(1, 25, 50, 32), /* GPP_B */
368}; 371};
369 372
370static const struct intel_padgroup cnlh_community1_gpps[] = { 373static const struct intel_padgroup cnlh_community1_gpps[] = {
371 CNL_GPP(0, 51, 74), /* GPP_C */ 374 CNL_GPP(0, 51, 74, 64), /* GPP_C */
372 CNL_GPP(1, 75, 98), /* GPP_D */ 375 CNL_GPP(1, 75, 98, 96), /* GPP_D */
373 CNL_GPP(2, 99, 106), /* GPP_G */ 376 CNL_GPP(2, 99, 106, 128), /* GPP_G */
374 CNL_GPP(3, 107, 114), /* AZA */ 377 CNL_GPP(3, 107, 114, CNL_NO_GPIO), /* AZA */
375 CNL_GPP(4, 115, 146), /* vGPIO_0 */ 378 CNL_GPP(4, 115, 146, 160), /* vGPIO_0 */
376 CNL_GPP(5, 147, 154), /* vGPIO_1 */ 379 CNL_GPP(5, 147, 154, CNL_NO_GPIO), /* vGPIO_1 */
377}; 380};
378 381
379static const struct intel_padgroup cnlh_community3_gpps[] = { 382static const struct intel_padgroup cnlh_community3_gpps[] = {
380 CNL_GPP(0, 155, 178), /* GPP_K */ 383 CNL_GPP(0, 155, 178, 192), /* GPP_K */
381 CNL_GPP(1, 179, 202), /* GPP_H */ 384 CNL_GPP(1, 179, 202, 224), /* GPP_H */
382 CNL_GPP(2, 203, 215), /* GPP_E */ 385 CNL_GPP(2, 203, 215, 258), /* GPP_E */
383 CNL_GPP(3, 216, 239), /* GPP_F */ 386 CNL_GPP(3, 216, 239, 288), /* GPP_F */
384 CNL_GPP(4, 240, 248), /* SPI */ 387 CNL_GPP(4, 240, 248, CNL_NO_GPIO), /* SPI */
385}; 388};
386 389
387static const struct intel_padgroup cnlh_community4_gpps[] = { 390static const struct intel_padgroup cnlh_community4_gpps[] = {
388 CNL_GPP(0, 249, 259), /* CPU */ 391 CNL_GPP(0, 249, 259, CNL_NO_GPIO), /* CPU */
389 CNL_GPP(1, 260, 268), /* JTAG */ 392 CNL_GPP(1, 260, 268, CNL_NO_GPIO), /* JTAG */
390 CNL_GPP(2, 269, 286), /* GPP_I */ 393 CNL_GPP(2, 269, 286, 320), /* GPP_I */
391 CNL_GPP(3, 287, 298), /* GPP_J */ 394 CNL_GPP(3, 287, 298, 352), /* GPP_J */
392}; 395};
393 396
394static const unsigned int cnlh_spi0_pins[] = { 40, 41, 42, 43 }; 397static const unsigned int cnlh_spi0_pins[] = { 40, 41, 42, 43 };
@@ -785,25 +788,25 @@ static const struct intel_function cnllp_functions[] = {
785}; 788};
786 789
787static const struct intel_padgroup cnllp_community0_gpps[] = { 790static const struct intel_padgroup cnllp_community0_gpps[] = {
788 CNL_GPP(0, 0, 24), /* GPP_A */ 791 CNL_GPP(0, 0, 24, 0), /* GPP_A */
789 CNL_GPP(1, 25, 50), /* GPP_B */ 792 CNL_GPP(1, 25, 50, 32), /* GPP_B */
790 CNL_GPP(2, 51, 58), /* GPP_G */ 793 CNL_GPP(2, 51, 58, 64), /* GPP_G */
791 CNL_GPP(3, 59, 67), /* SPI */ 794 CNL_GPP(3, 59, 67, CNL_NO_GPIO), /* SPI */
792}; 795};
793 796
794static const struct intel_padgroup cnllp_community1_gpps[] = { 797static const struct intel_padgroup cnllp_community1_gpps[] = {
795 CNL_GPP(0, 68, 92), /* GPP_D */ 798 CNL_GPP(0, 68, 92, 96), /* GPP_D */
796 CNL_GPP(1, 93, 116), /* GPP_F */ 799 CNL_GPP(1, 93, 116, 128), /* GPP_F */
797 CNL_GPP(2, 117, 140), /* GPP_H */ 800 CNL_GPP(2, 117, 140, 160), /* GPP_H */
798 CNL_GPP(3, 141, 172), /* vGPIO */ 801 CNL_GPP(3, 141, 172, 192), /* vGPIO */
799 CNL_GPP(4, 173, 180), /* vGPIO */ 802 CNL_GPP(4, 173, 180, 224), /* vGPIO */
800}; 803};
801 804
802static const struct intel_padgroup cnllp_community4_gpps[] = { 805static const struct intel_padgroup cnllp_community4_gpps[] = {
803 CNL_GPP(0, 181, 204), /* GPP_C */ 806 CNL_GPP(0, 181, 204, 256), /* GPP_C */
804 CNL_GPP(1, 205, 228), /* GPP_E */ 807 CNL_GPP(1, 205, 228, 288), /* GPP_E */
805 CNL_GPP(2, 229, 237), /* JTAG */ 808 CNL_GPP(2, 229, 237, CNL_NO_GPIO), /* JTAG */
806 CNL_GPP(3, 238, 243), /* HVCMOS */ 809 CNL_GPP(3, 238, 243, CNL_NO_GPIO), /* HVCMOS */
807}; 810};
808 811
809static const struct intel_community cnllp_communities[] = { 812static const struct intel_community cnllp_communities[] = {
diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c
index 4471fd94e1fe..b1ae1618fefe 100644
--- a/drivers/pinctrl/intel/pinctrl-cherryview.c
+++ b/drivers/pinctrl/intel/pinctrl-cherryview.c
@@ -131,10 +131,8 @@ struct chv_gpio_pinrange {
131 * @ngroups: Number of groups 131 * @ngroups: Number of groups
132 * @functions: All functions in this community 132 * @functions: All functions in this community
133 * @nfunctions: Number of functions 133 * @nfunctions: Number of functions
134 * @ngpios: Number of GPIOs in this community
135 * @gpio_ranges: An array of GPIO ranges in this community 134 * @gpio_ranges: An array of GPIO ranges in this community
136 * @ngpio_ranges: Number of GPIO ranges 135 * @ngpio_ranges: Number of GPIO ranges
137 * @ngpios: Total number of GPIOs in this community
138 * @nirqs: Total number of IRQs this community can generate 136 * @nirqs: Total number of IRQs this community can generate
139 */ 137 */
140struct chv_community { 138struct chv_community {
@@ -147,7 +145,6 @@ struct chv_community {
147 size_t nfunctions; 145 size_t nfunctions;
148 const struct chv_gpio_pinrange *gpio_ranges; 146 const struct chv_gpio_pinrange *gpio_ranges;
149 size_t ngpio_ranges; 147 size_t ngpio_ranges;
150 size_t ngpios;
151 size_t nirqs; 148 size_t nirqs;
152 acpi_adr_space_type acpi_space_id; 149 acpi_adr_space_type acpi_space_id;
153}; 150};
@@ -399,7 +396,6 @@ static const struct chv_community southwest_community = {
399 .nfunctions = ARRAY_SIZE(southwest_functions), 396 .nfunctions = ARRAY_SIZE(southwest_functions),
400 .gpio_ranges = southwest_gpio_ranges, 397 .gpio_ranges = southwest_gpio_ranges,
401 .ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges), 398 .ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges),
402 .ngpios = ARRAY_SIZE(southwest_pins),
403 /* 399 /*
404 * Southwest community can benerate GPIO interrupts only for the 400 * Southwest community can benerate GPIO interrupts only for the
405 * first 8 interrupts. The upper half (8-15) can only be used to 401 * first 8 interrupts. The upper half (8-15) can only be used to
@@ -489,7 +485,6 @@ static const struct chv_community north_community = {
489 .npins = ARRAY_SIZE(north_pins), 485 .npins = ARRAY_SIZE(north_pins),
490 .gpio_ranges = north_gpio_ranges, 486 .gpio_ranges = north_gpio_ranges,
491 .ngpio_ranges = ARRAY_SIZE(north_gpio_ranges), 487 .ngpio_ranges = ARRAY_SIZE(north_gpio_ranges),
492 .ngpios = ARRAY_SIZE(north_pins),
493 /* 488 /*
494 * North community can generate GPIO interrupts only for the first 489 * North community can generate GPIO interrupts only for the first
495 * 8 interrupts. The upper half (8-15) can only be used to trigger 490 * 8 interrupts. The upper half (8-15) can only be used to trigger
@@ -538,7 +533,6 @@ static const struct chv_community east_community = {
538 .npins = ARRAY_SIZE(east_pins), 533 .npins = ARRAY_SIZE(east_pins),
539 .gpio_ranges = east_gpio_ranges, 534 .gpio_ranges = east_gpio_ranges,
540 .ngpio_ranges = ARRAY_SIZE(east_gpio_ranges), 535 .ngpio_ranges = ARRAY_SIZE(east_gpio_ranges),
541 .ngpios = ARRAY_SIZE(east_pins),
542 .nirqs = 16, 536 .nirqs = 16,
543 .acpi_space_id = 0x93, 537 .acpi_space_id = 0x93,
544}; 538};
@@ -665,7 +659,6 @@ static const struct chv_community southeast_community = {
665 .nfunctions = ARRAY_SIZE(southeast_functions), 659 .nfunctions = ARRAY_SIZE(southeast_functions),
666 .gpio_ranges = southeast_gpio_ranges, 660 .gpio_ranges = southeast_gpio_ranges,
667 .ngpio_ranges = ARRAY_SIZE(southeast_gpio_ranges), 661 .ngpio_ranges = ARRAY_SIZE(southeast_gpio_ranges),
668 .ngpios = ARRAY_SIZE(southeast_pins),
669 .nirqs = 16, 662 .nirqs = 16,
670 .acpi_space_id = 0x94, 663 .acpi_space_id = 0x94,
671}; 664};
@@ -1253,21 +1246,14 @@ static struct pinctrl_desc chv_pinctrl_desc = {
1253 .owner = THIS_MODULE, 1246 .owner = THIS_MODULE,
1254}; 1247};
1255 1248
1256static unsigned chv_gpio_offset_to_pin(struct chv_pinctrl *pctrl,
1257 unsigned offset)
1258{
1259 return pctrl->community->pins[offset].number;
1260}
1261
1262static int chv_gpio_get(struct gpio_chip *chip, unsigned offset) 1249static int chv_gpio_get(struct gpio_chip *chip, unsigned offset)
1263{ 1250{
1264 struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 1251 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1265 int pin = chv_gpio_offset_to_pin(pctrl, offset);
1266 unsigned long flags; 1252 unsigned long flags;
1267 u32 ctrl0, cfg; 1253 u32 ctrl0, cfg;
1268 1254
1269 raw_spin_lock_irqsave(&chv_lock, flags); 1255 raw_spin_lock_irqsave(&chv_lock, flags);
1270 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1256 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
1271 raw_spin_unlock_irqrestore(&chv_lock, flags); 1257 raw_spin_unlock_irqrestore(&chv_lock, flags);
1272 1258
1273 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 1259 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
@@ -1281,14 +1267,13 @@ static int chv_gpio_get(struct gpio_chip *chip, unsigned offset)
1281static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 1267static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1282{ 1268{
1283 struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 1269 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1284 unsigned pin = chv_gpio_offset_to_pin(pctrl, offset);
1285 unsigned long flags; 1270 unsigned long flags;
1286 void __iomem *reg; 1271 void __iomem *reg;
1287 u32 ctrl0; 1272 u32 ctrl0;
1288 1273
1289 raw_spin_lock_irqsave(&chv_lock, flags); 1274 raw_spin_lock_irqsave(&chv_lock, flags);
1290 1275
1291 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); 1276 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
1292 ctrl0 = readl(reg); 1277 ctrl0 = readl(reg);
1293 1278
1294 if (value) 1279 if (value)
@@ -1304,12 +1289,11 @@ static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1304static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 1289static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1305{ 1290{
1306 struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 1291 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1307 unsigned pin = chv_gpio_offset_to_pin(pctrl, offset);
1308 u32 ctrl0, direction; 1292 u32 ctrl0, direction;
1309 unsigned long flags; 1293 unsigned long flags;
1310 1294
1311 raw_spin_lock_irqsave(&chv_lock, flags); 1295 raw_spin_lock_irqsave(&chv_lock, flags);
1312 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1296 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
1313 raw_spin_unlock_irqrestore(&chv_lock, flags); 1297 raw_spin_unlock_irqrestore(&chv_lock, flags);
1314 1298
1315 direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 1299 direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
@@ -1345,7 +1329,7 @@ static void chv_gpio_irq_ack(struct irq_data *d)
1345{ 1329{
1346 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1330 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1347 struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1331 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1348 int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d)); 1332 int pin = irqd_to_hwirq(d);
1349 u32 intr_line; 1333 u32 intr_line;
1350 1334
1351 raw_spin_lock(&chv_lock); 1335 raw_spin_lock(&chv_lock);
@@ -1362,7 +1346,7 @@ static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
1362{ 1346{
1363 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1347 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1364 struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1348 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1365 int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d)); 1349 int pin = irqd_to_hwirq(d);
1366 u32 value, intr_line; 1350 u32 value, intr_line;
1367 unsigned long flags; 1351 unsigned long flags;
1368 1352
@@ -1407,8 +1391,7 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
1407 if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) { 1391 if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) {
1408 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1392 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1409 struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1393 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1410 unsigned offset = irqd_to_hwirq(d); 1394 unsigned pin = irqd_to_hwirq(d);
1411 int pin = chv_gpio_offset_to_pin(pctrl, offset);
1412 irq_flow_handler_t handler; 1395 irq_flow_handler_t handler;
1413 unsigned long flags; 1396 unsigned long flags;
1414 u32 intsel, value; 1397 u32 intsel, value;
@@ -1426,7 +1409,7 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
1426 1409
1427 if (!pctrl->intr_lines[intsel]) { 1410 if (!pctrl->intr_lines[intsel]) {
1428 irq_set_handler_locked(d, handler); 1411 irq_set_handler_locked(d, handler);
1429 pctrl->intr_lines[intsel] = offset; 1412 pctrl->intr_lines[intsel] = pin;
1430 } 1413 }
1431 raw_spin_unlock_irqrestore(&chv_lock, flags); 1414 raw_spin_unlock_irqrestore(&chv_lock, flags);
1432 } 1415 }
@@ -1439,8 +1422,7 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned type)
1439{ 1422{
1440 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1423 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1441 struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1424 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1442 unsigned offset = irqd_to_hwirq(d); 1425 unsigned pin = irqd_to_hwirq(d);
1443 int pin = chv_gpio_offset_to_pin(pctrl, offset);
1444 unsigned long flags; 1426 unsigned long flags;
1445 u32 value; 1427 u32 value;
1446 1428
@@ -1486,7 +1468,7 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned type)
1486 value &= CHV_PADCTRL0_INTSEL_MASK; 1468 value &= CHV_PADCTRL0_INTSEL_MASK;
1487 value >>= CHV_PADCTRL0_INTSEL_SHIFT; 1469 value >>= CHV_PADCTRL0_INTSEL_SHIFT;
1488 1470
1489 pctrl->intr_lines[value] = offset; 1471 pctrl->intr_lines[value] = pin;
1490 1472
1491 if (type & IRQ_TYPE_EDGE_BOTH) 1473 if (type & IRQ_TYPE_EDGE_BOTH)
1492 irq_set_handler_locked(d, handle_edge_irq); 1474 irq_set_handler_locked(d, handle_edge_irq);
@@ -1576,12 +1558,12 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
1576 const struct chv_gpio_pinrange *range; 1558 const struct chv_gpio_pinrange *range;
1577 struct gpio_chip *chip = &pctrl->chip; 1559 struct gpio_chip *chip = &pctrl->chip;
1578 bool need_valid_mask = !dmi_check_system(chv_no_valid_mask); 1560 bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
1579 int ret, i, offset; 1561 const struct chv_community *community = pctrl->community;
1580 int irq_base; 1562 int ret, i, irq_base;
1581 1563
1582 *chip = chv_gpio_chip; 1564 *chip = chv_gpio_chip;
1583 1565
1584 chip->ngpio = pctrl->community->ngpios; 1566 chip->ngpio = community->pins[community->npins - 1].number + 1;
1585 chip->label = dev_name(pctrl->dev); 1567 chip->label = dev_name(pctrl->dev);
1586 chip->parent = pctrl->dev; 1568 chip->parent = pctrl->dev;
1587 chip->base = -1; 1569 chip->base = -1;
@@ -1593,30 +1575,29 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
1593 return ret; 1575 return ret;
1594 } 1576 }
1595 1577
1596 for (i = 0, offset = 0; i < pctrl->community->ngpio_ranges; i++) { 1578 for (i = 0; i < community->ngpio_ranges; i++) {
1597 range = &pctrl->community->gpio_ranges[i]; 1579 range = &community->gpio_ranges[i];
1598 ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev), offset, 1580 ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev),
1599 range->base, range->npins); 1581 range->base, range->base,
1582 range->npins);
1600 if (ret) { 1583 if (ret) {
1601 dev_err(pctrl->dev, "failed to add GPIO pin range\n"); 1584 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1602 return ret; 1585 return ret;
1603 } 1586 }
1604
1605 offset += range->npins;
1606 } 1587 }
1607 1588
1608 /* Do not add GPIOs that can only generate GPEs to the IRQ domain */ 1589 /* Do not add GPIOs that can only generate GPEs to the IRQ domain */
1609 for (i = 0; i < pctrl->community->npins; i++) { 1590 for (i = 0; i < community->npins; i++) {
1610 const struct pinctrl_pin_desc *desc; 1591 const struct pinctrl_pin_desc *desc;
1611 u32 intsel; 1592 u32 intsel;
1612 1593
1613 desc = &pctrl->community->pins[i]; 1594 desc = &community->pins[i];
1614 1595
1615 intsel = readl(chv_padreg(pctrl, desc->number, CHV_PADCTRL0)); 1596 intsel = readl(chv_padreg(pctrl, desc->number, CHV_PADCTRL0));
1616 intsel &= CHV_PADCTRL0_INTSEL_MASK; 1597 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1617 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; 1598 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1618 1599
1619 if (need_valid_mask && intsel >= pctrl->community->nirqs) 1600 if (need_valid_mask && intsel >= community->nirqs)
1620 clear_bit(i, chip->irq.valid_mask); 1601 clear_bit(i, chip->irq.valid_mask);
1621 } 1602 }
1622 1603
diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
index 12a1af45acb9..96e73e30204e 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.c
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -425,6 +425,18 @@ static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
425 writel(value, padcfg0); 425 writel(value, padcfg0);
426} 426}
427 427
428static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
429{
430 u32 value;
431
432 /* Put the pad into GPIO mode */
433 value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
434 /* Disable SCI/SMI/NMI generation */
435 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
436 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
437 writel(value, padcfg0);
438}
439
428static int intel_gpio_request_enable(struct pinctrl_dev *pctldev, 440static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
429 struct pinctrl_gpio_range *range, 441 struct pinctrl_gpio_range *range,
430 unsigned pin) 442 unsigned pin)
@@ -432,7 +444,6 @@ static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
432 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 444 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
433 void __iomem *padcfg0; 445 void __iomem *padcfg0;
434 unsigned long flags; 446 unsigned long flags;
435 u32 value;
436 447
437 raw_spin_lock_irqsave(&pctrl->lock, flags); 448 raw_spin_lock_irqsave(&pctrl->lock, flags);
438 449
@@ -442,13 +453,7 @@ static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
442 } 453 }
443 454
444 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 455 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
445 /* Put the pad into GPIO mode */ 456 intel_gpio_set_gpio_mode(padcfg0);
446 value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
447 /* Disable SCI/SMI/NMI generation */
448 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
449 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
450 writel(value, padcfg0);
451
452 /* Disable TX buffer and enable RX (this will be input) */ 457 /* Disable TX buffer and enable RX (this will be input) */
453 __intel_gpio_set_direction(padcfg0, true); 458 __intel_gpio_set_direction(padcfg0, true);
454 459
@@ -806,22 +811,63 @@ static const struct gpio_chip intel_gpio_chip = {
806 .set_config = gpiochip_generic_config, 811 .set_config = gpiochip_generic_config,
807}; 812};
808 813
814/**
815 * intel_gpio_to_pin() - Translate from GPIO offset to pin number
816 * @pctrl: Pinctrl structure
817 * @offset: GPIO offset from gpiolib
818 * @commmunity: Community is filled here if not %NULL
819 * @padgrp: Pad group is filled here if not %NULL
820 *
821 * When coming through gpiolib irqchip, the GPIO offset is not
822 * automatically translated to pinctrl pin number. This function can be
823 * used to find out the corresponding pinctrl pin.
824 */
825static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned offset,
826 const struct intel_community **community,
827 const struct intel_padgroup **padgrp)
828{
829 int i;
830
831 for (i = 0; i < pctrl->ncommunities; i++) {
832 const struct intel_community *comm = &pctrl->communities[i];
833 int j;
834
835 for (j = 0; j < comm->ngpps; j++) {
836 const struct intel_padgroup *pgrp = &comm->gpps[j];
837
838 if (pgrp->gpio_base < 0)
839 continue;
840
841 if (offset >= pgrp->gpio_base &&
842 offset < pgrp->gpio_base + pgrp->size) {
843 int pin;
844
845 pin = pgrp->base + offset - pgrp->gpio_base;
846 if (community)
847 *community = comm;
848 if (padgrp)
849 *padgrp = pgrp;
850
851 return pin;
852 }
853 }
854 }
855
856 return -EINVAL;
857}
858
809static void intel_gpio_irq_ack(struct irq_data *d) 859static void intel_gpio_irq_ack(struct irq_data *d)
810{ 860{
811 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 861 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
812 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 862 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
813 const struct intel_community *community; 863 const struct intel_community *community;
814 unsigned pin = irqd_to_hwirq(d); 864 const struct intel_padgroup *padgrp;
865 int pin;
815 866
816 community = intel_get_community(pctrl, pin); 867 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
817 if (community) { 868 if (pin >= 0) {
818 const struct intel_padgroup *padgrp;
819 unsigned gpp, gpp_offset, is_offset; 869 unsigned gpp, gpp_offset, is_offset;
820 870
821 padgrp = intel_community_get_padgroup(community, pin);
822 if (!padgrp)
823 return;
824
825 gpp = padgrp->reg_num; 871 gpp = padgrp->reg_num;
826 gpp_offset = padgroup_offset(padgrp, pin); 872 gpp_offset = padgroup_offset(padgrp, pin);
827 is_offset = community->is_offset + gpp * 4; 873 is_offset = community->is_offset + gpp * 4;
@@ -837,19 +883,15 @@ static void intel_gpio_irq_enable(struct irq_data *d)
837 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 883 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
838 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 884 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
839 const struct intel_community *community; 885 const struct intel_community *community;
840 unsigned pin = irqd_to_hwirq(d); 886 const struct intel_padgroup *padgrp;
887 int pin;
841 888
842 community = intel_get_community(pctrl, pin); 889 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
843 if (community) { 890 if (pin >= 0) {
844 const struct intel_padgroup *padgrp;
845 unsigned gpp, gpp_offset, is_offset; 891 unsigned gpp, gpp_offset, is_offset;
846 unsigned long flags; 892 unsigned long flags;
847 u32 value; 893 u32 value;
848 894
849 padgrp = intel_community_get_padgroup(community, pin);
850 if (!padgrp)
851 return;
852
853 gpp = padgrp->reg_num; 895 gpp = padgrp->reg_num;
854 gpp_offset = padgroup_offset(padgrp, pin); 896 gpp_offset = padgroup_offset(padgrp, pin);
855 is_offset = community->is_offset + gpp * 4; 897 is_offset = community->is_offset + gpp * 4;
@@ -870,20 +912,16 @@ static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
870 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 912 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
871 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 913 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
872 const struct intel_community *community; 914 const struct intel_community *community;
873 unsigned pin = irqd_to_hwirq(d); 915 const struct intel_padgroup *padgrp;
916 int pin;
874 917
875 community = intel_get_community(pctrl, pin); 918 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
876 if (community) { 919 if (pin >= 0) {
877 const struct intel_padgroup *padgrp;
878 unsigned gpp, gpp_offset; 920 unsigned gpp, gpp_offset;
879 unsigned long flags; 921 unsigned long flags;
880 void __iomem *reg; 922 void __iomem *reg;
881 u32 value; 923 u32 value;
882 924
883 padgrp = intel_community_get_padgroup(community, pin);
884 if (!padgrp)
885 return;
886
887 gpp = padgrp->reg_num; 925 gpp = padgrp->reg_num;
888 gpp_offset = padgroup_offset(padgrp, pin); 926 gpp_offset = padgroup_offset(padgrp, pin);
889 927
@@ -914,7 +952,7 @@ static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
914{ 952{
915 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 953 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
916 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 954 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
917 unsigned pin = irqd_to_hwirq(d); 955 unsigned pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
918 unsigned long flags; 956 unsigned long flags;
919 void __iomem *reg; 957 void __iomem *reg;
920 u32 value; 958 u32 value;
@@ -935,6 +973,8 @@ static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
935 973
936 raw_spin_lock_irqsave(&pctrl->lock, flags); 974 raw_spin_lock_irqsave(&pctrl->lock, flags);
937 975
976 intel_gpio_set_gpio_mode(reg);
977
938 value = readl(reg); 978 value = readl(reg);
939 979
940 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV); 980 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
@@ -969,7 +1009,7 @@ static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
969{ 1009{
970 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1010 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
971 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1011 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
972 unsigned pin = irqd_to_hwirq(d); 1012 unsigned pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
973 1013
974 if (on) 1014 if (on)
975 enable_irq_wake(pctrl->irq); 1015 enable_irq_wake(pctrl->irq);
@@ -1000,14 +1040,10 @@ static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
1000 pending &= enabled; 1040 pending &= enabled;
1001 1041
1002 for_each_set_bit(gpp_offset, &pending, padgrp->size) { 1042 for_each_set_bit(gpp_offset, &pending, padgrp->size) {
1003 unsigned padno, irq; 1043 unsigned irq;
1004
1005 padno = padgrp->base - community->pin_base + gpp_offset;
1006 if (padno >= community->npins)
1007 break;
1008 1044
1009 irq = irq_find_mapping(gc->irq.domain, 1045 irq = irq_find_mapping(gc->irq.domain,
1010 community->pin_base + padno); 1046 padgrp->gpio_base + gpp_offset);
1011 generic_handle_irq(irq); 1047 generic_handle_irq(irq);
1012 1048
1013 ret |= IRQ_HANDLED; 1049 ret |= IRQ_HANDLED;
@@ -1044,13 +1080,56 @@ static struct irq_chip intel_gpio_irqchip = {
1044 .flags = IRQCHIP_MASK_ON_SUSPEND, 1080 .flags = IRQCHIP_MASK_ON_SUSPEND,
1045}; 1081};
1046 1082
1083static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl,
1084 const struct intel_community *community)
1085{
1086 int ret = 0, i;
1087
1088 for (i = 0; i < community->ngpps; i++) {
1089 const struct intel_padgroup *gpp = &community->gpps[i];
1090
1091 if (gpp->gpio_base < 0)
1092 continue;
1093
1094 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
1095 gpp->gpio_base, gpp->base,
1096 gpp->size);
1097 if (ret)
1098 return ret;
1099 }
1100
1101 return ret;
1102}
1103
1104static unsigned intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
1105{
1106 const struct intel_community *community;
1107 unsigned ngpio = 0;
1108 int i, j;
1109
1110 for (i = 0; i < pctrl->ncommunities; i++) {
1111 community = &pctrl->communities[i];
1112 for (j = 0; j < community->ngpps; j++) {
1113 const struct intel_padgroup *gpp = &community->gpps[j];
1114
1115 if (gpp->gpio_base < 0)
1116 continue;
1117
1118 if (gpp->gpio_base + gpp->size > ngpio)
1119 ngpio = gpp->gpio_base + gpp->size;
1120 }
1121 }
1122
1123 return ngpio;
1124}
1125
1047static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) 1126static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1048{ 1127{
1049 int ret; 1128 int ret, i;
1050 1129
1051 pctrl->chip = intel_gpio_chip; 1130 pctrl->chip = intel_gpio_chip;
1052 1131
1053 pctrl->chip.ngpio = pctrl->soc->npins; 1132 pctrl->chip.ngpio = intel_gpio_ngpio(pctrl);
1054 pctrl->chip.label = dev_name(pctrl->dev); 1133 pctrl->chip.label = dev_name(pctrl->dev);
1055 pctrl->chip.parent = pctrl->dev; 1134 pctrl->chip.parent = pctrl->dev;
1056 pctrl->chip.base = -1; 1135 pctrl->chip.base = -1;
@@ -1062,11 +1141,14 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1062 return ret; 1141 return ret;
1063 } 1142 }
1064 1143
1065 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 1144 for (i = 0; i < pctrl->ncommunities; i++) {
1066 0, 0, pctrl->soc->npins); 1145 struct intel_community *community = &pctrl->communities[i];
1067 if (ret) { 1146
1068 dev_err(pctrl->dev, "failed to add GPIO pin range\n"); 1147 ret = intel_gpio_add_pin_ranges(pctrl, community);
1069 return ret; 1148 if (ret) {
1149 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1150 return ret;
1151 }
1070 } 1152 }
1071 1153
1072 /* 1154 /*
@@ -1126,6 +1208,9 @@ static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl,
1126 if (gpps[i].size > 32) 1208 if (gpps[i].size > 32)
1127 return -EINVAL; 1209 return -EINVAL;
1128 1210
1211 if (!gpps[i].gpio_base)
1212 gpps[i].gpio_base = gpps[i].base;
1213
1129 gpps[i].padown_num = padown_num; 1214 gpps[i].padown_num = padown_num;
1130 1215
1131 /* 1216 /*
diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h
index 13b0bd6eb2a2..98fdf9adf623 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.h
+++ b/drivers/pinctrl/intel/pinctrl-intel.h
@@ -51,6 +51,8 @@ struct intel_function {
51 * @reg_num: GPI_IS register number 51 * @reg_num: GPI_IS register number
52 * @base: Starting pin of this group 52 * @base: Starting pin of this group
53 * @size: Size of this group (maximum is 32). 53 * @size: Size of this group (maximum is 32).
54 * @gpio_base: Starting GPIO base of this group (%0 if matches with @base,
55 * and %-1 if no GPIO mapping should be created)
54 * @padown_num: PAD_OWN register number (assigned by the core driver) 56 * @padown_num: PAD_OWN register number (assigned by the core driver)
55 * 57 *
56 * If pad groups of a community are not the same size, use this structure 58 * If pad groups of a community are not the same size, use this structure
@@ -60,6 +62,7 @@ struct intel_padgroup {
60 unsigned reg_num; 62 unsigned reg_num;
61 unsigned base; 63 unsigned base;
62 unsigned size; 64 unsigned size;
65 int gpio_base;
63 unsigned padown_num; 66 unsigned padown_num;
64}; 67};
65 68
diff --git a/drivers/pinctrl/intel/pinctrl-merrifield.c b/drivers/pinctrl/intel/pinctrl-merrifield.c
index 86c4b3fab7b0..d9357054d41d 100644
--- a/drivers/pinctrl/intel/pinctrl-merrifield.c
+++ b/drivers/pinctrl/intel/pinctrl-merrifield.c
@@ -931,10 +931,17 @@ static int mrfld_pinctrl_probe(struct platform_device *pdev)
931 return 0; 931 return 0;
932} 932}
933 933
934static const struct acpi_device_id mrfld_acpi_table[] = {
935 { "INTC1002" },
936 { }
937};
938MODULE_DEVICE_TABLE(acpi, mrfld_acpi_table);
939
934static struct platform_driver mrfld_pinctrl_driver = { 940static struct platform_driver mrfld_pinctrl_driver = {
935 .probe = mrfld_pinctrl_probe, 941 .probe = mrfld_pinctrl_probe,
936 .driver = { 942 .driver = {
937 .name = "pinctrl-merrifield", 943 .name = "pinctrl-merrifield",
944 .acpi_match_table = mrfld_acpi_table,
938 }, 945 },
939}; 946};
940 947
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index fac9866311f3..3e598740b379 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -1,4 +1,5 @@
1if ARCH_MEDIATEK || COMPILE_TEST 1menu "MediaTek pinctrl drivers"
2 depends on ARCH_MEDIATEK || COMPILE_TEST
2 3
3config PINCTRL_MTK 4config PINCTRL_MTK
4 bool 5 bool
@@ -31,6 +32,16 @@ config PINCTRL_MT8127
31 select PINCTRL_MTK 32 select PINCTRL_MTK
32 33
33# For ARMv8 SoCs 34# For ARMv8 SoCs
35config PINCTRL_MT7622
36 bool "MediaTek MT7622 pin control"
37 depends on OF
38 depends on ARM64 || COMPILE_TEST
39 select GENERIC_PINCONF
40 select GENERIC_PINCTRL_GROUPS
41 select GENERIC_PINMUX_FUNCTIONS
42 select GPIOLIB
43 select OF_GPIO
44
34config PINCTRL_MT8173 45config PINCTRL_MT8173
35 bool "Mediatek MT8173 pin control" 46 bool "Mediatek MT8173 pin control"
36 depends on OF 47 depends on OF
@@ -46,4 +57,4 @@ config PINCTRL_MT6397
46 default MFD_MT6397 57 default MFD_MT6397
47 select PINCTRL_MTK 58 select PINCTRL_MTK
48 59
49endif 60endmenu
diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
index 10d90140a38a..ed7d2b2cc6e9 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -1,10 +1,11 @@
1# SPDX-License-Identifier: GPL-2.0 1# SPDX-License-Identifier: GPL-2.0
2# Core 2# Core
3obj-y += pinctrl-mtk-common.o 3obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
4 4
5# SoC Drivers 5# SoC Drivers
6obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o 6obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o
7obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o 7obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
8obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o 8obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
9obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
9obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o 10obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
10obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o 11obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7622.c b/drivers/pinctrl/mediatek/pinctrl-mt7622.c
new file mode 100644
index 000000000000..06e8406c4440
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c
@@ -0,0 +1,1597 @@
1/*
2 * MediaTek MT7622 Pinctrl Driver
3 *
4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/gpio.h>
17#include <linux/gpio/driver.h>
18#include <linux/io.h>
19#include <linux/init.h>
20#include <linux/mfd/syscon.h>
21#include <linux/of.h>
22#include <linux/of_platform.h>
23#include <linux/platform_device.h>
24#include <linux/pinctrl/pinctrl.h>
25#include <linux/pinctrl/pinmux.h>
26#include <linux/pinctrl/pinconf.h>
27#include <linux/pinctrl/pinconf-generic.h>
28#include <linux/regmap.h>
29
30#include "../core.h"
31#include "../pinconf.h"
32#include "../pinmux.h"
33
34#define PINCTRL_PINCTRL_DEV KBUILD_MODNAME
35#define MTK_RANGE(_a) { .range = (_a), .nranges = ARRAY_SIZE(_a), }
36#define PINCTRL_PIN_GROUP(name, id) \
37 { \
38 name, \
39 id##_pins, \
40 ARRAY_SIZE(id##_pins), \
41 id##_funcs, \
42 }
43
44#define MTK_GPIO_MODE 1
45#define MTK_INPUT 0
46#define MTK_OUTPUT 1
47#define MTK_DISABLE 0
48#define MTK_ENABLE 1
49
50/* Custom pinconf parameters */
51#define MTK_PIN_CONFIG_TDSEL (PIN_CONFIG_END + 1)
52#define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2)
53
54/* List these attributes which could be modified for the pin */
55enum {
56 PINCTRL_PIN_REG_MODE,
57 PINCTRL_PIN_REG_DIR,
58 PINCTRL_PIN_REG_DI,
59 PINCTRL_PIN_REG_DO,
60 PINCTRL_PIN_REG_SR,
61 PINCTRL_PIN_REG_SMT,
62 PINCTRL_PIN_REG_PD,
63 PINCTRL_PIN_REG_PU,
64 PINCTRL_PIN_REG_E4,
65 PINCTRL_PIN_REG_E8,
66 PINCTRL_PIN_REG_TDSEL,
67 PINCTRL_PIN_REG_RDSEL,
68 PINCTRL_PIN_REG_MAX,
69};
70
71/* struct mtk_pin_field - the structure that holds the information of the field
72 * used to describe the attribute for the pin
73 * @offset: the register offset relative to the base address
74 * @mask: the mask used to filter out the field from the register
75 * @bitpos: the start bit relative to the register
76 * @next: the indication that the field would be extended to the
77 next register
78 */
79struct mtk_pin_field {
80 u32 offset;
81 u32 mask;
82 u8 bitpos;
83 u8 next;
84};
85
86/* struct mtk_pin_field_calc - the structure that holds the range providing
87 * the guide used to look up the relevant field
88 * @s_pin: the start pin within the range
89 * @e_pin: the end pin within the range
90 * @s_addr: the start address for the range
91 * @x_addrs: the address distance between two consecutive registers
92 * within the range
93 * @s_bit: the start bit for the first register within the range
94 * @x_bits: the bit distance between two consecutive pins within
95 * the range
96 */
97struct mtk_pin_field_calc {
98 u16 s_pin;
99 u16 e_pin;
100 u32 s_addr;
101 u8 x_addrs;
102 u8 s_bit;
103 u8 x_bits;
104};
105
106/* struct mtk_pin_reg_calc - the structure that holds all ranges used to
107 * determine which register the pin would make use of
108 * for certain pin attribute.
109 * @range: the start address for the range
110 * @nranges: the number of items in the range
111 */
112struct mtk_pin_reg_calc {
113 const struct mtk_pin_field_calc *range;
114 unsigned int nranges;
115};
116
117/* struct mtk_pin_soc - the structure that holds SoC-specific data */
118struct mtk_pin_soc {
119 const struct mtk_pin_reg_calc *reg_cal;
120 const struct pinctrl_pin_desc *pins;
121 unsigned int npins;
122 const struct group_desc *grps;
123 unsigned int ngrps;
124 const struct function_desc *funcs;
125 unsigned int nfuncs;
126};
127
128struct mtk_pinctrl {
129 struct pinctrl_dev *pctrl;
130 void __iomem *base;
131 struct device *dev;
132 struct gpio_chip chip;
133 const struct mtk_pin_soc *soc;
134};
135
136static const struct mtk_pin_field_calc mt7622_pin_mode_range[] = {
137 {0, 0, 0x320, 0x10, 16, 4},
138 {1, 4, 0x3a0, 0x10, 16, 4},
139 {5, 5, 0x320, 0x10, 0, 4},
140 {6, 6, 0x300, 0x10, 4, 4},
141 {7, 7, 0x300, 0x10, 4, 4},
142 {8, 9, 0x350, 0x10, 20, 4},
143 {10, 10, 0x300, 0x10, 8, 4},
144 {11, 11, 0x300, 0x10, 8, 4},
145 {12, 12, 0x300, 0x10, 8, 4},
146 {13, 13, 0x300, 0x10, 8, 4},
147 {14, 15, 0x320, 0x10, 4, 4},
148 {16, 17, 0x320, 0x10, 20, 4},
149 {18, 21, 0x310, 0x10, 16, 4},
150 {22, 22, 0x380, 0x10, 16, 4},
151 {23, 23, 0x300, 0x10, 24, 4},
152 {24, 24, 0x300, 0x10, 24, 4},
153 {25, 25, 0x300, 0x10, 12, 4},
154 {25, 25, 0x300, 0x10, 12, 4},
155 {26, 26, 0x300, 0x10, 12, 4},
156 {27, 27, 0x300, 0x10, 12, 4},
157 {28, 28, 0x300, 0x10, 12, 4},
158 {29, 29, 0x300, 0x10, 12, 4},
159 {30, 30, 0x300, 0x10, 12, 4},
160 {31, 31, 0x300, 0x10, 12, 4},
161 {32, 32, 0x300, 0x10, 12, 4},
162 {33, 33, 0x300, 0x10, 12, 4},
163 {34, 34, 0x300, 0x10, 12, 4},
164 {35, 35, 0x300, 0x10, 12, 4},
165 {36, 36, 0x300, 0x10, 12, 4},
166 {37, 37, 0x300, 0x10, 20, 4},
167 {38, 38, 0x300, 0x10, 20, 4},
168 {39, 39, 0x300, 0x10, 20, 4},
169 {40, 40, 0x300, 0x10, 20, 4},
170 {41, 41, 0x300, 0x10, 20, 4},
171 {42, 42, 0x300, 0x10, 20, 4},
172 {43, 43, 0x300, 0x10, 20, 4},
173 {44, 44, 0x300, 0x10, 20, 4},
174 {45, 46, 0x300, 0x10, 20, 4},
175 {47, 47, 0x300, 0x10, 20, 4},
176 {48, 48, 0x300, 0x10, 20, 4},
177 {49, 49, 0x300, 0x10, 20, 4},
178 {50, 50, 0x300, 0x10, 20, 4},
179 {51, 70, 0x330, 0x10, 4, 4},
180 {71, 71, 0x300, 0x10, 16, 4},
181 {72, 72, 0x300, 0x10, 16, 4},
182 {73, 76, 0x310, 0x10, 0, 4},
183 {77, 77, 0x320, 0x10, 28, 4},
184 {78, 78, 0x320, 0x10, 12, 4},
185 {79, 82, 0x3a0, 0x10, 0, 4},
186 {83, 83, 0x350, 0x10, 28, 4},
187 {84, 84, 0x330, 0x10, 0, 4},
188 {85, 90, 0x360, 0x10, 4, 4},
189 {91, 94, 0x390, 0x10, 16, 4},
190 {95, 97, 0x380, 0x10, 20, 4},
191 {98, 101, 0x390, 0x10, 0, 4},
192 {102, 102, 0x360, 0x10, 0, 4},
193};
194
195static const struct mtk_pin_field_calc mt7622_pin_dir_range[] = {
196 {0, 102, 0x0, 0x10, 0, 1},
197};
198
199static const struct mtk_pin_field_calc mt7622_pin_di_range[] = {
200 {0, 102, 0x200, 0x10, 0, 1},
201};
202
203static const struct mtk_pin_field_calc mt7622_pin_do_range[] = {
204 {0, 102, 0x100, 0x10, 0, 1},
205};
206
207static const struct mtk_pin_field_calc mt7622_pin_sr_range[] = {
208 {0, 31, 0x910, 0x10, 0, 1},
209 {32, 50, 0xa10, 0x10, 0, 1},
210 {51, 70, 0x810, 0x10, 0, 1},
211 {71, 72, 0xb10, 0x10, 0, 1},
212 {73, 86, 0xb10, 0x10, 4, 1},
213 {87, 90, 0xc10, 0x10, 0, 1},
214 {91, 102, 0xb10, 0x10, 18, 1},
215};
216
217static const struct mtk_pin_field_calc mt7622_pin_smt_range[] = {
218 {0, 31, 0x920, 0x10, 0, 1},
219 {32, 50, 0xa20, 0x10, 0, 1},
220 {51, 70, 0x820, 0x10, 0, 1},
221 {71, 72, 0xb20, 0x10, 0, 1},
222 {73, 86, 0xb20, 0x10, 4, 1},
223 {87, 90, 0xc20, 0x10, 0, 1},
224 {91, 102, 0xb20, 0x10, 18, 1},
225};
226
227static const struct mtk_pin_field_calc mt7622_pin_pu_range[] = {
228 {0, 31, 0x930, 0x10, 0, 1},
229 {32, 50, 0xa30, 0x10, 0, 1},
230 {51, 70, 0x830, 0x10, 0, 1},
231 {71, 72, 0xb30, 0x10, 0, 1},
232 {73, 86, 0xb30, 0x10, 4, 1},
233 {87, 90, 0xc30, 0x10, 0, 1},
234 {91, 102, 0xb30, 0x10, 18, 1},
235};
236
237static const struct mtk_pin_field_calc mt7622_pin_pd_range[] = {
238 {0, 31, 0x940, 0x10, 0, 1},
239 {32, 50, 0xa40, 0x10, 0, 1},
240 {51, 70, 0x840, 0x10, 0, 1},
241 {71, 72, 0xb40, 0x10, 0, 1},
242 {73, 86, 0xb40, 0x10, 4, 1},
243 {87, 90, 0xc40, 0x10, 0, 1},
244 {91, 102, 0xb40, 0x10, 18, 1},
245};
246
247static const struct mtk_pin_field_calc mt7622_pin_e4_range[] = {
248 {0, 31, 0x960, 0x10, 0, 1},
249 {32, 50, 0xa60, 0x10, 0, 1},
250 {51, 70, 0x860, 0x10, 0, 1},
251 {71, 72, 0xb60, 0x10, 0, 1},
252 {73, 86, 0xb60, 0x10, 4, 1},
253 {87, 90, 0xc60, 0x10, 0, 1},
254 {91, 102, 0xb60, 0x10, 18, 1},
255};
256
257static const struct mtk_pin_field_calc mt7622_pin_e8_range[] = {
258 {0, 31, 0x970, 0x10, 0, 1},
259 {32, 50, 0xa70, 0x10, 0, 1},
260 {51, 70, 0x870, 0x10, 0, 1},
261 {71, 72, 0xb70, 0x10, 0, 1},
262 {73, 86, 0xb70, 0x10, 4, 1},
263 {87, 90, 0xc70, 0x10, 0, 1},
264 {91, 102, 0xb70, 0x10, 18, 1},
265};
266
267static const struct mtk_pin_field_calc mt7622_pin_tdsel_range[] = {
268 {0, 31, 0x980, 0x4, 0, 4},
269 {32, 50, 0xa80, 0x4, 0, 4},
270 {51, 70, 0x880, 0x4, 0, 4},
271 {71, 72, 0xb80, 0x4, 0, 4},
272 {73, 86, 0xb80, 0x4, 16, 4},
273 {87, 90, 0xc80, 0x4, 0, 4},
274 {91, 102, 0xb88, 0x4, 8, 4},
275};
276
277static const struct mtk_pin_field_calc mt7622_pin_rdsel_range[] = {
278 {0, 31, 0x990, 0x4, 0, 6},
279 {32, 50, 0xa90, 0x4, 0, 6},
280 {51, 58, 0x890, 0x4, 0, 6},
281 {59, 60, 0x894, 0x4, 28, 6},
282 {61, 62, 0x894, 0x4, 16, 6},
283 {63, 66, 0x898, 0x4, 8, 6},
284 {67, 68, 0x89c, 0x4, 12, 6},
285 {69, 70, 0x89c, 0x4, 0, 6},
286 {71, 72, 0xb90, 0x4, 0, 6},
287 {73, 86, 0xb90, 0x4, 24, 6},
288 {87, 90, 0xc90, 0x4, 0, 6},
289 {91, 102, 0xb9c, 0x4, 12, 6},
290};
291
292static const struct mtk_pin_reg_calc mt7622_reg_cals[PINCTRL_PIN_REG_MAX] = {
293 [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7622_pin_mode_range),
294 [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7622_pin_dir_range),
295 [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7622_pin_di_range),
296 [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7622_pin_do_range),
297 [PINCTRL_PIN_REG_SR] = MTK_RANGE(mt7622_pin_sr_range),
298 [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7622_pin_smt_range),
299 [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7622_pin_pu_range),
300 [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7622_pin_pd_range),
301 [PINCTRL_PIN_REG_E4] = MTK_RANGE(mt7622_pin_e4_range),
302 [PINCTRL_PIN_REG_E8] = MTK_RANGE(mt7622_pin_e8_range),
303 [PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt7622_pin_tdsel_range),
304 [PINCTRL_PIN_REG_RDSEL] = MTK_RANGE(mt7622_pin_rdsel_range),
305};
306
307static const struct pinctrl_pin_desc mt7622_pins[] = {
308 PINCTRL_PIN(0, "GPIO_A"),
309 PINCTRL_PIN(1, "I2S1_IN"),
310 PINCTRL_PIN(2, "I2S1_OUT"),
311 PINCTRL_PIN(3, "I2S_BCLK"),
312 PINCTRL_PIN(4, "I2S_WS"),
313 PINCTRL_PIN(5, "I2S_MCLK"),
314 PINCTRL_PIN(6, "TXD0"),
315 PINCTRL_PIN(7, "RXD0"),
316 PINCTRL_PIN(8, "SPI_WP"),
317 PINCTRL_PIN(9, "SPI_HOLD"),
318 PINCTRL_PIN(10, "SPI_CLK"),
319 PINCTRL_PIN(11, "SPI_MOSI"),
320 PINCTRL_PIN(12, "SPI_MISO"),
321 PINCTRL_PIN(13, "SPI_CS"),
322 PINCTRL_PIN(14, "I2C_SDA"),
323 PINCTRL_PIN(15, "I2C_SCL"),
324 PINCTRL_PIN(16, "I2S2_IN"),
325 PINCTRL_PIN(17, "I2S3_IN"),
326 PINCTRL_PIN(18, "I2S4_IN"),
327 PINCTRL_PIN(19, "I2S2_OUT"),
328 PINCTRL_PIN(20, "I2S3_OUT"),
329 PINCTRL_PIN(21, "I2S4_OUT"),
330 PINCTRL_PIN(22, "GPIO_B"),
331 PINCTRL_PIN(23, "MDC"),
332 PINCTRL_PIN(24, "MDIO"),
333 PINCTRL_PIN(25, "G2_TXD0"),
334 PINCTRL_PIN(26, "G2_TXD1"),
335 PINCTRL_PIN(27, "G2_TXD2"),
336 PINCTRL_PIN(28, "G2_TXD3"),
337 PINCTRL_PIN(29, "G2_TXEN"),
338 PINCTRL_PIN(30, "G2_TXC"),
339 PINCTRL_PIN(31, "G2_RXD0"),
340 PINCTRL_PIN(32, "G2_RXD1"),
341 PINCTRL_PIN(33, "G2_RXD2"),
342 PINCTRL_PIN(34, "G2_RXD3"),
343 PINCTRL_PIN(35, "G2_RXDV"),
344 PINCTRL_PIN(36, "G2_RXC"),
345 PINCTRL_PIN(37, "NCEB"),
346 PINCTRL_PIN(38, "NWEB"),
347 PINCTRL_PIN(39, "NREB"),
348 PINCTRL_PIN(40, "NDL4"),
349 PINCTRL_PIN(41, "NDL5"),
350 PINCTRL_PIN(42, "NDL6"),
351 PINCTRL_PIN(43, "NDL7"),
352 PINCTRL_PIN(44, "NRB"),
353 PINCTRL_PIN(45, "NCLE"),
354 PINCTRL_PIN(46, "NALE"),
355 PINCTRL_PIN(47, "NDL0"),
356 PINCTRL_PIN(48, "NDL1"),
357 PINCTRL_PIN(49, "NDL2"),
358 PINCTRL_PIN(50, "NDL3"),
359 PINCTRL_PIN(51, "MDI_TP_P0"),
360 PINCTRL_PIN(52, "MDI_TN_P0"),
361 PINCTRL_PIN(53, "MDI_RP_P0"),
362 PINCTRL_PIN(54, "MDI_RN_P0"),
363 PINCTRL_PIN(55, "MDI_TP_P1"),
364 PINCTRL_PIN(56, "MDI_TN_P1"),
365 PINCTRL_PIN(57, "MDI_RP_P1"),
366 PINCTRL_PIN(58, "MDI_RN_P1"),
367 PINCTRL_PIN(59, "MDI_RP_P2"),
368 PINCTRL_PIN(60, "MDI_RN_P2"),
369 PINCTRL_PIN(61, "MDI_TP_P2"),
370 PINCTRL_PIN(62, "MDI_TN_P2"),
371 PINCTRL_PIN(63, "MDI_TP_P3"),
372 PINCTRL_PIN(64, "MDI_TN_P3"),
373 PINCTRL_PIN(65, "MDI_RP_P3"),
374 PINCTRL_PIN(66, "MDI_RN_P3"),
375 PINCTRL_PIN(67, "MDI_RP_P4"),
376 PINCTRL_PIN(68, "MDI_RN_P4"),
377 PINCTRL_PIN(69, "MDI_TP_P4"),
378 PINCTRL_PIN(70, "MDI_TN_P4"),
379 PINCTRL_PIN(71, "PMIC_SCL"),
380 PINCTRL_PIN(72, "PMIC_SDA"),
381 PINCTRL_PIN(73, "SPIC1_CLK"),
382 PINCTRL_PIN(74, "SPIC1_MOSI"),
383 PINCTRL_PIN(75, "SPIC1_MISO"),
384 PINCTRL_PIN(76, "SPIC1_CS"),
385 PINCTRL_PIN(77, "GPIO_D"),
386 PINCTRL_PIN(78, "WATCHDOG"),
387 PINCTRL_PIN(79, "RTS3_N"),
388 PINCTRL_PIN(80, "CTS3_N"),
389 PINCTRL_PIN(81, "TXD3"),
390 PINCTRL_PIN(82, "RXD3"),
391 PINCTRL_PIN(83, "PERST0_N"),
392 PINCTRL_PIN(84, "PERST1_N"),
393 PINCTRL_PIN(85, "WLED_N"),
394 PINCTRL_PIN(86, "EPHY_LED0_N"),
395 PINCTRL_PIN(87, "AUXIN0"),
396 PINCTRL_PIN(88, "AUXIN1"),
397 PINCTRL_PIN(89, "AUXIN2"),
398 PINCTRL_PIN(90, "AUXIN3"),
399 PINCTRL_PIN(91, "TXD4"),
400 PINCTRL_PIN(92, "RXD4"),
401 PINCTRL_PIN(93, "RTS4_N"),
402 PINCTRL_PIN(94, "CTS4_N"),
403 PINCTRL_PIN(95, "PWM1"),
404 PINCTRL_PIN(96, "PWM2"),
405 PINCTRL_PIN(97, "PWM3"),
406 PINCTRL_PIN(98, "PWM4"),
407 PINCTRL_PIN(99, "PWM5"),
408 PINCTRL_PIN(100, "PWM6"),
409 PINCTRL_PIN(101, "PWM7"),
410 PINCTRL_PIN(102, "GPIO_E"),
411};
412
413/* List all groups consisting of these pins dedicated to the enablement of
414 * certain hardware block and the corresponding mode for all of the pins. The
415 * hardware probably has multiple combinations of these pinouts.
416 */
417
418/* EMMC */
419static int mt7622_emmc_pins[] = { 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, };
420static int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
421
422static int mt7622_emmc_rst_pins[] = { 37, };
423static int mt7622_emmc_rst_funcs[] = { 1, };
424
425/* LED for EPHY */
426static int mt7622_ephy_leds_pins[] = { 86, 91, 92, 93, 94, };
427static int mt7622_ephy_leds_funcs[] = { 0, 0, 0, 0, 0, };
428static int mt7622_ephy0_led_pins[] = { 86, };
429static int mt7622_ephy0_led_funcs[] = { 0, };
430static int mt7622_ephy1_led_pins[] = { 91, };
431static int mt7622_ephy1_led_funcs[] = { 2, };
432static int mt7622_ephy2_led_pins[] = { 92, };
433static int mt7622_ephy2_led_funcs[] = { 2, };
434static int mt7622_ephy3_led_pins[] = { 93, };
435static int mt7622_ephy3_led_funcs[] = { 2, };
436static int mt7622_ephy4_led_pins[] = { 94, };
437static int mt7622_ephy4_led_funcs[] = { 2, };
438
439/* Embedded Switch */
440static int mt7622_esw_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
441 62, 63, 64, 65, 66, 67, 68, 69, 70, };
442static int mt7622_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
443 0, 0, 0, 0, 0, 0, 0, 0, 0, };
444static int mt7622_esw_p0_p1_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, };
445static int mt7622_esw_p0_p1_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
446static int mt7622_esw_p2_p3_p4_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, 67,
447 68, 69, 70, };
448static int mt7622_esw_p2_p3_p4_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
449 0, 0, 0, };
450/* RGMII via ESW */
451static int mt7622_rgmii_via_esw_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66,
452 67, 68, 69, 70, };
453static int mt7622_rgmii_via_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
454 0, };
455
456/* RGMII via GMAC1 */
457static int mt7622_rgmii_via_gmac1_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66,
458 67, 68, 69, 70, };
459static int mt7622_rgmii_via_gmac1_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
460 2, };
461
462/* RGMII via GMAC2 */
463static int mt7622_rgmii_via_gmac2_pins[] = { 25, 26, 27, 28, 29, 30, 31, 32,
464 33, 34, 35, 36, };
465static int mt7622_rgmii_via_gmac2_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
466 0, };
467
468/* I2C */
469static int mt7622_i2c0_pins[] = { 14, 15, };
470static int mt7622_i2c0_funcs[] = { 0, 0, };
471static int mt7622_i2c1_0_pins[] = { 55, 56, };
472static int mt7622_i2c1_0_funcs[] = { 0, 0, };
473static int mt7622_i2c1_1_pins[] = { 73, 74, };
474static int mt7622_i2c1_1_funcs[] = { 3, 3, };
475static int mt7622_i2c1_2_pins[] = { 87, 88, };
476static int mt7622_i2c1_2_funcs[] = { 0, 0, };
477static int mt7622_i2c2_0_pins[] = { 57, 58, };
478static int mt7622_i2c2_0_funcs[] = { 0, 0, };
479static int mt7622_i2c2_1_pins[] = { 75, 76, };
480static int mt7622_i2c2_1_funcs[] = { 3, 3, };
481static int mt7622_i2c2_2_pins[] = { 89, 90, };
482static int mt7622_i2c2_2_funcs[] = { 0, 0, };
483
484/* I2S */
485static int mt7622_i2s_in_mclk_bclk_ws_pins[] = { 3, 4, 5, };
486static int mt7622_i2s_in_mclk_bclk_ws_funcs[] = { 3, 3, 0, };
487static int mt7622_i2s1_in_data_pins[] = { 1, };
488static int mt7622_i2s1_in_data_funcs[] = { 0, };
489static int mt7622_i2s2_in_data_pins[] = { 16, };
490static int mt7622_i2s2_in_data_funcs[] = { 0, };
491static int mt7622_i2s3_in_data_pins[] = { 17, };
492static int mt7622_i2s3_in_data_funcs[] = { 0, };
493static int mt7622_i2s4_in_data_pins[] = { 18, };
494static int mt7622_i2s4_in_data_funcs[] = { 0, };
495static int mt7622_i2s_out_mclk_bclk_ws_pins[] = { 3, 4, 5, };
496static int mt7622_i2s_out_mclk_bclk_ws_funcs[] = { 0, 0, 0, };
497static int mt7622_i2s1_out_data_pins[] = { 2, };
498static int mt7622_i2s1_out_data_funcs[] = { 0, };
499static int mt7622_i2s2_out_data_pins[] = { 19, };
500static int mt7622_i2s2_out_data_funcs[] = { 0, };
501static int mt7622_i2s3_out_data_pins[] = { 20, };
502static int mt7622_i2s3_out_data_funcs[] = { 0, };
503static int mt7622_i2s4_out_data_pins[] = { 21, };
504static int mt7622_i2s4_out_data_funcs[] = { 0, };
505
506/* IR */
507static int mt7622_ir_0_tx_pins[] = { 16, };
508static int mt7622_ir_0_tx_funcs[] = { 4, };
509static int mt7622_ir_1_tx_pins[] = { 59, };
510static int mt7622_ir_1_tx_funcs[] = { 5, };
511static int mt7622_ir_2_tx_pins[] = { 99, };
512static int mt7622_ir_2_tx_funcs[] = { 3, };
513static int mt7622_ir_0_rx_pins[] = { 17, };
514static int mt7622_ir_0_rx_funcs[] = { 4, };
515static int mt7622_ir_1_rx_pins[] = { 60, };
516static int mt7622_ir_1_rx_funcs[] = { 5, };
517static int mt7622_ir_2_rx_pins[] = { 100, };
518static int mt7622_ir_2_rx_funcs[] = { 3, };
519
520/* MDIO */
521static int mt7622_mdc_mdio_pins[] = { 23, 24, };
522static int mt7622_mdc_mdio_funcs[] = { 0, 0, };
523
524/* PCIE */
525static int mt7622_pcie0_0_waken_pins[] = { 14, };
526static int mt7622_pcie0_0_waken_funcs[] = { 2, };
527static int mt7622_pcie0_0_clkreq_pins[] = { 15, };
528static int mt7622_pcie0_0_clkreq_funcs[] = { 2, };
529static int mt7622_pcie0_1_waken_pins[] = { 79, };
530static int mt7622_pcie0_1_waken_funcs[] = { 4, };
531static int mt7622_pcie0_1_clkreq_pins[] = { 80, };
532static int mt7622_pcie0_1_clkreq_funcs[] = { 4, };
533static int mt7622_pcie1_0_waken_pins[] = { 14, };
534static int mt7622_pcie1_0_waken_funcs[] = { 3, };
535static int mt7622_pcie1_0_clkreq_pins[] = { 15, };
536static int mt7622_pcie1_0_clkreq_funcs[] = { 3, };
537
538static int mt7622_pcie0_pad_perst_pins[] = { 83, };
539static int mt7622_pcie0_pad_perst_funcs[] = { 0, };
540static int mt7622_pcie1_pad_perst_pins[] = { 84, };
541static int mt7622_pcie1_pad_perst_funcs[] = { 0, };
542
543/* PMIC bus */
544static int mt7622_pmic_bus_pins[] = { 71, 72, };
545static int mt7622_pmic_bus_funcs[] = { 0, 0, };
546
547/* Parallel NAND */
548static int mt7622_pnand_pins[] = { 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
549 48, 49, 50, };
550static int mt7622_pnand_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
551 0, };
552
553/* PWM */
554static int mt7622_pwm_ch1_0_pins[] = { 51, };
555static int mt7622_pwm_ch1_0_funcs[] = { 3, };
556static int mt7622_pwm_ch1_1_pins[] = { 73, };
557static int mt7622_pwm_ch1_1_funcs[] = { 4, };
558static int mt7622_pwm_ch1_2_pins[] = { 95, };
559static int mt7622_pwm_ch1_2_funcs[] = { 0, };
560static int mt7622_pwm_ch2_0_pins[] = { 52, };
561static int mt7622_pwm_ch2_0_funcs[] = { 3, };
562static int mt7622_pwm_ch2_1_pins[] = { 74, };
563static int mt7622_pwm_ch2_1_funcs[] = { 4, };
564static int mt7622_pwm_ch2_2_pins[] = { 96, };
565static int mt7622_pwm_ch2_2_funcs[] = { 0, };
566static int mt7622_pwm_ch3_0_pins[] = { 53, };
567static int mt7622_pwm_ch3_0_funcs[] = { 3, };
568static int mt7622_pwm_ch3_1_pins[] = { 75, };
569static int mt7622_pwm_ch3_1_funcs[] = { 4, };
570static int mt7622_pwm_ch3_2_pins[] = { 97, };
571static int mt7622_pwm_ch3_2_funcs[] = { 0, };
572static int mt7622_pwm_ch4_0_pins[] = { 54, };
573static int mt7622_pwm_ch4_0_funcs[] = { 3, };
574static int mt7622_pwm_ch4_1_pins[] = { 67, };
575static int mt7622_pwm_ch4_1_funcs[] = { 3, };
576static int mt7622_pwm_ch4_2_pins[] = { 76, };
577static int mt7622_pwm_ch4_2_funcs[] = { 4, };
578static int mt7622_pwm_ch4_3_pins[] = { 98, };
579static int mt7622_pwm_ch4_3_funcs[] = { 0, };
580static int mt7622_pwm_ch5_0_pins[] = { 68, };
581static int mt7622_pwm_ch5_0_funcs[] = { 3, };
582static int mt7622_pwm_ch5_1_pins[] = { 77, };
583static int mt7622_pwm_ch5_1_funcs[] = { 4, };
584static int mt7622_pwm_ch5_2_pins[] = { 99, };
585static int mt7622_pwm_ch5_2_funcs[] = { 0, };
586static int mt7622_pwm_ch6_0_pins[] = { 69, };
587static int mt7622_pwm_ch6_0_funcs[] = { 3, };
588static int mt7622_pwm_ch6_1_pins[] = { 78, };
589static int mt7622_pwm_ch6_1_funcs[] = { 4, };
590static int mt7622_pwm_ch6_2_pins[] = { 81, };
591static int mt7622_pwm_ch6_2_funcs[] = { 4, };
592static int mt7622_pwm_ch6_3_pins[] = { 100, };
593static int mt7622_pwm_ch6_3_funcs[] = { 0, };
594static int mt7622_pwm_ch7_0_pins[] = { 70, };
595static int mt7622_pwm_ch7_0_funcs[] = { 3, };
596static int mt7622_pwm_ch7_1_pins[] = { 82, };
597static int mt7622_pwm_ch7_1_funcs[] = { 4, };
598static int mt7622_pwm_ch7_2_pins[] = { 101, };
599static int mt7622_pwm_ch7_2_funcs[] = { 0, };
600
601/* SD */
602static int mt7622_sd_0_pins[] = { 16, 17, 18, 19, 20, 21, };
603static int mt7622_sd_0_funcs[] = { 2, 2, 2, 2, 2, 2, };
604static int mt7622_sd_1_pins[] = { 25, 26, 27, 28, 29, 30, };
605static int mt7622_sd_1_funcs[] = { 2, 2, 2, 2, 2, 2, };
606
607/* Serial NAND */
608static int mt7622_snfi_pins[] = { 8, 9, 10, 11, 12, 13, };
609static int mt7622_snfi_funcs[] = { 2, 2, 2, 2, 2, 2, };
610
611/* SPI NOR */
612static int mt7622_spi_pins[] = { 8, 9, 10, 11, 12, 13 };
613static int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, };
614
615/* SPIC */
616static int mt7622_spic0_0_pins[] = { 63, 64, 65, 66, };
617static int mt7622_spic0_0_funcs[] = { 4, 4, 4, 4, };
618static int mt7622_spic0_1_pins[] = { 79, 80, 81, 82, };
619static int mt7622_spic0_1_funcs[] = { 3, 3, 3, 3, };
620static int mt7622_spic1_0_pins[] = { 67, 68, 69, 70, };
621static int mt7622_spic1_0_funcs[] = { 4, 4, 4, 4, };
622static int mt7622_spic1_1_pins[] = { 73, 74, 75, 76, };
623static int mt7622_spic1_1_funcs[] = { 0, 0, 0, 0, };
624static int mt7622_spic2_0_pins[] = { 10, 11, 12, 13, };
625static int mt7622_spic2_0_funcs[] = { 0, 0, 0, 0, };
626static int mt7622_spic2_0_wp_hold_pins[] = { 8, 9, };
627static int mt7622_spic2_0_wp_hold_funcs[] = { 0, 0, };
628
629/* TDM */
630static int mt7622_tdm_0_out_mclk_bclk_ws_pins[] = { 8, 9, 10, };
631static int mt7622_tdm_0_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
632static int mt7622_tdm_0_in_mclk_bclk_ws_pins[] = { 11, 12, 13, };
633static int mt7622_tdm_0_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
634static int mt7622_tdm_0_out_data_pins[] = { 20, };
635static int mt7622_tdm_0_out_data_funcs[] = { 3, };
636static int mt7622_tdm_0_in_data_pins[] = { 21, };
637static int mt7622_tdm_0_in_data_funcs[] = { 3, };
638static int mt7622_tdm_1_out_mclk_bclk_ws_pins[] = { 57, 58, 59, };
639static int mt7622_tdm_1_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
640static int mt7622_tdm_1_in_mclk_bclk_ws_pins[] = { 60, 61, 62, };
641static int mt7622_tdm_1_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
642static int mt7622_tdm_1_out_data_pins[] = { 55, };
643static int mt7622_tdm_1_out_data_funcs[] = { 3, };
644static int mt7622_tdm_1_in_data_pins[] = { 56, };
645static int mt7622_tdm_1_in_data_funcs[] = { 3, };
646
647/* UART */
648static int mt7622_uart0_0_tx_rx_pins[] = { 6, 7, };
649static int mt7622_uart0_0_tx_rx_funcs[] = { 0, 0, };
650static int mt7622_uart1_0_tx_rx_pins[] = { 55, 56, };
651static int mt7622_uart1_0_tx_rx_funcs[] = { 2, 2, };
652static int mt7622_uart1_0_rts_cts_pins[] = { 57, 58, };
653static int mt7622_uart1_0_rts_cts_funcs[] = { 2, 2, };
654static int mt7622_uart1_1_tx_rx_pins[] = { 73, 74, };
655static int mt7622_uart1_1_tx_rx_funcs[] = { 2, 2, };
656static int mt7622_uart1_1_rts_cts_pins[] = { 75, 76, };
657static int mt7622_uart1_1_rts_cts_funcs[] = { 2, 2, };
658static int mt7622_uart2_0_tx_rx_pins[] = { 3, 4, };
659static int mt7622_uart2_0_tx_rx_funcs[] = { 2, 2, };
660static int mt7622_uart2_0_rts_cts_pins[] = { 1, 2, };
661static int mt7622_uart2_0_rts_cts_funcs[] = { 2, 2, };
662static int mt7622_uart2_1_tx_rx_pins[] = { 51, 52, };
663static int mt7622_uart2_1_tx_rx_funcs[] = { 0, 0, };
664static int mt7622_uart2_1_rts_cts_pins[] = { 53, 54, };
665static int mt7622_uart2_1_rts_cts_funcs[] = { 0, 0, };
666static int mt7622_uart2_2_tx_rx_pins[] = { 59, 60, };
667static int mt7622_uart2_2_tx_rx_funcs[] = { 4, 4, };
668static int mt7622_uart2_2_rts_cts_pins[] = { 61, 62, };
669static int mt7622_uart2_2_rts_cts_funcs[] = { 4, 4, };
670static int mt7622_uart2_3_tx_rx_pins[] = { 95, 96, };
671static int mt7622_uart2_3_tx_rx_funcs[] = { 3, 3, };
672static int mt7622_uart3_0_tx_rx_pins[] = { 57, 58, };
673static int mt7622_uart3_0_tx_rx_funcs[] = { 5, 5, };
674static int mt7622_uart3_1_tx_rx_pins[] = { 81, 82, };
675static int mt7622_uart3_1_tx_rx_funcs[] = { 0, 0, };
676static int mt7622_uart3_1_rts_cts_pins[] = { 79, 80, };
677static int mt7622_uart3_1_rts_cts_funcs[] = { 0, 0, };
678static int mt7622_uart4_0_tx_rx_pins[] = { 61, 62, };
679static int mt7622_uart4_0_tx_rx_funcs[] = { 5, 5, };
680static int mt7622_uart4_1_tx_rx_pins[] = { 91, 92, };
681static int mt7622_uart4_1_tx_rx_funcs[] = { 0, 0, };
682static int mt7622_uart4_1_rts_cts_pins[] = { 93, 94 };
683static int mt7622_uart4_1_rts_cts_funcs[] = { 0, 0, };
684static int mt7622_uart4_2_tx_rx_pins[] = { 97, 98, };
685static int mt7622_uart4_2_tx_rx_funcs[] = { 2, 2, };
686static int mt7622_uart4_2_rts_cts_pins[] = { 95, 96 };
687static int mt7622_uart4_2_rts_cts_funcs[] = { 2, 2, };
688
689/* Watchdog */
690static int mt7622_watchdog_pins[] = { 78, };
691static int mt7622_watchdog_funcs[] = { 0, };
692
693/* WLAN LED */
694static int mt7622_wled_pins[] = { 85, };
695static int mt7622_wled_funcs[] = { 0, };
696
697static const struct group_desc mt7622_groups[] = {
698 PINCTRL_PIN_GROUP("emmc", mt7622_emmc),
699 PINCTRL_PIN_GROUP("emmc_rst", mt7622_emmc_rst),
700 PINCTRL_PIN_GROUP("ephy_leds", mt7622_ephy_leds),
701 PINCTRL_PIN_GROUP("ephy0_led", mt7622_ephy0_led),
702 PINCTRL_PIN_GROUP("ephy1_led", mt7622_ephy1_led),
703 PINCTRL_PIN_GROUP("ephy2_led", mt7622_ephy2_led),
704 PINCTRL_PIN_GROUP("ephy3_led", mt7622_ephy3_led),
705 PINCTRL_PIN_GROUP("ephy4_led", mt7622_ephy4_led),
706 PINCTRL_PIN_GROUP("esw", mt7622_esw),
707 PINCTRL_PIN_GROUP("esw_p0_p1", mt7622_esw_p0_p1),
708 PINCTRL_PIN_GROUP("esw_p2_p3_p4", mt7622_esw_p2_p3_p4),
709 PINCTRL_PIN_GROUP("rgmii_via_esw", mt7622_rgmii_via_esw),
710 PINCTRL_PIN_GROUP("rgmii_via_gmac1", mt7622_rgmii_via_gmac1),
711 PINCTRL_PIN_GROUP("rgmii_via_gmac2", mt7622_rgmii_via_gmac2),
712 PINCTRL_PIN_GROUP("i2c0", mt7622_i2c0),
713 PINCTRL_PIN_GROUP("i2c1_0", mt7622_i2c1_0),
714 PINCTRL_PIN_GROUP("i2c1_1", mt7622_i2c1_1),
715 PINCTRL_PIN_GROUP("i2c1_2", mt7622_i2c1_2),
716 PINCTRL_PIN_GROUP("i2c2_0", mt7622_i2c2_0),
717 PINCTRL_PIN_GROUP("i2c2_1", mt7622_i2c2_1),
718 PINCTRL_PIN_GROUP("i2c2_2", mt7622_i2c2_2),
719 PINCTRL_PIN_GROUP("i2s_out_mclk_bclk_ws", mt7622_i2s_out_mclk_bclk_ws),
720 PINCTRL_PIN_GROUP("i2s_in_mclk_bclk_ws", mt7622_i2s_in_mclk_bclk_ws),
721 PINCTRL_PIN_GROUP("i2s1_in_data", mt7622_i2s1_in_data),
722 PINCTRL_PIN_GROUP("i2s2_in_data", mt7622_i2s2_in_data),
723 PINCTRL_PIN_GROUP("i2s3_in_data", mt7622_i2s3_in_data),
724 PINCTRL_PIN_GROUP("i2s4_in_data", mt7622_i2s4_in_data),
725 PINCTRL_PIN_GROUP("i2s1_out_data", mt7622_i2s1_out_data),
726 PINCTRL_PIN_GROUP("i2s2_out_data", mt7622_i2s2_out_data),
727 PINCTRL_PIN_GROUP("i2s3_out_data", mt7622_i2s3_out_data),
728 PINCTRL_PIN_GROUP("i2s4_out_data", mt7622_i2s4_out_data),
729 PINCTRL_PIN_GROUP("ir_0_tx", mt7622_ir_0_tx),
730 PINCTRL_PIN_GROUP("ir_1_tx", mt7622_ir_1_tx),
731 PINCTRL_PIN_GROUP("ir_2_tx", mt7622_ir_2_tx),
732 PINCTRL_PIN_GROUP("ir_0_rx", mt7622_ir_0_rx),
733 PINCTRL_PIN_GROUP("ir_1_rx", mt7622_ir_1_rx),
734 PINCTRL_PIN_GROUP("ir_2_rx", mt7622_ir_2_rx),
735 PINCTRL_PIN_GROUP("mdc_mdio", mt7622_mdc_mdio),
736 PINCTRL_PIN_GROUP("pcie0_0_waken", mt7622_pcie0_0_waken),
737 PINCTRL_PIN_GROUP("pcie0_0_clkreq", mt7622_pcie0_0_clkreq),
738 PINCTRL_PIN_GROUP("pcie0_1_waken", mt7622_pcie0_1_waken),
739 PINCTRL_PIN_GROUP("pcie0_1_clkreq", mt7622_pcie0_1_clkreq),
740 PINCTRL_PIN_GROUP("pcie1_0_waken", mt7622_pcie1_0_waken),
741 PINCTRL_PIN_GROUP("pcie1_0_clkreq", mt7622_pcie1_0_clkreq),
742 PINCTRL_PIN_GROUP("pcie0_pad_perst", mt7622_pcie0_pad_perst),
743 PINCTRL_PIN_GROUP("pcie1_pad_perst", mt7622_pcie1_pad_perst),
744 PINCTRL_PIN_GROUP("par_nand", mt7622_pnand),
745 PINCTRL_PIN_GROUP("pmic_bus", mt7622_pmic_bus),
746 PINCTRL_PIN_GROUP("pwm_ch1_0", mt7622_pwm_ch1_0),
747 PINCTRL_PIN_GROUP("pwm_ch1_1", mt7622_pwm_ch1_1),
748 PINCTRL_PIN_GROUP("pwm_ch1_2", mt7622_pwm_ch1_2),
749 PINCTRL_PIN_GROUP("pwm_ch2_0", mt7622_pwm_ch2_0),
750 PINCTRL_PIN_GROUP("pwm_ch2_1", mt7622_pwm_ch2_1),
751 PINCTRL_PIN_GROUP("pwm_ch2_2", mt7622_pwm_ch2_2),
752 PINCTRL_PIN_GROUP("pwm_ch3_0", mt7622_pwm_ch3_0),
753 PINCTRL_PIN_GROUP("pwm_ch3_1", mt7622_pwm_ch3_1),
754 PINCTRL_PIN_GROUP("pwm_ch3_2", mt7622_pwm_ch3_2),
755 PINCTRL_PIN_GROUP("pwm_ch4_0", mt7622_pwm_ch4_0),
756 PINCTRL_PIN_GROUP("pwm_ch4_1", mt7622_pwm_ch4_1),
757 PINCTRL_PIN_GROUP("pwm_ch4_2", mt7622_pwm_ch4_2),
758 PINCTRL_PIN_GROUP("pwm_ch4_3", mt7622_pwm_ch4_3),
759 PINCTRL_PIN_GROUP("pwm_ch5_0", mt7622_pwm_ch5_0),
760 PINCTRL_PIN_GROUP("pwm_ch5_1", mt7622_pwm_ch5_1),
761 PINCTRL_PIN_GROUP("pwm_ch5_2", mt7622_pwm_ch5_2),
762 PINCTRL_PIN_GROUP("pwm_ch6_0", mt7622_pwm_ch6_0),
763 PINCTRL_PIN_GROUP("pwm_ch6_1", mt7622_pwm_ch6_1),
764 PINCTRL_PIN_GROUP("pwm_ch6_2", mt7622_pwm_ch6_2),
765 PINCTRL_PIN_GROUP("pwm_ch6_3", mt7622_pwm_ch6_3),
766 PINCTRL_PIN_GROUP("pwm_ch7_0", mt7622_pwm_ch7_0),
767 PINCTRL_PIN_GROUP("pwm_ch7_1", mt7622_pwm_ch7_1),
768 PINCTRL_PIN_GROUP("pwm_ch7_2", mt7622_pwm_ch7_2),
769 PINCTRL_PIN_GROUP("sd_0", mt7622_sd_0),
770 PINCTRL_PIN_GROUP("sd_1", mt7622_sd_1),
771 PINCTRL_PIN_GROUP("snfi", mt7622_snfi),
772 PINCTRL_PIN_GROUP("spi_nor", mt7622_spi),
773 PINCTRL_PIN_GROUP("spic0_0", mt7622_spic0_0),
774 PINCTRL_PIN_GROUP("spic0_1", mt7622_spic0_1),
775 PINCTRL_PIN_GROUP("spic1_0", mt7622_spic1_0),
776 PINCTRL_PIN_GROUP("spic1_1", mt7622_spic1_1),
777 PINCTRL_PIN_GROUP("spic2_0", mt7622_spic2_0),
778 PINCTRL_PIN_GROUP("spic2_0_wp_hold", mt7622_spic2_0_wp_hold),
779 PINCTRL_PIN_GROUP("tdm_0_out_mclk_bclk_ws",
780 mt7622_tdm_0_out_mclk_bclk_ws),
781 PINCTRL_PIN_GROUP("tdm_0_in_mclk_bclk_ws",
782 mt7622_tdm_0_in_mclk_bclk_ws),
783 PINCTRL_PIN_GROUP("tdm_0_out_data", mt7622_tdm_0_out_data),
784 PINCTRL_PIN_GROUP("tdm_0_in_data", mt7622_tdm_0_in_data),
785 PINCTRL_PIN_GROUP("tdm_1_out_mclk_bclk_ws",
786 mt7622_tdm_1_out_mclk_bclk_ws),
787 PINCTRL_PIN_GROUP("tdm_1_in_mclk_bclk_ws",
788 mt7622_tdm_1_in_mclk_bclk_ws),
789 PINCTRL_PIN_GROUP("tdm_1_out_data", mt7622_tdm_1_out_data),
790 PINCTRL_PIN_GROUP("tdm_1_in_data", mt7622_tdm_1_in_data),
791 PINCTRL_PIN_GROUP("uart0_0_tx_rx", mt7622_uart0_0_tx_rx),
792 PINCTRL_PIN_GROUP("uart1_0_tx_rx", mt7622_uart1_0_tx_rx),
793 PINCTRL_PIN_GROUP("uart1_0_rts_cts", mt7622_uart1_0_rts_cts),
794 PINCTRL_PIN_GROUP("uart1_1_tx_rx", mt7622_uart1_1_tx_rx),
795 PINCTRL_PIN_GROUP("uart1_1_rts_cts", mt7622_uart1_1_rts_cts),
796 PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7622_uart2_0_tx_rx),
797 PINCTRL_PIN_GROUP("uart2_0_rts_cts", mt7622_uart2_0_rts_cts),
798 PINCTRL_PIN_GROUP("uart2_1_tx_rx", mt7622_uart2_1_tx_rx),
799 PINCTRL_PIN_GROUP("uart2_1_rts_cts", mt7622_uart2_1_rts_cts),
800 PINCTRL_PIN_GROUP("uart2_2_tx_rx", mt7622_uart2_2_tx_rx),
801 PINCTRL_PIN_GROUP("uart2_2_rts_cts", mt7622_uart2_2_rts_cts),
802 PINCTRL_PIN_GROUP("uart2_3_tx_rx", mt7622_uart2_3_tx_rx),
803 PINCTRL_PIN_GROUP("uart3_0_tx_rx", mt7622_uart3_0_tx_rx),
804 PINCTRL_PIN_GROUP("uart3_1_tx_rx", mt7622_uart3_1_tx_rx),
805 PINCTRL_PIN_GROUP("uart3_1_rts_cts", mt7622_uart3_1_rts_cts),
806 PINCTRL_PIN_GROUP("uart4_0_tx_rx", mt7622_uart4_0_tx_rx),
807 PINCTRL_PIN_GROUP("uart4_1_tx_rx", mt7622_uart4_1_tx_rx),
808 PINCTRL_PIN_GROUP("uart4_1_rts_cts", mt7622_uart4_1_rts_cts),
809 PINCTRL_PIN_GROUP("uart4_2_tx_rx", mt7622_uart4_2_tx_rx),
810 PINCTRL_PIN_GROUP("uart4_2_rts_cts", mt7622_uart4_2_rts_cts),
811 PINCTRL_PIN_GROUP("watchdog", mt7622_watchdog),
812 PINCTRL_PIN_GROUP("wled", mt7622_wled),
813};
814
815/* Joint those groups owning the same capability in user point of view which
816 * allows that people tend to use through the device tree.
817 */
818static const char *mt7622_emmc_groups[] = { "emmc", "emmc_rst", };
819static const char *mt7622_ethernet_groups[] = { "esw", "esw_p0_p1",
820 "esw_p2_p3_p4", "mdc_mdio",
821 "rgmii_via_gmac1",
822 "rgmii_via_gmac2",
823 "rgmii_via_esw", };
824static const char *mt7622_i2c_groups[] = { "i2c0", "i2c1_0", "i2c1_1",
825 "i2c1_2", "i2c2_0", "i2c2_1",
826 "i2c2_2", };
827static const char *mt7622_i2s_groups[] = { "i2s_out_mclk_bclk_ws",
828 "i2s_in_mclk_bclk_ws",
829 "i2s1_in_data", "i2s2_in_data",
830 "i2s3_in_data", "i2s4_in_data",
831 "i2s1_out_data", "i2s2_out_data",
832 "i2s3_out_data", "i2s4_out_data", };
833static const char *mt7622_ir_groups[] = { "ir_0_tx", "ir_1_tx", "ir_2_tx",
834 "ir_0_rx", "ir_1_rx", "ir_2_rx"};
835static const char *mt7622_led_groups[] = { "ephy_leds", "ephy0_led",
836 "ephy1_led", "ephy2_led",
837 "ephy3_led", "ephy4_led",
838 "wled", };
839static const char *mt7622_flash_groups[] = { "par_nand", "snfi", "spi_nor"};
840static const char *mt7622_pcie_groups[] = { "pcie0_0_waken", "pcie0_0_clkreq",
841 "pcie0_1_waken", "pcie0_1_clkreq",
842 "pcie1_0_waken", "pcie1_0_clkreq",
843 "pcie0_pad_perst",
844 "pcie1_pad_perst", };
845static const char *mt7622_pmic_bus_groups[] = { "pmic_bus", };
846static const char *mt7622_pwm_groups[] = { "pwm_ch1_0", "pwm_ch1_1",
847 "pwm_ch1_2", "pwm_ch2_0",
848 "pwm_ch2_1", "pwm_ch2_2",
849 "pwm_ch3_0", "pwm_ch3_1",
850 "pwm_ch3_2", "pwm_ch4_0",
851 "pwm_ch4_1", "pwm_ch4_2",
852 "pwm_ch4_3", "pwm_ch5_0",
853 "pwm_ch5_1", "pwm_ch5_2",
854 "pwm_ch6_0", "pwm_ch6_1",
855 "pwm_ch6_2", "pwm_ch6_3",
856 "pwm_ch7_0", "pwm_ch7_1",
857 "pwm_ch7_2", };
858static const char *mt7622_sd_groups[] = { "sd_0", "sd_1", };
859static const char *mt7622_spic_groups[] = { "spic0_0", "spic0_1", "spic1_0",
860 "spic1_1", "spic2_0",
861 "spic2_0_wp_hold", };
862static const char *mt7622_tdm_groups[] = { "tdm_0_out_mclk_bclk_ws",
863 "tdm_0_in_mclk_bclk_ws",
864 "tdm_0_out_data",
865 "tdm_0_in_data",
866 "tdm_1_out_mclk_bclk_ws",
867 "tdm_1_in_mclk_bclk_ws",
868 "tdm_1_out_data",
869 "tdm_1_in_data", };
870
871static const char *mt7622_uart_groups[] = { "uart0_0_tx_rx",
872 "uart1_0_tx_rx", "uart1_0_rts_cts",
873 "uart1_1_tx_rx", "uart1_1_rts_cts",
874 "uart2_0_tx_rx", "uart2_0_rts_cts",
875 "uart2_1_tx_rx", "uart2_1_rts_cts",
876 "uart2_2_tx_rx", "uart2_2_rts_cts",
877 "uart2_3_tx_rx",
878 "uart3_0_tx_rx",
879 "uart3_1_tx_rx", "uart3_1_rts_cts",
880 "uart4_0_tx_rx",
881 "uart4_1_tx_rx", "uart4_1_rts_cts",
882 "uart4_2_tx_rx",
883 "uart4_2_rts_cts",};
884static const char *mt7622_wdt_groups[] = { "watchdog", };
885
886static const struct function_desc mt7622_functions[] = {
887 {"emmc", mt7622_emmc_groups, ARRAY_SIZE(mt7622_emmc_groups)},
888 {"eth", mt7622_ethernet_groups, ARRAY_SIZE(mt7622_ethernet_groups)},
889 {"i2c", mt7622_i2c_groups, ARRAY_SIZE(mt7622_i2c_groups)},
890 {"i2s", mt7622_i2s_groups, ARRAY_SIZE(mt7622_i2s_groups)},
891 {"ir", mt7622_ir_groups, ARRAY_SIZE(mt7622_ir_groups)},
892 {"led", mt7622_led_groups, ARRAY_SIZE(mt7622_led_groups)},
893 {"flash", mt7622_flash_groups, ARRAY_SIZE(mt7622_flash_groups)},
894 {"pcie", mt7622_pcie_groups, ARRAY_SIZE(mt7622_pcie_groups)},
895 {"pmic", mt7622_pmic_bus_groups, ARRAY_SIZE(mt7622_pmic_bus_groups)},
896 {"pwm", mt7622_pwm_groups, ARRAY_SIZE(mt7622_pwm_groups)},
897 {"sd", mt7622_sd_groups, ARRAY_SIZE(mt7622_sd_groups)},
898 {"spi", mt7622_spic_groups, ARRAY_SIZE(mt7622_spic_groups)},
899 {"tdm", mt7622_tdm_groups, ARRAY_SIZE(mt7622_tdm_groups)},
900 {"uart", mt7622_uart_groups, ARRAY_SIZE(mt7622_uart_groups)},
901 {"watchdog", mt7622_wdt_groups, ARRAY_SIZE(mt7622_wdt_groups)},
902};
903
904static const struct pinconf_generic_params mtk_custom_bindings[] = {
905 {"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0},
906 {"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0},
907};
908
909#ifdef CONFIG_DEBUG_FS
910static const struct pin_config_item mtk_conf_items[] = {
911 PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true),
912 PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true),
913};
914#endif
915
916static const struct mtk_pin_soc mt7622_data = {
917 .reg_cal = mt7622_reg_cals,
918 .pins = mt7622_pins,
919 .npins = ARRAY_SIZE(mt7622_pins),
920 .grps = mt7622_groups,
921 .ngrps = ARRAY_SIZE(mt7622_groups),
922 .funcs = mt7622_functions,
923 .nfuncs = ARRAY_SIZE(mt7622_functions),
924};
925
926static void mtk_w32(struct mtk_pinctrl *pctl, u32 reg, u32 val)
927{
928 writel_relaxed(val, pctl->base + reg);
929}
930
931static u32 mtk_r32(struct mtk_pinctrl *pctl, u32 reg)
932{
933 return readl_relaxed(pctl->base + reg);
934}
935
936static void mtk_rmw(struct mtk_pinctrl *pctl, u32 reg, u32 mask, u32 set)
937{
938 u32 val;
939
940 val = mtk_r32(pctl, reg);
941 val &= ~mask;
942 val |= set;
943 mtk_w32(pctl, reg, val);
944}
945
946static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw, int pin,
947 const struct mtk_pin_reg_calc *rc,
948 struct mtk_pin_field *pfd)
949{
950 const struct mtk_pin_field_calc *c, *e;
951 u32 bits;
952
953 c = rc->range;
954 e = c + rc->nranges;
955
956 while (c < e) {
957 if (pin >= c->s_pin && pin <= c->e_pin)
958 break;
959 c++;
960 }
961
962 if (c >= e) {
963 dev_err(hw->dev, "Out of range for pin = %d\n", pin);
964 return -EINVAL;
965 }
966
967 /* Caculated bits as the overall offset the pin is located at */
968 bits = c->s_bit + (pin - c->s_pin) * (c->x_bits);
969
970 /* Fill pfd from bits and 32-bit register applied is assumed */
971 pfd->offset = c->s_addr + c->x_addrs * (bits / 32);
972 pfd->bitpos = bits % 32;
973 pfd->mask = (1 << c->x_bits) - 1;
974
975 /* pfd->next is used for indicating that bit wrapping-around happens
976 * which requires the manipulation for bit 0 starting in the next
977 * register to form the complete field read/write.
978 */
979 pfd->next = pfd->bitpos + c->x_bits - 1 > 31 ? c->x_addrs : 0;
980
981 return 0;
982}
983
984static int mtk_hw_pin_field_get(struct mtk_pinctrl *hw, int pin,
985 int field, struct mtk_pin_field *pfd)
986{
987 const struct mtk_pin_reg_calc *rc;
988
989 if (field < 0 || field >= PINCTRL_PIN_REG_MAX) {
990 dev_err(hw->dev, "Invalid Field %d\n", field);
991 return -EINVAL;
992 }
993
994 if (hw->soc->reg_cal && hw->soc->reg_cal[field].range) {
995 rc = &hw->soc->reg_cal[field];
996 } else {
997 dev_err(hw->dev, "Undefined range for field %d\n", field);
998 return -EINVAL;
999 }
1000
1001 return mtk_hw_pin_field_lookup(hw, pin, rc, pfd);
1002}
1003
1004static void mtk_hw_bits_part(struct mtk_pin_field *pf, int *h, int *l)
1005{
1006 *l = 32 - pf->bitpos;
1007 *h = get_count_order(pf->mask) - *l;
1008}
1009
1010static void mtk_hw_write_cross_field(struct mtk_pinctrl *hw,
1011 struct mtk_pin_field *pf, int value)
1012{
1013 int nbits_l, nbits_h;
1014
1015 mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
1016
1017 mtk_rmw(hw, pf->offset, pf->mask << pf->bitpos,
1018 (value & pf->mask) << pf->bitpos);
1019
1020 mtk_rmw(hw, pf->offset + pf->next, BIT(nbits_h) - 1,
1021 (value & pf->mask) >> nbits_l);
1022}
1023
1024static void mtk_hw_read_cross_field(struct mtk_pinctrl *hw,
1025 struct mtk_pin_field *pf, int *value)
1026{
1027 int nbits_l, nbits_h, h, l;
1028
1029 mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
1030
1031 l = (mtk_r32(hw, pf->offset) >> pf->bitpos) & (BIT(nbits_l) - 1);
1032 h = (mtk_r32(hw, pf->offset + pf->next)) & (BIT(nbits_h) - 1);
1033
1034 *value = (h << nbits_l) | l;
1035}
1036
1037static int mtk_hw_set_value(struct mtk_pinctrl *hw, int pin, int field,
1038 int value)
1039{
1040 struct mtk_pin_field pf;
1041 int err;
1042
1043 err = mtk_hw_pin_field_get(hw, pin, field, &pf);
1044 if (err)
1045 return err;
1046
1047 if (!pf.next)
1048 mtk_rmw(hw, pf.offset, pf.mask << pf.bitpos,
1049 (value & pf.mask) << pf.bitpos);
1050 else
1051 mtk_hw_write_cross_field(hw, &pf, value);
1052
1053 return 0;
1054}
1055
1056static int mtk_hw_get_value(struct mtk_pinctrl *hw, int pin, int field,
1057 int *value)
1058{
1059 struct mtk_pin_field pf;
1060 int err;
1061
1062 err = mtk_hw_pin_field_get(hw, pin, field, &pf);
1063 if (err)
1064 return err;
1065
1066 if (!pf.next)
1067 *value = (mtk_r32(hw, pf.offset) >> pf.bitpos) & pf.mask;
1068 else
1069 mtk_hw_read_cross_field(hw, &pf, value);
1070
1071 return 0;
1072}
1073
1074static int mtk_pinmux_set_mux(struct pinctrl_dev *pctldev,
1075 unsigned int selector, unsigned int group)
1076{
1077 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
1078 struct function_desc *func;
1079 struct group_desc *grp;
1080 int i;
1081
1082 func = pinmux_generic_get_function(pctldev, selector);
1083 if (!func)
1084 return -EINVAL;
1085
1086 grp = pinctrl_generic_get_group(pctldev, group);
1087 if (!grp)
1088 return -EINVAL;
1089
1090 dev_dbg(pctldev->dev, "enable function %s group %s\n",
1091 func->name, grp->name);
1092
1093 for (i = 0; i < grp->num_pins; i++) {
1094 int *pin_modes = grp->data;
1095
1096 mtk_hw_set_value(hw, grp->pins[i], PINCTRL_PIN_REG_MODE,
1097 pin_modes[i]);
1098 }
1099
1100 return 0;
1101}
1102
1103static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
1104 struct pinctrl_gpio_range *range,
1105 unsigned int pin)
1106{
1107 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
1108
1109 return mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_MODE, MTK_GPIO_MODE);
1110}
1111
1112static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
1113 struct pinctrl_gpio_range *range,
1114 unsigned int pin, bool input)
1115{
1116 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
1117
1118 /* hardware would take 0 as input direction */
1119 return mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_DIR, !input);
1120}
1121
1122static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
1123 unsigned int pin, unsigned long *config)
1124{
1125 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
1126 u32 param = pinconf_to_config_param(*config);
1127 int val, val2, err, reg, ret = 1;
1128
1129 switch (param) {
1130 case PIN_CONFIG_BIAS_DISABLE:
1131 err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_PU, &val);
1132 if (err)
1133 return err;
1134
1135 err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_PD, &val2);
1136 if (err)
1137 return err;
1138
1139 if (val || val2)
1140 return -EINVAL;
1141
1142 break;
1143 case PIN_CONFIG_BIAS_PULL_UP:
1144 case PIN_CONFIG_BIAS_PULL_DOWN:
1145 case PIN_CONFIG_SLEW_RATE:
1146 reg = (param == PIN_CONFIG_BIAS_PULL_UP) ?
1147 PINCTRL_PIN_REG_PU :
1148 (param == PIN_CONFIG_BIAS_PULL_DOWN) ?
1149 PINCTRL_PIN_REG_PD : PINCTRL_PIN_REG_SR;
1150
1151 err = mtk_hw_get_value(hw, pin, reg, &val);
1152 if (err)
1153 return err;
1154
1155 if (!val)
1156 return -EINVAL;
1157
1158 break;
1159 case PIN_CONFIG_INPUT_ENABLE:
1160 case PIN_CONFIG_OUTPUT_ENABLE:
1161 err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_DIR, &val);
1162 if (err)
1163 return err;
1164
1165 /* HW takes input mode as zero; output mode as non-zero */
1166 if ((val && param == PIN_CONFIG_INPUT_ENABLE) ||
1167 (!val && param == PIN_CONFIG_OUTPUT_ENABLE))
1168 return -EINVAL;
1169
1170 break;
1171 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1172 err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_DIR, &val);
1173 if (err)
1174 return err;
1175
1176 err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_SMT, &val2);
1177 if (err)
1178 return err;
1179
1180 if (val || !val2)
1181 return -EINVAL;
1182
1183 break;
1184 case PIN_CONFIG_DRIVE_STRENGTH:
1185 err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_E4, &val);
1186 if (err)
1187 return err;
1188
1189 err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_E8, &val2);
1190 if (err)
1191 return err;
1192
1193 /* 4mA when (e8, e4) = (0, 0); 8mA when (e8, e4) = (0, 1)
1194 * 12mA when (e8, e4) = (1, 0); 16mA when (e8, e4) = (1, 1)
1195 */
1196 ret = ((val2 << 1) + val + 1) * 4;
1197
1198 break;
1199 case MTK_PIN_CONFIG_TDSEL:
1200 case MTK_PIN_CONFIG_RDSEL:
1201 reg = (param == MTK_PIN_CONFIG_TDSEL) ?
1202 PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
1203
1204 err = mtk_hw_get_value(hw, pin, reg, &val);
1205 if (err)
1206 return err;
1207
1208 ret = val;
1209
1210 break;
1211 default:
1212 return -ENOTSUPP;
1213 }
1214
1215 *config = pinconf_to_config_packed(param, ret);
1216
1217 return 0;
1218}
1219
1220static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1221 unsigned long *configs, unsigned int num_configs)
1222{
1223 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
1224 u32 reg, param, arg;
1225 int cfg, err = 0;
1226
1227 for (cfg = 0; cfg < num_configs; cfg++) {
1228 param = pinconf_to_config_param(configs[cfg]);
1229 arg = pinconf_to_config_argument(configs[cfg]);
1230
1231 switch (param) {
1232 case PIN_CONFIG_BIAS_DISABLE:
1233 case PIN_CONFIG_BIAS_PULL_UP:
1234 case PIN_CONFIG_BIAS_PULL_DOWN:
1235 arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 :
1236 (param == PIN_CONFIG_BIAS_PULL_UP) ? 1 : 2;
1237
1238 err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_PU,
1239 arg & 1);
1240 if (err)
1241 goto err;
1242
1243 err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_PD,
1244 !!(arg & 2));
1245 if (err)
1246 goto err;
1247 break;
1248 case PIN_CONFIG_OUTPUT_ENABLE:
1249 err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_SMT,
1250 MTK_DISABLE);
1251 if (err)
1252 goto err;
1253 case PIN_CONFIG_INPUT_ENABLE:
1254 case PIN_CONFIG_SLEW_RATE:
1255 reg = (param == PIN_CONFIG_SLEW_RATE) ?
1256 PINCTRL_PIN_REG_SR : PINCTRL_PIN_REG_DIR;
1257
1258 arg = (param == PIN_CONFIG_INPUT_ENABLE) ? 0 :
1259 (param == PIN_CONFIG_OUTPUT_ENABLE) ? 1 : arg;
1260 err = mtk_hw_set_value(hw, pin, reg, arg);
1261 if (err)
1262 goto err;
1263
1264 break;
1265 case PIN_CONFIG_OUTPUT:
1266 err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_DIR,
1267 MTK_OUTPUT);
1268 if (err)
1269 goto err;
1270
1271 err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_DO,
1272 arg);
1273 if (err)
1274 goto err;
1275 break;
1276 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1277 /* arg = 1: Input mode & SMT enable ;
1278 * arg = 0: Output mode & SMT disable
1279 */
1280 arg = arg ? 2 : 1;
1281 err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_DIR,
1282 arg & 1);
1283 if (err)
1284 goto err;
1285
1286 err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_SMT,
1287 !!(arg & 2));
1288 if (err)
1289 goto err;
1290 break;
1291 case PIN_CONFIG_DRIVE_STRENGTH:
1292 /* 4mA when (e8, e4) = (0, 0);
1293 * 8mA when (e8, e4) = (0, 1);
1294 * 12mA when (e8, e4) = (1, 0);
1295 * 16mA when (e8, e4) = (1, 1)
1296 */
1297 if (!(arg % 4) && (arg >= 4 && arg <= 16)) {
1298 arg = arg / 4 - 1;
1299 err = mtk_hw_set_value(hw, pin,
1300 PINCTRL_PIN_REG_E4,
1301 arg & 0x1);
1302 if (err)
1303 goto err;
1304
1305 err = mtk_hw_set_value(hw, pin,
1306 PINCTRL_PIN_REG_E8,
1307 (arg & 0x2) >> 1);
1308 if (err)
1309 goto err;
1310 } else {
1311 err = -ENOTSUPP;
1312 }
1313 break;
1314 case MTK_PIN_CONFIG_TDSEL:
1315 case MTK_PIN_CONFIG_RDSEL:
1316 reg = (param == MTK_PIN_CONFIG_TDSEL) ?
1317 PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
1318
1319 err = mtk_hw_set_value(hw, pin, reg, arg);
1320 if (err)
1321 goto err;
1322 break;
1323 default:
1324 err = -ENOTSUPP;
1325 }
1326 }
1327err:
1328 return err;
1329}
1330
1331static int mtk_pinconf_group_get(struct pinctrl_dev *pctldev,
1332 unsigned int group, unsigned long *config)
1333{
1334 const unsigned int *pins;
1335 unsigned int i, npins, old = 0;
1336 int ret;
1337
1338 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
1339 if (ret)
1340 return ret;
1341
1342 for (i = 0; i < npins; i++) {
1343 if (mtk_pinconf_get(pctldev, pins[i], config))
1344 return -ENOTSUPP;
1345
1346 /* configs do not match between two pins */
1347 if (i && old != *config)
1348 return -ENOTSUPP;
1349
1350 old = *config;
1351 }
1352
1353 return 0;
1354}
1355
1356static int mtk_pinconf_group_set(struct pinctrl_dev *pctldev,
1357 unsigned int group, unsigned long *configs,
1358 unsigned int num_configs)
1359{
1360 const unsigned int *pins;
1361 unsigned int i, npins;
1362 int ret;
1363
1364 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
1365 if (ret)
1366 return ret;
1367
1368 for (i = 0; i < npins; i++) {
1369 ret = mtk_pinconf_set(pctldev, pins[i], configs, num_configs);
1370 if (ret)
1371 return ret;
1372 }
1373
1374 return 0;
1375}
1376
1377static const struct pinctrl_ops mtk_pctlops = {
1378 .get_groups_count = pinctrl_generic_get_group_count,
1379 .get_group_name = pinctrl_generic_get_group_name,
1380 .get_group_pins = pinctrl_generic_get_group_pins,
1381 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
1382 .dt_free_map = pinconf_generic_dt_free_map,
1383};
1384
1385static const struct pinmux_ops mtk_pmxops = {
1386 .get_functions_count = pinmux_generic_get_function_count,
1387 .get_function_name = pinmux_generic_get_function_name,
1388 .get_function_groups = pinmux_generic_get_function_groups,
1389 .set_mux = mtk_pinmux_set_mux,
1390 .gpio_request_enable = mtk_pinmux_gpio_request_enable,
1391 .gpio_set_direction = mtk_pinmux_gpio_set_direction,
1392 .strict = true,
1393};
1394
1395static const struct pinconf_ops mtk_confops = {
1396 .is_generic = true,
1397 .pin_config_get = mtk_pinconf_get,
1398 .pin_config_set = mtk_pinconf_set,
1399 .pin_config_group_get = mtk_pinconf_group_get,
1400 .pin_config_group_set = mtk_pinconf_group_set,
1401 .pin_config_config_dbg_show = pinconf_generic_dump_config,
1402};
1403
1404static struct pinctrl_desc mtk_desc = {
1405 .name = PINCTRL_PINCTRL_DEV,
1406 .pctlops = &mtk_pctlops,
1407 .pmxops = &mtk_pmxops,
1408 .confops = &mtk_confops,
1409 .owner = THIS_MODULE,
1410};
1411
1412static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
1413{
1414 struct mtk_pinctrl *hw = dev_get_drvdata(chip->parent);
1415 int value, err;
1416
1417 err = mtk_hw_get_value(hw, gpio, PINCTRL_PIN_REG_DI, &value);
1418 if (err)
1419 return err;
1420
1421 return !!value;
1422}
1423
1424static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
1425{
1426 struct mtk_pinctrl *hw = dev_get_drvdata(chip->parent);
1427
1428 mtk_hw_set_value(hw, gpio, PINCTRL_PIN_REG_DO, !!value);
1429}
1430
1431static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
1432{
1433 return pinctrl_gpio_direction_input(chip->base + gpio);
1434}
1435
1436static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
1437 int value)
1438{
1439 mtk_gpio_set(chip, gpio, value);
1440
1441 return pinctrl_gpio_direction_output(chip->base + gpio);
1442}
1443
1444static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np)
1445{
1446 struct gpio_chip *chip = &hw->chip;
1447 int ret;
1448
1449 chip->label = PINCTRL_PINCTRL_DEV;
1450 chip->parent = hw->dev;
1451 chip->request = gpiochip_generic_request;
1452 chip->free = gpiochip_generic_free;
1453 chip->direction_input = mtk_gpio_direction_input;
1454 chip->direction_output = mtk_gpio_direction_output;
1455 chip->get = mtk_gpio_get;
1456 chip->set = mtk_gpio_set;
1457 chip->base = -1;
1458 chip->ngpio = hw->soc->npins;
1459 chip->of_node = np;
1460 chip->of_gpio_n_cells = 2;
1461
1462 ret = gpiochip_add_data(chip, hw);
1463 if (ret < 0)
1464 return ret;
1465
1466 ret = gpiochip_add_pin_range(chip, dev_name(hw->dev), 0, 0,
1467 chip->ngpio);
1468 if (ret < 0) {
1469 gpiochip_remove(chip);
1470 return ret;
1471 }
1472
1473 return 0;
1474}
1475
1476static int mtk_build_groups(struct mtk_pinctrl *hw)
1477{
1478 int err, i;
1479
1480 for (i = 0; i < hw->soc->ngrps; i++) {
1481 const struct group_desc *group = hw->soc->grps + i;
1482
1483 err = pinctrl_generic_add_group(hw->pctrl, group->name,
1484 group->pins, group->num_pins,
1485 group->data);
1486 if (err) {
1487 dev_err(hw->dev, "Failed to register group %s\n",
1488 group->name);
1489 return err;
1490 }
1491 }
1492
1493 return 0;
1494}
1495
1496static int mtk_build_functions(struct mtk_pinctrl *hw)
1497{
1498 int i, err;
1499
1500 for (i = 0; i < hw->soc->nfuncs ; i++) {
1501 const struct function_desc *func = hw->soc->funcs + i;
1502
1503 err = pinmux_generic_add_function(hw->pctrl, func->name,
1504 func->group_names,
1505 func->num_group_names,
1506 func->data);
1507 if (err) {
1508 dev_err(hw->dev, "Failed to register function %s\n",
1509 func->name);
1510 return err;
1511 }
1512 }
1513
1514 return 0;
1515}
1516
1517static const struct of_device_id mtk_pinctrl_of_match[] = {
1518 { .compatible = "mediatek,mt7622-pinctrl", .data = &mt7622_data},
1519 { }
1520};
1521
1522static int mtk_pinctrl_probe(struct platform_device *pdev)
1523{
1524 struct resource *res;
1525 struct mtk_pinctrl *hw;
1526 const struct of_device_id *of_id =
1527 of_match_device(mtk_pinctrl_of_match, &pdev->dev);
1528 int err;
1529
1530 hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
1531 if (!hw)
1532 return -ENOMEM;
1533
1534 hw->soc = of_id->data;
1535
1536 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1537 if (!res) {
1538 dev_err(&pdev->dev, "missing IO resource\n");
1539 return -ENXIO;
1540 }
1541
1542 hw->dev = &pdev->dev;
1543 hw->base = devm_ioremap_resource(&pdev->dev, res);
1544 if (IS_ERR(hw->base))
1545 return PTR_ERR(hw->base);
1546
1547 /* Setup pins descriptions per SoC types */
1548 mtk_desc.pins = hw->soc->pins;
1549 mtk_desc.npins = hw->soc->npins;
1550 mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings);
1551 mtk_desc.custom_params = mtk_custom_bindings;
1552#ifdef CONFIG_DEBUG_FS
1553 mtk_desc.custom_conf_items = mtk_conf_items;
1554#endif
1555
1556 hw->pctrl = devm_pinctrl_register(&pdev->dev, &mtk_desc, hw);
1557 if (IS_ERR(hw->pctrl))
1558 return PTR_ERR(hw->pctrl);
1559
1560 /* Setup groups descriptions per SoC types */
1561 err = mtk_build_groups(hw);
1562 if (err) {
1563 dev_err(&pdev->dev, "Failed to build groups\n");
1564 return 0;
1565 }
1566
1567 /* Setup functions descriptions per SoC types */
1568 err = mtk_build_functions(hw);
1569 if (err) {
1570 dev_err(&pdev->dev, "Failed to build functions\n");
1571 return err;
1572 }
1573
1574 err = mtk_build_gpiochip(hw, pdev->dev.of_node);
1575 if (err) {
1576 dev_err(&pdev->dev, "Failed to add gpio_chip\n");
1577 return err;
1578 }
1579
1580 platform_set_drvdata(pdev, hw);
1581
1582 return 0;
1583}
1584
1585static struct platform_driver mtk_pinctrl_driver = {
1586 .driver = {
1587 .name = "mtk-pinctrl",
1588 .of_match_table = mtk_pinctrl_of_match,
1589 },
1590 .probe = mtk_pinctrl_probe,
1591};
1592
1593static int __init mtk_pinctrl_init(void)
1594{
1595 return platform_driver_register(&mtk_pinctrl_driver);
1596}
1597arch_initcall(mtk_pinctrl_init);
diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig
index 1a51778759ea..c80951d6caff 100644
--- a/drivers/pinctrl/meson/Kconfig
+++ b/drivers/pinctrl/meson/Kconfig
@@ -38,4 +38,13 @@ config PINCTRL_MESON_GXL
38config PINCTRL_MESON8_PMX 38config PINCTRL_MESON8_PMX
39 bool 39 bool
40 40
41config PINCTRL_MESON_AXG
42 bool "Meson axg Soc pinctrl driver"
43 depends on ARM64
44 select PINCTRL_MESON_AXG_PMX
45 default y
46
47config PINCTRL_MESON_AXG_PMX
48 bool
49
41endif 50endif
diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
index cbd47bb74549..3c6580c2d9d7 100644
--- a/drivers/pinctrl/meson/Makefile
+++ b/drivers/pinctrl/meson/Makefile
@@ -4,3 +4,5 @@ obj-$(CONFIG_PINCTRL_MESON8) += pinctrl-meson8.o
4obj-$(CONFIG_PINCTRL_MESON8B) += pinctrl-meson8b.o 4obj-$(CONFIG_PINCTRL_MESON8B) += pinctrl-meson8b.o
5obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o 5obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o
6obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o 6obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o
7obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o
8obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o
diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c
new file mode 100644
index 000000000000..e8931d9cf863
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c
@@ -0,0 +1,118 @@
1/*
2 * Second generation of pinmux driver for Amlogic Meson-AXG SoC.
3 *
4 * Copyright (c) 2017 Baylibre SAS.
5 * Author: Jerome Brunet <jbrunet@baylibre.com>
6 *
7 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
8 * Author: Xingyu Chen <xingyu.chen@amlogic.com>
9 *
10 * SPDX-License-Identifier: (GPL-2.0+ or MIT)
11 */
12
13/*
14 * This new generation of pinctrl IP is mainly adopted by the
15 * Meson-AXG SoC and later series, which use 4-width continuous
16 * register bit to select the function for each pin.
17 *
18 * The value 0 is always selecting the GPIO mode, while other
19 * values (start from 1) for selecting the function mode.
20 */
21#include <linux/device.h>
22#include <linux/regmap.h>
23#include <linux/pinctrl/pinctrl.h>
24#include <linux/pinctrl/pinmux.h>
25
26#include "pinctrl-meson.h"
27#include "pinctrl-meson-axg-pmx.h"
28
29static int meson_axg_pmx_get_bank(struct meson_pinctrl *pc,
30 unsigned int pin,
31 struct meson_pmx_bank **bank)
32{
33 int i;
34 struct meson_axg_pmx_data *pmx = pc->data->pmx_data;
35
36 for (i = 0; i < pmx->num_pmx_banks; i++)
37 if (pin >= pmx->pmx_banks[i].first &&
38 pin <= pmx->pmx_banks[i].last) {
39 *bank = &pmx->pmx_banks[i];
40 return 0;
41 }
42
43 return -EINVAL;
44}
45
46static int meson_pmx_calc_reg_and_offset(struct meson_pmx_bank *bank,
47 unsigned int pin, unsigned int *reg,
48 unsigned int *offset)
49{
50 int shift;
51
52 shift = pin - bank->first;
53
54 *reg = bank->reg + (bank->offset + (shift << 2)) / 32;
55 *offset = (bank->offset + (shift << 2)) % 32;
56
57 return 0;
58}
59
60static int meson_axg_pmx_update_function(struct meson_pinctrl *pc,
61 unsigned int pin, unsigned int func)
62{
63 int ret;
64 int reg;
65 int offset;
66 struct meson_pmx_bank *bank;
67
68 ret = meson_axg_pmx_get_bank(pc, pin, &bank);
69 if (ret)
70 return ret;
71
72 meson_pmx_calc_reg_and_offset(bank, pin, &reg, &offset);
73
74 ret = regmap_update_bits(pc->reg_mux, reg << 2,
75 0xf << offset, (func & 0xf) << offset);
76
77 return ret;
78}
79
80static int meson_axg_pmx_set_mux(struct pinctrl_dev *pcdev,
81 unsigned int func_num, unsigned int group_num)
82{
83 int i;
84 int ret;
85 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
86 struct meson_pmx_func *func = &pc->data->funcs[func_num];
87 struct meson_pmx_group *group = &pc->data->groups[group_num];
88 struct meson_pmx_axg_data *pmx_data =
89 (struct meson_pmx_axg_data *)group->data;
90
91 dev_dbg(pc->dev, "enable function %s, group %s\n", func->name,
92 group->name);
93
94 for (i = 0; i < group->num_pins; i++) {
95 ret = meson_axg_pmx_update_function(pc, group->pins[i],
96 pmx_data->func);
97 if (ret)
98 return ret;
99 }
100
101 return 0;
102}
103
104static int meson_axg_pmx_request_gpio(struct pinctrl_dev *pcdev,
105 struct pinctrl_gpio_range *range, unsigned int offset)
106{
107 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
108
109 return meson_axg_pmx_update_function(pc, offset, 0);
110}
111
112const struct pinmux_ops meson_axg_pmx_ops = {
113 .set_mux = meson_axg_pmx_set_mux,
114 .get_functions_count = meson_pmx_get_funcs_count,
115 .get_function_name = meson_pmx_get_func_name,
116 .get_function_groups = meson_pmx_get_groups,
117 .gpio_request_enable = meson_axg_pmx_request_gpio,
118};
diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h
new file mode 100644
index 000000000000..8ff88bf2e849
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h
@@ -0,0 +1,62 @@
1/*
2 * Copyright (c) 2017 Baylibre SAS.
3 * Author: Jerome Brunet <jbrunet@baylibre.com>
4 *
5 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
6 * Author: Xingyu Chen <xingyu.chen@amlogic.com>
7 *
8 * SPDX-License-Identifier: (GPL-2.0+ or MIT)
9 */
10
11struct meson_pmx_bank {
12 const char *name;
13 unsigned int first;
14 unsigned int last;
15 unsigned int reg;
16 unsigned int offset;
17};
18
19struct meson_axg_pmx_data {
20 struct meson_pmx_bank *pmx_banks;
21 unsigned int num_pmx_banks;
22};
23
24#define BANK_PMX(n, f, l, r, o) \
25 { \
26 .name = n, \
27 .first = f, \
28 .last = l, \
29 .reg = r, \
30 .offset = o, \
31 }
32
33struct meson_pmx_axg_data {
34 unsigned int func;
35};
36
37#define PMX_DATA(f) \
38 { \
39 .func = f, \
40 }
41
42#define GROUP(grp, f) \
43 { \
44 .name = #grp, \
45 .pins = grp ## _pins, \
46 .num_pins = ARRAY_SIZE(grp ## _pins), \
47 .data = (const struct meson_pmx_axg_data[]){ \
48 PMX_DATA(f), \
49 }, \
50 }
51
52#define GPIO_GROUP(gpio) \
53 { \
54 .name = #gpio, \
55 .pins = (const unsigned int[]){ gpio }, \
56 .num_pins = 1, \
57 .data = (const struct meson_pmx_axg_data[]){ \
58 PMX_DATA(0), \
59 }, \
60 }
61
62extern const struct pinmux_ops meson_axg_pmx_ops;
diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.c b/drivers/pinctrl/meson/pinctrl-meson-axg.c
new file mode 100644
index 000000000000..1fda9d6c7ea3
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson-axg.c
@@ -0,0 +1,975 @@
1/*
2 * Pin controller and GPIO driver for Amlogic Meson AXG SoC.
3 *
4 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
5 * Author: Xingyu Chen <xingyu.chen@amlogic.com>
6 *
7 * SPDX-License-Identifier: (GPL-2.0+ or MIT)
8 */
9
10#include <dt-bindings/gpio/meson-axg-gpio.h>
11#include "pinctrl-meson.h"
12#include "pinctrl-meson-axg-pmx.h"
13
14static const struct pinctrl_pin_desc meson_axg_periphs_pins[] = {
15 MESON_PIN(GPIOZ_0),
16 MESON_PIN(GPIOZ_1),
17 MESON_PIN(GPIOZ_2),
18 MESON_PIN(GPIOZ_3),
19 MESON_PIN(GPIOZ_4),
20 MESON_PIN(GPIOZ_5),
21 MESON_PIN(GPIOZ_6),
22 MESON_PIN(GPIOZ_7),
23 MESON_PIN(GPIOZ_8),
24 MESON_PIN(GPIOZ_9),
25 MESON_PIN(GPIOZ_10),
26 MESON_PIN(BOOT_0),
27 MESON_PIN(BOOT_1),
28 MESON_PIN(BOOT_2),
29 MESON_PIN(BOOT_3),
30 MESON_PIN(BOOT_4),
31 MESON_PIN(BOOT_5),
32 MESON_PIN(BOOT_6),
33 MESON_PIN(BOOT_7),
34 MESON_PIN(BOOT_8),
35 MESON_PIN(BOOT_9),
36 MESON_PIN(BOOT_10),
37 MESON_PIN(BOOT_11),
38 MESON_PIN(BOOT_12),
39 MESON_PIN(BOOT_13),
40 MESON_PIN(BOOT_14),
41 MESON_PIN(GPIOA_0),
42 MESON_PIN(GPIOA_1),
43 MESON_PIN(GPIOA_2),
44 MESON_PIN(GPIOA_3),
45 MESON_PIN(GPIOA_4),
46 MESON_PIN(GPIOA_5),
47 MESON_PIN(GPIOA_6),
48 MESON_PIN(GPIOA_7),
49 MESON_PIN(GPIOA_8),
50 MESON_PIN(GPIOA_9),
51 MESON_PIN(GPIOA_10),
52 MESON_PIN(GPIOA_11),
53 MESON_PIN(GPIOA_12),
54 MESON_PIN(GPIOA_13),
55 MESON_PIN(GPIOA_14),
56 MESON_PIN(GPIOA_15),
57 MESON_PIN(GPIOA_16),
58 MESON_PIN(GPIOA_17),
59 MESON_PIN(GPIOA_18),
60 MESON_PIN(GPIOA_19),
61 MESON_PIN(GPIOA_20),
62 MESON_PIN(GPIOX_0),
63 MESON_PIN(GPIOX_1),
64 MESON_PIN(GPIOX_2),
65 MESON_PIN(GPIOX_3),
66 MESON_PIN(GPIOX_4),
67 MESON_PIN(GPIOX_5),
68 MESON_PIN(GPIOX_6),
69 MESON_PIN(GPIOX_7),
70 MESON_PIN(GPIOX_8),
71 MESON_PIN(GPIOX_9),
72 MESON_PIN(GPIOX_10),
73 MESON_PIN(GPIOX_11),
74 MESON_PIN(GPIOX_12),
75 MESON_PIN(GPIOX_13),
76 MESON_PIN(GPIOX_14),
77 MESON_PIN(GPIOX_15),
78 MESON_PIN(GPIOX_16),
79 MESON_PIN(GPIOX_17),
80 MESON_PIN(GPIOX_18),
81 MESON_PIN(GPIOX_19),
82 MESON_PIN(GPIOX_20),
83 MESON_PIN(GPIOX_21),
84 MESON_PIN(GPIOX_22),
85 MESON_PIN(GPIOY_0),
86 MESON_PIN(GPIOY_1),
87 MESON_PIN(GPIOY_2),
88 MESON_PIN(GPIOY_3),
89 MESON_PIN(GPIOY_4),
90 MESON_PIN(GPIOY_5),
91 MESON_PIN(GPIOY_6),
92 MESON_PIN(GPIOY_7),
93 MESON_PIN(GPIOY_8),
94 MESON_PIN(GPIOY_9),
95 MESON_PIN(GPIOY_10),
96 MESON_PIN(GPIOY_11),
97 MESON_PIN(GPIOY_12),
98 MESON_PIN(GPIOY_13),
99 MESON_PIN(GPIOY_14),
100 MESON_PIN(GPIOY_15),
101};
102
103static const struct pinctrl_pin_desc meson_axg_aobus_pins[] = {
104 MESON_PIN(GPIOAO_0),
105 MESON_PIN(GPIOAO_1),
106 MESON_PIN(GPIOAO_2),
107 MESON_PIN(GPIOAO_3),
108 MESON_PIN(GPIOAO_4),
109 MESON_PIN(GPIOAO_5),
110 MESON_PIN(GPIOAO_6),
111 MESON_PIN(GPIOAO_7),
112 MESON_PIN(GPIOAO_8),
113 MESON_PIN(GPIOAO_9),
114 MESON_PIN(GPIOAO_10),
115 MESON_PIN(GPIOAO_11),
116 MESON_PIN(GPIOAO_12),
117 MESON_PIN(GPIOAO_13),
118 MESON_PIN(GPIO_TEST_N),
119};
120
121/* emmc */
122static const unsigned int emmc_nand_d0_pins[] = {BOOT_0};
123static const unsigned int emmc_nand_d1_pins[] = {BOOT_1};
124static const unsigned int emmc_nand_d2_pins[] = {BOOT_2};
125static const unsigned int emmc_nand_d3_pins[] = {BOOT_3};
126static const unsigned int emmc_nand_d4_pins[] = {BOOT_4};
127static const unsigned int emmc_nand_d5_pins[] = {BOOT_5};
128static const unsigned int emmc_nand_d6_pins[] = {BOOT_6};
129static const unsigned int emmc_nand_d7_pins[] = {BOOT_7};
130
131static const unsigned int emmc_clk_pins[] = {BOOT_8};
132static const unsigned int emmc_cmd_pins[] = {BOOT_10};
133static const unsigned int emmc_ds_pins[] = {BOOT_13};
134
135/* nand */
136static const unsigned int nand_ce0_pins[] = {BOOT_8};
137static const unsigned int nand_ale_pins[] = {BOOT_9};
138static const unsigned int nand_cle_pins[] = {BOOT_10};
139static const unsigned int nand_wen_clk_pins[] = {BOOT_11};
140static const unsigned int nand_ren_wr_pins[] = {BOOT_12};
141static const unsigned int nand_rb0_pins[] = {BOOT_13};
142
143/* nor */
144static const unsigned int nor_hold_pins[] = {BOOT_3};
145static const unsigned int nor_d_pins[] = {BOOT_4};
146static const unsigned int nor_q_pins[] = {BOOT_5};
147static const unsigned int nor_c_pins[] = {BOOT_6};
148static const unsigned int nor_wp_pins[] = {BOOT_9};
149static const unsigned int nor_cs_pins[] = {BOOT_14};
150
151/* sdio */
152static const unsigned int sdio_d0_pins[] = {GPIOX_0};
153static const unsigned int sdio_d1_pins[] = {GPIOX_1};
154static const unsigned int sdio_d2_pins[] = {GPIOX_2};
155static const unsigned int sdio_d3_pins[] = {GPIOX_3};
156static const unsigned int sdio_clk_pins[] = {GPIOX_4};
157static const unsigned int sdio_cmd_pins[] = {GPIOX_5};
158
159/* spi0 */
160static const unsigned int spi0_clk_pins[] = {GPIOZ_0};
161static const unsigned int spi0_mosi_pins[] = {GPIOZ_1};
162static const unsigned int spi0_miso_pins[] = {GPIOZ_2};
163static const unsigned int spi0_ss0_pins[] = {GPIOZ_3};
164static const unsigned int spi0_ss1_pins[] = {GPIOZ_4};
165static const unsigned int spi0_ss2_pins[] = {GPIOZ_5};
166
167/* spi1 */
168static const unsigned int spi1_clk_x_pins[] = {GPIOX_19};
169static const unsigned int spi1_mosi_x_pins[] = {GPIOX_17};
170static const unsigned int spi1_miso_x_pins[] = {GPIOX_18};
171static const unsigned int spi1_ss0_x_pins[] = {GPIOX_16};
172
173static const unsigned int spi1_clk_a_pins[] = {GPIOA_4};
174static const unsigned int spi1_mosi_a_pins[] = {GPIOA_2};
175static const unsigned int spi1_miso_a_pins[] = {GPIOA_3};
176static const unsigned int spi1_ss0_a_pins[] = {GPIOA_5};
177static const unsigned int spi1_ss1_pins[] = {GPIOA_6};
178
179/* i2c0 */
180static const unsigned int i2c0_sck_pins[] = {GPIOZ_6};
181static const unsigned int i2c0_sda_pins[] = {GPIOZ_7};
182
183/* i2c1 */
184static const unsigned int i2c1_sck_z_pins[] = {GPIOZ_8};
185static const unsigned int i2c1_sda_z_pins[] = {GPIOZ_9};
186
187static const unsigned int i2c1_sck_x_pins[] = {GPIOX_16};
188static const unsigned int i2c1_sda_x_pins[] = {GPIOX_17};
189
190/* i2c2 */
191static const unsigned int i2c2_sck_x_pins[] = {GPIOX_18};
192static const unsigned int i2c2_sda_x_pins[] = {GPIOX_19};
193
194static const unsigned int i2c2_sda_a_pins[] = {GPIOA_17};
195static const unsigned int i2c2_sck_a_pins[] = {GPIOA_18};
196
197/* i2c3 */
198static const unsigned int i2c3_sda_a6_pins[] = {GPIOA_6};
199static const unsigned int i2c3_sck_a7_pins[] = {GPIOA_7};
200
201static const unsigned int i2c3_sda_a12_pins[] = {GPIOA_12};
202static const unsigned int i2c3_sck_a13_pins[] = {GPIOA_13};
203
204static const unsigned int i2c3_sda_a19_pins[] = {GPIOA_19};
205static const unsigned int i2c3_sck_a20_pins[] = {GPIOA_20};
206
207/* uart_a */
208static const unsigned int uart_rts_a_pins[] = {GPIOX_11};
209static const unsigned int uart_cts_a_pins[] = {GPIOX_10};
210static const unsigned int uart_tx_a_pins[] = {GPIOX_8};
211static const unsigned int uart_rx_a_pins[] = {GPIOX_9};
212
213/* uart_b */
214static const unsigned int uart_rts_b_z_pins[] = {GPIOZ_0};
215static const unsigned int uart_cts_b_z_pins[] = {GPIOZ_1};
216static const unsigned int uart_tx_b_z_pins[] = {GPIOZ_2};
217static const unsigned int uart_rx_b_z_pins[] = {GPIOZ_3};
218
219static const unsigned int uart_rts_b_x_pins[] = {GPIOX_18};
220static const unsigned int uart_cts_b_x_pins[] = {GPIOX_19};
221static const unsigned int uart_tx_b_x_pins[] = {GPIOX_16};
222static const unsigned int uart_rx_b_x_pins[] = {GPIOX_17};
223
224/* uart_ao_b */
225static const unsigned int uart_ao_tx_b_z_pins[] = {GPIOZ_8};
226static const unsigned int uart_ao_rx_b_z_pins[] = {GPIOZ_9};
227static const unsigned int uart_ao_cts_b_z_pins[] = {GPIOZ_6};
228static const unsigned int uart_ao_rts_b_z_pins[] = {GPIOZ_7};
229
230/* pwm_a */
231static const unsigned int pwm_a_z_pins[] = {GPIOZ_5};
232
233static const unsigned int pwm_a_x18_pins[] = {GPIOX_18};
234static const unsigned int pwm_a_x20_pins[] = {GPIOX_20};
235
236static const unsigned int pwm_a_a_pins[] = {GPIOA_14};
237
238/* pwm_b */
239static const unsigned int pwm_b_z_pins[] = {GPIOZ_4};
240
241static const unsigned int pwm_b_x_pins[] = {GPIOX_19};
242
243static const unsigned int pwm_b_a_pins[] = {GPIOA_15};
244
245/* pwm_c */
246static const unsigned int pwm_c_x10_pins[] = {GPIOX_10};
247static const unsigned int pwm_c_x17_pins[] = {GPIOX_17};
248
249static const unsigned int pwm_c_a_pins[] = {GPIOA_16};
250
251/* pwm_d */
252static const unsigned int pwm_d_x11_pins[] = {GPIOX_11};
253static const unsigned int pwm_d_x16_pins[] = {GPIOX_16};
254
255/* pwm_vs */
256static const unsigned int pwm_vs_pins[] = {GPIOA_0};
257
258/* spdif_in */
259static const unsigned int spdif_in_z_pins[] = {GPIOZ_4};
260
261static const unsigned int spdif_in_a1_pins[] = {GPIOA_1};
262static const unsigned int spdif_in_a7_pins[] = {GPIOA_7};
263static const unsigned int spdif_in_a19_pins[] = {GPIOA_19};
264static const unsigned int spdif_in_a20_pins[] = {GPIOA_20};
265
266/* spdif_out */
267static const unsigned int spdif_out_z_pins[] = {GPIOZ_5};
268
269static const unsigned int spdif_out_a1_pins[] = {GPIOA_1};
270static const unsigned int spdif_out_a11_pins[] = {GPIOA_11};
271static const unsigned int spdif_out_a19_pins[] = {GPIOA_19};
272static const unsigned int spdif_out_a20_pins[] = {GPIOA_20};
273
274/* jtag_ee */
275static const unsigned int jtag_tdo_x_pins[] = {GPIOX_0};
276static const unsigned int jtag_tdi_x_pins[] = {GPIOX_1};
277static const unsigned int jtag_clk_x_pins[] = {GPIOX_4};
278static const unsigned int jtag_tms_x_pins[] = {GPIOX_5};
279
280/* eth */
281static const unsigned int eth_txd0_x_pins[] = {GPIOX_8};
282static const unsigned int eth_txd1_x_pins[] = {GPIOX_9};
283static const unsigned int eth_txen_x_pins[] = {GPIOX_10};
284static const unsigned int eth_rgmii_rx_clk_x_pins[] = {GPIOX_12};
285static const unsigned int eth_rxd0_x_pins[] = {GPIOX_13};
286static const unsigned int eth_rxd1_x_pins[] = {GPIOX_14};
287static const unsigned int eth_rx_dv_x_pins[] = {GPIOX_15};
288static const unsigned int eth_mdio_x_pins[] = {GPIOX_21};
289static const unsigned int eth_mdc_x_pins[] = {GPIOX_22};
290
291static const unsigned int eth_txd0_y_pins[] = {GPIOY_10};
292static const unsigned int eth_txd1_y_pins[] = {GPIOY_11};
293static const unsigned int eth_txen_y_pins[] = {GPIOY_9};
294static const unsigned int eth_rgmii_rx_clk_y_pins[] = {GPIOY_2};
295static const unsigned int eth_rxd0_y_pins[] = {GPIOY_4};
296static const unsigned int eth_rxd1_y_pins[] = {GPIOY_5};
297static const unsigned int eth_rx_dv_y_pins[] = {GPIOY_3};
298static const unsigned int eth_mdio_y_pins[] = {GPIOY_0};
299static const unsigned int eth_mdc_y_pins[] = {GPIOY_1};
300
301static const unsigned int eth_rxd2_rgmii_pins[] = {GPIOY_6};
302static const unsigned int eth_rxd3_rgmii_pins[] = {GPIOY_7};
303static const unsigned int eth_rgmii_tx_clk_pins[] = {GPIOY_8};
304static const unsigned int eth_txd2_rgmii_pins[] = {GPIOY_12};
305static const unsigned int eth_txd3_rgmii_pins[] = {GPIOY_13};
306
307/* pdm */
308static const unsigned int pdm_dclk_a14_pins[] = {GPIOA_14};
309static const unsigned int pdm_dclk_a19_pins[] = {GPIOA_19};
310static const unsigned int pdm_din0_pins[] = {GPIOA_15};
311static const unsigned int pdm_din1_pins[] = {GPIOA_16};
312static const unsigned int pdm_din2_pins[] = {GPIOA_17};
313static const unsigned int pdm_din3_pins[] = {GPIOA_18};
314
315static struct meson_pmx_group meson_axg_periphs_groups[] = {
316 GPIO_GROUP(GPIOZ_0),
317 GPIO_GROUP(GPIOZ_1),
318 GPIO_GROUP(GPIOZ_2),
319 GPIO_GROUP(GPIOZ_3),
320 GPIO_GROUP(GPIOZ_4),
321 GPIO_GROUP(GPIOZ_5),
322 GPIO_GROUP(GPIOZ_6),
323 GPIO_GROUP(GPIOZ_7),
324 GPIO_GROUP(GPIOZ_8),
325 GPIO_GROUP(GPIOZ_9),
326 GPIO_GROUP(GPIOZ_10),
327
328 GPIO_GROUP(BOOT_0),
329 GPIO_GROUP(BOOT_1),
330 GPIO_GROUP(BOOT_2),
331 GPIO_GROUP(BOOT_3),
332 GPIO_GROUP(BOOT_4),
333 GPIO_GROUP(BOOT_5),
334 GPIO_GROUP(BOOT_6),
335 GPIO_GROUP(BOOT_7),
336 GPIO_GROUP(BOOT_8),
337 GPIO_GROUP(BOOT_9),
338 GPIO_GROUP(BOOT_10),
339 GPIO_GROUP(BOOT_11),
340 GPIO_GROUP(BOOT_12),
341 GPIO_GROUP(BOOT_13),
342 GPIO_GROUP(BOOT_14),
343
344 GPIO_GROUP(GPIOA_0),
345 GPIO_GROUP(GPIOA_1),
346 GPIO_GROUP(GPIOA_2),
347 GPIO_GROUP(GPIOA_3),
348 GPIO_GROUP(GPIOA_4),
349 GPIO_GROUP(GPIOA_5),
350 GPIO_GROUP(GPIOA_6),
351 GPIO_GROUP(GPIOA_7),
352 GPIO_GROUP(GPIOA_8),
353 GPIO_GROUP(GPIOA_9),
354 GPIO_GROUP(GPIOA_10),
355 GPIO_GROUP(GPIOA_11),
356 GPIO_GROUP(GPIOA_12),
357 GPIO_GROUP(GPIOA_13),
358 GPIO_GROUP(GPIOA_14),
359 GPIO_GROUP(GPIOA_15),
360 GPIO_GROUP(GPIOA_16),
361 GPIO_GROUP(GPIOA_17),
362 GPIO_GROUP(GPIOA_19),
363 GPIO_GROUP(GPIOA_20),
364
365 GPIO_GROUP(GPIOX_0),
366 GPIO_GROUP(GPIOX_1),
367 GPIO_GROUP(GPIOX_2),
368 GPIO_GROUP(GPIOX_3),
369 GPIO_GROUP(GPIOX_4),
370 GPIO_GROUP(GPIOX_5),
371 GPIO_GROUP(GPIOX_6),
372 GPIO_GROUP(GPIOX_7),
373 GPIO_GROUP(GPIOX_8),
374 GPIO_GROUP(GPIOX_9),
375 GPIO_GROUP(GPIOX_10),
376 GPIO_GROUP(GPIOX_11),
377 GPIO_GROUP(GPIOX_12),
378 GPIO_GROUP(GPIOX_13),
379 GPIO_GROUP(GPIOX_14),
380 GPIO_GROUP(GPIOX_15),
381 GPIO_GROUP(GPIOX_16),
382 GPIO_GROUP(GPIOX_17),
383 GPIO_GROUP(GPIOX_18),
384 GPIO_GROUP(GPIOX_19),
385 GPIO_GROUP(GPIOX_20),
386 GPIO_GROUP(GPIOX_21),
387 GPIO_GROUP(GPIOX_22),
388
389 GPIO_GROUP(GPIOY_0),
390 GPIO_GROUP(GPIOY_1),
391 GPIO_GROUP(GPIOY_2),
392 GPIO_GROUP(GPIOY_3),
393 GPIO_GROUP(GPIOY_4),
394 GPIO_GROUP(GPIOY_5),
395 GPIO_GROUP(GPIOY_6),
396 GPIO_GROUP(GPIOY_7),
397 GPIO_GROUP(GPIOY_8),
398 GPIO_GROUP(GPIOY_9),
399 GPIO_GROUP(GPIOY_10),
400 GPIO_GROUP(GPIOY_11),
401 GPIO_GROUP(GPIOY_12),
402 GPIO_GROUP(GPIOY_13),
403 GPIO_GROUP(GPIOY_14),
404 GPIO_GROUP(GPIOY_15),
405
406 /* bank BOOT */
407 GROUP(emmc_nand_d0, 1),
408 GROUP(emmc_nand_d1, 1),
409 GROUP(emmc_nand_d2, 1),
410 GROUP(emmc_nand_d3, 1),
411 GROUP(emmc_nand_d4, 1),
412 GROUP(emmc_nand_d5, 1),
413 GROUP(emmc_nand_d6, 1),
414 GROUP(emmc_nand_d7, 1),
415 GROUP(emmc_clk, 1),
416 GROUP(emmc_cmd, 1),
417 GROUP(emmc_ds, 1),
418 GROUP(nand_ce0, 2),
419 GROUP(nand_ale, 2),
420 GROUP(nand_cle, 2),
421 GROUP(nand_wen_clk, 2),
422 GROUP(nand_ren_wr, 2),
423 GROUP(nand_rb0, 2),
424 GROUP(nor_hold, 3),
425 GROUP(nor_d, 3),
426 GROUP(nor_q, 3),
427 GROUP(nor_c, 3),
428 GROUP(nor_wp, 3),
429 GROUP(nor_cs, 3),
430
431 /* bank GPIOZ */
432 GROUP(spi0_clk, 1),
433 GROUP(spi0_mosi, 1),
434 GROUP(spi0_miso, 1),
435 GROUP(spi0_ss0, 1),
436 GROUP(spi0_ss1, 1),
437 GROUP(spi0_ss2, 1),
438 GROUP(i2c0_sck, 1),
439 GROUP(i2c0_sda, 1),
440 GROUP(i2c1_sck_z, 1),
441 GROUP(i2c1_sda_z, 1),
442 GROUP(uart_rts_b_z, 2),
443 GROUP(uart_cts_b_z, 2),
444 GROUP(uart_tx_b_z, 2),
445 GROUP(uart_rx_b_z, 2),
446 GROUP(pwm_a_z, 2),
447 GROUP(pwm_b_z, 2),
448 GROUP(spdif_in_z, 3),
449 GROUP(spdif_out_z, 3),
450 GROUP(uart_ao_tx_b_z, 2),
451 GROUP(uart_ao_rx_b_z, 2),
452 GROUP(uart_ao_cts_b_z, 2),
453 GROUP(uart_ao_rts_b_z, 2),
454
455 /* bank GPIOX */
456 GROUP(sdio_d0, 1),
457 GROUP(sdio_d1, 1),
458 GROUP(sdio_d2, 1),
459 GROUP(sdio_d3, 1),
460 GROUP(sdio_clk, 1),
461 GROUP(sdio_cmd, 1),
462 GROUP(i2c1_sck_x, 1),
463 GROUP(i2c1_sda_x, 1),
464 GROUP(i2c2_sck_x, 1),
465 GROUP(i2c2_sda_x, 1),
466 GROUP(uart_rts_a, 1),
467 GROUP(uart_cts_a, 1),
468 GROUP(uart_tx_a, 1),
469 GROUP(uart_rx_a, 1),
470 GROUP(uart_rts_b_x, 2),
471 GROUP(uart_cts_b_x, 2),
472 GROUP(uart_tx_b_x, 2),
473 GROUP(uart_rx_b_x, 2),
474 GROUP(jtag_tdo_x, 2),
475 GROUP(jtag_tdi_x, 2),
476 GROUP(jtag_clk_x, 2),
477 GROUP(jtag_tms_x, 2),
478 GROUP(spi1_clk_x, 4),
479 GROUP(spi1_mosi_x, 4),
480 GROUP(spi1_miso_x, 4),
481 GROUP(spi1_ss0_x, 4),
482 GROUP(pwm_a_x18, 3),
483 GROUP(pwm_a_x20, 1),
484 GROUP(pwm_b_x, 3),
485 GROUP(pwm_c_x10, 3),
486 GROUP(pwm_c_x17, 3),
487 GROUP(pwm_d_x11, 3),
488 GROUP(pwm_d_x16, 3),
489 GROUP(eth_txd0_x, 4),
490 GROUP(eth_txd1_x, 4),
491 GROUP(eth_txen_x, 4),
492 GROUP(eth_rgmii_rx_clk_x, 4),
493 GROUP(eth_rxd0_x, 4),
494 GROUP(eth_rxd1_x, 4),
495 GROUP(eth_rx_dv_x, 4),
496 GROUP(eth_mdio_x, 4),
497 GROUP(eth_mdc_x, 4),
498
499 /* bank GPIOY */
500 GROUP(eth_txd0_y, 1),
501 GROUP(eth_txd1_y, 1),
502 GROUP(eth_txen_y, 1),
503 GROUP(eth_rgmii_rx_clk_y, 1),
504 GROUP(eth_rxd0_y, 1),
505 GROUP(eth_rxd1_y, 1),
506 GROUP(eth_rx_dv_y, 1),
507 GROUP(eth_mdio_y, 1),
508 GROUP(eth_mdc_y, 1),
509 GROUP(eth_rxd2_rgmii, 1),
510 GROUP(eth_rxd3_rgmii, 1),
511 GROUP(eth_rgmii_tx_clk, 1),
512 GROUP(eth_txd2_rgmii, 1),
513 GROUP(eth_txd3_rgmii, 1),
514
515 /* bank GPIOA */
516 GROUP(spdif_out_a1, 4),
517 GROUP(spdif_out_a11, 3),
518 GROUP(spdif_out_a19, 2),
519 GROUP(spdif_out_a20, 1),
520 GROUP(spdif_in_a1, 3),
521 GROUP(spdif_in_a7, 3),
522 GROUP(spdif_in_a19, 1),
523 GROUP(spdif_in_a20, 2),
524 GROUP(spi1_clk_a, 3),
525 GROUP(spi1_mosi_a, 3),
526 GROUP(spi1_miso_a, 3),
527 GROUP(spi1_ss0_a, 3),
528 GROUP(spi1_ss1, 3),
529 GROUP(pwm_a_a, 3),
530 GROUP(pwm_b_a, 3),
531 GROUP(pwm_c_a, 3),
532 GROUP(pwm_vs, 2),
533 GROUP(i2c2_sda_a, 3),
534 GROUP(i2c2_sck_a, 3),
535 GROUP(i2c3_sda_a6, 4),
536 GROUP(i2c3_sck_a7, 4),
537 GROUP(i2c3_sda_a12, 4),
538 GROUP(i2c3_sck_a13, 4),
539 GROUP(i2c3_sda_a19, 4),
540 GROUP(i2c3_sck_a20, 4),
541 GROUP(pdm_dclk_a14, 1),
542 GROUP(pdm_dclk_a19, 3),
543 GROUP(pdm_din0, 1),
544 GROUP(pdm_din1, 1),
545 GROUP(pdm_din2, 1),
546 GROUP(pdm_din3, 1),
547};
548
549/* uart_ao_a */
550static const unsigned int uart_ao_tx_a_pins[] = {GPIOAO_0};
551static const unsigned int uart_ao_rx_a_pins[] = {GPIOAO_1};
552static const unsigned int uart_ao_cts_a_pins[] = {GPIOAO_2};
553static const unsigned int uart_ao_rts_a_pins[] = {GPIOAO_3};
554
555/* uart_ao_b */
556static const unsigned int uart_ao_tx_b_pins[] = {GPIOAO_4};
557static const unsigned int uart_ao_rx_b_pins[] = {GPIOAO_5};
558static const unsigned int uart_ao_cts_b_pins[] = {GPIOAO_2};
559static const unsigned int uart_ao_rts_b_pins[] = {GPIOAO_3};
560
561/* i2c_ao */
562static const unsigned int i2c_ao_sck_4_pins[] = {GPIOAO_4};
563static const unsigned int i2c_ao_sda_5_pins[] = {GPIOAO_5};
564static const unsigned int i2c_ao_sck_8_pins[] = {GPIOAO_8};
565static const unsigned int i2c_ao_sda_9_pins[] = {GPIOAO_9};
566static const unsigned int i2c_ao_sck_10_pins[] = {GPIOAO_10};
567static const unsigned int i2c_ao_sda_11_pins[] = {GPIOAO_11};
568
569/* i2c_ao_slave */
570static const unsigned int i2c_ao_slave_sck_pins[] = {GPIOAO_10};
571static const unsigned int i2c_ao_slave_sda_pins[] = {GPIOAO_11};
572
573/* ir_in */
574static const unsigned int remote_input_ao_pins[] = {GPIOAO_6};
575
576/* ir_out */
577static const unsigned int remote_out_ao_pins[] = {GPIOAO_7};
578
579/* pwm_ao_a */
580static const unsigned int pwm_ao_a_pins[] = {GPIOAO_3};
581
582/* pwm_ao_b */
583static const unsigned int pwm_ao_b_ao2_pins[] = {GPIOAO_2};
584static const unsigned int pwm_ao_b_ao12_pins[] = {GPIOAO_12};
585
586/* pwm_ao_c */
587static const unsigned int pwm_ao_c_ao8_pins[] = {GPIOAO_8};
588static const unsigned int pwm_ao_c_ao13_pins[] = {GPIOAO_13};
589
590/* pwm_ao_d */
591static const unsigned int pwm_ao_d_pins[] = {GPIOAO_9};
592
593/* jtag_ao */
594static const unsigned int jtag_ao_tdi_pins[] = {GPIOAO_3};
595static const unsigned int jtag_ao_tdo_pins[] = {GPIOAO_4};
596static const unsigned int jtag_ao_clk_pins[] = {GPIOAO_5};
597static const unsigned int jtag_ao_tms_pins[] = {GPIOAO_7};
598
599static struct meson_pmx_group meson_axg_aobus_groups[] = {
600 GPIO_GROUP(GPIOAO_0),
601 GPIO_GROUP(GPIOAO_1),
602 GPIO_GROUP(GPIOAO_2),
603 GPIO_GROUP(GPIOAO_3),
604 GPIO_GROUP(GPIOAO_4),
605 GPIO_GROUP(GPIOAO_5),
606 GPIO_GROUP(GPIOAO_6),
607 GPIO_GROUP(GPIOAO_7),
608 GPIO_GROUP(GPIOAO_8),
609 GPIO_GROUP(GPIOAO_9),
610 GPIO_GROUP(GPIOAO_10),
611 GPIO_GROUP(GPIOAO_11),
612 GPIO_GROUP(GPIOAO_12),
613 GPIO_GROUP(GPIOAO_13),
614 GPIO_GROUP(GPIO_TEST_N),
615
616 /* bank AO */
617 GROUP(uart_ao_tx_a, 1),
618 GROUP(uart_ao_rx_a, 1),
619 GROUP(uart_ao_cts_a, 2),
620 GROUP(uart_ao_rts_a, 2),
621 GROUP(uart_ao_tx_b, 1),
622 GROUP(uart_ao_rx_b, 1),
623 GROUP(uart_ao_cts_b, 1),
624 GROUP(uart_ao_rts_b, 1),
625 GROUP(i2c_ao_sck_4, 2),
626 GROUP(i2c_ao_sda_5, 2),
627 GROUP(i2c_ao_sck_8, 2),
628 GROUP(i2c_ao_sda_9, 2),
629 GROUP(i2c_ao_sck_10, 2),
630 GROUP(i2c_ao_sda_11, 2),
631 GROUP(i2c_ao_slave_sck, 1),
632 GROUP(i2c_ao_slave_sda, 1),
633 GROUP(remote_input_ao, 1),
634 GROUP(remote_out_ao, 1),
635 GROUP(pwm_ao_a, 3),
636 GROUP(pwm_ao_b_ao2, 3),
637 GROUP(pwm_ao_b_ao12, 3),
638 GROUP(pwm_ao_c_ao8, 3),
639 GROUP(pwm_ao_c_ao13, 3),
640 GROUP(pwm_ao_d, 3),
641 GROUP(jtag_ao_tdi, 4),
642 GROUP(jtag_ao_tdo, 4),
643 GROUP(jtag_ao_clk, 4),
644 GROUP(jtag_ao_tms, 4),
645};
646
647static const char * const gpio_periphs_groups[] = {
648 "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4",
649 "GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9",
650 "GPIOZ_10",
651
652 "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4",
653 "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9",
654 "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14",
655
656 "GPIOA_0", "GPIOA_1", "GPIOA_2", "GPIOA_3", "GPIOA_4",
657 "GPIOA_5", "GPIOA_6", "GPIOA_7", "GPIOA_8", "GPIOA_9",
658 "GPIOA_10", "GPIOA_11", "GPIOA_12", "GPIOA_13", "GPIOA_14",
659 "GPIOA_15", "GPIOA_16", "GPIOA_17", "GPIOA_18", "GPIOA_19",
660 "GPIOA_20",
661
662 "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
663 "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
664 "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
665 "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19",
666 "GPIOX_20", "GPIOX_21", "GPIOX_22",
667
668 "GPIOY_0", "GPIOY_1", "GPIOY_2", "GPIOY_3", "GPIOY_4",
669 "GPIOY_5", "GPIOY_6", "GPIOY_7", "GPIOY_8", "GPIOY_9",
670 "GPIOY_10", "GPIOY_11", "GPIOY_12", "GPIOY_13", "GPIOY_14",
671 "GPIOY_15",
672};
673
674static const char * const emmc_groups[] = {
675 "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2",
676 "emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5",
677 "emmc_nand_d6", "emmc_nand_d7",
678 "emmc_clk", "emmc_cmd", "emmc_ds",
679};
680
681static const char * const nand_groups[] = {
682 "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2",
683 "emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5",
684 "emmc_nand_d6", "emmc_nand_d7",
685 "nand_ce0", "nand_ale", "nand_cle",
686 "nand_wen_clk", "nand_ren_wr", "nand_rb0",
687};
688
689static const char * const nor_groups[] = {
690 "nor_d", "nor_q", "nor_c", "nor_cs",
691 "nor_hold", "nor_wp",
692};
693
694static const char * const sdio_groups[] = {
695 "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3",
696 "sdio_cmd", "sdio_clk",
697};
698
699static const char * const spi0_groups[] = {
700 "spi0_clk", "spi0_mosi", "spi0_miso", "spi0_ss0",
701 "spi0_ss1", "spi0_ss2"
702};
703
704static const char * const spi1_groups[] = {
705 "spi1_clk_x", "spi1_mosi_x", "spi1_miso_x", "spi1_ss0_x",
706 "spi1_clk_a", "spi1_mosi_a", "spi1_miso_a", "spi1_ss0_a",
707 "spi1_ss1"
708};
709
710static const char * const uart_a_groups[] = {
711 "uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a",
712};
713
714static const char * const uart_b_groups[] = {
715 "uart_tx_b_z", "uart_rx_b_z", "uart_cts_b_z", "uart_rts_b_z",
716 "uart_tx_b_x", "uart_rx_b_x", "uart_cts_b_x", "uart_rts_b_x",
717};
718
719static const char * const uart_ao_b_gpioz_groups[] = {
720 "uart_ao_tx_b_z", "uart_ao_rx_b_z",
721 "uart_ao_cts_b_z", "uart_ao_rts_b_z",
722};
723
724static const char * const i2c0_groups[] = {
725 "i2c0_sck", "i2c0_sda",
726};
727
728static const char * const i2c1_groups[] = {
729 "i2c1_sck_z", "i2c1_sda_z",
730 "i2c1_sck_x", "i2c1_sda_x",
731};
732
733static const char * const i2c2_groups[] = {
734 "i2c2_sck_x", "i2c2_sda_x",
735 "i2c2_sda_a", "i2c2_sck_a",
736};
737
738static const char * const i2c3_groups[] = {
739 "i2c3_sda_a6", "i2c3_sck_a7",
740 "i2c3_sda_a12", "i2c3_sck_a13",
741 "i2c3_sda_a19", "i2c3_sck_a20",
742};
743
744static const char * const eth_groups[] = {
745 "eth_rxd2_rgmii", "eth_rxd3_rgmii", "eth_rgmii_tx_clk",
746 "eth_txd2_rgmii", "eth_txd3_rgmii",
747 "eth_txd0_x", "eth_txd1_x", "eth_txen_x", "eth_rgmii_rx_clk_x",
748 "eth_rxd0_x", "eth_rxd1_x", "eth_rx_dv_x", "eth_mdio_x",
749 "eth_mdc_x",
750 "eth_txd0_y", "eth_txd1_y", "eth_txen_y", "eth_rgmii_rx_clk_y",
751 "eth_rxd0_y", "eth_rxd1_y", "eth_rx_dv_y", "eth_mdio_y",
752 "eth_mdc_y",
753};
754
755static const char * const pwm_a_groups[] = {
756 "pwm_a_z", "pwm_a_x18", "pwm_a_x20", "pwm_a_a",
757};
758
759static const char * const pwm_b_groups[] = {
760 "pwm_b_z", "pwm_b_x", "pwm_b_a",
761};
762
763static const char * const pwm_c_groups[] = {
764 "pwm_c_x10", "pwm_c_x17", "pwm_c_a",
765};
766
767static const char * const pwm_d_groups[] = {
768 "pwm_d_x11", "pwm_d_x16",
769};
770
771static const char * const pwm_vs_groups[] = {
772 "pwm_vs",
773};
774
775static const char * const spdif_out_groups[] = {
776 "spdif_out_z", "spdif_out_a1", "spdif_out_a11",
777 "spdif_out_a19", "spdif_out_a20",
778};
779
780static const char * const spdif_in_groups[] = {
781 "spdif_in_z", "spdif_in_a1", "spdif_in_a7",
782 "spdif_in_a19", "spdif_in_a20",
783};
784
785static const char * const jtag_ee_groups[] = {
786 "jtag_tdo_x", "jtag_tdi_x", "jtag_clk_x",
787 "jtag_tms_x",
788};
789
790static const char * const pdm_groups[] = {
791 "pdm_din0", "pdm_din1", "pdm_din2", "pdm_din3",
792 "pdm_dclk_a14", "pdm_dclk_a19",
793};
794
795static const char * const gpio_aobus_groups[] = {
796 "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4",
797 "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9",
798 "GPIOAO_10", "GPIOAO_11", "GPIOAO_12", "GPIOAO_13",
799 "GPIO_TEST_N",
800};
801
802static const char * const uart_ao_a_groups[] = {
803 "uart_ao_tx_a", "uart_ao_rx_a", "uart_ao_cts_a", "uart_ao_rts_a",
804};
805
806static const char * const uart_ao_b_groups[] = {
807 "uart_ao_tx_b", "uart_ao_rx_b", "uart_ao_cts_b", "uart_ao_rts_b",
808};
809
810static const char * const i2c_ao_groups[] = {
811 "i2c_ao_sck_4", "i2c_ao_sda_5",
812 "i2c_ao_sck_8", "i2c_ao_sda_9",
813 "i2c_ao_sck_10", "i2c_ao_sda_11",
814};
815
816static const char * const i2c_ao_slave_groups[] = {
817 "i2c_ao_slave_sck", "i2c_ao_slave_sda",
818};
819
820static const char * const remote_input_ao_groups[] = {
821 "remote_input_ao",
822};
823
824static const char * const remote_out_ao_groups[] = {
825 "remote_out_ao",
826};
827
828static const char * const pwm_ao_a_groups[] = {
829 "pwm_ao_a",
830};
831
832static const char * const pwm_ao_b_groups[] = {
833 "pwm_ao_b_ao2", "pwm_ao_b_ao12",
834};
835
836static const char * const pwm_ao_c_groups[] = {
837 "pwm_ao_c_ao8", "pwm_ao_c_ao13",
838};
839
840static const char * const pwm_ao_d_groups[] = {
841 "pwm_ao_d",
842};
843
844static const char * const jtag_ao_groups[] = {
845 "jtag_ao_tdi", "jtag_ao_tdo", "jtag_ao_clk", "jtag_ao_tms",
846};
847
848static struct meson_pmx_func meson_axg_periphs_functions[] = {
849 FUNCTION(gpio_periphs),
850 FUNCTION(emmc),
851 FUNCTION(nor),
852 FUNCTION(spi0),
853 FUNCTION(spi1),
854 FUNCTION(sdio),
855 FUNCTION(nand),
856 FUNCTION(uart_a),
857 FUNCTION(uart_b),
858 FUNCTION(uart_ao_b_gpioz),
859 FUNCTION(i2c0),
860 FUNCTION(i2c1),
861 FUNCTION(i2c2),
862 FUNCTION(i2c3),
863 FUNCTION(eth),
864 FUNCTION(pwm_a),
865 FUNCTION(pwm_b),
866 FUNCTION(pwm_c),
867 FUNCTION(pwm_d),
868 FUNCTION(pwm_vs),
869 FUNCTION(spdif_out),
870 FUNCTION(spdif_in),
871 FUNCTION(jtag_ee),
872 FUNCTION(pdm),
873};
874
875static struct meson_pmx_func meson_axg_aobus_functions[] = {
876 FUNCTION(gpio_aobus),
877 FUNCTION(uart_ao_a),
878 FUNCTION(uart_ao_b),
879 FUNCTION(i2c_ao),
880 FUNCTION(i2c_ao_slave),
881 FUNCTION(remote_input_ao),
882 FUNCTION(remote_out_ao),
883 FUNCTION(pwm_ao_a),
884 FUNCTION(pwm_ao_b),
885 FUNCTION(pwm_ao_c),
886 FUNCTION(pwm_ao_d),
887 FUNCTION(jtag_ao),
888};
889
890static struct meson_bank meson_axg_periphs_banks[] = {
891 /* name first last irq pullen pull dir out in */
892 BANK("Z", GPIOZ_0, GPIOZ_10, 14, 24, 3, 0, 3, 0, 9, 0, 10, 0, 11, 0),
893 BANK("BOOT", BOOT_0, BOOT_14, 25, 39, 4, 0, 4, 0, 12, 0, 13, 0, 14, 0),
894 BANK("A", GPIOA_0, GPIOA_20, 40, 60, 0, 0, 0, 0, 0, 0, 1, 0, 2, 0),
895 BANK("X", GPIOX_0, GPIOX_22, 61, 83, 2, 0, 2, 0, 6, 0, 7, 0, 8, 0),
896 BANK("Y", GPIOY_0, GPIOY_15, 84, 99, 1, 0, 1, 0, 3, 0, 4, 0, 5, 0),
897};
898
899static struct meson_bank meson_axg_aobus_banks[] = {
900 /* name first last irq pullen pull dir out in */
901 BANK("AO", GPIOAO_0, GPIOAO_9, 0, 13, 0, 16, 0, 0, 0, 0, 0, 16, 1, 0),
902};
903
904static struct meson_pmx_bank meson_axg_periphs_pmx_banks[] = {
905 /* name first lask reg offset */
906 BANK_PMX("Z", GPIOZ_0, GPIOZ_10, 0x2, 0),
907 BANK_PMX("BOOT", BOOT_0, BOOT_14, 0x0, 0),
908 BANK_PMX("A", GPIOA_0, GPIOA_20, 0xb, 0),
909 BANK_PMX("X", GPIOX_0, GPIOX_22, 0x4, 0),
910 BANK_PMX("Y", GPIOY_0, GPIOY_15, 0x8, 0),
911};
912
913static struct meson_axg_pmx_data meson_axg_periphs_pmx_banks_data = {
914 .pmx_banks = meson_axg_periphs_pmx_banks,
915 .num_pmx_banks = ARRAY_SIZE(meson_axg_periphs_pmx_banks),
916};
917
918static struct meson_pmx_bank meson_axg_aobus_pmx_banks[] = {
919 BANK_PMX("AO", GPIOAO_0, GPIOAO_13, 0x0, 0),
920};
921
922static struct meson_axg_pmx_data meson_axg_aobus_pmx_banks_data = {
923 .pmx_banks = meson_axg_aobus_pmx_banks,
924 .num_pmx_banks = ARRAY_SIZE(meson_axg_aobus_pmx_banks),
925};
926
927static struct meson_pinctrl_data meson_axg_periphs_pinctrl_data = {
928 .name = "periphs-banks",
929 .pins = meson_axg_periphs_pins,
930 .groups = meson_axg_periphs_groups,
931 .funcs = meson_axg_periphs_functions,
932 .banks = meson_axg_periphs_banks,
933 .num_pins = ARRAY_SIZE(meson_axg_periphs_pins),
934 .num_groups = ARRAY_SIZE(meson_axg_periphs_groups),
935 .num_funcs = ARRAY_SIZE(meson_axg_periphs_functions),
936 .num_banks = ARRAY_SIZE(meson_axg_periphs_banks),
937 .pmx_ops = &meson_axg_pmx_ops,
938 .pmx_data = &meson_axg_periphs_pmx_banks_data,
939};
940
941static struct meson_pinctrl_data meson_axg_aobus_pinctrl_data = {
942 .name = "aobus-banks",
943 .pins = meson_axg_aobus_pins,
944 .groups = meson_axg_aobus_groups,
945 .funcs = meson_axg_aobus_functions,
946 .banks = meson_axg_aobus_banks,
947 .num_pins = ARRAY_SIZE(meson_axg_aobus_pins),
948 .num_groups = ARRAY_SIZE(meson_axg_aobus_groups),
949 .num_funcs = ARRAY_SIZE(meson_axg_aobus_functions),
950 .num_banks = ARRAY_SIZE(meson_axg_aobus_banks),
951 .pmx_ops = &meson_axg_pmx_ops,
952 .pmx_data = &meson_axg_aobus_pmx_banks_data,
953};
954
955static const struct of_device_id meson_axg_pinctrl_dt_match[] = {
956 {
957 .compatible = "amlogic,meson-axg-periphs-pinctrl",
958 .data = &meson_axg_periphs_pinctrl_data,
959 },
960 {
961 .compatible = "amlogic,meson-axg-aobus-pinctrl",
962 .data = &meson_axg_aobus_pinctrl_data,
963 },
964 { },
965};
966
967static struct platform_driver meson_axg_pinctrl_driver = {
968 .probe = meson_pinctrl_probe,
969 .driver = {
970 .name = "meson-axg-pinctrl",
971 .of_match_table = meson_axg_pinctrl_dt_match,
972 },
973};
974
975builtin_platform_driver(meson_axg_pinctrl_driver);
diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h
index 183b6e471635..12a391109329 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.h
+++ b/drivers/pinctrl/meson/pinctrl-meson.h
@@ -108,6 +108,7 @@ struct meson_pinctrl_data {
108 struct meson_bank *banks; 108 struct meson_bank *banks;
109 unsigned int num_banks; 109 unsigned int num_banks;
110 const struct pinmux_ops *pmx_ops; 110 const struct pinmux_ops *pmx_ops;
111 void *pmx_data;
111}; 112};
112 113
113struct meson_pinctrl { 114struct meson_pinctrl {
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index bdb8d174efef..5b63248c8209 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -1006,11 +1006,11 @@ static int armada_37xx_pinctrl_register(struct platform_device *pdev,
1006static const struct of_device_id armada_37xx_pinctrl_of_match[] = { 1006static const struct of_device_id armada_37xx_pinctrl_of_match[] = {
1007 { 1007 {
1008 .compatible = "marvell,armada3710-sb-pinctrl", 1008 .compatible = "marvell,armada3710-sb-pinctrl",
1009 .data = (void *)&armada_37xx_pin_sb, 1009 .data = &armada_37xx_pin_sb,
1010 }, 1010 },
1011 { 1011 {
1012 .compatible = "marvell,armada3710-nb-pinctrl", 1012 .compatible = "marvell,armada3710-nb-pinctrl",
1013 .data = (void *)&armada_37xx_pin_nb, 1013 .data = &armada_37xx_pin_nb,
1014 }, 1014 },
1015 { }, 1015 { },
1016}; 1016};
diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c b/drivers/pinctrl/mvebu/pinctrl-mvebu.c
index 163d4614b0f8..9e05cfaf75f0 100644
--- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c
+++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c
@@ -636,10 +636,9 @@ int mvebu_pinctrl_probe(struct platform_device *pdev)
636 */ 636 */
637 size = pctl->num_groups * sizeof(*pctl->groups) + noname * 8; 637 size = pctl->num_groups * sizeof(*pctl->groups) + noname * 8;
638 p = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); 638 p = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
639 if (!p) { 639 if (!p)
640 dev_err(&pdev->dev, "failed to alloc group data\n");
641 return -ENOMEM; 640 return -ENOMEM;
642 } 641
643 pctl->groups = p; 642 pctl->groups = p;
644 noname_buf = p + pctl->num_groups * sizeof(*pctl->groups); 643 noname_buf = p + pctl->num_groups * sizeof(*pctl->groups);
645 644
diff --git a/drivers/pinctrl/nomadik/pinctrl-abx500.c b/drivers/pinctrl/nomadik/pinctrl-abx500.c
index b32c0d602024..d56a49e53f56 100644
--- a/drivers/pinctrl/nomadik/pinctrl-abx500.c
+++ b/drivers/pinctrl/nomadik/pinctrl-abx500.c
@@ -633,7 +633,7 @@ static void abx500_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
633 for (i = 0; i < chip->ngpio; i++, gpio++) { 633 for (i = 0; i < chip->ngpio; i++, gpio++) {
634 /* On AB8500, there is no GPIO0, the first is the GPIO 1 */ 634 /* On AB8500, there is no GPIO0, the first is the GPIO 1 */
635 abx500_gpio_dbg_show_one(s, pctldev, chip, i + 1, gpio); 635 abx500_gpio_dbg_show_one(s, pctldev, chip, i + 1, gpio);
636 seq_printf(s, "\n"); 636 seq_putc(s, '\n');
637 } 637 }
638} 638}
639 639
@@ -1155,13 +1155,9 @@ static int abx500_gpio_probe(struct platform_device *pdev)
1155 return -ENODEV; 1155 return -ENODEV;
1156 } 1156 }
1157 1157
1158 pct = devm_kzalloc(&pdev->dev, sizeof(struct abx500_pinctrl), 1158 pct = devm_kzalloc(&pdev->dev, sizeof(*pct), GFP_KERNEL);
1159 GFP_KERNEL); 1159 if (!pct)
1160 if (pct == NULL) {
1161 dev_err(&pdev->dev,
1162 "failed to allocate memory for pct\n");
1163 return -ENOMEM; 1160 return -ENOMEM;
1164 }
1165 1161
1166 pct->dev = &pdev->dev; 1162 pct->dev = &pdev->dev;
1167 pct->parent = dev_get_drvdata(pdev->dev.parent); 1163 pct->parent = dev_get_drvdata(pdev->dev.parent);
diff --git a/drivers/pinctrl/pinctrl-adi2.c b/drivers/pinctrl/pinctrl-adi2.c
index 56aa181084ac..094a451db2a2 100644
--- a/drivers/pinctrl/pinctrl-adi2.c
+++ b/drivers/pinctrl/pinctrl-adi2.c
@@ -827,13 +827,10 @@ static int adi_gpio_pint_probe(struct platform_device *pdev)
827{ 827{
828 struct device *dev = &pdev->dev; 828 struct device *dev = &pdev->dev;
829 struct resource *res; 829 struct resource *res;
830 struct gpio_pint *pint; 830 struct gpio_pint *pint = devm_kzalloc(dev, sizeof(*pint), GFP_KERNEL);
831 831
832 pint = devm_kzalloc(dev, sizeof(struct gpio_pint), GFP_KERNEL); 832 if (!pint)
833 if (!pint) {
834 dev_err(dev, "Memory alloc failed\n");
835 return -ENOMEM; 833 return -ENOMEM;
836 }
837 834
838 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 835 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
839 pint->base = devm_ioremap_resource(dev, res); 836 pint->base = devm_ioremap_resource(dev, res);
@@ -945,11 +942,9 @@ static int adi_gpio_probe(struct platform_device *pdev)
945 if (!pdata) 942 if (!pdata)
946 return -EINVAL; 943 return -EINVAL;
947 944
948 port = devm_kzalloc(dev, sizeof(struct gpio_port), GFP_KERNEL); 945 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
949 if (!port) { 946 if (!port)
950 dev_err(dev, "Memory alloc failed\n");
951 return -ENOMEM; 947 return -ENOMEM;
952 }
953 948
954 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 949 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
955 port->base = devm_ioremap_resource(dev, res); 950 port->base = devm_ioremap_resource(dev, res);
diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c
index b1ca838dd80a..4b57a13758a4 100644
--- a/drivers/pinctrl/pinctrl-at91-pio4.c
+++ b/drivers/pinctrl/pinctrl-at91-pio4.c
@@ -910,7 +910,7 @@ static int atmel_pinctrl_probe(struct platform_device *pdev)
910 int i, ret; 910 int i, ret;
911 struct resource *res; 911 struct resource *res;
912 struct atmel_pioctrl *atmel_pioctrl; 912 struct atmel_pioctrl *atmel_pioctrl;
913 struct atmel_pioctrl_data *atmel_pioctrl_data; 913 const struct atmel_pioctrl_data *atmel_pioctrl_data;
914 914
915 atmel_pioctrl = devm_kzalloc(dev, sizeof(*atmel_pioctrl), GFP_KERNEL); 915 atmel_pioctrl = devm_kzalloc(dev, sizeof(*atmel_pioctrl), GFP_KERNEL);
916 if (!atmel_pioctrl) 916 if (!atmel_pioctrl)
@@ -924,7 +924,7 @@ static int atmel_pinctrl_probe(struct platform_device *pdev)
924 dev_err(dev, "unknown compatible string\n"); 924 dev_err(dev, "unknown compatible string\n");
925 return -ENODEV; 925 return -ENODEV;
926 } 926 }
927 atmel_pioctrl_data = (struct atmel_pioctrl_data *)match->data; 927 atmel_pioctrl_data = match->data;
928 atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks; 928 atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks;
929 atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK; 929 atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK;
930 930
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 03492e3c09fa..297f1d161211 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -1050,10 +1050,8 @@ static int at91_pinctrl_mux_mask(struct at91_pinctrl *info,
1050 info->nmux = size / gpio_banks; 1050 info->nmux = size / gpio_banks;
1051 1051
1052 info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL); 1052 info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL);
1053 if (!info->mux_mask) { 1053 if (!info->mux_mask)
1054 dev_err(info->dev, "could not alloc mux_mask\n");
1055 return -ENOMEM; 1054 return -ENOMEM;
1056 }
1057 1055
1058 ret = of_property_read_u32_array(np, "atmel,mux-mask", 1056 ret = of_property_read_u32_array(np, "atmel,mux-mask",
1059 info->mux_mask, size); 1057 info->mux_mask, size);
diff --git a/drivers/pinctrl/pinctrl-axp209.c b/drivers/pinctrl/pinctrl-axp209.c
index 22d3bb0bf927..1231bbbfa744 100644
--- a/drivers/pinctrl/pinctrl-axp209.c
+++ b/drivers/pinctrl/pinctrl-axp209.c
@@ -413,9 +413,11 @@ static int axp20x_pctl_probe(struct platform_device *pdev)
413 pctl->chip.set = axp20x_gpio_set; 413 pctl->chip.set = axp20x_gpio_set;
414 pctl->chip.direction_input = axp20x_gpio_input; 414 pctl->chip.direction_input = axp20x_gpio_input;
415 pctl->chip.direction_output = axp20x_gpio_output; 415 pctl->chip.direction_output = axp20x_gpio_output;
416
417 pctl->desc = of_device_get_match_data(dev);
418
416 pctl->chip.ngpio = pctl->desc->npins; 419 pctl->chip.ngpio = pctl->desc->npins;
417 420
418 pctl->desc = (struct axp20x_pctrl_desc *)of_device_get_match_data(dev);
419 pctl->regmap = axp20x->regmap; 421 pctl->regmap = axp20x->regmap;
420 pctl->dev = &pdev->dev; 422 pctl->dev = &pdev->dev;
421 423
diff --git a/drivers/pinctrl/pinctrl-gemini.c b/drivers/pinctrl/pinctrl-gemini.c
index c11b8f14d841..8c9970ae8505 100644
--- a/drivers/pinctrl/pinctrl-gemini.c
+++ b/drivers/pinctrl/pinctrl-gemini.c
@@ -67,6 +67,9 @@ struct gemini_pmx {
67 * elements in .pins so we can iterate over that array 67 * elements in .pins so we can iterate over that array
68 * @mask: bits to clear to enable this when doing pin muxing 68 * @mask: bits to clear to enable this when doing pin muxing
69 * @value: bits to set to enable this when doing pin muxing 69 * @value: bits to set to enable this when doing pin muxing
70 * @driving_mask: bitmask for the IO Pad driving register for this
71 * group, if it supports altering the driving strength of
72 * its lines.
70 */ 73 */
71struct gemini_pin_group { 74struct gemini_pin_group {
72 const char *name; 75 const char *name;
@@ -74,12 +77,14 @@ struct gemini_pin_group {
74 const unsigned int num_pins; 77 const unsigned int num_pins;
75 u32 mask; 78 u32 mask;
76 u32 value; 79 u32 value;
80 u32 driving_mask;
77}; 81};
78 82
79/* Some straight-forward control registers */ 83/* Some straight-forward control registers */
80#define GLOBAL_WORD_ID 0x00 84#define GLOBAL_WORD_ID 0x00
81#define GLOBAL_STATUS 0x04 85#define GLOBAL_STATUS 0x04
82#define GLOBAL_STATUS_FLPIN BIT(20) 86#define GLOBAL_STATUS_FLPIN BIT(20)
87#define GLOBAL_IODRIVE 0x10
83#define GLOBAL_GMAC_CTRL_SKEW 0x1c 88#define GLOBAL_GMAC_CTRL_SKEW 0x1c
84#define GLOBAL_GMAC0_DATA_SKEW 0x20 89#define GLOBAL_GMAC0_DATA_SKEW 0x20
85#define GLOBAL_GMAC1_DATA_SKEW 0x24 90#define GLOBAL_GMAC1_DATA_SKEW 0x24
@@ -738,6 +743,7 @@ static const struct gemini_pin_group gemini_3512_pin_groups[] = {
738 /* Conflict with all flash usage */ 743 /* Conflict with all flash usage */
739 .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE | 744 .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE |
740 PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE, 745 PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
746 .driving_mask = GENMASK(21, 20),
741 }, 747 },
742 { 748 {
743 .name = "satagrp", 749 .name = "satagrp",
@@ -753,6 +759,7 @@ static const struct gemini_pin_group gemini_3512_pin_groups[] = {
753 .name = "gmii_gmac0_grp", 759 .name = "gmii_gmac0_grp",
754 .pins = gmii_gmac0_3512_pins, 760 .pins = gmii_gmac0_3512_pins,
755 .num_pins = ARRAY_SIZE(gmii_gmac0_3512_pins), 761 .num_pins = ARRAY_SIZE(gmii_gmac0_3512_pins),
762 .driving_mask = GENMASK(17, 16),
756 }, 763 },
757 { 764 {
758 .name = "gmii_gmac1_grp", 765 .name = "gmii_gmac1_grp",
@@ -760,6 +767,7 @@ static const struct gemini_pin_group gemini_3512_pin_groups[] = {
760 .num_pins = ARRAY_SIZE(gmii_gmac1_3512_pins), 767 .num_pins = ARRAY_SIZE(gmii_gmac1_3512_pins),
761 /* Bring out RGMII on the GMAC1 pins */ 768 /* Bring out RGMII on the GMAC1 pins */
762 .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, 769 .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
770 .driving_mask = GENMASK(19, 18),
763 }, 771 },
764 { 772 {
765 .name = "pcigrp", 773 .name = "pcigrp",
@@ -767,6 +775,7 @@ static const struct gemini_pin_group gemini_3512_pin_groups[] = {
767 .num_pins = ARRAY_SIZE(pci_3512_pins), 775 .num_pins = ARRAY_SIZE(pci_3512_pins),
768 /* Conflict only with GPIO2 */ 776 /* Conflict only with GPIO2 */
769 .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE, 777 .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE,
778 .driving_mask = GENMASK(23, 22),
770 }, 779 },
771 { 780 {
772 .name = "lpcgrp", 781 .name = "lpcgrp",
@@ -1671,6 +1680,7 @@ static const struct gemini_pin_group gemini_3516_pin_groups[] = {
1671 /* Conflict with all flash usage */ 1680 /* Conflict with all flash usage */
1672 .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE | 1681 .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE |
1673 PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE, 1682 PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
1683 .driving_mask = GENMASK(21, 20),
1674 }, 1684 },
1675 { 1685 {
1676 .name = "satagrp", 1686 .name = "satagrp",
@@ -1686,6 +1696,7 @@ static const struct gemini_pin_group gemini_3516_pin_groups[] = {
1686 .name = "gmii_gmac0_grp", 1696 .name = "gmii_gmac0_grp",
1687 .pins = gmii_gmac0_3516_pins, 1697 .pins = gmii_gmac0_3516_pins,
1688 .num_pins = ARRAY_SIZE(gmii_gmac0_3516_pins), 1698 .num_pins = ARRAY_SIZE(gmii_gmac0_3516_pins),
1699 .driving_mask = GENMASK(17, 16),
1689 }, 1700 },
1690 { 1701 {
1691 .name = "gmii_gmac1_grp", 1702 .name = "gmii_gmac1_grp",
@@ -1693,6 +1704,7 @@ static const struct gemini_pin_group gemini_3516_pin_groups[] = {
1693 .num_pins = ARRAY_SIZE(gmii_gmac1_3516_pins), 1704 .num_pins = ARRAY_SIZE(gmii_gmac1_3516_pins),
1694 /* Bring out RGMII on the GMAC1 pins */ 1705 /* Bring out RGMII on the GMAC1 pins */
1695 .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, 1706 .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
1707 .driving_mask = GENMASK(19, 18),
1696 }, 1708 },
1697 { 1709 {
1698 .name = "pcigrp", 1710 .name = "pcigrp",
@@ -1700,6 +1712,7 @@ static const struct gemini_pin_group gemini_3516_pin_groups[] = {
1700 .num_pins = ARRAY_SIZE(pci_3516_pins), 1712 .num_pins = ARRAY_SIZE(pci_3516_pins),
1701 /* Conflict only with GPIO2 */ 1713 /* Conflict only with GPIO2 */
1702 .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE, 1714 .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE,
1715 .driving_mask = GENMASK(23, 22),
1703 }, 1716 },
1704 { 1717 {
1705 .name = "lpcgrp", 1718 .name = "lpcgrp",
@@ -2015,7 +2028,8 @@ static const char * const sflashgrps[] = { "sflashgrp" };
2015static const char * const gpio0grps[] = { "gpio0agrp", "gpio0bgrp", "gpio0cgrp", 2028static const char * const gpio0grps[] = { "gpio0agrp", "gpio0bgrp", "gpio0cgrp",
2016 "gpio0dgrp", "gpio0egrp", "gpio0fgrp", 2029 "gpio0dgrp", "gpio0egrp", "gpio0fgrp",
2017 "gpio0ggrp", "gpio0hgrp", "gpio0igrp", 2030 "gpio0ggrp", "gpio0hgrp", "gpio0igrp",
2018 "gpio0jgrp", "gpio0kgrp" }; 2031 "gpio0jgrp", "gpio0kgrp", "gpio0lgrp",
2032 "gpio0mgrp" };
2019static const char * const gpio1grps[] = { "gpio1agrp", "gpio1bgrp", "gpio1cgrp", 2033static const char * const gpio1grps[] = { "gpio1agrp", "gpio1bgrp", "gpio1cgrp",
2020 "gpio1dgrp" }; 2034 "gpio1dgrp" };
2021static const char * const gpio2grps[] = { "gpio2agrp", "gpio2bgrp", "gpio2cgrp" }; 2035static const char * const gpio2grps[] = { "gpio2agrp", "gpio2bgrp", "gpio2cgrp" };
@@ -2393,9 +2407,77 @@ static int gemini_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2393 return ret; 2407 return ret;
2394} 2408}
2395 2409
2410static int gemini_pinconf_group_set(struct pinctrl_dev *pctldev,
2411 unsigned selector,
2412 unsigned long *configs,
2413 unsigned num_configs)
2414{
2415 struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
2416 const struct gemini_pin_group *grp = NULL;
2417 enum pin_config_param param;
2418 u32 arg;
2419 u32 val;
2420 int i;
2421
2422 if (pmx->is_3512)
2423 grp = &gemini_3512_pin_groups[selector];
2424 if (pmx->is_3516)
2425 grp = &gemini_3516_pin_groups[selector];
2426
2427 /* First figure out if this group supports configs */
2428 if (!grp->driving_mask) {
2429 dev_err(pmx->dev, "pin config group \"%s\" does "
2430 "not support drive strength setting\n",
2431 grp->name);
2432 return -EINVAL;
2433 }
2434
2435 for (i = 0; i < num_configs; i++) {
2436 param = pinconf_to_config_param(configs[i]);
2437 arg = pinconf_to_config_argument(configs[i]);
2438
2439 switch (param) {
2440 case PIN_CONFIG_DRIVE_STRENGTH:
2441 switch (arg) {
2442 case 4:
2443 val = 0;
2444 break;
2445 case 8:
2446 val = 1;
2447 break;
2448 case 12:
2449 val = 2;
2450 break;
2451 case 16:
2452 val = 3;
2453 break;
2454 default:
2455 dev_err(pmx->dev,
2456 "invalid drive strength %d mA\n",
2457 arg);
2458 return -ENOTSUPP;
2459 }
2460 val <<= (ffs(grp->driving_mask) - 1);
2461 regmap_update_bits(pmx->map, GLOBAL_IODRIVE,
2462 grp->driving_mask,
2463 val);
2464 dev_info(pmx->dev,
2465 "set group %s to %d mA drive strength mask %08x val %08x\n",
2466 grp->name, arg, grp->driving_mask, val);
2467 break;
2468 default:
2469 dev_err(pmx->dev, "invalid config param %04x\n", param);
2470 return -ENOTSUPP;
2471 }
2472 }
2473
2474 return 0;
2475}
2476
2396static const struct pinconf_ops gemini_pinconf_ops = { 2477static const struct pinconf_ops gemini_pinconf_ops = {
2397 .pin_config_get = gemini_pinconf_get, 2478 .pin_config_get = gemini_pinconf_get,
2398 .pin_config_set = gemini_pinconf_set, 2479 .pin_config_set = gemini_pinconf_set,
2480 .pin_config_group_set = gemini_pinconf_group_set,
2399 .is_generic = true, 2481 .is_generic = true,
2400}; 2482};
2401 2483
diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c
index 372ddf386bdb..ac38a3f9f86b 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -736,10 +736,8 @@ static int ingenic_pinctrl_probe(struct platform_device *pdev)
736 736
737 base = devm_ioremap_resource(dev, 737 base = devm_ioremap_resource(dev,
738 platform_get_resource(pdev, IORESOURCE_MEM, 0)); 738 platform_get_resource(pdev, IORESOURCE_MEM, 0));
739 if (IS_ERR(base)) { 739 if (IS_ERR(base))
740 dev_err(dev, "Failed to ioremap registers\n");
741 return PTR_ERR(base); 740 return PTR_ERR(base);
742 }
743 741
744 jzpc->map = devm_regmap_init_mmio(dev, base, 742 jzpc->map = devm_regmap_init_mmio(dev, base,
745 &ingenic_pinctrl_regmap_config); 743 &ingenic_pinctrl_regmap_config);
diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c
index 4a6ea159c65d..644c5beb05cb 100644
--- a/drivers/pinctrl/pinctrl-mcp23s08.c
+++ b/drivers/pinctrl/pinctrl-mcp23s08.c
@@ -455,31 +455,22 @@ static irqreturn_t mcp23s08_irq(int irq, void *data)
455 defval_changed, gpio_set; 455 defval_changed, gpio_set;
456 456
457 mutex_lock(&mcp->lock); 457 mutex_lock(&mcp->lock);
458 if (mcp_read(mcp, MCP_INTF, &intf) < 0) { 458 if (mcp_read(mcp, MCP_INTF, &intf))
459 mutex_unlock(&mcp->lock); 459 goto unlock;
460 return IRQ_HANDLED;
461 }
462 460
463 if (mcp_read(mcp, MCP_INTCAP, &intcap) < 0) { 461 if (mcp_read(mcp, MCP_INTCAP, &intcap))
464 mutex_unlock(&mcp->lock); 462 goto unlock;
465 return IRQ_HANDLED;
466 }
467 463
468 if (mcp_read(mcp, MCP_INTCON, &intcon) < 0) { 464 if (mcp_read(mcp, MCP_INTCON, &intcon))
469 mutex_unlock(&mcp->lock); 465 goto unlock;
470 return IRQ_HANDLED;
471 }
472 466
473 if (mcp_read(mcp, MCP_DEFVAL, &defval) < 0) { 467 if (mcp_read(mcp, MCP_DEFVAL, &defval))
474 mutex_unlock(&mcp->lock); 468 goto unlock;
475 return IRQ_HANDLED;
476 }
477 469
478 /* This clears the interrupt(configurable on S18) */ 470 /* This clears the interrupt(configurable on S18) */
479 if (mcp_read(mcp, MCP_GPIO, &gpio) < 0) { 471 if (mcp_read(mcp, MCP_GPIO, &gpio))
480 mutex_unlock(&mcp->lock); 472 goto unlock;
481 return IRQ_HANDLED; 473
482 }
483 gpio_orig = mcp->cached_gpio; 474 gpio_orig = mcp->cached_gpio;
484 mcp->cached_gpio = gpio; 475 mcp->cached_gpio = gpio;
485 mutex_unlock(&mcp->lock); 476 mutex_unlock(&mcp->lock);
@@ -541,6 +532,10 @@ static irqreturn_t mcp23s08_irq(int irq, void *data)
541 } 532 }
542 533
543 return IRQ_HANDLED; 534 return IRQ_HANDLED;
535
536unlock:
537 mutex_unlock(&mcp->lock);
538 return IRQ_HANDLED;
544} 539}
545 540
546static void mcp23s08_irq_mask(struct irq_data *data) 541static void mcp23s08_irq_mask(struct irq_data *data)
@@ -753,13 +748,12 @@ static void mcp23s08_dbg_show(struct seq_file *s, struct gpio_chip *chip)
753 if (!label) 748 if (!label)
754 continue; 749 continue;
755 750
756 seq_printf(s, " gpio-%-3d P%c.%d (%-12s) %s %s %s", 751 seq_printf(s, " gpio-%-3d P%c.%d (%-12s) %s %s %s\n",
757 chip->base + t, bank, t, label, 752 chip->base + t, bank, t, label,
758 (iodir & mask) ? "in " : "out", 753 (iodir & mask) ? "in " : "out",
759 (gpio & mask) ? "hi" : "lo", 754 (gpio & mask) ? "hi" : "lo",
760 (gppu & mask) ? "up" : " "); 755 (gppu & mask) ? "up" : " ");
761 /* NOTE: ignoring the irq-related registers */ 756 /* NOTE: ignoring the irq-related registers */
762 seq_puts(s, "\n");
763 } 757 }
764done: 758done:
765 mutex_unlock(&mcp->lock); 759 mutex_unlock(&mcp->lock);
@@ -896,16 +890,16 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
896 goto fail; 890 goto fail;
897 } 891 }
898 892
899 ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp);
900 if (ret < 0)
901 goto fail;
902
903 if (mcp->irq && mcp->irq_controller) { 893 if (mcp->irq && mcp->irq_controller) {
904 ret = mcp23s08_irq_setup(mcp); 894 ret = mcp23s08_irq_setup(mcp);
905 if (ret) 895 if (ret)
906 goto fail; 896 goto fail;
907 } 897 }
908 898
899 ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp);
900 if (ret < 0)
901 goto fail;
902
909 mcp->pinctrl_desc.name = "mcp23xxx-pinctrl"; 903 mcp->pinctrl_desc.name = "mcp23xxx-pinctrl";
910 mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops; 904 mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops;
911 mcp->pinctrl_desc.confops = &mcp_pinconf_ops; 905 mcp->pinctrl_desc.confops = &mcp_pinconf_ops;
diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c
new file mode 100644
index 000000000000..01a50d969111
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-ocelot.c
@@ -0,0 +1,511 @@
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Microsemi SoCs pinctrl driver
4 *
5 * Author: <alexandre.belloni@free-electrons.com>
6 * License: Dual MIT/GPL
7 * Copyright (c) 2017 Microsemi Corporation
8 */
9
10#include <linux/gpio/driver.h>
11#include <linux/interrupt.h>
12#include <linux/io.h>
13#include <linux/of_device.h>
14#include <linux/of_platform.h>
15#include <linux/pinctrl/pinctrl.h>
16#include <linux/pinctrl/pinmux.h>
17#include <linux/pinctrl/pinconf.h>
18#include <linux/pinctrl/pinconf-generic.h>
19#include <linux/platform_device.h>
20#include <linux/regmap.h>
21#include <linux/slab.h>
22
23#include "core.h"
24#include "pinconf.h"
25#include "pinmux.h"
26
27#define OCELOT_GPIO_OUT_SET 0x0
28#define OCELOT_GPIO_OUT_CLR 0x4
29#define OCELOT_GPIO_OUT 0x8
30#define OCELOT_GPIO_IN 0xc
31#define OCELOT_GPIO_OE 0x10
32#define OCELOT_GPIO_INTR 0x14
33#define OCELOT_GPIO_INTR_ENA 0x18
34#define OCELOT_GPIO_INTR_IDENT 0x1c
35#define OCELOT_GPIO_ALT0 0x20
36#define OCELOT_GPIO_ALT1 0x24
37#define OCELOT_GPIO_SD_MAP 0x28
38
39#define OCELOT_PINS 22
40#define OCELOT_FUNC_PER_PIN 4
41
42enum {
43 FUNC_NONE,
44 FUNC_GPIO,
45 FUNC_IRQ0_IN,
46 FUNC_IRQ0_OUT,
47 FUNC_IRQ1_IN,
48 FUNC_IRQ1_OUT,
49 FUNC_MIIM1,
50 FUNC_PCI_WAKE,
51 FUNC_PTP0,
52 FUNC_PTP1,
53 FUNC_PTP2,
54 FUNC_PTP3,
55 FUNC_PWM,
56 FUNC_RECO_CLK0,
57 FUNC_RECO_CLK1,
58 FUNC_SFP0,
59 FUNC_SFP1,
60 FUNC_SFP2,
61 FUNC_SFP3,
62 FUNC_SFP4,
63 FUNC_SFP5,
64 FUNC_SG0,
65 FUNC_SI,
66 FUNC_TACHO,
67 FUNC_TWI,
68 FUNC_TWI_SCL_M,
69 FUNC_UART,
70 FUNC_UART2,
71 FUNC_MAX
72};
73
74static const char *const ocelot_function_names[] = {
75 [FUNC_NONE] = "none",
76 [FUNC_GPIO] = "gpio",
77 [FUNC_IRQ0_IN] = "irq0_in",
78 [FUNC_IRQ0_OUT] = "irq0_out",
79 [FUNC_IRQ1_IN] = "irq1_in",
80 [FUNC_IRQ1_OUT] = "irq1_out",
81 [FUNC_MIIM1] = "miim1",
82 [FUNC_PCI_WAKE] = "pci_wake",
83 [FUNC_PTP0] = "ptp0",
84 [FUNC_PTP1] = "ptp1",
85 [FUNC_PTP2] = "ptp2",
86 [FUNC_PTP3] = "ptp3",
87 [FUNC_PWM] = "pwm",
88 [FUNC_RECO_CLK0] = "reco_clk0",
89 [FUNC_RECO_CLK1] = "reco_clk1",
90 [FUNC_SFP0] = "sfp0",
91 [FUNC_SFP1] = "sfp1",
92 [FUNC_SFP2] = "sfp2",
93 [FUNC_SFP3] = "sfp3",
94 [FUNC_SFP4] = "sfp4",
95 [FUNC_SFP5] = "sfp5",
96 [FUNC_SG0] = "sg0",
97 [FUNC_SI] = "si",
98 [FUNC_TACHO] = "tacho",
99 [FUNC_TWI] = "twi",
100 [FUNC_TWI_SCL_M] = "twi_scl_m",
101 [FUNC_UART] = "uart",
102 [FUNC_UART2] = "uart2",
103};
104
105struct ocelot_pmx_func {
106 const char **groups;
107 unsigned int ngroups;
108};
109
110struct ocelot_pin_caps {
111 unsigned int pin;
112 unsigned char functions[OCELOT_FUNC_PER_PIN];
113};
114
115struct ocelot_pinctrl {
116 struct device *dev;
117 struct pinctrl_dev *pctl;
118 struct gpio_chip gpio_chip;
119 struct regmap *map;
120 struct ocelot_pmx_func func[FUNC_MAX];
121};
122
123#define OCELOT_P(p, f0, f1, f2) \
124static struct ocelot_pin_caps ocelot_pin_##p = { \
125 .pin = p, \
126 .functions = { \
127 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \
128 }, \
129}
130
131OCELOT_P(0, SG0, NONE, NONE);
132OCELOT_P(1, SG0, NONE, NONE);
133OCELOT_P(2, SG0, NONE, NONE);
134OCELOT_P(3, SG0, NONE, NONE);
135OCELOT_P(4, IRQ0_IN, IRQ0_OUT, TWI);
136OCELOT_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE);
137OCELOT_P(6, UART, TWI_SCL_M, NONE);
138OCELOT_P(7, UART, TWI_SCL_M, NONE);
139OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT);
140OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT);
141OCELOT_P(10, PTP2, TWI_SCL_M, SFP0);
142OCELOT_P(11, PTP3, TWI_SCL_M, SFP1);
143OCELOT_P(12, UART2, TWI_SCL_M, SFP2);
144OCELOT_P(13, UART2, TWI_SCL_M, SFP3);
145OCELOT_P(14, MIIM1, TWI_SCL_M, SFP4);
146OCELOT_P(15, MIIM1, TWI_SCL_M, SFP5);
147OCELOT_P(16, TWI, NONE, SI);
148OCELOT_P(17, TWI, TWI_SCL_M, SI);
149OCELOT_P(18, PTP0, TWI_SCL_M, NONE);
150OCELOT_P(19, PTP1, TWI_SCL_M, NONE);
151OCELOT_P(20, RECO_CLK0, TACHO, NONE);
152OCELOT_P(21, RECO_CLK1, PWM, NONE);
153
154#define OCELOT_PIN(n) { \
155 .number = n, \
156 .name = "GPIO_"#n, \
157 .drv_data = &ocelot_pin_##n \
158}
159
160static const struct pinctrl_pin_desc ocelot_pins[] = {
161 OCELOT_PIN(0),
162 OCELOT_PIN(1),
163 OCELOT_PIN(2),
164 OCELOT_PIN(3),
165 OCELOT_PIN(4),
166 OCELOT_PIN(5),
167 OCELOT_PIN(6),
168 OCELOT_PIN(7),
169 OCELOT_PIN(8),
170 OCELOT_PIN(9),
171 OCELOT_PIN(10),
172 OCELOT_PIN(11),
173 OCELOT_PIN(12),
174 OCELOT_PIN(13),
175 OCELOT_PIN(14),
176 OCELOT_PIN(15),
177 OCELOT_PIN(16),
178 OCELOT_PIN(17),
179 OCELOT_PIN(18),
180 OCELOT_PIN(19),
181 OCELOT_PIN(20),
182 OCELOT_PIN(21),
183};
184
185static int ocelot_get_functions_count(struct pinctrl_dev *pctldev)
186{
187 return ARRAY_SIZE(ocelot_function_names);
188}
189
190static const char *ocelot_get_function_name(struct pinctrl_dev *pctldev,
191 unsigned int function)
192{
193 return ocelot_function_names[function];
194}
195
196static int ocelot_get_function_groups(struct pinctrl_dev *pctldev,
197 unsigned int function,
198 const char *const **groups,
199 unsigned *const num_groups)
200{
201 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
202
203 *groups = info->func[function].groups;
204 *num_groups = info->func[function].ngroups;
205
206 return 0;
207}
208
209static int ocelot_pin_function_idx(unsigned int pin, unsigned int function)
210{
211 struct ocelot_pin_caps *p = ocelot_pins[pin].drv_data;
212 int i;
213
214 for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) {
215 if (function == p->functions[i])
216 return i;
217 }
218
219 return -1;
220}
221
222static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev,
223 unsigned int selector, unsigned int group)
224{
225 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
226 struct ocelot_pin_caps *pin = ocelot_pins[group].drv_data;
227 int f;
228
229 f = ocelot_pin_function_idx(group, selector);
230 if (f < 0)
231 return -EINVAL;
232
233 /*
234 * f is encoded on two bits.
235 * bit 0 of f goes in BIT(pin) of ALT0, bit 1 of f goes in BIT(pin) of
236 * ALT1
237 * This is racy because both registers can't be updated at the same time
238 * but it doesn't matter much for now.
239 */
240 regmap_update_bits(info->map, OCELOT_GPIO_ALT0, BIT(pin->pin),
241 f << pin->pin);
242 regmap_update_bits(info->map, OCELOT_GPIO_ALT1, BIT(pin->pin),
243 f << (pin->pin - 1));
244
245 return 0;
246}
247
248static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev,
249 struct pinctrl_gpio_range *range,
250 unsigned int pin, bool input)
251{
252 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
253
254 regmap_update_bits(info->map, OCELOT_GPIO_OE, BIT(pin),
255 input ? BIT(pin) : 0);
256
257 return 0;
258}
259
260static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev,
261 struct pinctrl_gpio_range *range,
262 unsigned int offset)
263{
264 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
265
266 regmap_update_bits(info->map, OCELOT_GPIO_ALT0, BIT(offset), 0);
267 regmap_update_bits(info->map, OCELOT_GPIO_ALT1, BIT(offset), 0);
268
269 return 0;
270}
271
272static const struct pinmux_ops ocelot_pmx_ops = {
273 .get_functions_count = ocelot_get_functions_count,
274 .get_function_name = ocelot_get_function_name,
275 .get_function_groups = ocelot_get_function_groups,
276 .set_mux = ocelot_pinmux_set_mux,
277 .gpio_set_direction = ocelot_gpio_set_direction,
278 .gpio_request_enable = ocelot_gpio_request_enable,
279};
280
281static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev)
282{
283 return ARRAY_SIZE(ocelot_pins);
284}
285
286static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev,
287 unsigned int group)
288{
289 return ocelot_pins[group].name;
290}
291
292static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev,
293 unsigned int group,
294 const unsigned int **pins,
295 unsigned int *num_pins)
296{
297 *pins = &ocelot_pins[group].number;
298 *num_pins = 1;
299
300 return 0;
301}
302
303static const struct pinctrl_ops ocelot_pctl_ops = {
304 .get_groups_count = ocelot_pctl_get_groups_count,
305 .get_group_name = ocelot_pctl_get_group_name,
306 .get_group_pins = ocelot_pctl_get_group_pins,
307 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
308 .dt_free_map = pinconf_generic_dt_free_map,
309};
310
311static struct pinctrl_desc ocelot_desc = {
312 .name = "ocelot-pinctrl",
313 .pins = ocelot_pins,
314 .npins = ARRAY_SIZE(ocelot_pins),
315 .pctlops = &ocelot_pctl_ops,
316 .pmxops = &ocelot_pmx_ops,
317 .owner = THIS_MODULE,
318};
319
320static int ocelot_create_group_func_map(struct device *dev,
321 struct ocelot_pinctrl *info)
322{
323 u16 pins[ARRAY_SIZE(ocelot_pins)];
324 int f, npins, i;
325
326 for (f = 0; f < FUNC_MAX; f++) {
327 for (npins = 0, i = 0; i < ARRAY_SIZE(ocelot_pins); i++) {
328 if (ocelot_pin_function_idx(i, f) >= 0)
329 pins[npins++] = i;
330 }
331
332 info->func[f].ngroups = npins;
333 info->func[f].groups = devm_kzalloc(dev, npins *
334 sizeof(char *),
335 GFP_KERNEL);
336 if (!info->func[f].groups)
337 return -ENOMEM;
338
339 for (i = 0; i < npins; i++)
340 info->func[f].groups[i] = ocelot_pins[pins[i]].name;
341 }
342
343 return 0;
344}
345
346static int ocelot_pinctrl_register(struct platform_device *pdev,
347 struct ocelot_pinctrl *info)
348{
349 int ret;
350
351 ret = ocelot_create_group_func_map(&pdev->dev, info);
352 if (ret) {
353 dev_err(&pdev->dev, "Unable to create group func map.\n");
354 return ret;
355 }
356
357 info->pctl = devm_pinctrl_register(&pdev->dev, &ocelot_desc, info);
358 if (IS_ERR(info->pctl)) {
359 dev_err(&pdev->dev, "Failed to register pinctrl\n");
360 return PTR_ERR(info->pctl);
361 }
362
363 return 0;
364}
365
366static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset)
367{
368 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
369 unsigned int val;
370
371 regmap_read(info->map, OCELOT_GPIO_IN, &val);
372
373 return !!(val & BIT(offset));
374}
375
376static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset,
377 int value)
378{
379 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
380
381 if (value)
382 regmap_write(info->map, OCELOT_GPIO_OUT_SET, BIT(offset));
383 else
384 regmap_write(info->map, OCELOT_GPIO_OUT_CLR, BIT(offset));
385}
386
387static int ocelot_gpio_get_direction(struct gpio_chip *chip,
388 unsigned int offset)
389{
390 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
391 unsigned int val;
392
393 regmap_read(info->map, OCELOT_GPIO_OE, &val);
394
395 return !(val & BIT(offset));
396}
397
398static int ocelot_gpio_direction_input(struct gpio_chip *chip,
399 unsigned int offset)
400{
401 return pinctrl_gpio_direction_input(chip->base + offset);
402}
403
404static int ocelot_gpio_direction_output(struct gpio_chip *chip,
405 unsigned int offset, int value)
406{
407 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
408 unsigned int pin = BIT(offset);
409
410 if (value)
411 regmap_write(info->map, OCELOT_GPIO_OUT_SET, pin);
412 else
413 regmap_write(info->map, OCELOT_GPIO_OUT_CLR, pin);
414
415 return pinctrl_gpio_direction_output(chip->base + offset);
416}
417
418static const struct gpio_chip ocelot_gpiolib_chip = {
419 .request = gpiochip_generic_request,
420 .free = gpiochip_generic_free,
421 .set = ocelot_gpio_set,
422 .get = ocelot_gpio_get,
423 .get_direction = ocelot_gpio_get_direction,
424 .direction_input = ocelot_gpio_direction_input,
425 .direction_output = ocelot_gpio_direction_output,
426 .owner = THIS_MODULE,
427};
428
429static int ocelot_gpiochip_register(struct platform_device *pdev,
430 struct ocelot_pinctrl *info)
431{
432 struct gpio_chip *gc;
433 int ret;
434
435 info->gpio_chip = ocelot_gpiolib_chip;
436
437 gc = &info->gpio_chip;
438 gc->ngpio = OCELOT_PINS;
439 gc->parent = &pdev->dev;
440 gc->base = 0;
441 gc->of_node = info->dev->of_node;
442 gc->label = "ocelot-gpio";
443
444 ret = devm_gpiochip_add_data(&pdev->dev, gc, info);
445 if (ret)
446 return ret;
447
448 /* TODO: this can be used as an irqchip but no board is using that */
449
450 return 0;
451}
452
453static const struct regmap_config ocelot_pinctrl_regmap_config = {
454 .reg_bits = 32,
455 .val_bits = 32,
456 .reg_stride = 4,
457 .max_register = 0x64,
458};
459
460static const struct of_device_id ocelot_pinctrl_of_match[] = {
461 { .compatible = "mscc,ocelot-pinctrl" },
462 {},
463};
464
465int ocelot_pinctrl_probe(struct platform_device *pdev)
466{
467 struct device *dev = &pdev->dev;
468 struct ocelot_pinctrl *info;
469 void __iomem *base;
470 int ret;
471
472 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
473 if (!info)
474 return -ENOMEM;
475
476 base = devm_ioremap_resource(dev,
477 platform_get_resource(pdev, IORESOURCE_MEM, 0));
478 if (IS_ERR(base)) {
479 dev_err(dev, "Failed to ioremap registers\n");
480 return PTR_ERR(base);
481 }
482
483 info->map = devm_regmap_init_mmio(dev, base,
484 &ocelot_pinctrl_regmap_config);
485 if (IS_ERR(info->map)) {
486 dev_err(dev, "Failed to create regmap\n");
487 return PTR_ERR(info->map);
488 }
489 dev_set_drvdata(dev, info->map);
490 info->dev = dev;
491
492 ret = ocelot_pinctrl_register(pdev, info);
493 if (ret)
494 return ret;
495
496 ret = ocelot_gpiochip_register(pdev, info);
497 if (ret)
498 return ret;
499
500 return 0;
501}
502
503static struct platform_driver ocelot_pinctrl_driver = {
504 .driver = {
505 .name = "pinctrl-ocelot",
506 .of_match_table = of_match_ptr(ocelot_pinctrl_of_match),
507 .suppress_bind_attrs = true,
508 },
509 .probe = ocelot_pinctrl_probe,
510};
511builtin_platform_driver(ocelot_pinctrl_driver);
diff --git a/drivers/pinctrl/pinctrl-palmas.c b/drivers/pinctrl/pinctrl-palmas.c
index 4d6a5015b927..d42f18cb1bc7 100644
--- a/drivers/pinctrl/pinctrl-palmas.c
+++ b/drivers/pinctrl/pinctrl-palmas.c
@@ -1012,10 +1012,8 @@ static int palmas_pinctrl_probe(struct platform_device *pdev)
1012 } 1012 }
1013 1013
1014 pci = devm_kzalloc(&pdev->dev, sizeof(*pci), GFP_KERNEL); 1014 pci = devm_kzalloc(&pdev->dev, sizeof(*pci), GFP_KERNEL);
1015 if (!pci) { 1015 if (!pci)
1016 dev_err(&pdev->dev, "Malloc for pci failed\n");
1017 return -ENOMEM; 1016 return -ENOMEM;
1018 }
1019 1017
1020 pci->dev = &pdev->dev; 1018 pci->dev = &pdev->dev;
1021 pci->palmas = dev_get_drvdata(pdev->dev.parent); 1019 pci->palmas = dev_get_drvdata(pdev->dev.parent);
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 2ba17548ad5b..3924779f5578 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -136,7 +136,7 @@ struct rockchip_drv {
136 * @iomux: array describing the 4 iomux sources of the bank 136 * @iomux: array describing the 4 iomux sources of the bank
137 * @drv: array describing the 4 drive strength sources of the bank 137 * @drv: array describing the 4 drive strength sources of the bank
138 * @pull_type: array describing the 4 pull type sources of the bank 138 * @pull_type: array describing the 4 pull type sources of the bank
139 * @valid: are all necessary informations present 139 * @valid: is all necessary information present
140 * @of_node: dt node of this bank 140 * @of_node: dt node of this bank
141 * @drvdata: common pinctrl basedata 141 * @drvdata: common pinctrl basedata
142 * @domain: irqdomain of the gpio bank 142 * @domain: irqdomain of the gpio bank
@@ -1988,7 +1988,7 @@ static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
1988 info->functions[selector].name, info->groups[group].name); 1988 info->functions[selector].name, info->groups[group].name);
1989 1989
1990 /* 1990 /*
1991 * for each pin in the pin group selected, program the correspoding pin 1991 * for each pin in the pin group selected, program the corresponding
1992 * pin function number in the config register. 1992 * pin function number in the config register.
1993 */ 1993 */
1994 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { 1994 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
@@ -2014,8 +2014,16 @@ static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
2014{ 2014{
2015 struct rockchip_pin_bank *bank = gpiochip_get_data(chip); 2015 struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
2016 u32 data; 2016 u32 data;
2017 int ret;
2017 2018
2019 ret = clk_enable(bank->clk);
2020 if (ret < 0) {
2021 dev_err(bank->drvdata->dev,
2022 "failed to enable clock for bank %s\n", bank->name);
2023 return ret;
2024 }
2018 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 2025 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2026 clk_disable(bank->clk);
2019 2027
2020 return !(data & BIT(offset)); 2028 return !(data & BIT(offset));
2021} 2029}
@@ -2400,18 +2408,14 @@ static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
2400 info->functions = devm_kzalloc(dev, info->nfunctions * 2408 info->functions = devm_kzalloc(dev, info->nfunctions *
2401 sizeof(struct rockchip_pmx_func), 2409 sizeof(struct rockchip_pmx_func),
2402 GFP_KERNEL); 2410 GFP_KERNEL);
2403 if (!info->functions) { 2411 if (!info->functions)
2404 dev_err(dev, "failed to allocate memory for function list\n");
2405 return -EINVAL; 2412 return -EINVAL;
2406 }
2407 2413
2408 info->groups = devm_kzalloc(dev, info->ngroups * 2414 info->groups = devm_kzalloc(dev, info->ngroups *
2409 sizeof(struct rockchip_pin_group), 2415 sizeof(struct rockchip_pin_group),
2410 GFP_KERNEL); 2416 GFP_KERNEL);
2411 if (!info->groups) { 2417 if (!info->groups)
2412 dev_err(dev, "failed allocate memory for ping group list\n");
2413 return -EINVAL; 2418 return -EINVAL;
2414 }
2415 2419
2416 i = 0; 2420 i = 0;
2417 2421
@@ -2447,10 +2451,9 @@ static int rockchip_pinctrl_register(struct platform_device *pdev,
2447 2451
2448 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) * 2452 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
2449 info->ctrl->nr_pins, GFP_KERNEL); 2453 info->ctrl->nr_pins, GFP_KERNEL);
2450 if (!pindesc) { 2454 if (!pindesc)
2451 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
2452 return -ENOMEM; 2455 return -ENOMEM;
2453 } 2456
2454 ctrldesc->pins = pindesc; 2457 ctrldesc->pins = pindesc;
2455 ctrldesc->npins = info->ctrl->nr_pins; 2458 ctrldesc->npins = info->ctrl->nr_pins;
2456 2459
@@ -2532,7 +2535,7 @@ static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
2532 2535
2533/* 2536/*
2534 * gpiolib gpio_direction_input callback function. The setting of the pin 2537 * gpiolib gpio_direction_input callback function. The setting of the pin
2535 * mux function as 'gpio input' will be handled by the pinctrl susbsystem 2538 * mux function as 'gpio input' will be handled by the pinctrl subsystem
2536 * interface. 2539 * interface.
2537 */ 2540 */
2538static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 2541static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
@@ -2542,7 +2545,7 @@ static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
2542 2545
2543/* 2546/*
2544 * gpiolib gpio_direction_output callback function. The setting of the pin 2547 * gpiolib gpio_direction_output callback function. The setting of the pin
2545 * mux function as 'gpio output' will be handled by the pinctrl susbsystem 2548 * mux function as 'gpio output' will be handled by the pinctrl subsystem
2546 * interface. 2549 * interface.
2547 */ 2550 */
2548static int rockchip_gpio_direction_output(struct gpio_chip *gc, 2551static int rockchip_gpio_direction_output(struct gpio_chip *gc,
@@ -3163,7 +3166,7 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
3163 return -ENODEV; 3166 return -ENODEV;
3164 } 3167 }
3165 3168
3166 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL); 3169 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
3167 if (!info) 3170 if (!info)
3168 return -ENOMEM; 3171 return -ENOMEM;
3169 3172
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 3501491e5bfc..cec75379f936 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -1462,8 +1462,6 @@ static void pcs_irq_chain_handler(struct irq_desc *desc)
1462 pcs_irq_handle(pcs_soc); 1462 pcs_irq_handle(pcs_soc);
1463 /* REVISIT: export and add handle_bad_irq(irq, desc)? */ 1463 /* REVISIT: export and add handle_bad_irq(irq, desc)? */
1464 chained_irq_exit(chip, desc); 1464 chained_irq_exit(chip, desc);
1465
1466 return;
1467} 1465}
1468 1466
1469static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq, 1467static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
@@ -1649,10 +1647,9 @@ static int pcs_probe(struct platform_device *pdev)
1649 return -EINVAL; 1647 return -EINVAL;
1650 1648
1651 pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL); 1649 pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
1652 if (!pcs) { 1650 if (!pcs)
1653 dev_err(&pdev->dev, "could not allocate\n");
1654 return -ENOMEM; 1651 return -ENOMEM;
1655 } 1652
1656 pcs->dev = &pdev->dev; 1653 pcs->dev = &pdev->dev;
1657 pcs->np = np; 1654 pcs->np = np;
1658 raw_spin_lock_init(&pcs->lock); 1655 raw_spin_lock_init(&pcs->lock);
@@ -1777,8 +1774,7 @@ static int pcs_probe(struct platform_device *pdev)
1777 dev_warn(pcs->dev, "initialized with no interrupts\n"); 1774 dev_warn(pcs->dev, "initialized with no interrupts\n");
1778 } 1775 }
1779 1776
1780 dev_info(pcs->dev, "%i pins at pa %p size %u\n", 1777 dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size);
1781 pcs->desc.npins, pcs->base, pcs->size);
1782 1778
1783 return pinctrl_enable(pcs->pctl); 1779 return pinctrl_enable(pcs->pctl);
1784 1780
diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx150x.c
index fb242c542dc9..cbf58a10113d 100644
--- a/drivers/pinctrl/pinctrl-sx150x.c
+++ b/drivers/pinctrl/pinctrl-sx150x.c
@@ -1144,6 +1144,27 @@ static int sx150x_probe(struct i2c_client *client,
1144 if (ret) 1144 if (ret)
1145 return ret; 1145 return ret;
1146 1146
1147 /* Pinctrl_desc */
1148 pctl->pinctrl_desc.name = "sx150x-pinctrl";
1149 pctl->pinctrl_desc.pctlops = &sx150x_pinctrl_ops;
1150 pctl->pinctrl_desc.confops = &sx150x_pinconf_ops;
1151 pctl->pinctrl_desc.pins = pctl->data->pins;
1152 pctl->pinctrl_desc.npins = pctl->data->npins;
1153 pctl->pinctrl_desc.owner = THIS_MODULE;
1154
1155 ret = devm_pinctrl_register_and_init(dev, &pctl->pinctrl_desc,
1156 pctl, &pctl->pctldev);
1157 if (ret) {
1158 dev_err(dev, "Failed to register pinctrl device\n");
1159 return ret;
1160 }
1161
1162 ret = pinctrl_enable(pctl->pctldev);
1163 if (ret) {
1164 dev_err(dev, "Failed to enable pinctrl device\n");
1165 return ret;
1166 }
1167
1147 /* Register GPIO controller */ 1168 /* Register GPIO controller */
1148 pctl->gpio.label = devm_kstrdup(dev, client->name, GFP_KERNEL); 1169 pctl->gpio.label = devm_kstrdup(dev, client->name, GFP_KERNEL);
1149 pctl->gpio.base = -1; 1170 pctl->gpio.base = -1;
@@ -1172,6 +1193,11 @@ static int sx150x_probe(struct i2c_client *client,
1172 if (ret) 1193 if (ret)
1173 return ret; 1194 return ret;
1174 1195
1196 ret = gpiochip_add_pin_range(&pctl->gpio, dev_name(dev),
1197 0, 0, pctl->data->npins);
1198 if (ret)
1199 return ret;
1200
1175 /* Add Interrupt support if an irq is specified */ 1201 /* Add Interrupt support if an irq is specified */
1176 if (client->irq > 0) { 1202 if (client->irq > 0) {
1177 pctl->irq_chip.name = devm_kstrdup(dev, client->name, 1203 pctl->irq_chip.name = devm_kstrdup(dev, client->name,
@@ -1217,20 +1243,6 @@ static int sx150x_probe(struct i2c_client *client,
1217 client->irq); 1243 client->irq);
1218 } 1244 }
1219 1245
1220 /* Pinctrl_desc */
1221 pctl->pinctrl_desc.name = "sx150x-pinctrl";
1222 pctl->pinctrl_desc.pctlops = &sx150x_pinctrl_ops;
1223 pctl->pinctrl_desc.confops = &sx150x_pinconf_ops;
1224 pctl->pinctrl_desc.pins = pctl->data->pins;
1225 pctl->pinctrl_desc.npins = pctl->data->npins;
1226 pctl->pinctrl_desc.owner = THIS_MODULE;
1227
1228 pctl->pctldev = pinctrl_register(&pctl->pinctrl_desc, dev, pctl);
1229 if (IS_ERR(pctl->pctldev)) {
1230 dev_err(dev, "Failed to register pinctrl device\n");
1231 return PTR_ERR(pctl->pctldev);
1232 }
1233
1234 return 0; 1246 return 0;
1235} 1247}
1236 1248
diff --git a/drivers/pinctrl/pinctrl-tz1090-pdc.c b/drivers/pinctrl/pinctrl-tz1090-pdc.c
index 5cfa93cecf73..b16d1c96b7eb 100644
--- a/drivers/pinctrl/pinctrl-tz1090-pdc.c
+++ b/drivers/pinctrl/pinctrl-tz1090-pdc.c
@@ -357,10 +357,8 @@ static int add_map_configs(struct device *dev,
357 357
358 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), 358 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
359 GFP_KERNEL); 359 GFP_KERNEL);
360 if (!dup_configs) { 360 if (!dup_configs)
361 dev_err(dev, "kmemdup(configs) failed\n");
362 return -ENOMEM; 361 return -ENOMEM;
363 }
364 362
365 /* 363 /*
366 * We support both pins and pin groups, but we need to figure out which 364 * We support both pins and pin groups, but we need to figure out which
@@ -931,10 +929,9 @@ static int tz1090_pdc_pinctrl_probe(struct platform_device *pdev)
931 struct resource *res; 929 struct resource *res;
932 930
933 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); 931 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
934 if (!pmx) { 932 if (!pmx)
935 dev_err(&pdev->dev, "Can't alloc tz1090_pdc_pmx\n");
936 return -ENOMEM; 933 return -ENOMEM;
937 } 934
938 pmx->dev = &pdev->dev; 935 pmx->dev = &pdev->dev;
939 spin_lock_init(&pmx->lock); 936 spin_lock_init(&pmx->lock);
940 937
diff --git a/drivers/pinctrl/pinctrl-tz1090.c b/drivers/pinctrl/pinctrl-tz1090.c
index 74d1ffcc2199..2379ce2be365 100644
--- a/drivers/pinctrl/pinctrl-tz1090.c
+++ b/drivers/pinctrl/pinctrl-tz1090.c
@@ -1082,10 +1082,8 @@ static int add_map_configs(struct device *dev,
1082 1082
1083 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), 1083 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
1084 GFP_KERNEL); 1084 GFP_KERNEL);
1085 if (!dup_configs) { 1085 if (!dup_configs)
1086 dev_err(dev, "kmemdup(configs) failed\n");
1087 return -ENOMEM; 1086 return -ENOMEM;
1088 }
1089 1087
1090 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP; 1088 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
1091 (*map)[*num_maps].data.configs.group_or_pin = group; 1089 (*map)[*num_maps].data.configs.group_or_pin = group;
@@ -1946,10 +1944,9 @@ static int tz1090_pinctrl_probe(struct platform_device *pdev)
1946 struct resource *res; 1944 struct resource *res;
1947 1945
1948 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); 1946 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
1949 if (!pmx) { 1947 if (!pmx)
1950 dev_err(&pdev->dev, "Can't alloc tz1090_pmx\n");
1951 return -ENOMEM; 1948 return -ENOMEM;
1952 } 1949
1953 pmx->dev = &pdev->dev; 1950 pmx->dev = &pdev->dev;
1954 spin_lock_init(&pmx->lock); 1951 spin_lock_init(&pmx->lock);
1955 1952
diff --git a/drivers/pinctrl/pinctrl-utils.c b/drivers/pinctrl/pinctrl-utils.c
index 9189fbafb102..f2bcbf62c03d 100644
--- a/drivers/pinctrl/pinctrl-utils.c
+++ b/drivers/pinctrl/pinctrl-utils.c
@@ -83,10 +83,8 @@ int pinctrl_utils_add_map_configs(struct pinctrl_dev *pctldev,
83 83
84 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), 84 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
85 GFP_KERNEL); 85 GFP_KERNEL);
86 if (!dup_configs) { 86 if (!dup_configs)
87 dev_err(pctldev->dev, "kmemdup(configs) failed\n");
88 return -ENOMEM; 87 return -ENOMEM;
89 }
90 88
91 (*map)[*num_maps].type = type; 89 (*map)[*num_maps].type = type;
92 (*map)[*num_maps].data.configs.group_or_pin = group; 90 (*map)[*num_maps].data.configs.group_or_pin = group;
diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c
index f9e98a7d4f0c..cd0f402c1164 100644
--- a/drivers/pinctrl/pinctrl-xway.c
+++ b/drivers/pinctrl/pinctrl-xway.c
@@ -1730,18 +1730,16 @@ static int pinmux_xway_probe(struct platform_device *pdev)
1730 xway_info.pads = devm_kzalloc(&pdev->dev, 1730 xway_info.pads = devm_kzalloc(&pdev->dev,
1731 sizeof(struct pinctrl_pin_desc) * xway_chip.ngpio, 1731 sizeof(struct pinctrl_pin_desc) * xway_chip.ngpio,
1732 GFP_KERNEL); 1732 GFP_KERNEL);
1733 if (!xway_info.pads) { 1733 if (!xway_info.pads)
1734 dev_err(&pdev->dev, "Failed to allocate pads\n");
1735 return -ENOMEM; 1734 return -ENOMEM;
1736 } 1735
1737 for (i = 0; i < xway_chip.ngpio; i++) { 1736 for (i = 0; i < xway_chip.ngpio; i++) {
1738 /* strlen("ioXY") + 1 = 5 */ 1737 /* strlen("ioXY") + 1 = 5 */
1739 char *name = devm_kzalloc(&pdev->dev, 5, GFP_KERNEL); 1738 char *name = devm_kzalloc(&pdev->dev, 5, GFP_KERNEL);
1740 1739
1741 if (!name) { 1740 if (!name)
1742 dev_err(&pdev->dev, "Failed to allocate pad name\n");
1743 return -ENOMEM; 1741 return -ENOMEM;
1744 } 1742
1745 snprintf(name, 5, "io%d", i); 1743 snprintf(name, 5, "io%d", i);
1746 xway_info.pads[i].number = GPIO0 + i; 1744 xway_info.pads[i].number = GPIO0 + i;
1747 xway_info.pads[i].name = name; 1745 xway_info.pads[i].name = name;
diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c
index 55502fc4479c..b8e9bda8ec98 100644
--- a/drivers/pinctrl/pinmux.c
+++ b/drivers/pinctrl/pinmux.c
@@ -493,8 +493,6 @@ void pinmux_disable_setting(const struct pinctrl_setting *setting)
493 continue; 493 continue;
494 } 494 }
495 if (desc->mux_setting == &(setting->data.mux)) { 495 if (desc->mux_setting == &(setting->data.mux)) {
496 desc->mux_setting = NULL;
497 /* And release the pin */
498 pin_free(pctldev, pins[i], NULL); 496 pin_free(pctldev, pins[i], NULL);
499 } else { 497 } else {
500 const char *gname; 498 const char *gname;
@@ -619,7 +617,7 @@ static int pinmux_pins_show(struct seq_file *s, void *what)
619 pctlops->get_group_name(pctldev, 617 pctlops->get_group_name(pctldev,
620 desc->mux_setting->group)); 618 desc->mux_setting->group));
621 else 619 else
622 seq_printf(s, "\n"); 620 seq_putc(s, '\n');
623 } 621 }
624 622
625 mutex_unlock(&pctldev->mutex); 623 mutex_unlock(&pctldev->mutex);
diff --git a/drivers/pinctrl/pxa/pinctrl-pxa2xx.c b/drivers/pinctrl/pxa/pinctrl-pxa2xx.c
index 866aa3ce1ac9..6cf0006d4c8d 100644
--- a/drivers/pinctrl/pxa/pinctrl-pxa2xx.c
+++ b/drivers/pinctrl/pxa/pinctrl-pxa2xx.c
@@ -436,3 +436,7 @@ int pxa2xx_pinctrl_exit(struct platform_device *pdev)
436 return 0; 436 return 0;
437} 437}
438EXPORT_SYMBOL_GPL(pxa2xx_pinctrl_exit); 438EXPORT_SYMBOL_GPL(pxa2xx_pinctrl_exit);
439
440MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>");
441MODULE_DESCRIPTION("Marvell PXA2xx pinctrl driver");
442MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 9e504dbc7fb5..fcaaa92d76df 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -106,6 +106,14 @@ config PINCTRL_MSM8996
106 This is the pinctrl, pinmux, pinconf and gpiolib driver for the 106 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
107 Qualcomm TLMM block found in the Qualcomm MSM8996 platform. 107 Qualcomm TLMM block found in the Qualcomm MSM8996 platform.
108 108
109config PINCTRL_MSM8998
110 tristate "Qualcomm MSM8998 pin controller driver"
111 depends on GPIOLIB && OF
112 select PINCTRL_MSM
113 help
114 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
115 Qualcomm TLMM block found in the Qualcomm MSM8998 platform.
116
109config PINCTRL_QDF2XXX 117config PINCTRL_QDF2XXX
110 tristate "Qualcomm Technologies QDF2xxx pin controller driver" 118 tristate "Qualcomm Technologies QDF2xxx pin controller driver"
111 depends on GPIOLIB && ACPI 119 depends on GPIOLIB && ACPI
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index a1db345ded1c..8cb45bbd2e7f 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
12obj-$(CONFIG_PINCTRL_MSM8916) += pinctrl-msm8916.o 12obj-$(CONFIG_PINCTRL_MSM8916) += pinctrl-msm8916.o
13obj-$(CONFIG_PINCTRL_MSM8994) += pinctrl-msm8994.o 13obj-$(CONFIG_PINCTRL_MSM8994) += pinctrl-msm8994.o
14obj-$(CONFIG_PINCTRL_MSM8996) += pinctrl-msm8996.o 14obj-$(CONFIG_PINCTRL_MSM8996) += pinctrl-msm8996.o
15obj-$(CONFIG_PINCTRL_MSM8998) += pinctrl-msm8998.o
15obj-$(CONFIG_PINCTRL_QDF2XXX) += pinctrl-qdf2xxx.o 16obj-$(CONFIG_PINCTRL_QDF2XXX) += pinctrl-qdf2xxx.o
16obj-$(CONFIG_PINCTRL_MDM9615) += pinctrl-mdm9615.o 17obj-$(CONFIG_PINCTRL_MDM9615) += pinctrl-mdm9615.o
17obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o 18obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index 7a960590ecaa..495432f3341b 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -898,10 +898,9 @@ int msm_pinctrl_probe(struct platform_device *pdev,
898 int ret; 898 int ret;
899 899
900 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 900 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
901 if (!pctrl) { 901 if (!pctrl)
902 dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n");
903 return -ENOMEM; 902 return -ENOMEM;
904 } 903
905 pctrl->dev = &pdev->dev; 904 pctrl->dev = &pdev->dev;
906 pctrl->soc = soc_data; 905 pctrl->soc = soc_data;
907 pctrl->chip = msm_gpio_template; 906 pctrl->chip = msm_gpio_template;
diff --git a/drivers/pinctrl/qcom/pinctrl-msm8998.c b/drivers/pinctrl/qcom/pinctrl-msm8998.c
new file mode 100644
index 000000000000..c33953183013
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-msm8998.c
@@ -0,0 +1,1590 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/module.h>
7#include <linux/of.h>
8#include <linux/platform_device.h>
9#include <linux/pinctrl/pinctrl.h>
10
11#include "pinctrl-msm.h"
12
13#define NORTH 0x500000
14#define WEST 0x100000
15#define EAST 0x900000
16
17#define FUNCTION(fname) \
18 [msm_mux_##fname] = { \
19 .name = #fname, \
20 .groups = fname##_groups, \
21 .ngroups = ARRAY_SIZE(fname##_groups), \
22 }
23
24#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
25 { \
26 .name = "gpio" #id, \
27 .pins = gpio##id##_pins, \
28 .npins = ARRAY_SIZE(gpio##id##_pins), \
29 .funcs = (int[]){ \
30 msm_mux_gpio, /* gpio mode */ \
31 msm_mux_##f1, \
32 msm_mux_##f2, \
33 msm_mux_##f3, \
34 msm_mux_##f4, \
35 msm_mux_##f5, \
36 msm_mux_##f6, \
37 msm_mux_##f7, \
38 msm_mux_##f8, \
39 msm_mux_##f9 \
40 }, \
41 .nfuncs = 10, \
42 .ctl_reg = base + 0x1000 * id, \
43 .io_reg = base + 0x4 + 0x1000 * id, \
44 .intr_cfg_reg = base + 0x8 + 0x1000 * id, \
45 .intr_status_reg = base + 0xc + 0x1000 * id, \
46 .intr_target_reg = base + 0x8 + 0x1000 * id, \
47 .mux_bit = 2, \
48 .pull_bit = 0, \
49 .drv_bit = 6, \
50 .oe_bit = 9, \
51 .in_bit = 0, \
52 .out_bit = 1, \
53 .intr_enable_bit = 0, \
54 .intr_status_bit = 0, \
55 .intr_target_bit = 5, \
56 .intr_target_kpss_val = 3, \
57 .intr_raw_status_bit = 4, \
58 .intr_polarity_bit = 1, \
59 .intr_detection_bit = 2, \
60 .intr_detection_width = 2, \
61 }
62
63#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
64 { \
65 .name = #pg_name, \
66 .pins = pg_name##_pins, \
67 .npins = ARRAY_SIZE(pg_name##_pins), \
68 .ctl_reg = ctl, \
69 .io_reg = 0, \
70 .intr_cfg_reg = 0, \
71 .intr_status_reg = 0, \
72 .intr_target_reg = 0, \
73 .mux_bit = -1, \
74 .pull_bit = pull, \
75 .drv_bit = drv, \
76 .oe_bit = -1, \
77 .in_bit = -1, \
78 .out_bit = -1, \
79 .intr_enable_bit = -1, \
80 .intr_status_bit = -1, \
81 .intr_target_bit = -1, \
82 .intr_raw_status_bit = -1, \
83 .intr_polarity_bit = -1, \
84 .intr_detection_bit = -1, \
85 .intr_detection_width = -1, \
86 }
87
88#define UFS_RESET(pg_name, offset) \
89 { \
90 .name = #pg_name, \
91 .pins = pg_name##_pins, \
92 .npins = ARRAY_SIZE(pg_name##_pins), \
93 .ctl_reg = offset, \
94 .io_reg = offset + 0x4, \
95 .intr_cfg_reg = 0, \
96 .intr_status_reg = 0, \
97 .intr_target_reg = 0, \
98 .mux_bit = -1, \
99 .pull_bit = 3, \
100 .drv_bit = 0, \
101 .oe_bit = -1, \
102 .in_bit = -1, \
103 .out_bit = 0, \
104 .intr_enable_bit = -1, \
105 .intr_status_bit = -1, \
106 .intr_target_bit = -1, \
107 .intr_raw_status_bit = -1, \
108 .intr_polarity_bit = -1, \
109 .intr_detection_bit = -1, \
110 .intr_detection_width = -1, \
111 }
112
113static const struct pinctrl_pin_desc msm8998_pins[] = {
114 PINCTRL_PIN(0, "GPIO_0"),
115 PINCTRL_PIN(1, "GPIO_1"),
116 PINCTRL_PIN(2, "GPIO_2"),
117 PINCTRL_PIN(3, "GPIO_3"),
118 PINCTRL_PIN(4, "GPIO_4"),
119 PINCTRL_PIN(5, "GPIO_5"),
120 PINCTRL_PIN(6, "GPIO_6"),
121 PINCTRL_PIN(7, "GPIO_7"),
122 PINCTRL_PIN(8, "GPIO_8"),
123 PINCTRL_PIN(9, "GPIO_9"),
124 PINCTRL_PIN(10, "GPIO_10"),
125 PINCTRL_PIN(11, "GPIO_11"),
126 PINCTRL_PIN(12, "GPIO_12"),
127 PINCTRL_PIN(13, "GPIO_13"),
128 PINCTRL_PIN(14, "GPIO_14"),
129 PINCTRL_PIN(15, "GPIO_15"),
130 PINCTRL_PIN(16, "GPIO_16"),
131 PINCTRL_PIN(17, "GPIO_17"),
132 PINCTRL_PIN(18, "GPIO_18"),
133 PINCTRL_PIN(19, "GPIO_19"),
134 PINCTRL_PIN(20, "GPIO_20"),
135 PINCTRL_PIN(21, "GPIO_21"),
136 PINCTRL_PIN(22, "GPIO_22"),
137 PINCTRL_PIN(23, "GPIO_23"),
138 PINCTRL_PIN(24, "GPIO_24"),
139 PINCTRL_PIN(25, "GPIO_25"),
140 PINCTRL_PIN(26, "GPIO_26"),
141 PINCTRL_PIN(27, "GPIO_27"),
142 PINCTRL_PIN(28, "GPIO_28"),
143 PINCTRL_PIN(29, "GPIO_29"),
144 PINCTRL_PIN(30, "GPIO_30"),
145 PINCTRL_PIN(31, "GPIO_31"),
146 PINCTRL_PIN(32, "GPIO_32"),
147 PINCTRL_PIN(33, "GPIO_33"),
148 PINCTRL_PIN(34, "GPIO_34"),
149 PINCTRL_PIN(35, "GPIO_35"),
150 PINCTRL_PIN(36, "GPIO_36"),
151 PINCTRL_PIN(37, "GPIO_37"),
152 PINCTRL_PIN(38, "GPIO_38"),
153 PINCTRL_PIN(39, "GPIO_39"),
154 PINCTRL_PIN(40, "GPIO_40"),
155 PINCTRL_PIN(41, "GPIO_41"),
156 PINCTRL_PIN(42, "GPIO_42"),
157 PINCTRL_PIN(43, "GPIO_43"),
158 PINCTRL_PIN(44, "GPIO_44"),
159 PINCTRL_PIN(45, "GPIO_45"),
160 PINCTRL_PIN(46, "GPIO_46"),
161 PINCTRL_PIN(47, "GPIO_47"),
162 PINCTRL_PIN(48, "GPIO_48"),
163 PINCTRL_PIN(49, "GPIO_49"),
164 PINCTRL_PIN(50, "GPIO_50"),
165 PINCTRL_PIN(51, "GPIO_51"),
166 PINCTRL_PIN(52, "GPIO_52"),
167 PINCTRL_PIN(53, "GPIO_53"),
168 PINCTRL_PIN(54, "GPIO_54"),
169 PINCTRL_PIN(55, "GPIO_55"),
170 PINCTRL_PIN(56, "GPIO_56"),
171 PINCTRL_PIN(57, "GPIO_57"),
172 PINCTRL_PIN(58, "GPIO_58"),
173 PINCTRL_PIN(59, "GPIO_59"),
174 PINCTRL_PIN(60, "GPIO_60"),
175 PINCTRL_PIN(61, "GPIO_61"),
176 PINCTRL_PIN(62, "GPIO_62"),
177 PINCTRL_PIN(63, "GPIO_63"),
178 PINCTRL_PIN(64, "GPIO_64"),
179 PINCTRL_PIN(65, "GPIO_65"),
180 PINCTRL_PIN(66, "GPIO_66"),
181 PINCTRL_PIN(67, "GPIO_67"),
182 PINCTRL_PIN(68, "GPIO_68"),
183 PINCTRL_PIN(69, "GPIO_69"),
184 PINCTRL_PIN(70, "GPIO_70"),
185 PINCTRL_PIN(71, "GPIO_71"),
186 PINCTRL_PIN(72, "GPIO_72"),
187 PINCTRL_PIN(73, "GPIO_73"),
188 PINCTRL_PIN(74, "GPIO_74"),
189 PINCTRL_PIN(75, "GPIO_75"),
190 PINCTRL_PIN(76, "GPIO_76"),
191 PINCTRL_PIN(77, "GPIO_77"),
192 PINCTRL_PIN(78, "GPIO_78"),
193 PINCTRL_PIN(79, "GPIO_79"),
194 PINCTRL_PIN(80, "GPIO_80"),
195 PINCTRL_PIN(81, "GPIO_81"),
196 PINCTRL_PIN(82, "GPIO_82"),
197 PINCTRL_PIN(83, "GPIO_83"),
198 PINCTRL_PIN(84, "GPIO_84"),
199 PINCTRL_PIN(85, "GPIO_85"),
200 PINCTRL_PIN(86, "GPIO_86"),
201 PINCTRL_PIN(87, "GPIO_87"),
202 PINCTRL_PIN(88, "GPIO_88"),
203 PINCTRL_PIN(89, "GPIO_89"),
204 PINCTRL_PIN(90, "GPIO_90"),
205 PINCTRL_PIN(91, "GPIO_91"),
206 PINCTRL_PIN(92, "GPIO_92"),
207 PINCTRL_PIN(93, "GPIO_93"),
208 PINCTRL_PIN(94, "GPIO_94"),
209 PINCTRL_PIN(95, "GPIO_95"),
210 PINCTRL_PIN(96, "GPIO_96"),
211 PINCTRL_PIN(97, "GPIO_97"),
212 PINCTRL_PIN(98, "GPIO_98"),
213 PINCTRL_PIN(99, "GPIO_99"),
214 PINCTRL_PIN(100, "GPIO_100"),
215 PINCTRL_PIN(101, "GPIO_101"),
216 PINCTRL_PIN(102, "GPIO_102"),
217 PINCTRL_PIN(103, "GPIO_103"),
218 PINCTRL_PIN(104, "GPIO_104"),
219 PINCTRL_PIN(105, "GPIO_105"),
220 PINCTRL_PIN(106, "GPIO_106"),
221 PINCTRL_PIN(107, "GPIO_107"),
222 PINCTRL_PIN(108, "GPIO_108"),
223 PINCTRL_PIN(109, "GPIO_109"),
224 PINCTRL_PIN(110, "GPIO_110"),
225 PINCTRL_PIN(111, "GPIO_111"),
226 PINCTRL_PIN(112, "GPIO_112"),
227 PINCTRL_PIN(113, "GPIO_113"),
228 PINCTRL_PIN(114, "GPIO_114"),
229 PINCTRL_PIN(115, "GPIO_115"),
230 PINCTRL_PIN(116, "GPIO_116"),
231 PINCTRL_PIN(117, "GPIO_117"),
232 PINCTRL_PIN(118, "GPIO_118"),
233 PINCTRL_PIN(119, "GPIO_119"),
234 PINCTRL_PIN(120, "GPIO_120"),
235 PINCTRL_PIN(121, "GPIO_121"),
236 PINCTRL_PIN(122, "GPIO_122"),
237 PINCTRL_PIN(123, "GPIO_123"),
238 PINCTRL_PIN(124, "GPIO_124"),
239 PINCTRL_PIN(125, "GPIO_125"),
240 PINCTRL_PIN(126, "GPIO_126"),
241 PINCTRL_PIN(127, "GPIO_127"),
242 PINCTRL_PIN(128, "GPIO_128"),
243 PINCTRL_PIN(129, "GPIO_129"),
244 PINCTRL_PIN(130, "GPIO_130"),
245 PINCTRL_PIN(131, "GPIO_131"),
246 PINCTRL_PIN(132, "GPIO_132"),
247 PINCTRL_PIN(133, "GPIO_133"),
248 PINCTRL_PIN(134, "GPIO_134"),
249 PINCTRL_PIN(135, "GPIO_135"),
250 PINCTRL_PIN(136, "GPIO_136"),
251 PINCTRL_PIN(137, "GPIO_137"),
252 PINCTRL_PIN(138, "GPIO_138"),
253 PINCTRL_PIN(139, "GPIO_139"),
254 PINCTRL_PIN(140, "GPIO_140"),
255 PINCTRL_PIN(141, "GPIO_141"),
256 PINCTRL_PIN(142, "GPIO_142"),
257 PINCTRL_PIN(143, "GPIO_143"),
258 PINCTRL_PIN(144, "GPIO_144"),
259 PINCTRL_PIN(145, "GPIO_145"),
260 PINCTRL_PIN(146, "GPIO_146"),
261 PINCTRL_PIN(147, "GPIO_147"),
262 PINCTRL_PIN(148, "GPIO_148"),
263 PINCTRL_PIN(149, "GPIO_149"),
264 PINCTRL_PIN(150, "SDC2_CLK"),
265 PINCTRL_PIN(151, "SDC2_CMD"),
266 PINCTRL_PIN(152, "SDC2_DATA"),
267 PINCTRL_PIN(153, "UFS_RESET"),
268};
269
270#define DECLARE_MSM_GPIO_PINS(pin) \
271 static const unsigned int gpio##pin##_pins[] = { pin }
272DECLARE_MSM_GPIO_PINS(0);
273DECLARE_MSM_GPIO_PINS(1);
274DECLARE_MSM_GPIO_PINS(2);
275DECLARE_MSM_GPIO_PINS(3);
276DECLARE_MSM_GPIO_PINS(4);
277DECLARE_MSM_GPIO_PINS(5);
278DECLARE_MSM_GPIO_PINS(6);
279DECLARE_MSM_GPIO_PINS(7);
280DECLARE_MSM_GPIO_PINS(8);
281DECLARE_MSM_GPIO_PINS(9);
282DECLARE_MSM_GPIO_PINS(10);
283DECLARE_MSM_GPIO_PINS(11);
284DECLARE_MSM_GPIO_PINS(12);
285DECLARE_MSM_GPIO_PINS(13);
286DECLARE_MSM_GPIO_PINS(14);
287DECLARE_MSM_GPIO_PINS(15);
288DECLARE_MSM_GPIO_PINS(16);
289DECLARE_MSM_GPIO_PINS(17);
290DECLARE_MSM_GPIO_PINS(18);
291DECLARE_MSM_GPIO_PINS(19);
292DECLARE_MSM_GPIO_PINS(20);
293DECLARE_MSM_GPIO_PINS(21);
294DECLARE_MSM_GPIO_PINS(22);
295DECLARE_MSM_GPIO_PINS(23);
296DECLARE_MSM_GPIO_PINS(24);
297DECLARE_MSM_GPIO_PINS(25);
298DECLARE_MSM_GPIO_PINS(26);
299DECLARE_MSM_GPIO_PINS(27);
300DECLARE_MSM_GPIO_PINS(28);
301DECLARE_MSM_GPIO_PINS(29);
302DECLARE_MSM_GPIO_PINS(30);
303DECLARE_MSM_GPIO_PINS(31);
304DECLARE_MSM_GPIO_PINS(32);
305DECLARE_MSM_GPIO_PINS(33);
306DECLARE_MSM_GPIO_PINS(34);
307DECLARE_MSM_GPIO_PINS(35);
308DECLARE_MSM_GPIO_PINS(36);
309DECLARE_MSM_GPIO_PINS(37);
310DECLARE_MSM_GPIO_PINS(38);
311DECLARE_MSM_GPIO_PINS(39);
312DECLARE_MSM_GPIO_PINS(40);
313DECLARE_MSM_GPIO_PINS(41);
314DECLARE_MSM_GPIO_PINS(42);
315DECLARE_MSM_GPIO_PINS(43);
316DECLARE_MSM_GPIO_PINS(44);
317DECLARE_MSM_GPIO_PINS(45);
318DECLARE_MSM_GPIO_PINS(46);
319DECLARE_MSM_GPIO_PINS(47);
320DECLARE_MSM_GPIO_PINS(48);
321DECLARE_MSM_GPIO_PINS(49);
322DECLARE_MSM_GPIO_PINS(50);
323DECLARE_MSM_GPIO_PINS(51);
324DECLARE_MSM_GPIO_PINS(52);
325DECLARE_MSM_GPIO_PINS(53);
326DECLARE_MSM_GPIO_PINS(54);
327DECLARE_MSM_GPIO_PINS(55);
328DECLARE_MSM_GPIO_PINS(56);
329DECLARE_MSM_GPIO_PINS(57);
330DECLARE_MSM_GPIO_PINS(58);
331DECLARE_MSM_GPIO_PINS(59);
332DECLARE_MSM_GPIO_PINS(60);
333DECLARE_MSM_GPIO_PINS(61);
334DECLARE_MSM_GPIO_PINS(62);
335DECLARE_MSM_GPIO_PINS(63);
336DECLARE_MSM_GPIO_PINS(64);
337DECLARE_MSM_GPIO_PINS(65);
338DECLARE_MSM_GPIO_PINS(66);
339DECLARE_MSM_GPIO_PINS(67);
340DECLARE_MSM_GPIO_PINS(68);
341DECLARE_MSM_GPIO_PINS(69);
342DECLARE_MSM_GPIO_PINS(70);
343DECLARE_MSM_GPIO_PINS(71);
344DECLARE_MSM_GPIO_PINS(72);
345DECLARE_MSM_GPIO_PINS(73);
346DECLARE_MSM_GPIO_PINS(74);
347DECLARE_MSM_GPIO_PINS(75);
348DECLARE_MSM_GPIO_PINS(76);
349DECLARE_MSM_GPIO_PINS(77);
350DECLARE_MSM_GPIO_PINS(78);
351DECLARE_MSM_GPIO_PINS(79);
352DECLARE_MSM_GPIO_PINS(80);
353DECLARE_MSM_GPIO_PINS(81);
354DECLARE_MSM_GPIO_PINS(82);
355DECLARE_MSM_GPIO_PINS(83);
356DECLARE_MSM_GPIO_PINS(84);
357DECLARE_MSM_GPIO_PINS(85);
358DECLARE_MSM_GPIO_PINS(86);
359DECLARE_MSM_GPIO_PINS(87);
360DECLARE_MSM_GPIO_PINS(88);
361DECLARE_MSM_GPIO_PINS(89);
362DECLARE_MSM_GPIO_PINS(90);
363DECLARE_MSM_GPIO_PINS(91);
364DECLARE_MSM_GPIO_PINS(92);
365DECLARE_MSM_GPIO_PINS(93);
366DECLARE_MSM_GPIO_PINS(94);
367DECLARE_MSM_GPIO_PINS(95);
368DECLARE_MSM_GPIO_PINS(96);
369DECLARE_MSM_GPIO_PINS(97);
370DECLARE_MSM_GPIO_PINS(98);
371DECLARE_MSM_GPIO_PINS(99);
372DECLARE_MSM_GPIO_PINS(100);
373DECLARE_MSM_GPIO_PINS(101);
374DECLARE_MSM_GPIO_PINS(102);
375DECLARE_MSM_GPIO_PINS(103);
376DECLARE_MSM_GPIO_PINS(104);
377DECLARE_MSM_GPIO_PINS(105);
378DECLARE_MSM_GPIO_PINS(106);
379DECLARE_MSM_GPIO_PINS(107);
380DECLARE_MSM_GPIO_PINS(108);
381DECLARE_MSM_GPIO_PINS(109);
382DECLARE_MSM_GPIO_PINS(110);
383DECLARE_MSM_GPIO_PINS(111);
384DECLARE_MSM_GPIO_PINS(112);
385DECLARE_MSM_GPIO_PINS(113);
386DECLARE_MSM_GPIO_PINS(114);
387DECLARE_MSM_GPIO_PINS(115);
388DECLARE_MSM_GPIO_PINS(116);
389DECLARE_MSM_GPIO_PINS(117);
390DECLARE_MSM_GPIO_PINS(118);
391DECLARE_MSM_GPIO_PINS(119);
392DECLARE_MSM_GPIO_PINS(120);
393DECLARE_MSM_GPIO_PINS(121);
394DECLARE_MSM_GPIO_PINS(122);
395DECLARE_MSM_GPIO_PINS(123);
396DECLARE_MSM_GPIO_PINS(124);
397DECLARE_MSM_GPIO_PINS(125);
398DECLARE_MSM_GPIO_PINS(126);
399DECLARE_MSM_GPIO_PINS(127);
400DECLARE_MSM_GPIO_PINS(128);
401DECLARE_MSM_GPIO_PINS(129);
402DECLARE_MSM_GPIO_PINS(130);
403DECLARE_MSM_GPIO_PINS(131);
404DECLARE_MSM_GPIO_PINS(132);
405DECLARE_MSM_GPIO_PINS(133);
406DECLARE_MSM_GPIO_PINS(134);
407DECLARE_MSM_GPIO_PINS(135);
408DECLARE_MSM_GPIO_PINS(136);
409DECLARE_MSM_GPIO_PINS(137);
410DECLARE_MSM_GPIO_PINS(138);
411DECLARE_MSM_GPIO_PINS(139);
412DECLARE_MSM_GPIO_PINS(140);
413DECLARE_MSM_GPIO_PINS(141);
414DECLARE_MSM_GPIO_PINS(142);
415DECLARE_MSM_GPIO_PINS(143);
416DECLARE_MSM_GPIO_PINS(144);
417DECLARE_MSM_GPIO_PINS(145);
418DECLARE_MSM_GPIO_PINS(146);
419DECLARE_MSM_GPIO_PINS(147);
420DECLARE_MSM_GPIO_PINS(148);
421DECLARE_MSM_GPIO_PINS(149);
422
423static const unsigned int sdc2_clk_pins[] = { 150 };
424static const unsigned int sdc2_cmd_pins[] = { 151 };
425static const unsigned int sdc2_data_pins[] = { 152 };
426static const unsigned int ufs_reset_pins[] = { 153 };
427
428enum msm8998_functions {
429 msm_mux_adsp_ext,
430 msm_mux_agera_pll,
431 msm_mux_atest_char,
432 msm_mux_atest_gpsadc0,
433 msm_mux_atest_gpsadc1,
434 msm_mux_atest_tsens,
435 msm_mux_atest_tsens2,
436 msm_mux_atest_usb1,
437 msm_mux_atest_usb10,
438 msm_mux_atest_usb11,
439 msm_mux_atest_usb12,
440 msm_mux_atest_usb13,
441 msm_mux_audio_ref,
442 msm_mux_bimc_dte0,
443 msm_mux_bimc_dte1,
444 msm_mux_blsp10_spi,
445 msm_mux_blsp10_spi_a,
446 msm_mux_blsp10_spi_b,
447 msm_mux_blsp11_i2c,
448 msm_mux_blsp1_spi,
449 msm_mux_blsp1_spi_a,
450 msm_mux_blsp1_spi_b,
451 msm_mux_blsp2_spi,
452 msm_mux_blsp9_spi,
453 msm_mux_blsp_i2c1,
454 msm_mux_blsp_i2c10,
455 msm_mux_blsp_i2c11,
456 msm_mux_blsp_i2c12,
457 msm_mux_blsp_i2c2,
458 msm_mux_blsp_i2c3,
459 msm_mux_blsp_i2c4,
460 msm_mux_blsp_i2c5,
461 msm_mux_blsp_i2c6,
462 msm_mux_blsp_i2c7,
463 msm_mux_blsp_i2c8,
464 msm_mux_blsp_i2c9,
465 msm_mux_blsp_spi1,
466 msm_mux_blsp_spi10,
467 msm_mux_blsp_spi11,
468 msm_mux_blsp_spi12,
469 msm_mux_blsp_spi2,
470 msm_mux_blsp_spi3,
471 msm_mux_blsp_spi4,
472 msm_mux_blsp_spi5,
473 msm_mux_blsp_spi6,
474 msm_mux_blsp_spi7,
475 msm_mux_blsp_spi8,
476 msm_mux_blsp_spi9,
477 msm_mux_blsp_uart1_a,
478 msm_mux_blsp_uart1_b,
479 msm_mux_blsp_uart2_a,
480 msm_mux_blsp_uart2_b,
481 msm_mux_blsp_uart3_a,
482 msm_mux_blsp_uart3_b,
483 msm_mux_blsp_uart7_a,
484 msm_mux_blsp_uart7_b,
485 msm_mux_blsp_uart8,
486 msm_mux_blsp_uart8_a,
487 msm_mux_blsp_uart8_b,
488 msm_mux_blsp_uart9_a,
489 msm_mux_blsp_uart9_b,
490 msm_mux_blsp_uim1_a,
491 msm_mux_blsp_uim1_b,
492 msm_mux_blsp_uim2_a,
493 msm_mux_blsp_uim2_b,
494 msm_mux_blsp_uim3_a,
495 msm_mux_blsp_uim3_b,
496 msm_mux_blsp_uim7_a,
497 msm_mux_blsp_uim7_b,
498 msm_mux_blsp_uim8_a,
499 msm_mux_blsp_uim8_b,
500 msm_mux_blsp_uim9_a,
501 msm_mux_blsp_uim9_b,
502 msm_mux_bt_reset,
503 msm_mux_btfm_slimbus,
504 msm_mux_cam_mclk,
505 msm_mux_cci_async,
506 msm_mux_cci_i2c,
507 msm_mux_cci_timer0,
508 msm_mux_cci_timer1,
509 msm_mux_cci_timer2,
510 msm_mux_cci_timer3,
511 msm_mux_cci_timer4,
512 msm_mux_cri_trng,
513 msm_mux_cri_trng0,
514 msm_mux_cri_trng1,
515 msm_mux_dbg_out,
516 msm_mux_ddr_bist,
517 msm_mux_edp_hot,
518 msm_mux_edp_lcd,
519 msm_mux_gcc_gp1_a,
520 msm_mux_gcc_gp1_b,
521 msm_mux_gcc_gp2_a,
522 msm_mux_gcc_gp2_b,
523 msm_mux_gcc_gp3_a,
524 msm_mux_gcc_gp3_b,
525 msm_mux_gpio,
526 msm_mux_hdmi_cec,
527 msm_mux_hdmi_ddc,
528 msm_mux_hdmi_hot,
529 msm_mux_hdmi_rcv,
530 msm_mux_isense_dbg,
531 msm_mux_jitter_bist,
532 msm_mux_ldo_en,
533 msm_mux_ldo_update,
534 msm_mux_lpass_slimbus,
535 msm_mux_m_voc,
536 msm_mux_mdp_vsync,
537 msm_mux_mdp_vsync0,
538 msm_mux_mdp_vsync1,
539 msm_mux_mdp_vsync2,
540 msm_mux_mdp_vsync3,
541 msm_mux_mdp_vsync_a,
542 msm_mux_mdp_vsync_b,
543 msm_mux_modem_tsync,
544 msm_mux_mss_lte,
545 msm_mux_nav_dr,
546 msm_mux_nav_pps,
547 msm_mux_pa_indicator,
548 msm_mux_pci_e0,
549 msm_mux_phase_flag,
550 msm_mux_pll_bypassnl,
551 msm_mux_pll_reset,
552 msm_mux_pri_mi2s,
553 msm_mux_pri_mi2s_ws,
554 msm_mux_prng_rosc,
555 msm_mux_pwr_crypto,
556 msm_mux_pwr_modem,
557 msm_mux_pwr_nav,
558 msm_mux_qdss_cti0_a,
559 msm_mux_qdss_cti0_b,
560 msm_mux_qdss_cti1_a,
561 msm_mux_qdss_cti1_b,
562 msm_mux_qdss,
563 msm_mux_qlink_enable,
564 msm_mux_qlink_request,
565 msm_mux_qua_mi2s,
566 msm_mux_sd_card,
567 msm_mux_sd_write,
568 msm_mux_sdc40,
569 msm_mux_sdc41,
570 msm_mux_sdc42,
571 msm_mux_sdc43,
572 msm_mux_sdc4_clk,
573 msm_mux_sdc4_cmd,
574 msm_mux_sec_mi2s,
575 msm_mux_sp_cmu,
576 msm_mux_spkr_i2s,
577 msm_mux_ssbi1,
578 msm_mux_ssc_irq,
579 msm_mux_ter_mi2s,
580 msm_mux_tgu_ch0,
581 msm_mux_tgu_ch1,
582 msm_mux_tsense_pwm1,
583 msm_mux_tsense_pwm2,
584 msm_mux_tsif1_clk,
585 msm_mux_tsif1_data,
586 msm_mux_tsif1_en,
587 msm_mux_tsif1_error,
588 msm_mux_tsif1_sync,
589 msm_mux_tsif2_clk,
590 msm_mux_tsif2_data,
591 msm_mux_tsif2_en,
592 msm_mux_tsif2_error,
593 msm_mux_tsif2_sync,
594 msm_mux_uim1_clk,
595 msm_mux_uim1_data,
596 msm_mux_uim1_present,
597 msm_mux_uim1_reset,
598 msm_mux_uim2_clk,
599 msm_mux_uim2_data,
600 msm_mux_uim2_present,
601 msm_mux_uim2_reset,
602 msm_mux_uim_batt,
603 msm_mux_usb_phy,
604 msm_mux_vfr_1,
605 msm_mux_vsense_clkout,
606 msm_mux_vsense_data0,
607 msm_mux_vsense_data1,
608 msm_mux_vsense_mode,
609 msm_mux_wlan1_adc0,
610 msm_mux_wlan1_adc1,
611 msm_mux_wlan2_adc0,
612 msm_mux_wlan2_adc1,
613 msm_mux__,
614};
615
616static const char * const gpio_groups[] = {
617 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
618 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
619 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
620 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
621 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
622 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
623 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
624 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
625 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
626 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
627 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
628 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
629 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
630 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
631 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
632 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
633 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
634 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
635 "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
636 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
637 "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
638 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
639 "gpio147", "gpio148", "gpio149",
640};
641static const char * const blsp_spi1_groups[] = {
642 "gpio0", "gpio1", "gpio2", "gpio3",
643};
644static const char * const blsp_uim1_a_groups[] = {
645 "gpio0", "gpio1",
646};
647static const char * const blsp_uart1_a_groups[] = {
648 "gpio0", "gpio1", "gpio2", "gpio3",
649};
650static const char * const blsp_i2c1_groups[] = {
651 "gpio2", "gpio3",
652};
653static const char * const blsp_spi8_groups[] = {
654 "gpio4", "gpio5", "gpio6", "gpio7",
655};
656static const char * const blsp_uart8_a_groups[] = {
657 "gpio4", "gpio5", "gpio6", "gpio7",
658};
659static const char * const blsp_uim8_a_groups[] = {
660 "gpio4", "gpio5",
661};
662static const char * const qdss_cti0_b_groups[] = {
663 "gpio4", "gpio5",
664};
665static const char * const blsp_i2c8_groups[] = {
666 "gpio6", "gpio7",
667};
668static const char * const ddr_bist_groups[] = {
669 "gpio7", "gpio8", "gpio9", "gpio10",
670};
671static const char * const atest_tsens2_groups[] = {
672 "gpio7",
673};
674static const char * const atest_usb1_groups[] = {
675 "gpio7",
676};
677static const char * const blsp_spi4_groups[] = {
678 "gpio8", "gpio9", "gpio10", "gpio11",
679};
680static const char * const blsp_uart1_b_groups[] = {
681 "gpio8", "gpio9", "gpio10", "gpio11",
682};
683static const char * const blsp_uim1_b_groups[] = {
684 "gpio8", "gpio9",
685};
686static const char * const wlan1_adc1_groups[] = {
687 "gpio8",
688};
689static const char * const atest_usb13_groups[] = {
690 "gpio8",
691};
692static const char * const bimc_dte1_groups[] = {
693 "gpio8", "gpio10",
694};
695static const char * const tsif1_sync_groups[] = {
696 "gpio9",
697};
698static const char * const wlan1_adc0_groups[] = {
699 "gpio9",
700};
701static const char * const atest_usb12_groups[] = {
702 "gpio9",
703};
704static const char * const bimc_dte0_groups[] = {
705 "gpio9", "gpio11",
706};
707static const char * const mdp_vsync_a_groups[] = {
708 "gpio10", "gpio11",
709};
710static const char * const blsp_i2c4_groups[] = {
711 "gpio10", "gpio11",
712};
713static const char * const atest_gpsadc1_groups[] = {
714 "gpio10",
715};
716static const char * const wlan2_adc1_groups[] = {
717 "gpio10",
718};
719static const char * const atest_usb11_groups[] = {
720 "gpio10",
721};
722static const char * const edp_lcd_groups[] = {
723 "gpio11",
724};
725static const char * const dbg_out_groups[] = {
726 "gpio11",
727};
728static const char * const atest_gpsadc0_groups[] = {
729 "gpio11",
730};
731static const char * const wlan2_adc0_groups[] = {
732 "gpio11",
733};
734static const char * const atest_usb10_groups[] = {
735 "gpio11",
736};
737static const char * const mdp_vsync_groups[] = {
738 "gpio12",
739};
740static const char * const m_voc_groups[] = {
741 "gpio12",
742};
743static const char * const cam_mclk_groups[] = {
744 "gpio13", "gpio14", "gpio15", "gpio16",
745};
746static const char * const pll_bypassnl_groups[] = {
747 "gpio13",
748};
749static const char * const qdss_groups[] = {
750 "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19",
751 "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26",
752 "gpio27", "gpio28", "gpio29", "gpio30", "gpio41", "gpio42", "gpio43",
753 "gpio44", "gpio75", "gpio76", "gpio77", "gpio79", "gpio80", "gpio93",
754 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
755 "gpio123", "gpio124",
756};
757static const char * const pll_reset_groups[] = {
758 "gpio14",
759};
760static const char * const cci_i2c_groups[] = {
761 "gpio17", "gpio18", "gpio19", "gpio20",
762};
763static const char * const phase_flag_groups[] = {
764 "gpio18", "gpio19", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
765 "gpio89", "gpio91", "gpio92", "gpio96", "gpio114", "gpio115",
766 "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121",
767 "gpio122", "gpio123", "gpio124", "gpio125", "gpio126", "gpio128",
768 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
769};
770static const char * const cci_timer4_groups[] = {
771 "gpio25",
772};
773static const char * const blsp2_spi_groups[] = {
774 "gpio25", "gpio29", "gpio30",
775};
776static const char * const cci_timer0_groups[] = {
777 "gpio21",
778};
779static const char * const vsense_data0_groups[] = {
780 "gpio21",
781};
782static const char * const cci_timer1_groups[] = {
783 "gpio22",
784};
785static const char * const vsense_data1_groups[] = {
786 "gpio22",
787};
788static const char * const cci_timer2_groups[] = {
789 "gpio23",
790};
791static const char * const blsp1_spi_b_groups[] = {
792 "gpio23", "gpio28",
793};
794static const char * const vsense_mode_groups[] = {
795 "gpio23",
796};
797static const char * const cci_timer3_groups[] = {
798 "gpio24",
799};
800static const char * const cci_async_groups[] = {
801 "gpio24", "gpio25", "gpio26",
802};
803static const char * const blsp1_spi_a_groups[] = {
804 "gpio24", "gpio27",
805};
806static const char * const vsense_clkout_groups[] = {
807 "gpio24",
808};
809static const char * const hdmi_rcv_groups[] = {
810 "gpio30",
811};
812static const char * const hdmi_cec_groups[] = {
813 "gpio31",
814};
815static const char * const blsp_spi2_groups[] = {
816 "gpio31", "gpio32", "gpio33", "gpio34",
817};
818static const char * const blsp_uart2_a_groups[] = {
819 "gpio31", "gpio32", "gpio33", "gpio34",
820};
821static const char * const blsp_uim2_a_groups[] = {
822 "gpio31", "gpio34",
823};
824static const char * const pwr_modem_groups[] = {
825 "gpio31",
826};
827static const char * const hdmi_ddc_groups[] = {
828 "gpio32", "gpio33",
829};
830static const char * const blsp_i2c2_groups[] = {
831 "gpio32", "gpio33",
832};
833static const char * const pwr_nav_groups[] = {
834 "gpio32",
835};
836static const char * const pwr_crypto_groups[] = {
837 "gpio33",
838};
839static const char * const hdmi_hot_groups[] = {
840 "gpio34",
841};
842static const char * const edp_hot_groups[] = {
843 "gpio34",
844};
845static const char * const pci_e0_groups[] = {
846 "gpio35", "gpio36", "gpio37",
847};
848static const char * const jitter_bist_groups[] = {
849 "gpio35",
850};
851static const char * const agera_pll_groups[] = {
852 "gpio36", "gpio37",
853};
854static const char * const atest_tsens_groups[] = {
855 "gpio36",
856};
857static const char * const usb_phy_groups[] = {
858 "gpio38",
859};
860static const char * const lpass_slimbus_groups[] = {
861 "gpio39", "gpio70", "gpio71", "gpio72",
862};
863static const char * const sd_write_groups[] = {
864 "gpio40",
865};
866static const char * const tsif1_error_groups[] = {
867 "gpio40",
868};
869static const char * const blsp_spi6_groups[] = {
870 "gpio41", "gpio42", "gpio43", "gpio44",
871};
872static const char * const blsp_uart3_b_groups[] = {
873 "gpio41", "gpio42", "gpio43", "gpio44",
874};
875static const char * const blsp_uim3_b_groups[] = {
876 "gpio41", "gpio42",
877};
878static const char * const blsp_i2c6_groups[] = {
879 "gpio43", "gpio44",
880};
881static const char * const bt_reset_groups[] = {
882 "gpio45",
883};
884static const char * const blsp_spi3_groups[] = {
885 "gpio45", "gpio46", "gpio47", "gpio48",
886};
887static const char * const blsp_uart3_a_groups[] = {
888 "gpio45", "gpio46", "gpio47", "gpio48",
889};
890static const char * const blsp_uim3_a_groups[] = {
891 "gpio45", "gpio46",
892};
893static const char * const blsp_i2c3_groups[] = {
894 "gpio47", "gpio48",
895};
896static const char * const blsp_spi9_groups[] = {
897 "gpio49", "gpio50", "gpio51", "gpio52",
898};
899static const char * const blsp_uart9_a_groups[] = {
900 "gpio49", "gpio50", "gpio51", "gpio52",
901};
902static const char * const blsp_uim9_a_groups[] = {
903 "gpio49", "gpio50",
904};
905static const char * const blsp10_spi_b_groups[] = {
906 "gpio49", "gpio50",
907};
908static const char * const qdss_cti0_a_groups[] = {
909 "gpio49", "gpio50",
910};
911static const char * const blsp_i2c9_groups[] = {
912 "gpio51", "gpio52",
913};
914static const char * const blsp10_spi_a_groups[] = {
915 "gpio51", "gpio52",
916};
917static const char * const blsp_spi7_groups[] = {
918 "gpio53", "gpio54", "gpio55", "gpio56",
919};
920static const char * const blsp_uart7_a_groups[] = {
921 "gpio53", "gpio54", "gpio55", "gpio56",
922};
923static const char * const blsp_uim7_a_groups[] = {
924 "gpio53", "gpio54",
925};
926static const char * const blsp_i2c7_groups[] = {
927 "gpio55", "gpio56",
928};
929static const char * const qua_mi2s_groups[] = {
930 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
931};
932static const char * const blsp10_spi_groups[] = {
933 "gpio57",
934};
935static const char * const gcc_gp1_a_groups[] = {
936 "gpio57",
937};
938static const char * const ssc_irq_groups[] = {
939 "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", "gpio78",
940 "gpio79", "gpio80", "gpio117", "gpio118", "gpio119", "gpio120",
941 "gpio121", "gpio122", "gpio123", "gpio124", "gpio125",
942};
943static const char * const blsp_spi11_groups[] = {
944 "gpio58", "gpio59", "gpio60", "gpio61",
945};
946static const char * const blsp_uart8_b_groups[] = {
947 "gpio58", "gpio59", "gpio60", "gpio61",
948};
949static const char * const blsp_uim8_b_groups[] = {
950 "gpio58", "gpio59",
951};
952static const char * const gcc_gp2_a_groups[] = {
953 "gpio58",
954};
955static const char * const qdss_cti1_a_groups[] = {
956 "gpio58", "gpio59",
957};
958static const char * const gcc_gp3_a_groups[] = {
959 "gpio59",
960};
961static const char * const blsp_i2c11_groups[] = {
962 "gpio60", "gpio61",
963};
964static const char * const cri_trng0_groups[] = {
965 "gpio60",
966};
967static const char * const cri_trng1_groups[] = {
968 "gpio61",
969};
970static const char * const cri_trng_groups[] = {
971 "gpio62",
972};
973static const char * const pri_mi2s_groups[] = {
974 "gpio64", "gpio65", "gpio67", "gpio68",
975};
976static const char * const sp_cmu_groups[] = {
977 "gpio64",
978};
979static const char * const blsp_spi10_groups[] = {
980 "gpio65", "gpio66", "gpio67", "gpio68",
981};
982static const char * const blsp_uart7_b_groups[] = {
983 "gpio65", "gpio66", "gpio67", "gpio68",
984};
985static const char * const blsp_uim7_b_groups[] = {
986 "gpio65", "gpio66",
987};
988static const char * const pri_mi2s_ws_groups[] = {
989 "gpio66",
990};
991static const char * const blsp_i2c10_groups[] = {
992 "gpio67", "gpio68",
993};
994static const char * const spkr_i2s_groups[] = {
995 "gpio69", "gpio70", "gpio71", "gpio72",
996};
997static const char * const audio_ref_groups[] = {
998 "gpio69",
999};
1000static const char * const blsp9_spi_groups[] = {
1001 "gpio70", "gpio71", "gpio72",
1002};
1003static const char * const tsense_pwm1_groups[] = {
1004 "gpio71",
1005};
1006static const char * const tsense_pwm2_groups[] = {
1007 "gpio71",
1008};
1009static const char * const btfm_slimbus_groups[] = {
1010 "gpio73", "gpio74",
1011};
1012static const char * const ter_mi2s_groups[] = {
1013 "gpio74", "gpio75", "gpio76", "gpio77", "gpio78",
1014};
1015static const char * const gcc_gp1_b_groups[] = {
1016 "gpio78",
1017};
1018static const char * const sec_mi2s_groups[] = {
1019 "gpio79", "gpio80", "gpio81", "gpio82", "gpio83",
1020};
1021static const char * const blsp_spi12_groups[] = {
1022 "gpio81", "gpio82", "gpio83", "gpio84",
1023};
1024static const char * const blsp_uart9_b_groups[] = {
1025 "gpio81", "gpio82", "gpio83", "gpio84",
1026};
1027static const char * const blsp_uim9_b_groups[] = {
1028 "gpio81", "gpio82",
1029};
1030static const char * const gcc_gp2_b_groups[] = {
1031 "gpio81",
1032};
1033static const char * const gcc_gp3_b_groups[] = {
1034 "gpio82",
1035};
1036static const char * const blsp_i2c12_groups[] = {
1037 "gpio83", "gpio84",
1038};
1039static const char * const blsp_spi5_groups[] = {
1040 "gpio85", "gpio86", "gpio87", "gpio88",
1041};
1042static const char * const blsp_uart2_b_groups[] = {
1043 "gpio85", "gpio86", "gpio87", "gpio88",
1044};
1045static const char * const blsp_uim2_b_groups[] = {
1046 "gpio85", "gpio86",
1047};
1048static const char * const blsp_i2c5_groups[] = {
1049 "gpio87", "gpio88",
1050};
1051static const char * const tsif1_clk_groups[] = {
1052 "gpio89",
1053};
1054static const char * const tsif1_en_groups[] = {
1055 "gpio90",
1056};
1057static const char * const mdp_vsync0_groups[] = {
1058 "gpio90",
1059};
1060static const char * const mdp_vsync1_groups[] = {
1061 "gpio90",
1062};
1063static const char * const mdp_vsync2_groups[] = {
1064 "gpio90",
1065};
1066static const char * const mdp_vsync3_groups[] = {
1067 "gpio90",
1068};
1069static const char * const blsp1_spi_groups[] = {
1070 "gpio90",
1071};
1072static const char * const tgu_ch0_groups[] = {
1073 "gpio90",
1074};
1075static const char * const qdss_cti1_b_groups[] = {
1076 "gpio90", "gpio91",
1077};
1078static const char * const tsif1_data_groups[] = {
1079 "gpio91",
1080};
1081static const char * const sdc4_cmd_groups[] = {
1082 "gpio91",
1083};
1084static const char * const tgu_ch1_groups[] = {
1085 "gpio91",
1086};
1087static const char * const tsif2_error_groups[] = {
1088 "gpio92",
1089};
1090static const char * const sdc43_groups[] = {
1091 "gpio92",
1092};
1093static const char * const vfr_1_groups[] = {
1094 "gpio92",
1095};
1096static const char * const tsif2_clk_groups[] = {
1097 "gpio93",
1098};
1099static const char * const sdc4_clk_groups[] = {
1100 "gpio93",
1101};
1102static const char * const tsif2_en_groups[] = {
1103 "gpio94",
1104};
1105static const char * const sdc42_groups[] = {
1106 "gpio94",
1107};
1108static const char * const sd_card_groups[] = {
1109 "gpio95",
1110};
1111static const char * const tsif2_data_groups[] = {
1112 "gpio95",
1113};
1114static const char * const sdc41_groups[] = {
1115 "gpio95",
1116};
1117static const char * const tsif2_sync_groups[] = {
1118 "gpio96",
1119};
1120static const char * const sdc40_groups[] = {
1121 "gpio96",
1122};
1123static const char * const mdp_vsync_b_groups[] = {
1124 "gpio97", "gpio98",
1125};
1126static const char * const ldo_en_groups[] = {
1127 "gpio97",
1128};
1129static const char * const ldo_update_groups[] = {
1130 "gpio98",
1131};
1132static const char * const blsp_uart8_groups[] = {
1133 "gpio100", "gpio101",
1134};
1135static const char * const blsp11_i2c_groups[] = {
1136 "gpio102", "gpio103",
1137};
1138static const char * const prng_rosc_groups[] = {
1139 "gpio102",
1140};
1141static const char * const uim2_data_groups[] = {
1142 "gpio105",
1143};
1144static const char * const uim2_clk_groups[] = {
1145 "gpio106",
1146};
1147static const char * const uim2_reset_groups[] = {
1148 "gpio107",
1149};
1150static const char * const uim2_present_groups[] = {
1151 "gpio108",
1152};
1153static const char * const uim1_data_groups[] = {
1154 "gpio109",
1155};
1156static const char * const uim1_clk_groups[] = {
1157 "gpio110",
1158};
1159static const char * const uim1_reset_groups[] = {
1160 "gpio111",
1161};
1162static const char * const uim1_present_groups[] = {
1163 "gpio112",
1164};
1165static const char * const uim_batt_groups[] = {
1166 "gpio113",
1167};
1168static const char * const nav_dr_groups[] = {
1169 "gpio115",
1170};
1171static const char * const atest_char_groups[] = {
1172 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121",
1173};
1174static const char * const adsp_ext_groups[] = {
1175 "gpio118",
1176};
1177static const char * const modem_tsync_groups[] = {
1178 "gpio128",
1179};
1180static const char * const nav_pps_groups[] = {
1181 "gpio128",
1182};
1183static const char * const qlink_request_groups[] = {
1184 "gpio130",
1185};
1186static const char * const qlink_enable_groups[] = {
1187 "gpio131",
1188};
1189static const char * const pa_indicator_groups[] = {
1190 "gpio135",
1191};
1192static const char * const ssbi1_groups[] = {
1193 "gpio142",
1194};
1195static const char * const isense_dbg_groups[] = {
1196 "gpio143",
1197};
1198static const char * const mss_lte_groups[] = {
1199 "gpio144", "gpio145",
1200};
1201
1202static const struct msm_function msm8998_functions[] = {
1203 FUNCTION(gpio),
1204 FUNCTION(adsp_ext),
1205 FUNCTION(agera_pll),
1206 FUNCTION(atest_char),
1207 FUNCTION(atest_gpsadc0),
1208 FUNCTION(atest_gpsadc1),
1209 FUNCTION(atest_tsens),
1210 FUNCTION(atest_tsens2),
1211 FUNCTION(atest_usb1),
1212 FUNCTION(atest_usb10),
1213 FUNCTION(atest_usb11),
1214 FUNCTION(atest_usb12),
1215 FUNCTION(atest_usb13),
1216 FUNCTION(audio_ref),
1217 FUNCTION(bimc_dte0),
1218 FUNCTION(bimc_dte1),
1219 FUNCTION(blsp10_spi),
1220 FUNCTION(blsp10_spi_a),
1221 FUNCTION(blsp10_spi_b),
1222 FUNCTION(blsp11_i2c),
1223 FUNCTION(blsp1_spi),
1224 FUNCTION(blsp1_spi_a),
1225 FUNCTION(blsp1_spi_b),
1226 FUNCTION(blsp2_spi),
1227 FUNCTION(blsp9_spi),
1228 FUNCTION(blsp_i2c1),
1229 FUNCTION(blsp_i2c2),
1230 FUNCTION(blsp_i2c3),
1231 FUNCTION(blsp_i2c4),
1232 FUNCTION(blsp_i2c5),
1233 FUNCTION(blsp_i2c6),
1234 FUNCTION(blsp_i2c7),
1235 FUNCTION(blsp_i2c8),
1236 FUNCTION(blsp_i2c9),
1237 FUNCTION(blsp_i2c10),
1238 FUNCTION(blsp_i2c11),
1239 FUNCTION(blsp_i2c12),
1240 FUNCTION(blsp_spi1),
1241 FUNCTION(blsp_spi2),
1242 FUNCTION(blsp_spi3),
1243 FUNCTION(blsp_spi4),
1244 FUNCTION(blsp_spi5),
1245 FUNCTION(blsp_spi6),
1246 FUNCTION(blsp_spi7),
1247 FUNCTION(blsp_spi8),
1248 FUNCTION(blsp_spi9),
1249 FUNCTION(blsp_spi10),
1250 FUNCTION(blsp_spi11),
1251 FUNCTION(blsp_spi12),
1252 FUNCTION(blsp_uart1_a),
1253 FUNCTION(blsp_uart1_b),
1254 FUNCTION(blsp_uart2_a),
1255 FUNCTION(blsp_uart2_b),
1256 FUNCTION(blsp_uart3_a),
1257 FUNCTION(blsp_uart3_b),
1258 FUNCTION(blsp_uart7_a),
1259 FUNCTION(blsp_uart7_b),
1260 FUNCTION(blsp_uart8),
1261 FUNCTION(blsp_uart8_a),
1262 FUNCTION(blsp_uart8_b),
1263 FUNCTION(blsp_uart9_a),
1264 FUNCTION(blsp_uart9_b),
1265 FUNCTION(blsp_uim1_a),
1266 FUNCTION(blsp_uim1_b),
1267 FUNCTION(blsp_uim2_a),
1268 FUNCTION(blsp_uim2_b),
1269 FUNCTION(blsp_uim3_a),
1270 FUNCTION(blsp_uim3_b),
1271 FUNCTION(blsp_uim7_a),
1272 FUNCTION(blsp_uim7_b),
1273 FUNCTION(blsp_uim8_a),
1274 FUNCTION(blsp_uim8_b),
1275 FUNCTION(blsp_uim9_a),
1276 FUNCTION(blsp_uim9_b),
1277 FUNCTION(bt_reset),
1278 FUNCTION(btfm_slimbus),
1279 FUNCTION(cam_mclk),
1280 FUNCTION(cci_async),
1281 FUNCTION(cci_i2c),
1282 FUNCTION(cci_timer0),
1283 FUNCTION(cci_timer1),
1284 FUNCTION(cci_timer2),
1285 FUNCTION(cci_timer3),
1286 FUNCTION(cci_timer4),
1287 FUNCTION(cri_trng),
1288 FUNCTION(cri_trng0),
1289 FUNCTION(cri_trng1),
1290 FUNCTION(dbg_out),
1291 FUNCTION(ddr_bist),
1292 FUNCTION(edp_hot),
1293 FUNCTION(edp_lcd),
1294 FUNCTION(gcc_gp1_a),
1295 FUNCTION(gcc_gp1_b),
1296 FUNCTION(gcc_gp2_a),
1297 FUNCTION(gcc_gp2_b),
1298 FUNCTION(gcc_gp3_a),
1299 FUNCTION(gcc_gp3_b),
1300 FUNCTION(hdmi_cec),
1301 FUNCTION(hdmi_ddc),
1302 FUNCTION(hdmi_hot),
1303 FUNCTION(hdmi_rcv),
1304 FUNCTION(isense_dbg),
1305 FUNCTION(jitter_bist),
1306 FUNCTION(ldo_en),
1307 FUNCTION(ldo_update),
1308 FUNCTION(lpass_slimbus),
1309 FUNCTION(m_voc),
1310 FUNCTION(mdp_vsync),
1311 FUNCTION(mdp_vsync0),
1312 FUNCTION(mdp_vsync1),
1313 FUNCTION(mdp_vsync2),
1314 FUNCTION(mdp_vsync3),
1315 FUNCTION(mdp_vsync_a),
1316 FUNCTION(mdp_vsync_b),
1317 FUNCTION(modem_tsync),
1318 FUNCTION(mss_lte),
1319 FUNCTION(nav_dr),
1320 FUNCTION(nav_pps),
1321 FUNCTION(pa_indicator),
1322 FUNCTION(pci_e0),
1323 FUNCTION(phase_flag),
1324 FUNCTION(pll_bypassnl),
1325 FUNCTION(pll_reset),
1326 FUNCTION(pri_mi2s),
1327 FUNCTION(pri_mi2s_ws),
1328 FUNCTION(prng_rosc),
1329 FUNCTION(pwr_crypto),
1330 FUNCTION(pwr_modem),
1331 FUNCTION(pwr_nav),
1332 FUNCTION(qdss_cti0_a),
1333 FUNCTION(qdss_cti0_b),
1334 FUNCTION(qdss_cti1_a),
1335 FUNCTION(qdss_cti1_b),
1336 FUNCTION(qdss),
1337 FUNCTION(qlink_enable),
1338 FUNCTION(qlink_request),
1339 FUNCTION(qua_mi2s),
1340 FUNCTION(sd_card),
1341 FUNCTION(sd_write),
1342 FUNCTION(sdc40),
1343 FUNCTION(sdc41),
1344 FUNCTION(sdc42),
1345 FUNCTION(sdc43),
1346 FUNCTION(sdc4_clk),
1347 FUNCTION(sdc4_cmd),
1348 FUNCTION(sec_mi2s),
1349 FUNCTION(sp_cmu),
1350 FUNCTION(spkr_i2s),
1351 FUNCTION(ssbi1),
1352 FUNCTION(ssc_irq),
1353 FUNCTION(ter_mi2s),
1354 FUNCTION(tgu_ch0),
1355 FUNCTION(tgu_ch1),
1356 FUNCTION(tsense_pwm1),
1357 FUNCTION(tsense_pwm2),
1358 FUNCTION(tsif1_clk),
1359 FUNCTION(tsif1_data),
1360 FUNCTION(tsif1_en),
1361 FUNCTION(tsif1_error),
1362 FUNCTION(tsif1_sync),
1363 FUNCTION(tsif2_clk),
1364 FUNCTION(tsif2_data),
1365 FUNCTION(tsif2_en),
1366 FUNCTION(tsif2_error),
1367 FUNCTION(tsif2_sync),
1368 FUNCTION(uim1_clk),
1369 FUNCTION(uim1_data),
1370 FUNCTION(uim1_present),
1371 FUNCTION(uim1_reset),
1372 FUNCTION(uim2_clk),
1373 FUNCTION(uim2_data),
1374 FUNCTION(uim2_present),
1375 FUNCTION(uim2_reset),
1376 FUNCTION(uim_batt),
1377 FUNCTION(usb_phy),
1378 FUNCTION(vfr_1),
1379 FUNCTION(vsense_clkout),
1380 FUNCTION(vsense_data0),
1381 FUNCTION(vsense_data1),
1382 FUNCTION(vsense_mode),
1383 FUNCTION(wlan1_adc0),
1384 FUNCTION(wlan1_adc1),
1385 FUNCTION(wlan2_adc0),
1386 FUNCTION(wlan2_adc1),
1387};
1388
1389static const struct msm_pingroup msm8998_groups[] = {
1390 PINGROUP(0, EAST, blsp_spi1, blsp_uart1_a, blsp_uim1_a, _, _, _, _, _, _),
1391 PINGROUP(1, EAST, blsp_spi1, blsp_uart1_a, blsp_uim1_a, _, _, _, _, _, _),
1392 PINGROUP(2, EAST, blsp_spi1, blsp_uart1_a, blsp_i2c1, _, _, _, _, _, _),
1393 PINGROUP(3, EAST, blsp_spi1, blsp_uart1_a, blsp_i2c1, _, _, _, _, _, _),
1394 PINGROUP(4, WEST, blsp_spi8, blsp_uart8_a, blsp_uim8_a, _, qdss_cti0_b, _, _, _, _),
1395 PINGROUP(5, WEST, blsp_spi8, blsp_uart8_a, blsp_uim8_a, _, qdss_cti0_b, _, _, _, _),
1396 PINGROUP(6, WEST, blsp_spi8, blsp_uart8_a, blsp_i2c8, _, _, _, _, _, _),
1397 PINGROUP(7, WEST, blsp_spi8, blsp_uart8_a, blsp_i2c8, ddr_bist, _, atest_tsens2, atest_usb1, _, _),
1398 PINGROUP(8, EAST, blsp_spi4, blsp_uart1_b, blsp_uim1_b, _, ddr_bist, _, wlan1_adc1, atest_usb13, bimc_dte1),
1399 PINGROUP(9, EAST, blsp_spi4, blsp_uart1_b, blsp_uim1_b, tsif1_sync, ddr_bist, _, wlan1_adc0, atest_usb12, bimc_dte0),
1400 PINGROUP(10, EAST, mdp_vsync_a, blsp_spi4, blsp_uart1_b, blsp_i2c4, ddr_bist, atest_gpsadc1, wlan2_adc1, atest_usb11, bimc_dte1),
1401 PINGROUP(11, EAST, mdp_vsync_a, edp_lcd, blsp_spi4, blsp_uart1_b, blsp_i2c4, dbg_out, atest_gpsadc0, wlan2_adc0, atest_usb10),
1402 PINGROUP(12, EAST, mdp_vsync, m_voc, _, _, _, _, _, _, _),
1403 PINGROUP(13, EAST, cam_mclk, pll_bypassnl, qdss, _, _, _, _, _, _),
1404 PINGROUP(14, EAST, cam_mclk, pll_reset, qdss, _, _, _, _, _, _),
1405 PINGROUP(15, EAST, cam_mclk, qdss, _, _, _, _, _, _, _),
1406 PINGROUP(16, EAST, cam_mclk, qdss, _, _, _, _, _, _, _),
1407 PINGROUP(17, EAST, cci_i2c, qdss, _, _, _, _, _, _, _),
1408 PINGROUP(18, EAST, cci_i2c, phase_flag, qdss, _, _, _, _, _, _),
1409 PINGROUP(19, EAST, cci_i2c, phase_flag, qdss, _, _, _, _, _, _),
1410 PINGROUP(20, EAST, cci_i2c, qdss, _, _, _, _, _, _, _),
1411 PINGROUP(21, EAST, cci_timer0, _, qdss, vsense_data0, _, _, _, _, _),
1412 PINGROUP(22, EAST, cci_timer1, _, qdss, vsense_data1, _, _, _, _, _),
1413 PINGROUP(23, EAST, cci_timer2, blsp1_spi_b, qdss, vsense_mode, _, _, _, _, _),
1414 PINGROUP(24, EAST, cci_timer3, cci_async, blsp1_spi_a, _, qdss, vsense_clkout, _, _, _),
1415 PINGROUP(25, EAST, cci_timer4, cci_async, blsp2_spi, _, qdss, _, _, _, _),
1416 PINGROUP(26, EAST, cci_async, qdss, _, _, _, _, _, _, _),
1417 PINGROUP(27, EAST, blsp1_spi_a, qdss, _, _, _, _, _, _, _),
1418 PINGROUP(28, EAST, blsp1_spi_b, qdss, _, _, _, _, _, _, _),
1419 PINGROUP(29, EAST, blsp2_spi, _, qdss, _, _, _, _, _, _),
1420 PINGROUP(30, EAST, hdmi_rcv, blsp2_spi, qdss, _, _, _, _, _, _),
1421 PINGROUP(31, EAST, hdmi_cec, blsp_spi2, blsp_uart2_a, blsp_uim2_a, pwr_modem, _, _, _, _),
1422 PINGROUP(32, EAST, hdmi_ddc, blsp_spi2, blsp_uart2_a, blsp_i2c2, pwr_nav, _, _, _, _),
1423 PINGROUP(33, EAST, hdmi_ddc, blsp_spi2, blsp_uart2_a, blsp_i2c2, pwr_crypto, _, _, _, _),
1424 PINGROUP(34, EAST, hdmi_hot, edp_hot, blsp_spi2, blsp_uart2_a, blsp_uim2_a, _, _, _, _),
1425 PINGROUP(35, NORTH, pci_e0, jitter_bist, _, _, _, _, _, _, _),
1426 PINGROUP(36, NORTH, pci_e0, agera_pll, _, atest_tsens, _, _, _, _, _),
1427 PINGROUP(37, NORTH, agera_pll, _, _, _, _, _, _, _, _),
1428 PINGROUP(38, WEST, usb_phy, _, _, _, _, _, _, _, _),
1429 PINGROUP(39, WEST, lpass_slimbus, _, _, _, _, _, _, _, _),
1430 PINGROUP(40, EAST, sd_write, tsif1_error, _, _, _, _, _, _, _),
1431 PINGROUP(41, EAST, blsp_spi6, blsp_uart3_b, blsp_uim3_b, _, qdss, _, _, _, _),
1432 PINGROUP(42, EAST, blsp_spi6, blsp_uart3_b, blsp_uim3_b, _, qdss, _, _, _, _),
1433 PINGROUP(43, EAST, blsp_spi6, blsp_uart3_b, blsp_i2c6, _, qdss, _, _, _, _),
1434 PINGROUP(44, EAST, blsp_spi6, blsp_uart3_b, blsp_i2c6, _, qdss, _, _, _, _),
1435 PINGROUP(45, EAST, blsp_spi3, blsp_uart3_a, blsp_uim3_a, _, _, _, _, _, _),
1436 PINGROUP(46, EAST, blsp_spi3, blsp_uart3_a, blsp_uim3_a, _, _, _, _, _, _),
1437 PINGROUP(47, EAST, blsp_spi3, blsp_uart3_a, blsp_i2c3, _, _, _, _, _, _),
1438 PINGROUP(48, EAST, blsp_spi3, blsp_uart3_a, blsp_i2c3, _, _, _, _, _, _),
1439 PINGROUP(49, NORTH, blsp_spi9, blsp_uart9_a, blsp_uim9_a, blsp10_spi_b, qdss_cti0_a, _, _, _, _),
1440 PINGROUP(50, NORTH, blsp_spi9, blsp_uart9_a, blsp_uim9_a, blsp10_spi_b, qdss_cti0_a, _, _, _, _),
1441 PINGROUP(51, NORTH, blsp_spi9, blsp_uart9_a, blsp_i2c9, blsp10_spi_a, _, _, _, _, _),
1442 PINGROUP(52, NORTH, blsp_spi9, blsp_uart9_a, blsp_i2c9, blsp10_spi_a, _, _, _, _, _),
1443 PINGROUP(53, WEST, blsp_spi7, blsp_uart7_a, blsp_uim7_a, _, _, _, _, _, _),
1444 PINGROUP(54, WEST, blsp_spi7, blsp_uart7_a, blsp_uim7_a, _, _, _, _, _, _),
1445 PINGROUP(55, WEST, blsp_spi7, blsp_uart7_a, blsp_i2c7, _, _, _, _, _, _),
1446 PINGROUP(56, WEST, blsp_spi7, blsp_uart7_a, blsp_i2c7, _, _, _, _, _, _),
1447 PINGROUP(57, WEST, qua_mi2s, blsp10_spi, gcc_gp1_a, _, _, _, _, _, _),
1448 PINGROUP(58, WEST, qua_mi2s, blsp_spi11, blsp_uart8_b, blsp_uim8_b, gcc_gp2_a, _, qdss_cti1_a, _, _),
1449 PINGROUP(59, WEST, qua_mi2s, blsp_spi11, blsp_uart8_b, blsp_uim8_b, gcc_gp3_a, _, qdss_cti1_a, _, _),
1450 PINGROUP(60, WEST, qua_mi2s, blsp_spi11, blsp_uart8_b, blsp_i2c11, cri_trng0, _, _, _, _),
1451 PINGROUP(61, WEST, qua_mi2s, blsp_spi11, blsp_uart8_b, blsp_i2c11, cri_trng1, _, _, _, _),
1452 PINGROUP(62, WEST, qua_mi2s, cri_trng, _, _, _, _, _, _, _),
1453 PINGROUP(63, WEST, qua_mi2s, _, _, _, _, _, _, _, _),
1454 PINGROUP(64, WEST, pri_mi2s, sp_cmu, _, _, _, _, _, _, _),
1455 PINGROUP(65, WEST, pri_mi2s, blsp_spi10, blsp_uart7_b, blsp_uim7_b, _, _, _, _, _),
1456 PINGROUP(66, WEST, pri_mi2s_ws, blsp_spi10, blsp_uart7_b, blsp_uim7_b, _, _, _, _, _),
1457 PINGROUP(67, WEST, pri_mi2s, blsp_spi10, blsp_uart7_b, blsp_i2c10, _, _, _, _, _),
1458 PINGROUP(68, WEST, pri_mi2s, blsp_spi10, blsp_uart7_b, blsp_i2c10, _, _, _, _, _),
1459 PINGROUP(69, WEST, spkr_i2s, audio_ref, _, _, _, _, _, _, _),
1460 PINGROUP(70, WEST, lpass_slimbus, spkr_i2s, blsp9_spi, _, _, _, _, _, _),
1461 PINGROUP(71, WEST, lpass_slimbus, spkr_i2s, blsp9_spi, tsense_pwm1, tsense_pwm2, _, _, _, _),
1462 PINGROUP(72, WEST, lpass_slimbus, spkr_i2s, blsp9_spi, _, _, _, _, _, _),
1463 PINGROUP(73, WEST, btfm_slimbus, phase_flag, _, _, _, _, _, _, _),
1464 PINGROUP(74, WEST, btfm_slimbus, ter_mi2s, phase_flag, _, _, _, _, _, _),
1465 PINGROUP(75, WEST, ter_mi2s, phase_flag, qdss, _, _, _, _, _, _),
1466 PINGROUP(76, WEST, ter_mi2s, phase_flag, qdss, _, _, _, _, _, _),
1467 PINGROUP(77, WEST, ter_mi2s, phase_flag, qdss, _, _, _, _, _, _),
1468 PINGROUP(78, WEST, ter_mi2s, gcc_gp1_b, _, _, _, _, _, _, _),
1469 PINGROUP(79, WEST, sec_mi2s, _, qdss, _, _, _, _, _, _),
1470 PINGROUP(80, WEST, sec_mi2s, _, qdss, _, _, _, _, _, _),
1471 PINGROUP(81, WEST, sec_mi2s, blsp_spi12, blsp_uart9_b, blsp_uim9_b, gcc_gp2_b, _, _, _, _),
1472 PINGROUP(82, WEST, sec_mi2s, blsp_spi12, blsp_uart9_b, blsp_uim9_b, gcc_gp3_b, _, _, _, _),
1473 PINGROUP(83, WEST, sec_mi2s, blsp_spi12, blsp_uart9_b, blsp_i2c12, _, _, _, _, _),
1474 PINGROUP(84, WEST, blsp_spi12, blsp_uart9_b, blsp_i2c12, _, _, _, _, _, _),
1475 PINGROUP(85, EAST, blsp_spi5, blsp_uart2_b, blsp_uim2_b, _, _, _, _, _, _),
1476 PINGROUP(86, EAST, blsp_spi5, blsp_uart2_b, blsp_uim2_b, _, _, _, _, _, _),
1477 PINGROUP(87, EAST, blsp_spi5, blsp_uart2_b, blsp_i2c5, _, _, _, _, _, _),
1478 PINGROUP(88, EAST, blsp_spi5, blsp_uart2_b, blsp_i2c5, _, _, _, _, _, _),
1479 PINGROUP(89, EAST, tsif1_clk, phase_flag, _, _, _, _, _, _, _),
1480 PINGROUP(90, EAST, tsif1_en, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, blsp1_spi, tgu_ch0, qdss_cti1_b, _),
1481 PINGROUP(91, EAST, tsif1_data, sdc4_cmd, tgu_ch1, phase_flag, qdss_cti1_b, _, _, _, _),
1482 PINGROUP(92, EAST, tsif2_error, sdc43, vfr_1, phase_flag, _, _, _, _, _),
1483 PINGROUP(93, EAST, tsif2_clk, sdc4_clk, _, qdss, _, _, _, _, _),
1484 PINGROUP(94, EAST, tsif2_en, sdc42, _, _, _, _, _, _, _),
1485 PINGROUP(95, EAST, tsif2_data, sdc41, _, _, _, _, _, _, _),
1486 PINGROUP(96, EAST, tsif2_sync, sdc40, phase_flag, _, _, _, _, _, _),
1487 PINGROUP(97, WEST, _, mdp_vsync_b, ldo_en, _, _, _, _, _, _),
1488 PINGROUP(98, WEST, _, mdp_vsync_b, ldo_update, _, _, _, _, _, _),
1489 PINGROUP(99, WEST, _, _, _, _, _, _, _, _, _),
1490 PINGROUP(100, WEST, _, _, blsp_uart8, _, _, _, _, _, _),
1491 PINGROUP(101, WEST, _, blsp_uart8, _, _, _, _, _, _, _),
1492 PINGROUP(102, WEST, _, blsp11_i2c, prng_rosc, _, _, _, _, _, _),
1493 PINGROUP(103, WEST, _, blsp11_i2c, phase_flag, _, _, _, _, _, _),
1494 PINGROUP(104, WEST, _, _, _, _, _, _, _, _, _),
1495 PINGROUP(105, NORTH, uim2_data, _, _, _, _, _, _, _, _),
1496 PINGROUP(106, NORTH, uim2_clk, _, _, _, _, _, _, _, _),
1497 PINGROUP(107, NORTH, uim2_reset, _, _, _, _, _, _, _, _),
1498 PINGROUP(108, NORTH, uim2_present, _, _, _, _, _, _, _, _),
1499 PINGROUP(109, NORTH, uim1_data, _, _, _, _, _, _, _, _),
1500 PINGROUP(110, NORTH, uim1_clk, _, _, _, _, _, _, _, _),
1501 PINGROUP(111, NORTH, uim1_reset, _, _, _, _, _, _, _, _),
1502 PINGROUP(112, NORTH, uim1_present, _, _, _, _, _, _, _, _),
1503 PINGROUP(113, NORTH, uim_batt, _, _, _, _, _, _, _, _),
1504 PINGROUP(114, WEST, _, _, phase_flag, _, _, _, _, _, _),
1505 PINGROUP(115, WEST, _, nav_dr, phase_flag, _, _, _, _, _, _),
1506 PINGROUP(116, WEST, phase_flag, _, _, _, _, _, _, _, _),
1507 PINGROUP(117, EAST, phase_flag, qdss, atest_char, _, _, _, _, _, _),
1508 PINGROUP(118, EAST, adsp_ext, phase_flag, qdss, atest_char, _, _, _, _, _),
1509 PINGROUP(119, EAST, phase_flag, qdss, atest_char, _, _, _, _, _, _),
1510 PINGROUP(120, EAST, phase_flag, qdss, atest_char, _, _, _, _, _, _),
1511 PINGROUP(121, EAST, phase_flag, qdss, atest_char, _, _, _, _, _, _),
1512 PINGROUP(122, EAST, phase_flag, qdss, _, _, _, _, _, _, _),
1513 PINGROUP(123, EAST, phase_flag, qdss, _, _, _, _, _, _, _),
1514 PINGROUP(124, EAST, phase_flag, qdss, _, _, _, _, _, _, _),
1515 PINGROUP(125, EAST, phase_flag, _, _, _, _, _, _, _, _),
1516 PINGROUP(126, EAST, phase_flag, _, _, _, _, _, _, _, _),
1517 PINGROUP(127, WEST, _, _, _, _, _, _, _, _, _),
1518 PINGROUP(128, WEST, modem_tsync, nav_pps, phase_flag, _, _, _, _, _, _),
1519 PINGROUP(129, WEST, phase_flag, _, _, _, _, _, _, _, _),
1520 PINGROUP(130, NORTH, qlink_request, phase_flag, _, _, _, _, _, _, _),
1521 PINGROUP(131, NORTH, qlink_enable, phase_flag, _, _, _, _, _, _, _),
1522 PINGROUP(132, WEST, _, phase_flag, _, _, _, _, _, _, _),
1523 PINGROUP(133, WEST, phase_flag, _, _, _, _, _, _, _, _),
1524 PINGROUP(134, WEST, phase_flag, _, _, _, _, _, _, _, _),
1525 PINGROUP(135, WEST, _, pa_indicator, _, _, _, _, _, _, _),
1526 PINGROUP(136, WEST, _, _, _, _, _, _, _, _, _),
1527 PINGROUP(137, WEST, _, _, _, _, _, _, _, _, _),
1528 PINGROUP(138, WEST, _, _, _, _, _, _, _, _, _),
1529 PINGROUP(139, WEST, _, _, _, _, _, _, _, _, _),
1530 PINGROUP(140, WEST, _, _, _, _, _, _, _, _, _),
1531 PINGROUP(141, WEST, _, _, _, _, _, _, _, _, _),
1532 PINGROUP(142, WEST, _, ssbi1, _, _, _, _, _, _, _),
1533 PINGROUP(143, WEST, isense_dbg, _, _, _, _, _, _, _, _),
1534 PINGROUP(144, WEST, mss_lte, _, _, _, _, _, _, _, _),
1535 PINGROUP(145, WEST, mss_lte, _, _, _, _, _, _, _, _),
1536 PINGROUP(146, WEST, _, _, _, _, _, _, _, _, _),
1537 PINGROUP(147, WEST, _, _, _, _, _, _, _, _, _),
1538 PINGROUP(148, WEST, _, _, _, _, _, _, _, _, _),
1539 PINGROUP(149, WEST, _, _, _, _, _, _, _, _, _),
1540 SDC_QDSD_PINGROUP(sdc2_clk, 0x999000, 14, 6),
1541 SDC_QDSD_PINGROUP(sdc2_cmd, 0x999000, 11, 3),
1542 SDC_QDSD_PINGROUP(sdc2_data, 0x999000, 9, 0),
1543 UFS_RESET(ufs_reset, 0x19d000),
1544};
1545
1546static const struct msm_pinctrl_soc_data msm8998_pinctrl = {
1547 .pins = msm8998_pins,
1548 .npins = ARRAY_SIZE(msm8998_pins),
1549 .functions = msm8998_functions,
1550 .nfunctions = ARRAY_SIZE(msm8998_functions),
1551 .groups = msm8998_groups,
1552 .ngroups = ARRAY_SIZE(msm8998_groups),
1553 .ngpios = 150,
1554};
1555
1556static int msm8998_pinctrl_probe(struct platform_device *pdev)
1557{
1558 return msm_pinctrl_probe(pdev, &msm8998_pinctrl);
1559}
1560
1561static const struct of_device_id msm8998_pinctrl_of_match[] = {
1562 { .compatible = "qcom,msm8998-pinctrl", },
1563 { },
1564};
1565
1566static struct platform_driver msm8998_pinctrl_driver = {
1567 .driver = {
1568 .name = "msm8998-pinctrl",
1569 .owner = THIS_MODULE,
1570 .of_match_table = msm8998_pinctrl_of_match,
1571 },
1572 .probe = msm8998_pinctrl_probe,
1573 .remove = msm_pinctrl_remove,
1574};
1575
1576static int __init msm8998_pinctrl_init(void)
1577{
1578 return platform_driver_register(&msm8998_pinctrl_driver);
1579}
1580arch_initcall(msm8998_pinctrl_init);
1581
1582static void __exit msm8998_pinctrl_exit(void)
1583{
1584 platform_driver_unregister(&msm8998_pinctrl_driver);
1585}
1586module_exit(msm8998_pinctrl_exit);
1587
1588MODULE_DESCRIPTION("QTI msm8998 pinctrl driver");
1589MODULE_LICENSE("GPL v2");
1590MODULE_DEVICE_TABLE(of, msm8998_pinctrl_of_match);
diff --git a/drivers/pinctrl/samsung/Kconfig b/drivers/pinctrl/samsung/Kconfig
index ecfb90059eeb..11b5eeb14c4a 100644
--- a/drivers/pinctrl/samsung/Kconfig
+++ b/drivers/pinctrl/samsung/Kconfig
@@ -1,3 +1,4 @@
1# SPDX-License-Identifier: GPL-2.0
1# 2#
2# Samsung Pin control drivers 3# Samsung Pin control drivers
3# 4#
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm.c
index 071084d3ee9c..c32399faff57 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos-arm.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm.c
@@ -1,22 +1,17 @@
1/* 1// SPDX-License-Identifier: GPL-2.0+
2 * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support. 2//
3 * 3// Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 4//
5 * http://www.samsung.com 5// Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 * Copyright (c) 2012 Linaro Ltd 6// http://www.samsung.com
7 * http://www.linaro.org 7// Copyright (c) 2012 Linaro Ltd
8 * 8// http://www.linaro.org
9 * Author: Thomas Abraham <thomas.ab@samsung.com> 9//
10 * 10// Author: Thomas Abraham <thomas.ab@samsung.com>
11 * This program is free software; you can redistribute it and/or modify 11//
12 * it under the terms of the GNU General Public License as published by 12// This file contains the Samsung Exynos specific information required by the
13 * the Free Software Foundation; either version 2 of the License, or 13// the Samsung pinctrl/gpiolib driver. It also includes the implementation of
14 * (at your option) any later version. 14// external gpio and wakeup interrupt support.
15 *
16 * This file contains the Samsung Exynos specific information required by the
17 * the Samsung pinctrl/gpiolib driver. It also includes the implementation of
18 * external gpio and wakeup interrupt support.
19 */
20 15
21#include <linux/device.h> 16#include <linux/device.h>
22#include <linux/of_address.h> 17#include <linux/of_address.h>
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
index 08e9fdb58fd2..fc8f7833bec0 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
@@ -1,22 +1,17 @@
1/* 1// SPDX-License-Identifier: GPL-2.0+
2 * Exynos ARMv8 specific support for Samsung pinctrl/gpiolib driver 2//
3 * with eint support. 3// Exynos ARMv8 specific support for Samsung pinctrl/gpiolib driver
4 * 4// with eint support.
5 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 5//
6 * http://www.samsung.com 6// Copyright (c) 2012 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2012 Linaro Ltd 7// http://www.samsung.com
8 * http://www.linaro.org 8// Copyright (c) 2012 Linaro Ltd
9 * Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org> 9// http://www.linaro.org
10 * 10// Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org>
11 * This program is free software; you can redistribute it and/or modify 11//
12 * it under the terms of the GNU General Public License as published by 12// This file contains the Samsung Exynos specific information required by the
13 * the Free Software Foundation; either version 2 of the License, or 13// the Samsung pinctrl/gpiolib driver. It also includes the implementation of
14 * (at your option) any later version. 14// external gpio and wakeup interrupt support.
15 *
16 * This file contains the Samsung Exynos specific information required by the
17 * the Samsung pinctrl/gpiolib driver. It also includes the implementation of
18 * external gpio and wakeup interrupt support.
19 */
20 15
21#include <linux/slab.h> 16#include <linux/slab.h>
22#include <linux/soc/samsung/exynos-regs-pmu.h> 17#include <linux/soc/samsung/exynos-regs-pmu.h>
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index c8d0de7ea160..0a625a64ff5d 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -1,22 +1,17 @@
1/* 1// SPDX-License-Identifier: GPL-2.0+
2 * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support. 2//
3 * 3// Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 4//
5 * http://www.samsung.com 5// Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 * Copyright (c) 2012 Linaro Ltd 6// http://www.samsung.com
7 * http://www.linaro.org 7// Copyright (c) 2012 Linaro Ltd
8 * 8// http://www.linaro.org
9 * Author: Thomas Abraham <thomas.ab@samsung.com> 9//
10 * 10// Author: Thomas Abraham <thomas.ab@samsung.com>
11 * This program is free software; you can redistribute it and/or modify 11//
12 * it under the terms of the GNU General Public License as published by 12// This file contains the Samsung Exynos specific information required by the
13 * the Free Software Foundation; either version 2 of the License, or 13// the Samsung pinctrl/gpiolib driver. It also includes the implementation of
14 * (at your option) any later version. 14// external gpio and wakeup interrupt support.
15 *
16 * This file contains the Samsung Exynos specific information required by the
17 * the Samsung pinctrl/gpiolib driver. It also includes the implementation of
18 * external gpio and wakeup interrupt support.
19 */
20 15
21#include <linux/device.h> 16#include <linux/device.h>
22#include <linux/interrupt.h> 17#include <linux/interrupt.h>
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
index 7639b926c5c1..abd43aa7eb0d 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.h
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
@@ -1,3 +1,4 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
1/* 2/*
2 * Exynos specific definitions for Samsung pinctrl and gpiolib driver. 3 * Exynos specific definitions for Samsung pinctrl and gpiolib driver.
3 * 4 *
@@ -10,11 +11,6 @@
10 * pinctrl/gpiolib interface drivers. 11 * pinctrl/gpiolib interface drivers.
11 * 12 *
12 * Author: Thomas Abraham <thomas.ab@samsung.com> 13 * Author: Thomas Abraham <thomas.ab@samsung.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 */ 14 */
19 15
20#ifndef __PINCTRL_SAMSUNG_EXYNOS_H 16#ifndef __PINCTRL_SAMSUNG_EXYNOS_H
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos5440.c b/drivers/pinctrl/samsung/pinctrl-exynos5440.c
index 32a3a9fd65c4..3d8d5e812839 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos5440.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos5440.c
@@ -1,16 +1,11 @@
1/* 1// SPDX-License-Identifier: GPL-2.0+
2 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's EXYNOS5440 SoC. 2//
3 * 3// pin-controller/pin-mux/pin-config/gpio-driver for Samsung's EXYNOS5440 SoC.
4 * Author: Thomas Abraham <thomas.ab@samsung.com> 4//
5 * 5// Author: Thomas Abraham <thomas.ab@samsung.com>
6 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 6//
7 * http://www.samsung.com 7// Copyright (c) 2012 Samsung Electronics Co., Ltd.
8 * 8// http://www.samsung.com
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14 9
15#include <linux/init.h> 10#include <linux/init.h>
16#include <linux/platform_device.h> 11#include <linux/platform_device.h>
diff --git a/drivers/pinctrl/samsung/pinctrl-s3c24xx.c b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c
index edf27264b603..10187cb0e9b9 100644
--- a/drivers/pinctrl/samsung/pinctrl-s3c24xx.c
+++ b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c
@@ -1,17 +1,12 @@
1/* 1// SPDX-License-Identifier: GPL-2.0+
2 * S3C24XX specific support for Samsung pinctrl/gpiolib driver. 2//
3 * 3// S3C24XX specific support for Samsung pinctrl/gpiolib driver.
4 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> 4//
5 * 5// Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
6 * This program is free software; you can redistribute it and/or modify 6//
7 * it under the terms of the GNU General Public License as published by 7// This file contains the SamsungS3C24XX specific information required by the
8 * the Free Software Foundation; either version 2 of the License, or 8// Samsung pinctrl/gpiolib driver. It also includes the implementation of
9 * (at your option) any later version. 9// external gpio and wakeup interrupt support.
10 *
11 * This file contains the SamsungS3C24XX specific information required by the
12 * Samsung pinctrl/gpiolib driver. It also includes the implementation of
13 * external gpio and wakeup interrupt support.
14 */
15 10
16#include <linux/init.h> 11#include <linux/init.h>
17#include <linux/device.h> 12#include <linux/device.h>
diff --git a/drivers/pinctrl/samsung/pinctrl-s3c64xx.c b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c
index e63663b32907..679628ac4b31 100644
--- a/drivers/pinctrl/samsung/pinctrl-s3c64xx.c
+++ b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c
@@ -1,19 +1,14 @@
1/* 1// SPDX-License-Identifier: GPL-2.0+
2 * S3C64xx specific support for pinctrl-samsung driver. 2//
3 * 3// S3C64xx specific support for pinctrl-samsung driver.
4 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com> 4//
5 * 5// Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
6 * Based on pinctrl-exynos.c, please see the file for original copyrights. 6//
7 * 7// Based on pinctrl-exynos.c, please see the file for original copyrights.
8 * This program is free software; you can redistribute it and/or modify 8//
9 * it under the terms of the GNU General Public License as published by 9// This file contains the Samsung S3C64xx specific information required by the
10 * the Free Software Foundation; either version 2 of the License, or 10// the Samsung pinctrl/gpiolib driver. It also includes the implementation of
11 * (at your option) any later version. 11// external gpio and wakeup interrupt support.
12 *
13 * This file contains the Samsung S3C64xx specific information required by the
14 * the Samsung pinctrl/gpiolib driver. It also includes the implementation of
15 * external gpio and wakeup interrupt support.
16 */
17 12
18#include <linux/init.h> 13#include <linux/init.h>
19#include <linux/device.h> 14#include <linux/device.h>
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index e04f7fe0a65d..da58e4554137 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -1,24 +1,19 @@
1/* 1// SPDX-License-Identifier: GPL-2.0+
2 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's. 2//
3 * 3// pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 4//
5 * http://www.samsung.com 5// Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 * Copyright (c) 2012 Linaro Ltd 6// http://www.samsung.com
7 * http://www.linaro.org 7// Copyright (c) 2012 Linaro Ltd
8 * 8// http://www.linaro.org
9 * Author: Thomas Abraham <thomas.ab@samsung.com> 9//
10 * 10// Author: Thomas Abraham <thomas.ab@samsung.com>
11 * This program is free software; you can redistribute it and/or modify 11//
12 * it under the terms of the GNU General Public License as published by 12// This driver implements the Samsung pinctrl driver. It supports setting up of
13 * the Free Software Foundation; either version 2 of the License, or 13// pinmux and pinconf configurations. The gpiolib interface is also included.
14 * (at your option) any later version. 14// External interrupt (gpio and wakeup) support are not included in this driver
15 * 15// but provides extensions to which platform specific implementation of the gpio
16 * This driver implements the Samsung pinctrl driver. It supports setting up of 16// and wakeup interrupts can be hooked to.
17 * pinmux and pinconf configurations. The gpiolib interface is also included.
18 * External interrupt (gpio and wakeup) support are not included in this driver
19 * but provides extensions to which platform specific implementation of the gpio
20 * and wakeup interrupts can be hooked to.
21 */
22 17
23#include <linux/init.h> 18#include <linux/init.h>
24#include <linux/platform_device.h> 19#include <linux/platform_device.h>
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
index 9af07af6cad6..e204f609823b 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -1,3 +1,4 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
1/* 2/*
2 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's. 3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
3 * 4 *
@@ -7,11 +8,6 @@
7 * http://www.linaro.org 8 * http://www.linaro.org
8 * 9 *
9 * Author: Thomas Abraham <thomas.ab@samsung.com> 10 * Author: Thomas Abraham <thomas.ab@samsung.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */ 11 */
16 12
17#ifndef __PINCTRL_SAMSUNG_H 13#ifndef __PINCTRL_SAMSUNG_H
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index 5d5312eb7102..4ed3761418f9 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -89,6 +89,11 @@ config PINCTRL_PFC_R8A7796
89 depends on ARCH_R8A7796 89 depends on ARCH_R8A7796
90 select PINCTRL_SH_PFC 90 select PINCTRL_SH_PFC
91 91
92config PINCTRL_PFC_R8A77970
93 def_bool y
94 depends on ARCH_R8A77970
95 select PINCTRL_SH_PFC
96
92config PINCTRL_PFC_R8A77995 97config PINCTRL_PFC_R8A77995
93 def_bool y 98 def_bool y
94 depends on ARCH_R8A77995 99 depends on ARCH_R8A77995
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index a7903904b64e..22e758ce1fc2 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
16obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o 16obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
17obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795-es1.o 17obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795-es1.o
18obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o 18obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o
19obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o
19obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o 20obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
20obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o 21obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
21obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o 22obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index cf4ae4bc9115..e9eb7a7c6fac 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -557,6 +557,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
557 .data = &r8a7796_pinmux_info, 557 .data = &r8a7796_pinmux_info,
558 }, 558 },
559#endif 559#endif
560#ifdef CONFIG_PINCTRL_PFC_R8A77970
561 {
562 .compatible = "renesas,pfc-r8a77970",
563 .data = &r8a77970_pinmux_info,
564 },
565#endif
560#ifdef CONFIG_PINCTRL_PFC_R8A77995 566#ifdef CONFIG_PINCTRL_PFC_R8A77995
561 { 567 {
562 .compatible = "renesas,pfc-r8a77995", 568 .compatible = "renesas,pfc-r8a77995",
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
index 10bd35f8c894..5811784d88cb 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
@@ -4145,6 +4145,32 @@ static const unsigned int ssi9_ctrl_b_mux[] = {
4145 SSI_SCK9_B_MARK, SSI_WS9_B_MARK, 4145 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
4146}; 4146};
4147 4147
4148/* - TPU -------------------------------------------------------------------- */
4149static const unsigned int tpu_to0_pins[] = {
4150 RCAR_GP_PIN(6, 14),
4151};
4152static const unsigned int tpu_to0_mux[] = {
4153 TPU_TO0_MARK,
4154};
4155static const unsigned int tpu_to1_pins[] = {
4156 RCAR_GP_PIN(1, 17),
4157};
4158static const unsigned int tpu_to1_mux[] = {
4159 TPU_TO1_MARK,
4160};
4161static const unsigned int tpu_to2_pins[] = {
4162 RCAR_GP_PIN(1, 18),
4163};
4164static const unsigned int tpu_to2_mux[] = {
4165 TPU_TO2_MARK,
4166};
4167static const unsigned int tpu_to3_pins[] = {
4168 RCAR_GP_PIN(1, 24),
4169};
4170static const unsigned int tpu_to3_mux[] = {
4171 TPU_TO3_MARK,
4172};
4173
4148/* - USB0 ------------------------------------------------------------------- */ 4174/* - USB0 ------------------------------------------------------------------- */
4149static const unsigned int usb0_pins[] = { 4175static const unsigned int usb0_pins[] = {
4150 RCAR_GP_PIN(7, 23), /* PWEN */ 4176 RCAR_GP_PIN(7, 23), /* PWEN */
@@ -4431,7 +4457,7 @@ static const unsigned int vin2_clk_mux[] = {
4431}; 4457};
4432 4458
4433static const struct { 4459static const struct {
4434 struct sh_pfc_pin_group common[342]; 4460 struct sh_pfc_pin_group common[346];
4435 struct sh_pfc_pin_group r8a779x[9]; 4461 struct sh_pfc_pin_group r8a779x[9];
4436} pinmux_groups = { 4462} pinmux_groups = {
4437 .common = { 4463 .common = {
@@ -4743,6 +4769,10 @@ static const struct {
4743 SH_PFC_PIN_GROUP(ssi9_data_b), 4769 SH_PFC_PIN_GROUP(ssi9_data_b),
4744 SH_PFC_PIN_GROUP(ssi9_ctrl), 4770 SH_PFC_PIN_GROUP(ssi9_ctrl),
4745 SH_PFC_PIN_GROUP(ssi9_ctrl_b), 4771 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4772 SH_PFC_PIN_GROUP(tpu_to0),
4773 SH_PFC_PIN_GROUP(tpu_to1),
4774 SH_PFC_PIN_GROUP(tpu_to2),
4775 SH_PFC_PIN_GROUP(tpu_to3),
4746 SH_PFC_PIN_GROUP(usb0), 4776 SH_PFC_PIN_GROUP(usb0),
4747 SH_PFC_PIN_GROUP(usb1), 4777 SH_PFC_PIN_GROUP(usb1),
4748 VIN_DATA_PIN_GROUP(vin0_data, 24), 4778 VIN_DATA_PIN_GROUP(vin0_data, 24),
@@ -4826,6 +4856,10 @@ static const char * const can0_groups[] = {
4826 "can0_data_d", 4856 "can0_data_d",
4827 "can0_data_e", 4857 "can0_data_e",
4828 "can0_data_f", 4858 "can0_data_f",
4859 /*
4860 * Retained for backwards compatibility, use can_clk_groups in new
4861 * designs.
4862 */
4829 "can_clk", 4863 "can_clk",
4830 "can_clk_b", 4864 "can_clk_b",
4831 "can_clk_c", 4865 "can_clk_c",
@@ -4837,6 +4871,21 @@ static const char * const can1_groups[] = {
4837 "can1_data_b", 4871 "can1_data_b",
4838 "can1_data_c", 4872 "can1_data_c",
4839 "can1_data_d", 4873 "can1_data_d",
4874 /*
4875 * Retained for backwards compatibility, use can_clk_groups in new
4876 * designs.
4877 */
4878 "can_clk",
4879 "can_clk_b",
4880 "can_clk_c",
4881 "can_clk_d",
4882};
4883
4884/*
4885 * can_clk_groups allows for independent configuration, use can_clk function
4886 * in new designs.
4887 */
4888static const char * const can_clk_groups[] = {
4840 "can_clk", 4889 "can_clk",
4841 "can_clk_b", 4890 "can_clk_b",
4842 "can_clk_c", 4891 "can_clk_c",
@@ -5259,6 +5308,13 @@ static const char * const ssi_groups[] = {
5259 "ssi9_ctrl_b", 5308 "ssi9_ctrl_b",
5260}; 5309};
5261 5310
5311static const char * const tpu_groups[] = {
5312 "tpu_to0",
5313 "tpu_to1",
5314 "tpu_to2",
5315 "tpu_to3",
5316};
5317
5262static const char * const usb0_groups[] = { 5318static const char * const usb0_groups[] = {
5263 "usb0", 5319 "usb0",
5264}; 5320};
@@ -5308,7 +5364,7 @@ static const char * const vin2_groups[] = {
5308}; 5364};
5309 5365
5310static const struct { 5366static const struct {
5311 struct sh_pfc_function common[56]; 5367 struct sh_pfc_function common[58];
5312 struct sh_pfc_function r8a779x[2]; 5368 struct sh_pfc_function r8a779x[2];
5313} pinmux_functions = { 5369} pinmux_functions = {
5314 .common = { 5370 .common = {
@@ -5316,6 +5372,7 @@ static const struct {
5316 SH_PFC_FUNCTION(avb), 5372 SH_PFC_FUNCTION(avb),
5317 SH_PFC_FUNCTION(can0), 5373 SH_PFC_FUNCTION(can0),
5318 SH_PFC_FUNCTION(can1), 5374 SH_PFC_FUNCTION(can1),
5375 SH_PFC_FUNCTION(can_clk),
5319 SH_PFC_FUNCTION(du), 5376 SH_PFC_FUNCTION(du),
5320 SH_PFC_FUNCTION(du0), 5377 SH_PFC_FUNCTION(du0),
5321 SH_PFC_FUNCTION(du1), 5378 SH_PFC_FUNCTION(du1),
@@ -5363,6 +5420,7 @@ static const struct {
5363 SH_PFC_FUNCTION(sdhi1), 5420 SH_PFC_FUNCTION(sdhi1),
5364 SH_PFC_FUNCTION(sdhi2), 5421 SH_PFC_FUNCTION(sdhi2),
5365 SH_PFC_FUNCTION(ssi), 5422 SH_PFC_FUNCTION(ssi),
5423 SH_PFC_FUNCTION(tpu),
5366 SH_PFC_FUNCTION(usb0), 5424 SH_PFC_FUNCTION(usb0),
5367 SH_PFC_FUNCTION(usb1), 5425 SH_PFC_FUNCTION(usb1),
5368 SH_PFC_FUNCTION(vin0), 5426 SH_PFC_FUNCTION(vin0),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
index 333a3470e842..164002437594 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
@@ -1608,6 +1608,116 @@ static const unsigned int avb_gmii_mux[] = {
1608 AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK, 1608 AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
1609 AVB_COL_MARK, 1609 AVB_COL_MARK,
1610}; 1610};
1611
1612/* - CAN -------------------------------------------------------------------- */
1613static const unsigned int can0_data_pins[] = {
1614 /* TX, RX */
1615 RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),
1616};
1617
1618static const unsigned int can0_data_mux[] = {
1619 CAN0_TX_MARK, CAN0_RX_MARK,
1620};
1621
1622static const unsigned int can0_data_b_pins[] = {
1623 /* TX, RX */
1624 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
1625};
1626
1627static const unsigned int can0_data_b_mux[] = {
1628 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1629};
1630
1631static const unsigned int can0_data_c_pins[] = {
1632 /* TX, RX */
1633 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16),
1634};
1635
1636static const unsigned int can0_data_c_mux[] = {
1637 CAN0_TX_C_MARK, CAN0_RX_C_MARK,
1638};
1639
1640static const unsigned int can0_data_d_pins[] = {
1641 /* TX, RX */
1642 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
1643};
1644
1645static const unsigned int can0_data_d_mux[] = {
1646 CAN0_TX_D_MARK, CAN0_RX_D_MARK,
1647};
1648
1649static const unsigned int can1_data_pins[] = {
1650 /* TX, RX */
1651 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 24),
1652};
1653
1654static const unsigned int can1_data_mux[] = {
1655 CAN1_TX_MARK, CAN1_RX_MARK,
1656};
1657
1658static const unsigned int can1_data_b_pins[] = {
1659 /* TX, RX */
1660 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
1661};
1662
1663static const unsigned int can1_data_b_mux[] = {
1664 CAN1_TX_B_MARK, CAN1_RX_B_MARK,
1665};
1666
1667static const unsigned int can1_data_c_pins[] = {
1668 /* TX, RX */
1669 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
1670};
1671
1672static const unsigned int can1_data_c_mux[] = {
1673 CAN1_TX_C_MARK, CAN1_RX_C_MARK,
1674};
1675
1676static const unsigned int can1_data_d_pins[] = {
1677 /* TX, RX */
1678 RCAR_GP_PIN(3, 31), RCAR_GP_PIN(3, 30),
1679};
1680
1681static const unsigned int can1_data_d_mux[] = {
1682 CAN1_TX_D_MARK, CAN1_RX_D_MARK,
1683};
1684
1685static const unsigned int can_clk_pins[] = {
1686 /* CLK */
1687 RCAR_GP_PIN(3, 31),
1688};
1689
1690static const unsigned int can_clk_mux[] = {
1691 CAN_CLK_MARK,
1692};
1693
1694static const unsigned int can_clk_b_pins[] = {
1695 /* CLK */
1696 RCAR_GP_PIN(1, 23),
1697};
1698
1699static const unsigned int can_clk_b_mux[] = {
1700 CAN_CLK_B_MARK,
1701};
1702
1703static const unsigned int can_clk_c_pins[] = {
1704 /* CLK */
1705 RCAR_GP_PIN(1, 0),
1706};
1707
1708static const unsigned int can_clk_c_mux[] = {
1709 CAN_CLK_C_MARK,
1710};
1711
1712static const unsigned int can_clk_d_pins[] = {
1713 /* CLK */
1714 RCAR_GP_PIN(5, 0),
1715};
1716
1717static const unsigned int can_clk_d_mux[] = {
1718 CAN_CLK_D_MARK,
1719};
1720
1611/* - DU --------------------------------------------------------------------- */ 1721/* - DU --------------------------------------------------------------------- */
1612static const unsigned int du0_rgb666_pins[] = { 1722static const unsigned int du0_rgb666_pins[] = {
1613 /* R[7:2], G[7:2], B[7:2] */ 1723 /* R[7:2], G[7:2], B[7:2] */
@@ -2118,6 +2228,35 @@ static const unsigned int i2c4_e_pins[] = {
2118static const unsigned int i2c4_e_mux[] = { 2228static const unsigned int i2c4_e_mux[] = {
2119 I2C4_SCL_E_MARK, I2C4_SDA_E_MARK, 2229 I2C4_SCL_E_MARK, I2C4_SDA_E_MARK,
2120}; 2230};
2231/* - I2C5 ------------------------------------------------------------------- */
2232static const unsigned int i2c5_pins[] = {
2233 /* SCL, SDA */
2234 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
2235};
2236static const unsigned int i2c5_mux[] = {
2237 I2C5_SCL_MARK, I2C5_SDA_MARK,
2238};
2239static const unsigned int i2c5_b_pins[] = {
2240 /* SCL, SDA */
2241 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2242};
2243static const unsigned int i2c5_b_mux[] = {
2244 I2C5_SCL_B_MARK, I2C5_SDA_B_MARK,
2245};
2246static const unsigned int i2c5_c_pins[] = {
2247 /* SCL, SDA */
2248 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2249};
2250static const unsigned int i2c5_c_mux[] = {
2251 I2C5_SCL_C_MARK, I2C5_SDA_C_MARK,
2252};
2253static const unsigned int i2c5_d_pins[] = {
2254 /* SCL, SDA */
2255 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
2256};
2257static const unsigned int i2c5_d_mux[] = {
2258 I2C5_SCL_D_MARK, I2C5_SDA_D_MARK,
2259};
2121/* - INTC ------------------------------------------------------------------- */ 2260/* - INTC ------------------------------------------------------------------- */
2122static const unsigned int intc_irq0_pins[] = { 2261static const unsigned int intc_irq0_pins[] = {
2123 /* IRQ0 */ 2262 /* IRQ0 */
@@ -2436,6 +2575,109 @@ static const unsigned int msiof2_tx_b_pins[] = {
2436static const unsigned int msiof2_tx_b_mux[] = { 2575static const unsigned int msiof2_tx_b_mux[] = {
2437 MSIOF2_TXD_B_MARK, 2576 MSIOF2_TXD_B_MARK,
2438}; 2577};
2578/* - PWM -------------------------------------------------------------------- */
2579static const unsigned int pwm0_pins[] = {
2580 RCAR_GP_PIN(1, 14),
2581};
2582static const unsigned int pwm0_mux[] = {
2583 PWM0_MARK,
2584};
2585static const unsigned int pwm0_b_pins[] = {
2586 RCAR_GP_PIN(5, 3),
2587};
2588static const unsigned int pwm0_b_mux[] = {
2589 PWM0_B_MARK,
2590};
2591static const unsigned int pwm1_pins[] = {
2592 RCAR_GP_PIN(4, 5),
2593};
2594static const unsigned int pwm1_mux[] = {
2595 PWM1_MARK,
2596};
2597static const unsigned int pwm1_b_pins[] = {
2598 RCAR_GP_PIN(5, 10),
2599};
2600static const unsigned int pwm1_b_mux[] = {
2601 PWM1_B_MARK,
2602};
2603static const unsigned int pwm1_c_pins[] = {
2604 RCAR_GP_PIN(1, 18),
2605};
2606static const unsigned int pwm1_c_mux[] = {
2607 PWM1_C_MARK,
2608};
2609static const unsigned int pwm2_pins[] = {
2610 RCAR_GP_PIN(4, 10),
2611};
2612static const unsigned int pwm2_mux[] = {
2613 PWM2_MARK,
2614};
2615static const unsigned int pwm2_b_pins[] = {
2616 RCAR_GP_PIN(5, 17),
2617};
2618static const unsigned int pwm2_b_mux[] = {
2619 PWM2_B_MARK,
2620};
2621static const unsigned int pwm2_c_pins[] = {
2622 RCAR_GP_PIN(0, 13),
2623};
2624static const unsigned int pwm2_c_mux[] = {
2625 PWM2_C_MARK,
2626};
2627static const unsigned int pwm3_pins[] = {
2628 RCAR_GP_PIN(4, 13),
2629};
2630static const unsigned int pwm3_mux[] = {
2631 PWM3_MARK,
2632};
2633static const unsigned int pwm3_b_pins[] = {
2634 RCAR_GP_PIN(0, 16),
2635};
2636static const unsigned int pwm3_b_mux[] = {
2637 PWM3_B_MARK,
2638};
2639static const unsigned int pwm4_pins[] = {
2640 RCAR_GP_PIN(1, 3),
2641};
2642static const unsigned int pwm4_mux[] = {
2643 PWM4_MARK,
2644};
2645static const unsigned int pwm4_b_pins[] = {
2646 RCAR_GP_PIN(0, 21),
2647};
2648static const unsigned int pwm4_b_mux[] = {
2649 PWM4_B_MARK,
2650};
2651static const unsigned int pwm5_pins[] = {
2652 RCAR_GP_PIN(3, 30),
2653};
2654static const unsigned int pwm5_mux[] = {
2655 PWM5_MARK,
2656};
2657static const unsigned int pwm5_b_pins[] = {
2658 RCAR_GP_PIN(4, 0),
2659};
2660static const unsigned int pwm5_b_mux[] = {
2661 PWM5_B_MARK,
2662};
2663static const unsigned int pwm5_c_pins[] = {
2664 RCAR_GP_PIN(0, 10),
2665};
2666static const unsigned int pwm5_c_mux[] = {
2667 PWM5_C_MARK,
2668};
2669static const unsigned int pwm6_pins[] = {
2670 RCAR_GP_PIN(4, 8),
2671};
2672static const unsigned int pwm6_mux[] = {
2673 PWM6_MARK,
2674};
2675static const unsigned int pwm6_b_pins[] = {
2676 RCAR_GP_PIN(0, 7),
2677};
2678static const unsigned int pwm6_b_mux[] = {
2679 PWM6_B_MARK,
2680};
2439/* - QSPI ------------------------------------------------------------------- */ 2681/* - QSPI ------------------------------------------------------------------- */
2440static const unsigned int qspi_ctrl_pins[] = { 2682static const unsigned int qspi_ctrl_pins[] = {
2441 /* SPCLK, SSL */ 2683 /* SPCLK, SSL */
@@ -3280,6 +3522,79 @@ static const unsigned int ssi9_ctrl_b_pins[] = {
3280static const unsigned int ssi9_ctrl_b_mux[] = { 3522static const unsigned int ssi9_ctrl_b_mux[] = {
3281 SSI_SCK9_B_MARK, SSI_WS9_B_MARK, 3523 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3282}; 3524};
3525/* - TPU -------------------------------------------------------------------- */
3526static const unsigned int tpu_to0_pins[] = {
3527 RCAR_GP_PIN(3, 31),
3528};
3529static const unsigned int tpu_to0_mux[] = {
3530 TPUTO0_MARK,
3531};
3532static const unsigned int tpu_to0_b_pins[] = {
3533 RCAR_GP_PIN(3, 30),
3534};
3535static const unsigned int tpu_to0_b_mux[] = {
3536 TPUTO0_B_MARK,
3537};
3538static const unsigned int tpu_to0_c_pins[] = {
3539 RCAR_GP_PIN(1, 18),
3540};
3541static const unsigned int tpu_to0_c_mux[] = {
3542 TPUTO0_C_MARK,
3543};
3544static const unsigned int tpu_to1_pins[] = {
3545 RCAR_GP_PIN(4, 9),
3546};
3547static const unsigned int tpu_to1_mux[] = {
3548 TPUTO1_MARK,
3549};
3550static const unsigned int tpu_to1_b_pins[] = {
3551 RCAR_GP_PIN(4, 0),
3552};
3553static const unsigned int tpu_to1_b_mux[] = {
3554 TPUTO1_B_MARK,
3555};
3556static const unsigned int tpu_to1_c_pins[] = {
3557 RCAR_GP_PIN(4, 4),
3558};
3559static const unsigned int tpu_to1_c_mux[] = {
3560 TPUTO1_C_MARK,
3561};
3562static const unsigned int tpu_to2_pins[] = {
3563 RCAR_GP_PIN(1, 3),
3564};
3565static const unsigned int tpu_to2_mux[] = {
3566 TPUTO2_MARK,
3567};
3568static const unsigned int tpu_to2_b_pins[] = {
3569 RCAR_GP_PIN(1, 0),
3570};
3571static const unsigned int tpu_to2_b_mux[] = {
3572 TPUTO2_B_MARK,
3573};
3574static const unsigned int tpu_to2_c_pins[] = {
3575 RCAR_GP_PIN(0, 22),
3576};
3577static const unsigned int tpu_to2_c_mux[] = {
3578 TPUTO2_C_MARK,
3579};
3580static const unsigned int tpu_to3_pins[] = {
3581 RCAR_GP_PIN(1, 14),
3582};
3583static const unsigned int tpu_to3_mux[] = {
3584 TPUTO3_MARK,
3585};
3586static const unsigned int tpu_to3_b_pins[] = {
3587 RCAR_GP_PIN(1, 13),
3588};
3589static const unsigned int tpu_to3_b_mux[] = {
3590 TPUTO3_B_MARK,
3591};
3592static const unsigned int tpu_to3_c_pins[] = {
3593 RCAR_GP_PIN(0, 21),
3594};
3595static const unsigned int tpu_to3_c_mux[] = {
3596 TPUTO3_C_MARK,
3597};
3283/* - USB0 ------------------------------------------------------------------- */ 3598/* - USB0 ------------------------------------------------------------------- */
3284static const unsigned int usb0_pins[] = { 3599static const unsigned int usb0_pins[] = {
3285 RCAR_GP_PIN(5, 24), /* PWEN */ 3600 RCAR_GP_PIN(5, 24), /* PWEN */
@@ -3459,6 +3774,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
3459 SH_PFC_PIN_GROUP(avb_mdio), 3774 SH_PFC_PIN_GROUP(avb_mdio),
3460 SH_PFC_PIN_GROUP(avb_mii), 3775 SH_PFC_PIN_GROUP(avb_mii),
3461 SH_PFC_PIN_GROUP(avb_gmii), 3776 SH_PFC_PIN_GROUP(avb_gmii),
3777 SH_PFC_PIN_GROUP(can0_data),
3778 SH_PFC_PIN_GROUP(can0_data_b),
3779 SH_PFC_PIN_GROUP(can0_data_c),
3780 SH_PFC_PIN_GROUP(can0_data_d),
3781 SH_PFC_PIN_GROUP(can1_data),
3782 SH_PFC_PIN_GROUP(can1_data_b),
3783 SH_PFC_PIN_GROUP(can1_data_c),
3784 SH_PFC_PIN_GROUP(can1_data_d),
3785 SH_PFC_PIN_GROUP(can_clk),
3786 SH_PFC_PIN_GROUP(can_clk_b),
3787 SH_PFC_PIN_GROUP(can_clk_c),
3788 SH_PFC_PIN_GROUP(can_clk_d),
3462 SH_PFC_PIN_GROUP(du0_rgb666), 3789 SH_PFC_PIN_GROUP(du0_rgb666),
3463 SH_PFC_PIN_GROUP(du0_rgb888), 3790 SH_PFC_PIN_GROUP(du0_rgb888),
3464 SH_PFC_PIN_GROUP(du0_clk0_out), 3791 SH_PFC_PIN_GROUP(du0_clk0_out),
@@ -3523,6 +3850,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
3523 SH_PFC_PIN_GROUP(i2c4_c), 3850 SH_PFC_PIN_GROUP(i2c4_c),
3524 SH_PFC_PIN_GROUP(i2c4_d), 3851 SH_PFC_PIN_GROUP(i2c4_d),
3525 SH_PFC_PIN_GROUP(i2c4_e), 3852 SH_PFC_PIN_GROUP(i2c4_e),
3853 SH_PFC_PIN_GROUP(i2c5),
3854 SH_PFC_PIN_GROUP(i2c5_b),
3855 SH_PFC_PIN_GROUP(i2c5_c),
3856 SH_PFC_PIN_GROUP(i2c5_d),
3526 SH_PFC_PIN_GROUP(intc_irq0), 3857 SH_PFC_PIN_GROUP(intc_irq0),
3527 SH_PFC_PIN_GROUP(intc_irq1), 3858 SH_PFC_PIN_GROUP(intc_irq1),
3528 SH_PFC_PIN_GROUP(intc_irq2), 3859 SH_PFC_PIN_GROUP(intc_irq2),
@@ -3567,6 +3898,23 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
3567 SH_PFC_PIN_GROUP(msiof2_ss2_b), 3898 SH_PFC_PIN_GROUP(msiof2_ss2_b),
3568 SH_PFC_PIN_GROUP(msiof2_rx_b), 3899 SH_PFC_PIN_GROUP(msiof2_rx_b),
3569 SH_PFC_PIN_GROUP(msiof2_tx_b), 3900 SH_PFC_PIN_GROUP(msiof2_tx_b),
3901 SH_PFC_PIN_GROUP(pwm0),
3902 SH_PFC_PIN_GROUP(pwm0_b),
3903 SH_PFC_PIN_GROUP(pwm1),
3904 SH_PFC_PIN_GROUP(pwm1_b),
3905 SH_PFC_PIN_GROUP(pwm1_c),
3906 SH_PFC_PIN_GROUP(pwm2),
3907 SH_PFC_PIN_GROUP(pwm2_b),
3908 SH_PFC_PIN_GROUP(pwm2_c),
3909 SH_PFC_PIN_GROUP(pwm3),
3910 SH_PFC_PIN_GROUP(pwm3_b),
3911 SH_PFC_PIN_GROUP(pwm4),
3912 SH_PFC_PIN_GROUP(pwm4_b),
3913 SH_PFC_PIN_GROUP(pwm5),
3914 SH_PFC_PIN_GROUP(pwm5_b),
3915 SH_PFC_PIN_GROUP(pwm5_c),
3916 SH_PFC_PIN_GROUP(pwm6),
3917 SH_PFC_PIN_GROUP(pwm6_b),
3570 SH_PFC_PIN_GROUP(qspi_ctrl), 3918 SH_PFC_PIN_GROUP(qspi_ctrl),
3571 SH_PFC_PIN_GROUP(qspi_data2), 3919 SH_PFC_PIN_GROUP(qspi_data2),
3572 SH_PFC_PIN_GROUP(qspi_data4), 3920 SH_PFC_PIN_GROUP(qspi_data4),
@@ -3684,6 +4032,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
3684 SH_PFC_PIN_GROUP(ssi9_ctrl), 4032 SH_PFC_PIN_GROUP(ssi9_ctrl),
3685 SH_PFC_PIN_GROUP(ssi9_data_b), 4033 SH_PFC_PIN_GROUP(ssi9_data_b),
3686 SH_PFC_PIN_GROUP(ssi9_ctrl_b), 4034 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4035 SH_PFC_PIN_GROUP(tpu_to0),
4036 SH_PFC_PIN_GROUP(tpu_to0_b),
4037 SH_PFC_PIN_GROUP(tpu_to0_c),
4038 SH_PFC_PIN_GROUP(tpu_to1),
4039 SH_PFC_PIN_GROUP(tpu_to1_b),
4040 SH_PFC_PIN_GROUP(tpu_to1_c),
4041 SH_PFC_PIN_GROUP(tpu_to2),
4042 SH_PFC_PIN_GROUP(tpu_to2_b),
4043 SH_PFC_PIN_GROUP(tpu_to2_c),
4044 SH_PFC_PIN_GROUP(tpu_to3),
4045 SH_PFC_PIN_GROUP(tpu_to3_b),
4046 SH_PFC_PIN_GROUP(tpu_to3_c),
3687 SH_PFC_PIN_GROUP(usb0), 4047 SH_PFC_PIN_GROUP(usb0),
3688 SH_PFC_PIN_GROUP(usb1), 4048 SH_PFC_PIN_GROUP(usb1),
3689 VIN_DATA_PIN_GROUP(vin0_data, 24), 4049 VIN_DATA_PIN_GROUP(vin0_data, 24),
@@ -3731,6 +4091,47 @@ static const char * const avb_groups[] = {
3731 "avb_gmii", 4091 "avb_gmii",
3732}; 4092};
3733 4093
4094static const char * const can0_groups[] = {
4095 "can0_data",
4096 "can0_data_b",
4097 "can0_data_c",
4098 "can0_data_d",
4099 /*
4100 * Retained for backwards compatibility, use can_clk_groups in new
4101 * designs.
4102 */
4103 "can_clk",
4104 "can_clk_b",
4105 "can_clk_c",
4106 "can_clk_d",
4107};
4108
4109static const char * const can1_groups[] = {
4110 "can1_data",
4111 "can1_data_b",
4112 "can1_data_c",
4113 "can1_data_d",
4114 /*
4115 * Retained for backwards compatibility, use can_clk_groups in new
4116 * designs.
4117 */
4118 "can_clk",
4119 "can_clk_b",
4120 "can_clk_c",
4121 "can_clk_d",
4122};
4123
4124/*
4125 * can_clk_groups allows for independent configuration, use can_clk function
4126 * in new designs.
4127 */
4128static const char * const can_clk_groups[] = {
4129 "can_clk",
4130 "can_clk_b",
4131 "can_clk_c",
4132 "can_clk_d",
4133};
4134
3734static const char * const du0_groups[] = { 4135static const char * const du0_groups[] = {
3735 "du0_rgb666", 4136 "du0_rgb666",
3736 "du0_rgb888", 4137 "du0_rgb888",
@@ -3828,6 +4229,13 @@ static const char * const i2c4_groups[] = {
3828 "i2c4_e", 4229 "i2c4_e",
3829}; 4230};
3830 4231
4232static const char * const i2c5_groups[] = {
4233 "i2c5",
4234 "i2c5_b",
4235 "i2c5_c",
4236 "i2c5_d",
4237};
4238
3831static const char * const intc_groups[] = { 4239static const char * const intc_groups[] = {
3832 "intc_irq0", 4240 "intc_irq0",
3833 "intc_irq1", 4241 "intc_irq1",
@@ -3887,6 +4295,44 @@ static const char * const msiof2_groups[] = {
3887 "msiof2_tx_b", 4295 "msiof2_tx_b",
3888}; 4296};
3889 4297
4298static const char * const pwm0_groups[] = {
4299 "pwm0",
4300 "pwm0_b",
4301};
4302
4303static const char * const pwm1_groups[] = {
4304 "pwm1",
4305 "pwm1_b",
4306 "pwm1_c",
4307};
4308
4309static const char * const pwm2_groups[] = {
4310 "pwm2",
4311 "pwm2_b",
4312 "pwm2_c",
4313};
4314
4315static const char * const pwm3_groups[] = {
4316 "pwm3",
4317 "pwm3_b",
4318};
4319
4320static const char * const pwm4_groups[] = {
4321 "pwm4",
4322 "pwm4_b",
4323};
4324
4325static const char * const pwm5_groups[] = {
4326 "pwm5",
4327 "pwm5_b",
4328 "pwm5_c",
4329};
4330
4331static const char * const pwm6_groups[] = {
4332 "pwm6",
4333 "pwm6_b",
4334};
4335
3890static const char * const qspi_groups[] = { 4336static const char * const qspi_groups[] = {
3891 "qspi_ctrl", 4337 "qspi_ctrl",
3892 "qspi_data2", 4338 "qspi_data2",
@@ -4067,6 +4513,21 @@ static const char * const ssi_groups[] = {
4067 "ssi9_ctrl_b", 4513 "ssi9_ctrl_b",
4068}; 4514};
4069 4515
4516static const char * const tpu_groups[] = {
4517 "tpu_to0",
4518 "tpu_to0_b",
4519 "tpu_to0_c",
4520 "tpu_to1",
4521 "tpu_to1_b",
4522 "tpu_to1_c",
4523 "tpu_to2",
4524 "tpu_to2_b",
4525 "tpu_to2_c",
4526 "tpu_to3",
4527 "tpu_to3_b",
4528 "tpu_to3_c",
4529};
4530
4070static const char * const usb0_groups[] = { 4531static const char * const usb0_groups[] = {
4071 "usb0", 4532 "usb0",
4072}; 4533};
@@ -4102,6 +4563,9 @@ static const char * const vin1_groups[] = {
4102static const struct sh_pfc_function pinmux_functions[] = { 4563static const struct sh_pfc_function pinmux_functions[] = {
4103 SH_PFC_FUNCTION(audio_clk), 4564 SH_PFC_FUNCTION(audio_clk),
4104 SH_PFC_FUNCTION(avb), 4565 SH_PFC_FUNCTION(avb),
4566 SH_PFC_FUNCTION(can0),
4567 SH_PFC_FUNCTION(can1),
4568 SH_PFC_FUNCTION(can_clk),
4105 SH_PFC_FUNCTION(du0), 4569 SH_PFC_FUNCTION(du0),
4106 SH_PFC_FUNCTION(du1), 4570 SH_PFC_FUNCTION(du1),
4107 SH_PFC_FUNCTION(eth), 4571 SH_PFC_FUNCTION(eth),
@@ -4113,11 +4577,19 @@ static const struct sh_pfc_function pinmux_functions[] = {
4113 SH_PFC_FUNCTION(i2c2), 4577 SH_PFC_FUNCTION(i2c2),
4114 SH_PFC_FUNCTION(i2c3), 4578 SH_PFC_FUNCTION(i2c3),
4115 SH_PFC_FUNCTION(i2c4), 4579 SH_PFC_FUNCTION(i2c4),
4580 SH_PFC_FUNCTION(i2c5),
4116 SH_PFC_FUNCTION(intc), 4581 SH_PFC_FUNCTION(intc),
4117 SH_PFC_FUNCTION(mmc), 4582 SH_PFC_FUNCTION(mmc),
4118 SH_PFC_FUNCTION(msiof0), 4583 SH_PFC_FUNCTION(msiof0),
4119 SH_PFC_FUNCTION(msiof1), 4584 SH_PFC_FUNCTION(msiof1),
4120 SH_PFC_FUNCTION(msiof2), 4585 SH_PFC_FUNCTION(msiof2),
4586 SH_PFC_FUNCTION(pwm0),
4587 SH_PFC_FUNCTION(pwm1),
4588 SH_PFC_FUNCTION(pwm2),
4589 SH_PFC_FUNCTION(pwm3),
4590 SH_PFC_FUNCTION(pwm4),
4591 SH_PFC_FUNCTION(pwm5),
4592 SH_PFC_FUNCTION(pwm6),
4121 SH_PFC_FUNCTION(qspi), 4593 SH_PFC_FUNCTION(qspi),
4122 SH_PFC_FUNCTION(scif0), 4594 SH_PFC_FUNCTION(scif0),
4123 SH_PFC_FUNCTION(scif1), 4595 SH_PFC_FUNCTION(scif1),
@@ -4139,6 +4611,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
4139 SH_PFC_FUNCTION(sdhi1), 4611 SH_PFC_FUNCTION(sdhi1),
4140 SH_PFC_FUNCTION(sdhi2), 4612 SH_PFC_FUNCTION(sdhi2),
4141 SH_PFC_FUNCTION(ssi), 4613 SH_PFC_FUNCTION(ssi),
4614 SH_PFC_FUNCTION(tpu),
4142 SH_PFC_FUNCTION(usb0), 4615 SH_PFC_FUNCTION(usb0),
4143 SH_PFC_FUNCTION(usb1), 4616 SH_PFC_FUNCTION(usb1),
4144 SH_PFC_FUNCTION(vin0), 4617 SH_PFC_FUNCTION(vin0),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
index 1d4d84f34d60..292e35d4d2f4 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
@@ -1397,7 +1397,7 @@ static const u16 pinmux_data[] = {
1397 PINMUX_IPSR_MSEL(IP16_27_24, AUDIO_CLKOUT_B, SEL_ADG_1), 1397 PINMUX_IPSR_MSEL(IP16_27_24, AUDIO_CLKOUT_B, SEL_ADG_1),
1398 PINMUX_IPSR_MSEL(IP16_27_24, SSI_SCK2_B, SEL_SSI_1), 1398 PINMUX_IPSR_MSEL(IP16_27_24, SSI_SCK2_B, SEL_SSI_1),
1399 PINMUX_IPSR_MSEL(IP16_27_24, TS_SDEN1_D, SEL_TSIF1_3), 1399 PINMUX_IPSR_MSEL(IP16_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1400 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISEN_1_D, SEL_SSP1_1_2), 1400 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1401 PINMUX_IPSR_MSEL(IP16_27_24, STP_OPWM_0_E, SEL_SSP1_0_4), 1401 PINMUX_IPSR_MSEL(IP16_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1402 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D0_B, SEL_DRIF3_1), 1402 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D0_B, SEL_DRIF3_1),
1403 PINMUX_IPSR_MSEL(IP16_27_24, TCLK2_B, SEL_TIMER_TMU_1), 1403 PINMUX_IPSR_MSEL(IP16_27_24, TCLK2_B, SEL_TIMER_TMU_1),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index d1cec6d12e81..18aeee592fdc 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -20,7 +20,7 @@
20 20
21#define CPU_ALL_PORT(fn, sfx) \ 21#define CPU_ALL_PORT(fn, sfx) \
22 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ 22 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \ 23 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ 24 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ 25 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
26 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ 26 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
@@ -55,6 +55,7 @@
55#define GPSR0_0 F_(D0, IP5_15_12) 55#define GPSR0_0 F_(D0, IP5_15_12)
56 56
57/* GPSR1 */ 57/* GPSR1 */
58#define GPSR1_28 FM(CLKOUT)
58#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8) 59#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
59#define GPSR1_26 F_(WE1_N, IP5_7_4) 60#define GPSR1_26 F_(WE1_N, IP5_7_4)
60#define GPSR1_25 F_(WE0_N, IP5_3_0) 61#define GPSR1_25 F_(WE0_N, IP5_3_0)
@@ -157,11 +158,11 @@
157#define GPSR5_11 F_(RX2_A, IP13_7_4) 158#define GPSR5_11 F_(RX2_A, IP13_7_4)
158#define GPSR5_10 F_(TX2_A, IP13_3_0) 159#define GPSR5_10 F_(TX2_A, IP13_3_0)
159#define GPSR5_9 F_(SCK2, IP12_31_28) 160#define GPSR5_9 F_(SCK2, IP12_31_28)
160#define GPSR5_8 F_(RTS1_N_TANS, IP12_27_24) 161#define GPSR5_8 F_(RTS1_N, IP12_27_24)
161#define GPSR5_7 F_(CTS1_N, IP12_23_20) 162#define GPSR5_7 F_(CTS1_N, IP12_23_20)
162#define GPSR5_6 F_(TX1_A, IP12_19_16) 163#define GPSR5_6 F_(TX1_A, IP12_19_16)
163#define GPSR5_5 F_(RX1_A, IP12_15_12) 164#define GPSR5_5 F_(RX1_A, IP12_15_12)
164#define GPSR5_4 F_(RTS0_N_TANS, IP12_11_8) 165#define GPSR5_4 F_(RTS0_N, IP12_11_8)
165#define GPSR5_3 F_(CTS0_N, IP12_7_4) 166#define GPSR5_3 F_(CTS0_N, IP12_7_4)
166#define GPSR5_2 F_(TX0, IP12_3_0) 167#define GPSR5_2 F_(TX0, IP12_3_0)
167#define GPSR5_1 F_(RX0, IP11_31_28) 168#define GPSR5_1 F_(RX0, IP11_31_28)
@@ -214,16 +215,16 @@
214#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 215#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 216#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 217#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 218#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 219#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 220#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 221#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 222#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 223#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 224#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 225#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 226#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 227#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 228#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 229#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 230#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -236,7 +237,7 @@
236#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 237#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 238#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 239#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 240#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 241#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 242#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 243#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -252,7 +253,7 @@
252#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 253#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 254#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 255#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 256#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 257#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 258#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 259#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -265,7 +266,7 @@
265#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 266#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 267#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 268#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 269#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 270#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 271#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 272#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -312,11 +313,11 @@
312#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 313#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 314#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 315#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 316#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 317#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 318#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 319#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 320#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 321#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 322#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 323#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -368,7 +369,7 @@
368 GPSR6_31 \ 369 GPSR6_31 \
369 GPSR6_30 \ 370 GPSR6_30 \
370 GPSR6_29 \ 371 GPSR6_29 \
371 GPSR6_28 \ 372 GPSR1_28 GPSR6_28 \
372 GPSR1_27 GPSR6_27 \ 373 GPSR1_27 GPSR6_27 \
373 GPSR1_26 GPSR6_26 \ 374 GPSR1_26 GPSR6_26 \
374 GPSR1_25 GPSR5_25 GPSR6_25 \ 375 GPSR1_25 GPSR5_25 GPSR6_25 \
@@ -548,7 +549,7 @@ MOD_SEL0_4_3 MOD_SEL1_4 \
548 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \ 549 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
549 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \ 550 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
550 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \ 551 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
551 FM(CLKOUT) FM(PRESETOUT) \ 552 FM(PRESETOUT) \
552 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \ 553 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
553 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) 554 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
554 555
@@ -587,6 +588,7 @@ static const u16 pinmux_data[] = {
587 588
588 PINMUX_SINGLE(AVS1), 589 PINMUX_SINGLE(AVS1),
589 PINMUX_SINGLE(AVS2), 590 PINMUX_SINGLE(AVS2),
591 PINMUX_SINGLE(CLKOUT),
590 PINMUX_SINGLE(HDMI0_CEC), 592 PINMUX_SINGLE(HDMI0_CEC),
591 PINMUX_SINGLE(HDMI1_CEC), 593 PINMUX_SINGLE(HDMI1_CEC),
592 PINMUX_SINGLE(I2C_SEL_0_1), 594 PINMUX_SINGLE(I2C_SEL_0_1),
@@ -622,7 +624,7 @@ static const u16 pinmux_data[] = {
622 624
623 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0), 625 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
624 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2), 626 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
625 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0), 627 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0),
626 628
627 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), 629 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
628 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), 630 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
@@ -650,7 +652,6 @@ static const u16 pinmux_data[] = {
650 652
651 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3), 653 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
652 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE), 654 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
653 PINMUX_IPSR_GPSR(IP1_7_4, A25),
654 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1), 655 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
655 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1), 656 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
656 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1), 657 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
@@ -658,7 +659,6 @@ static const u16 pinmux_data[] = {
658 659
659 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4), 660 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
660 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS), 661 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
661 PINMUX_IPSR_GPSR(IP1_11_8, A24),
662 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC), 662 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
663 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1), 663 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
664 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1), 664 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
@@ -666,7 +666,6 @@ static const u16 pinmux_data[] = {
666 666
667 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5), 667 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
668 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE), 668 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
669 PINMUX_IPSR_GPSR(IP1_15_12, A23),
670 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC), 669 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
671 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1), 670 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
672 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1), 671 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
@@ -675,18 +674,15 @@ static const u16 pinmux_data[] = {
675 674
676 PINMUX_IPSR_GPSR(IP1_19_16, PWM0), 675 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
677 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS), 676 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
678 PINMUX_IPSR_GPSR(IP1_19_16, A22),
679 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), 677 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
680 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), 678 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
681 679
682 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0), 680 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
683 PINMUX_IPSR_GPSR(IP1_23_20, A21),
684 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3), 681 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
685 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1), 682 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
686 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1), 683 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
687 684
688 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0), 685 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
689 PINMUX_IPSR_GPSR(IP1_27_24, A20),
690 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3), 686 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
691 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1), 687 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
692 688
@@ -766,7 +762,7 @@ static const u16 pinmux_data[] = {
766 762
767 PINMUX_IPSR_GPSR(IP3_7_4, A10), 763 PINMUX_IPSR_GPSR(IP3_7_4, A10),
768 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0), 764 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
769 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1), 765 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
770 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N), 766 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
771 767
772 PINMUX_IPSR_GPSR(IP3_11_8, A11), 768 PINMUX_IPSR_GPSR(IP3_11_8, A11),
@@ -869,7 +865,7 @@ static const u16 pinmux_data[] = {
869 865
870 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N), 866 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
871 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3), 867 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
872 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS), 868 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
873 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N), 869 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
874 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1), 870 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
875 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX), 871 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
@@ -950,7 +946,7 @@ static const u16 pinmux_data[] = {
950 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3), 946 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
951 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1), 947 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
952 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0), 948 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
953 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2), 949 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
954 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3), 950 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
955 951
956 PINMUX_IPSR_GPSR(IP6_31_28, D12), 952 PINMUX_IPSR_GPSR(IP6_31_28, D12),
@@ -1159,7 +1155,7 @@ static const u16 pinmux_data[] = {
1159 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C), 1155 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1160 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP), 1156 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1161 1157
1162 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N_TANS), 1158 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
1163 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), 1159 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1164 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), 1160 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1165 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1), 1161 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
@@ -1188,7 +1184,7 @@ static const u16 pinmux_data[] = {
1188 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1), 1184 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1189 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA), 1185 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1190 1186
1191 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N_TANS), 1187 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
1192 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0), 1188 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1193 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1), 1189 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1194 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2), 1190 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
@@ -1781,6 +1777,61 @@ static const unsigned int avb_avtp_capture_b_mux[] = {
1781 AVB_AVTP_CAPTURE_B_MARK, 1777 AVB_AVTP_CAPTURE_B_MARK,
1782}; 1778};
1783 1779
1780/* - CAN ------------------------------------------------------------------ */
1781static const unsigned int can0_data_a_pins[] = {
1782 /* TX, RX */
1783 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1784};
1785static const unsigned int can0_data_a_mux[] = {
1786 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1787};
1788static const unsigned int can0_data_b_pins[] = {
1789 /* TX, RX */
1790 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1791};
1792static const unsigned int can0_data_b_mux[] = {
1793 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1794};
1795static const unsigned int can1_data_pins[] = {
1796 /* TX, RX */
1797 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1798};
1799static const unsigned int can1_data_mux[] = {
1800 CAN1_TX_MARK, CAN1_RX_MARK,
1801};
1802
1803/* - CAN Clock -------------------------------------------------------------- */
1804static const unsigned int can_clk_pins[] = {
1805 /* CLK */
1806 RCAR_GP_PIN(1, 25),
1807};
1808static const unsigned int can_clk_mux[] = {
1809 CAN_CLK_MARK,
1810};
1811
1812/* - CAN FD --------------------------------------------------------------- */
1813static const unsigned int canfd0_data_a_pins[] = {
1814 /* TX, RX */
1815 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1816};
1817static const unsigned int canfd0_data_a_mux[] = {
1818 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1819};
1820static const unsigned int canfd0_data_b_pins[] = {
1821 /* TX, RX */
1822 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1823};
1824static const unsigned int canfd0_data_b_mux[] = {
1825 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1826};
1827static const unsigned int canfd1_data_pins[] = {
1828 /* TX, RX */
1829 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1830};
1831static const unsigned int canfd1_data_mux[] = {
1832 CANFD1_TX_MARK, CANFD1_RX_MARK,
1833};
1834
1784/* - DRIF0 --------------------------------------------------------------- */ 1835/* - DRIF0 --------------------------------------------------------------- */
1785static const unsigned int drif0_ctrl_a_pins[] = { 1836static const unsigned int drif0_ctrl_a_pins[] = {
1786 /* CLK, SYNC */ 1837 /* CLK, SYNC */
@@ -3176,6 +3227,22 @@ static const unsigned int pwm6_b_mux[] = {
3176 PWM6_B_MARK, 3227 PWM6_B_MARK,
3177}; 3228};
3178 3229
3230/* - SATA --------------------------------------------------------------------*/
3231static const unsigned int sata0_devslp_a_pins[] = {
3232 /* DEVSLP */
3233 RCAR_GP_PIN(6, 16),
3234};
3235static const unsigned int sata0_devslp_a_mux[] = {
3236 SATA_DEVSLP_A_MARK,
3237};
3238static const unsigned int sata0_devslp_b_pins[] = {
3239 /* DEVSLP */
3240 RCAR_GP_PIN(4, 6),
3241};
3242static const unsigned int sata0_devslp_b_mux[] = {
3243 SATA_DEVSLP_B_MARK,
3244};
3245
3179/* - SCIF0 ------------------------------------------------------------------ */ 3246/* - SCIF0 ------------------------------------------------------------------ */
3180static const unsigned int scif0_data_pins[] = { 3247static const unsigned int scif0_data_pins[] = {
3181 /* RX, TX */ 3248 /* RX, TX */
@@ -3196,7 +3263,7 @@ static const unsigned int scif0_ctrl_pins[] = {
3196 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), 3263 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3197}; 3264};
3198static const unsigned int scif0_ctrl_mux[] = { 3265static const unsigned int scif0_ctrl_mux[] = {
3199 RTS0_N_TANS_MARK, CTS0_N_MARK, 3266 RTS0_N_MARK, CTS0_N_MARK,
3200}; 3267};
3201/* - SCIF1 ------------------------------------------------------------------ */ 3268/* - SCIF1 ------------------------------------------------------------------ */
3202static const unsigned int scif1_data_a_pins[] = { 3269static const unsigned int scif1_data_a_pins[] = {
@@ -3218,7 +3285,7 @@ static const unsigned int scif1_ctrl_pins[] = {
3218 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), 3285 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3219}; 3286};
3220static const unsigned int scif1_ctrl_mux[] = { 3287static const unsigned int scif1_ctrl_mux[] = {
3221 RTS1_N_TANS_MARK, CTS1_N_MARK, 3288 RTS1_N_MARK, CTS1_N_MARK,
3222}; 3289};
3223 3290
3224static const unsigned int scif1_data_b_pins[] = { 3291static const unsigned int scif1_data_b_pins[] = {
@@ -3270,7 +3337,7 @@ static const unsigned int scif3_ctrl_pins[] = {
3270 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 3337 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3271}; 3338};
3272static const unsigned int scif3_ctrl_mux[] = { 3339static const unsigned int scif3_ctrl_mux[] = {
3273 RTS3_N_TANS_MARK, CTS3_N_MARK, 3340 RTS3_N_MARK, CTS3_N_MARK,
3274}; 3341};
3275static const unsigned int scif3_data_b_pins[] = { 3342static const unsigned int scif3_data_b_pins[] = {
3276 /* RX, TX */ 3343 /* RX, TX */
@@ -3299,7 +3366,7 @@ static const unsigned int scif4_ctrl_a_pins[] = {
3299 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), 3366 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3300}; 3367};
3301static const unsigned int scif4_ctrl_a_mux[] = { 3368static const unsigned int scif4_ctrl_a_mux[] = {
3302 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK, 3369 RTS4_N_A_MARK, CTS4_N_A_MARK,
3303}; 3370};
3304static const unsigned int scif4_data_b_pins[] = { 3371static const unsigned int scif4_data_b_pins[] = {
3305 /* RX, TX */ 3372 /* RX, TX */
@@ -3320,7 +3387,7 @@ static const unsigned int scif4_ctrl_b_pins[] = {
3320 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), 3387 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3321}; 3388};
3322static const unsigned int scif4_ctrl_b_mux[] = { 3389static const unsigned int scif4_ctrl_b_mux[] = {
3323 RTS4_N_TANS_B_MARK, CTS4_N_B_MARK, 3390 RTS4_N_B_MARK, CTS4_N_B_MARK,
3324}; 3391};
3325static const unsigned int scif4_data_c_pins[] = { 3392static const unsigned int scif4_data_c_pins[] = {
3326 /* RX, TX */ 3393 /* RX, TX */
@@ -3341,7 +3408,7 @@ static const unsigned int scif4_ctrl_c_pins[] = {
3341 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 3408 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3342}; 3409};
3343static const unsigned int scif4_ctrl_c_mux[] = { 3410static const unsigned int scif4_ctrl_c_mux[] = {
3344 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK, 3411 RTS4_N_C_MARK, CTS4_N_C_MARK,
3345}; 3412};
3346/* - SCIF5 ------------------------------------------------------------------ */ 3413/* - SCIF5 ------------------------------------------------------------------ */
3347static const unsigned int scif5_data_a_pins[] = { 3414static const unsigned int scif5_data_a_pins[] = {
@@ -3843,6 +3910,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
3843 SH_PFC_PIN_GROUP(avb_avtp_capture_a), 3910 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3844 SH_PFC_PIN_GROUP(avb_avtp_match_b), 3911 SH_PFC_PIN_GROUP(avb_avtp_match_b),
3845 SH_PFC_PIN_GROUP(avb_avtp_capture_b), 3912 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
3913 SH_PFC_PIN_GROUP(can0_data_a),
3914 SH_PFC_PIN_GROUP(can0_data_b),
3915 SH_PFC_PIN_GROUP(can1_data),
3916 SH_PFC_PIN_GROUP(can_clk),
3917 SH_PFC_PIN_GROUP(canfd0_data_a),
3918 SH_PFC_PIN_GROUP(canfd0_data_b),
3919 SH_PFC_PIN_GROUP(canfd1_data),
3846 SH_PFC_PIN_GROUP(drif0_ctrl_a), 3920 SH_PFC_PIN_GROUP(drif0_ctrl_a),
3847 SH_PFC_PIN_GROUP(drif0_data0_a), 3921 SH_PFC_PIN_GROUP(drif0_data0_a),
3848 SH_PFC_PIN_GROUP(drif0_data1_a), 3922 SH_PFC_PIN_GROUP(drif0_data1_a),
@@ -4034,6 +4108,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
4034 SH_PFC_PIN_GROUP(pwm5_b), 4108 SH_PFC_PIN_GROUP(pwm5_b),
4035 SH_PFC_PIN_GROUP(pwm6_a), 4109 SH_PFC_PIN_GROUP(pwm6_a),
4036 SH_PFC_PIN_GROUP(pwm6_b), 4110 SH_PFC_PIN_GROUP(pwm6_b),
4111 SH_PFC_PIN_GROUP(sata0_devslp_a),
4112 SH_PFC_PIN_GROUP(sata0_devslp_b),
4037 SH_PFC_PIN_GROUP(scif0_data), 4113 SH_PFC_PIN_GROUP(scif0_data),
4038 SH_PFC_PIN_GROUP(scif0_clk), 4114 SH_PFC_PIN_GROUP(scif0_clk),
4039 SH_PFC_PIN_GROUP(scif0_ctrl), 4115 SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -4154,6 +4230,28 @@ static const char * const avb_groups[] = {
4154 "avb_avtp_capture_b", 4230 "avb_avtp_capture_b",
4155}; 4231};
4156 4232
4233static const char * const can0_groups[] = {
4234 "can0_data_a",
4235 "can0_data_b",
4236};
4237
4238static const char * const can1_groups[] = {
4239 "can1_data",
4240};
4241
4242static const char * const can_clk_groups[] = {
4243 "can_clk",
4244};
4245
4246static const char * const canfd0_groups[] = {
4247 "canfd0_data_a",
4248 "canfd0_data_b",
4249};
4250
4251static const char * const canfd1_groups[] = {
4252 "canfd1_data",
4253};
4254
4157static const char * const drif0_groups[] = { 4255static const char * const drif0_groups[] = {
4158 "drif0_ctrl_a", 4256 "drif0_ctrl_a",
4159 "drif0_data0_a", 4257 "drif0_data0_a",
@@ -4420,6 +4518,11 @@ static const char * const pwm6_groups[] = {
4420 "pwm6_b", 4518 "pwm6_b",
4421}; 4519};
4422 4520
4521static const char * const sata0_groups[] = {
4522 "sata0_devslp_a",
4523 "sata0_devslp_b",
4524};
4525
4423static const char * const scif0_groups[] = { 4526static const char * const scif0_groups[] = {
4424 "scif0_data", 4527 "scif0_data",
4425 "scif0_clk", 4528 "scif0_clk",
@@ -4559,6 +4662,11 @@ static const char * const usb30_groups[] = {
4559static const struct sh_pfc_function pinmux_functions[] = { 4662static const struct sh_pfc_function pinmux_functions[] = {
4560 SH_PFC_FUNCTION(audio_clk), 4663 SH_PFC_FUNCTION(audio_clk),
4561 SH_PFC_FUNCTION(avb), 4664 SH_PFC_FUNCTION(avb),
4665 SH_PFC_FUNCTION(can0),
4666 SH_PFC_FUNCTION(can1),
4667 SH_PFC_FUNCTION(can_clk),
4668 SH_PFC_FUNCTION(canfd0),
4669 SH_PFC_FUNCTION(canfd1),
4562 SH_PFC_FUNCTION(drif0), 4670 SH_PFC_FUNCTION(drif0),
4563 SH_PFC_FUNCTION(drif1), 4671 SH_PFC_FUNCTION(drif1),
4564 SH_PFC_FUNCTION(drif2), 4672 SH_PFC_FUNCTION(drif2),
@@ -4584,6 +4692,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
4584 SH_PFC_FUNCTION(pwm4), 4692 SH_PFC_FUNCTION(pwm4),
4585 SH_PFC_FUNCTION(pwm5), 4693 SH_PFC_FUNCTION(pwm5),
4586 SH_PFC_FUNCTION(pwm6), 4694 SH_PFC_FUNCTION(pwm6),
4695 SH_PFC_FUNCTION(sata0),
4587 SH_PFC_FUNCTION(scif0), 4696 SH_PFC_FUNCTION(scif0),
4588 SH_PFC_FUNCTION(scif1), 4697 SH_PFC_FUNCTION(scif1),
4589 SH_PFC_FUNCTION(scif2), 4698 SH_PFC_FUNCTION(scif2),
@@ -4644,7 +4753,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4644 0, 0, 4753 0, 0,
4645 0, 0, 4754 0, 0,
4646 0, 0, 4755 0, 0,
4647 0, 0, 4756 GP_1_28_FN, GPSR1_28,
4648 GP_1_27_FN, GPSR1_27, 4757 GP_1_27_FN, GPSR1_27,
4649 GP_1_26_FN, GPSR1_26, 4758 GP_1_26_FN, GPSR1_26,
4650 GP_1_25_FN, GPSR1_25, 4759 GP_1_25_FN, GPSR1_25,
@@ -5246,7 +5355,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5246 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */ 5355 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5247 } }, 5356 } },
5248 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) { 5357 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5249 { PIN_NUMBER('F', 1), 28, 3 }, /* CLKOUT */ 5358 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
5250 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */ 5359 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5251 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */ 5360 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5252 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */ 5361 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
@@ -5342,11 +5451,11 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5342 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */ 5451 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5343 } }, 5452 } },
5344 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) { 5453 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5345 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */ 5454 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
5346 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */ 5455 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5347 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */ 5456 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5348 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */ 5457 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
5349 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */ 5458 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
5350 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */ 5459 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5351 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */ 5460 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5352 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */ 5461 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
@@ -5507,7 +5616,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5507 [31] = RCAR_GP_PIN(1, 19), /* A19 */ 5616 [31] = RCAR_GP_PIN(1, 19), /* A19 */
5508 } }, 5617 } },
5509 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { 5618 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5510 [ 0] = PIN_NUMBER('F', 1), /* CLKOUT */ 5619 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
5511 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */ 5620 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
5512 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */ 5621 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
5513 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */ 5622 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
@@ -5591,11 +5700,11 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5591 [13] = RCAR_GP_PIN(5, 1), /* RX0 */ 5700 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
5592 [14] = RCAR_GP_PIN(5, 2), /* TX0 */ 5701 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
5593 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */ 5702 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
5594 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N_TANS */ 5703 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
5595 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */ 5704 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
5596 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */ 5705 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
5597 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */ 5706 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
5598 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N_TANS */ 5707 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
5599 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */ 5708 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
5600 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */ 5709 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
5601 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */ 5710 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 73ed9c74c137..e5807d1ce0dc 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -163,11 +163,11 @@
163#define GPSR5_11 F_(RX2_A, IP13_7_4) 163#define GPSR5_11 F_(RX2_A, IP13_7_4)
164#define GPSR5_10 F_(TX2_A, IP13_3_0) 164#define GPSR5_10 F_(TX2_A, IP13_3_0)
165#define GPSR5_9 F_(SCK2, IP12_31_28) 165#define GPSR5_9 F_(SCK2, IP12_31_28)
166#define GPSR5_8 F_(RTS1_N_TANS, IP12_27_24) 166#define GPSR5_8 F_(RTS1_N, IP12_27_24)
167#define GPSR5_7 F_(CTS1_N, IP12_23_20) 167#define GPSR5_7 F_(CTS1_N, IP12_23_20)
168#define GPSR5_6 F_(TX1_A, IP12_19_16) 168#define GPSR5_6 F_(TX1_A, IP12_19_16)
169#define GPSR5_5 F_(RX1_A, IP12_15_12) 169#define GPSR5_5 F_(RX1_A, IP12_15_12)
170#define GPSR5_4 F_(RTS0_N_TANS, IP12_11_8) 170#define GPSR5_4 F_(RTS0_N, IP12_11_8)
171#define GPSR5_3 F_(CTS0_N, IP12_7_4) 171#define GPSR5_3 F_(CTS0_N, IP12_7_4)
172#define GPSR5_2 F_(TX0, IP12_3_0) 172#define GPSR5_2 F_(TX0, IP12_3_0)
173#define GPSR5_1 F_(RX0, IP11_31_28) 173#define GPSR5_1 F_(RX0, IP11_31_28)
@@ -220,16 +220,16 @@
220#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 220#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 221#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 222#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 223#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 224#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 225#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 226#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 227#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 228#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 229#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 230#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231#define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 231#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232#define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 232#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 233#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 234#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 235#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -240,7 +240,7 @@
240#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 240#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 241#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 242#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 243#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 244#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245 245
246/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 246/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
@@ -258,7 +258,7 @@
258#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 258#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 259#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 260#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 261#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 262#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 263#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 264#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -271,7 +271,7 @@
271#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 271#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 272#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 273#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 274#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 275#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 276
277/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 277/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
@@ -318,11 +318,11 @@
318#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 318#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 319#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 320#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 321#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 322#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 323#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 324#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 325#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 326#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 327#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 328#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -626,7 +626,7 @@ static const u16 pinmux_data[] = {
626 626
627 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0), 627 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
628 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2), 628 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
629 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0), 629 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0),
630 630
631 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), 631 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
632 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), 632 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
@@ -654,7 +654,6 @@ static const u16 pinmux_data[] = {
654 654
655 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3), 655 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
656 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE), 656 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
657 PINMUX_IPSR_GPSR(IP1_7_4, A25),
658 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1), 657 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
659 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1), 658 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
660 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1), 659 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
@@ -662,7 +661,6 @@ static const u16 pinmux_data[] = {
662 661
663 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4), 662 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
664 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS), 663 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
665 PINMUX_IPSR_GPSR(IP1_11_8, A24),
666 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC), 664 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
667 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1), 665 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
668 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1), 666 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
@@ -670,7 +668,6 @@ static const u16 pinmux_data[] = {
670 668
671 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5), 669 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
672 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE), 670 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
673 PINMUX_IPSR_GPSR(IP1_15_12, A23),
674 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC), 671 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
675 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1), 672 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
676 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1), 673 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
@@ -678,18 +675,15 @@ static const u16 pinmux_data[] = {
678 675
679 PINMUX_IPSR_GPSR(IP1_19_16, PWM0), 676 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
680 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS), 677 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
681 PINMUX_IPSR_GPSR(IP1_19_16, A22),
682 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), 678 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
683 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), 679 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
684 680
685 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0), 681 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
686 PINMUX_IPSR_GPSR(IP1_23_20, A21),
687 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3), 682 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
688 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1), 683 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
689 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1), 684 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
690 685
691 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0), 686 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
692 PINMUX_IPSR_GPSR(IP1_27_24, A20),
693 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3), 687 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
694 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1), 688 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
695 689
@@ -769,7 +763,7 @@ static const u16 pinmux_data[] = {
769 763
770 PINMUX_IPSR_GPSR(IP3_7_4, A10), 764 PINMUX_IPSR_GPSR(IP3_7_4, A10),
771 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0), 765 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
772 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1), 766 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
773 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N), 767 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
774 768
775 PINMUX_IPSR_GPSR(IP3_11_8, A11), 769 PINMUX_IPSR_GPSR(IP3_11_8, A11),
@@ -872,7 +866,7 @@ static const u16 pinmux_data[] = {
872 866
873 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N), 867 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
874 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3), 868 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
875 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS), 869 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
876 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N), 870 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
877 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1), 871 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
878 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX), 872 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
@@ -953,7 +947,7 @@ static const u16 pinmux_data[] = {
953 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3), 947 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
954 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1), 948 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
955 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0), 949 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
956 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2), 950 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
957 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3), 951 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
958 952
959 PINMUX_IPSR_GPSR(IP6_31_28, D12), 953 PINMUX_IPSR_GPSR(IP6_31_28, D12),
@@ -1161,7 +1155,7 @@ static const u16 pinmux_data[] = {
1161 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C), 1155 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1162 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP), 1156 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1163 1157
1164 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N_TANS), 1158 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
1165 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), 1159 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1166 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), 1160 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1167 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1), 1161 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
@@ -1190,7 +1184,7 @@ static const u16 pinmux_data[] = {
1190 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1), 1184 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1191 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA), 1185 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1192 1186
1193 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N_TANS), 1187 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
1194 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0), 1188 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1195 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1), 1189 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1196 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2), 1190 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
@@ -3255,7 +3249,7 @@ static const unsigned int scif0_ctrl_pins[] = {
3255 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), 3249 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3256}; 3250};
3257static const unsigned int scif0_ctrl_mux[] = { 3251static const unsigned int scif0_ctrl_mux[] = {
3258 RTS0_N_TANS_MARK, CTS0_N_MARK, 3252 RTS0_N_MARK, CTS0_N_MARK,
3259}; 3253};
3260/* - SCIF1 ------------------------------------------------------------------ */ 3254/* - SCIF1 ------------------------------------------------------------------ */
3261static const unsigned int scif1_data_a_pins[] = { 3255static const unsigned int scif1_data_a_pins[] = {
@@ -3277,7 +3271,7 @@ static const unsigned int scif1_ctrl_pins[] = {
3277 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), 3271 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3278}; 3272};
3279static const unsigned int scif1_ctrl_mux[] = { 3273static const unsigned int scif1_ctrl_mux[] = {
3280 RTS1_N_TANS_MARK, CTS1_N_MARK, 3274 RTS1_N_MARK, CTS1_N_MARK,
3281}; 3275};
3282 3276
3283static const unsigned int scif1_data_b_pins[] = { 3277static const unsigned int scif1_data_b_pins[] = {
@@ -3329,7 +3323,7 @@ static const unsigned int scif3_ctrl_pins[] = {
3329 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 3323 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3330}; 3324};
3331static const unsigned int scif3_ctrl_mux[] = { 3325static const unsigned int scif3_ctrl_mux[] = {
3332 RTS3_N_TANS_MARK, CTS3_N_MARK, 3326 RTS3_N_MARK, CTS3_N_MARK,
3333}; 3327};
3334static const unsigned int scif3_data_b_pins[] = { 3328static const unsigned int scif3_data_b_pins[] = {
3335 /* RX, TX */ 3329 /* RX, TX */
@@ -3358,7 +3352,7 @@ static const unsigned int scif4_ctrl_a_pins[] = {
3358 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), 3352 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3359}; 3353};
3360static const unsigned int scif4_ctrl_a_mux[] = { 3354static const unsigned int scif4_ctrl_a_mux[] = {
3361 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK, 3355 RTS4_N_A_MARK, CTS4_N_A_MARK,
3362}; 3356};
3363static const unsigned int scif4_data_b_pins[] = { 3357static const unsigned int scif4_data_b_pins[] = {
3364 /* RX, TX */ 3358 /* RX, TX */
@@ -3379,7 +3373,7 @@ static const unsigned int scif4_ctrl_b_pins[] = {
3379 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), 3373 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3380}; 3374};
3381static const unsigned int scif4_ctrl_b_mux[] = { 3375static const unsigned int scif4_ctrl_b_mux[] = {
3382 RTS4_N_TANS_B_MARK, CTS4_N_B_MARK, 3376 RTS4_N_B_MARK, CTS4_N_B_MARK,
3383}; 3377};
3384static const unsigned int scif4_data_c_pins[] = { 3378static const unsigned int scif4_data_c_pins[] = {
3385 /* RX, TX */ 3379 /* RX, TX */
@@ -3400,7 +3394,7 @@ static const unsigned int scif4_ctrl_c_pins[] = {
3400 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 3394 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3401}; 3395};
3402static const unsigned int scif4_ctrl_c_mux[] = { 3396static const unsigned int scif4_ctrl_c_mux[] = {
3403 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK, 3397 RTS4_N_C_MARK, CTS4_N_C_MARK,
3404}; 3398};
3405/* - SCIF5 ------------------------------------------------------------------ */ 3399/* - SCIF5 ------------------------------------------------------------------ */
3406static const unsigned int scif5_data_a_pins[] = { 3400static const unsigned int scif5_data_a_pins[] = {
@@ -5406,11 +5400,11 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5406 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */ 5400 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5407 } }, 5401 } },
5408 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) { 5402 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5409 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */ 5403 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
5410 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */ 5404 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5411 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */ 5405 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5412 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */ 5406 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
5413 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */ 5407 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
5414 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */ 5408 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5415 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */ 5409 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5416 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */ 5410 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
@@ -5655,11 +5649,11 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5655 [13] = RCAR_GP_PIN(5, 1), /* RX0 */ 5649 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
5656 [14] = RCAR_GP_PIN(5, 2), /* TX0 */ 5650 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
5657 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */ 5651 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
5658 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N_TANS */ 5652 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
5659 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */ 5653 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
5660 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */ 5654 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
5661 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */ 5655 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
5662 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N_TANS */ 5656 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
5663 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */ 5657 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
5664 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */ 5658 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
5665 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */ 5659 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77970.c b/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
new file mode 100644
index 000000000000..794f12d74449
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
@@ -0,0 +1,2329 @@
1/*
2 * R8A77970 processor support - PFC hardware block.
3 *
4 * Copyright (C) 2016 Renesas Electronics Corp.
5 * Copyright (C) 2017 Cogent Embedded, Inc. <source@cogentembedded.com>
6 *
7 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
8 *
9 * R-Car Gen3 processor support - PFC hardware block.
10 *
11 * Copyright (C) 2015 Renesas Electronics Corporation
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
16 */
17
18#include <linux/io.h>
19#include <linux/kernel.h>
20
21#include "core.h"
22#include "sh_pfc.h"
23
24#define CPU_ALL_PORT(fn, sfx) \
25 PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
26 PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
27 PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
28 PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
29 PORT_GP_CFG_6(4, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
30 PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH)
31/*
32 * F_() : just information
33 * FM() : macro for FN_xxx / xxx_MARK
34 */
35
36/* GPSR0 */
37#define GPSR0_21 F_(DU_EXODDF_DU_ODDF_DISP_CDE, IP2_23_20)
38#define GPSR0_20 F_(DU_EXVSYNC_DU_VSYNC, IP2_19_16)
39#define GPSR0_19 F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12)
40#define GPSR0_18 F_(DU_DOTCLKOUT, IP2_11_8)
41#define GPSR0_17 F_(DU_DB7, IP2_7_4)
42#define GPSR0_16 F_(DU_DB6, IP2_3_0)
43#define GPSR0_15 F_(DU_DB5, IP1_31_28)
44#define GPSR0_14 F_(DU_DB4, IP1_27_24)
45#define GPSR0_13 F_(DU_DB3, IP1_23_20)
46#define GPSR0_12 F_(DU_DB2, IP1_19_16)
47#define GPSR0_11 F_(DU_DG7, IP1_15_12)
48#define GPSR0_10 F_(DU_DG6, IP1_11_8)
49#define GPSR0_9 F_(DU_DG5, IP1_7_4)
50#define GPSR0_8 F_(DU_DG4, IP1_3_0)
51#define GPSR0_7 F_(DU_DG3, IP0_31_28)
52#define GPSR0_6 F_(DU_DG2, IP0_27_24)
53#define GPSR0_5 F_(DU_DR7, IP0_23_20)
54#define GPSR0_4 F_(DU_DR6, IP0_19_16)
55#define GPSR0_3 F_(DU_DR5, IP0_15_12)
56#define GPSR0_2 F_(DU_DR4, IP0_11_8)
57#define GPSR0_1 F_(DU_DR3, IP0_7_4)
58#define GPSR0_0 F_(DU_DR2, IP0_3_0)
59
60/* GPSR1 */
61#define GPSR1_27 F_(DIGRF_CLKOUT, IP8_27_24)
62#define GPSR1_26 F_(DIGRF_CLKIN, IP8_23_20)
63#define GPSR1_25 F_(CANFD_CLK_A, IP8_19_16)
64#define GPSR1_24 F_(CANFD1_RX, IP8_15_12)
65#define GPSR1_23 F_(CANFD1_TX, IP8_11_8)
66#define GPSR1_22 F_(CANFD0_RX_A, IP8_7_4)
67#define GPSR1_21 F_(CANFD0_TX_A, IP8_3_0)
68#define GPSR1_20 F_(AVB0_AVTP_CAPTURE, IP7_31_28)
69#define GPSR1_19 FM(AVB0_AVTP_MATCH)
70#define GPSR1_18 FM(AVB0_LINK)
71#define GPSR1_17 FM(AVB0_PHY_INT)
72#define GPSR1_16 FM(AVB0_MAGIC)
73#define GPSR1_15 FM(AVB0_MDC)
74#define GPSR1_14 FM(AVB0_MDIO)
75#define GPSR1_13 FM(AVB0_TXCREFCLK)
76#define GPSR1_12 FM(AVB0_TD3)
77#define GPSR1_11 FM(AVB0_TD2)
78#define GPSR1_10 FM(AVB0_TD1)
79#define GPSR1_9 FM(AVB0_TD0)
80#define GPSR1_8 FM(AVB0_TXC)
81#define GPSR1_7 FM(AVB0_TX_CTL)
82#define GPSR1_6 FM(AVB0_RD3)
83#define GPSR1_5 FM(AVB0_RD2)
84#define GPSR1_4 FM(AVB0_RD1)
85#define GPSR1_3 FM(AVB0_RD0)
86#define GPSR1_2 FM(AVB0_RXC)
87#define GPSR1_1 FM(AVB0_RX_CTL)
88#define GPSR1_0 F_(IRQ0, IP2_27_24)
89
90/* GPSR2 */
91#define GPSR2_16 F_(VI0_FIELD, IP4_31_28)
92#define GPSR2_15 F_(VI0_DATA11, IP4_27_24)
93#define GPSR2_14 F_(VI0_DATA10, IP4_23_20)
94#define GPSR2_13 F_(VI0_DATA9, IP4_19_16)
95#define GPSR2_12 F_(VI0_DATA8, IP4_15_12)
96#define GPSR2_11 F_(VI0_DATA7, IP4_11_8)
97#define GPSR2_10 F_(VI0_DATA6, IP4_7_4)
98#define GPSR2_9 F_(VI0_DATA5, IP4_3_0)
99#define GPSR2_8 F_(VI0_DATA4, IP3_31_28)
100#define GPSR2_7 F_(VI0_DATA3, IP3_27_24)
101#define GPSR2_6 F_(VI0_DATA2, IP3_23_20)
102#define GPSR2_5 F_(VI0_DATA1, IP3_19_16)
103#define GPSR2_4 F_(VI0_DATA0, IP3_15_12)
104#define GPSR2_3 F_(VI0_VSYNC_N, IP3_11_8)
105#define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4)
106#define GPSR2_1 F_(VI0_CLKENB, IP3_3_0)
107#define GPSR2_0 F_(VI0_CLK, IP2_31_28)
108
109/* GPSR3 */
110#define GPSR3_16 F_(VI1_FIELD, IP7_3_0)
111#define GPSR3_15 F_(VI1_DATA11, IP6_31_28)
112#define GPSR3_14 F_(VI1_DATA10, IP6_27_24)
113#define GPSR3_13 F_(VI1_DATA9, IP6_23_20)
114#define GPSR3_12 F_(VI1_DATA8, IP6_19_16)
115#define GPSR3_11 F_(VI1_DATA7, IP6_15_12)
116#define GPSR3_10 F_(VI1_DATA6, IP6_11_8)
117#define GPSR3_9 F_(VI1_DATA5, IP6_7_4)
118#define GPSR3_8 F_(VI1_DATA4, IP6_3_0)
119#define GPSR3_7 F_(VI1_DATA3, IP5_31_28)
120#define GPSR3_6 F_(VI1_DATA2, IP5_27_24)
121#define GPSR3_5 F_(VI1_DATA1, IP5_23_20)
122#define GPSR3_4 F_(VI1_DATA0, IP5_19_16)
123#define GPSR3_3 F_(VI1_VSYNC_N, IP5_15_12)
124#define GPSR3_2 F_(VI1_HSYNC_N, IP5_11_8)
125#define GPSR3_1 F_(VI1_CLKENB, IP5_7_4)
126#define GPSR3_0 F_(VI1_CLK, IP5_3_0)
127
128/* GPSR4 */
129#define GPSR4_5 F_(SDA2, IP7_27_24)
130#define GPSR4_4 F_(SCL2, IP7_23_20)
131#define GPSR4_3 F_(SDA1, IP7_19_16)
132#define GPSR4_2 F_(SCL1, IP7_15_12)
133#define GPSR4_1 F_(SDA0, IP7_11_8)
134#define GPSR4_0 F_(SCL0, IP7_7_4)
135
136/* GPSR5 */
137#define GPSR5_14 FM(RPC_INT_N)
138#define GPSR5_13 FM(RPC_WP_N)
139#define GPSR5_12 FM(RPC_RESET_N)
140#define GPSR5_11 FM(QSPI1_SSL)
141#define GPSR5_10 FM(QSPI1_IO3)
142#define GPSR5_9 FM(QSPI1_IO2)
143#define GPSR5_8 FM(QSPI1_MISO_IO1)
144#define GPSR5_7 FM(QSPI1_MOSI_IO0)
145#define GPSR5_6 FM(QSPI1_SPCLK)
146#define GPSR5_5 FM(QSPI0_SSL)
147#define GPSR5_4 FM(QSPI0_IO3)
148#define GPSR5_3 FM(QSPI0_IO2)
149#define GPSR5_2 FM(QSPI0_MISO_IO1)
150#define GPSR5_1 FM(QSPI0_MOSI_IO0)
151#define GPSR5_0 FM(QSPI0_SPCLK)
152
153
154/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
155#define IP0_3_0 FM(DU_DR2) FM(HSCK0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
156#define IP0_7_4 FM(DU_DR3) FM(HRTS0_N) F_(0, 0) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
157#define IP0_11_8 FM(DU_DR4) FM(HCTS0_N) F_(0, 0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
158#define IP0_15_12 FM(DU_DR5) FM(HTX0) F_(0, 0) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
159#define IP0_19_16 FM(DU_DR6) FM(MSIOF3_RXD) F_(0, 0) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
160#define IP0_23_20 FM(DU_DR7) FM(MSIOF3_TXD) F_(0, 0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
161#define IP0_27_24 FM(DU_DG2) FM(MSIOF3_SS1) F_(0, 0) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
162#define IP0_31_28 FM(DU_DG3) FM(MSIOF3_SS2) F_(0, 0) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
163#define IP1_3_0 FM(DU_DG4) F_(0, 0) F_(0, 0) FM(A8) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
164#define IP1_7_4 FM(DU_DG5) F_(0, 0) F_(0, 0) FM(A9) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
165#define IP1_11_8 FM(DU_DG6) F_(0, 0) F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
166#define IP1_15_12 FM(DU_DG7) F_(0, 0) F_(0, 0) FM(A11) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
167#define IP1_19_16 FM(DU_DB2) F_(0, 0) F_(0, 0) FM(A12) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
168#define IP1_23_20 FM(DU_DB3) F_(0, 0) F_(0, 0) FM(A13) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
169#define IP1_27_24 FM(DU_DB4) F_(0, 0) F_(0, 0) FM(A14) FM(FXR_CLKOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
170#define IP1_31_28 FM(DU_DB5) F_(0, 0) F_(0, 0) FM(A15) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
171#define IP2_3_0 FM(DU_DB6) F_(0, 0) F_(0, 0) FM(A16) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
172#define IP2_7_4 FM(DU_DB7) F_(0, 0) F_(0, 0) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
173#define IP2_11_8 FM(DU_DOTCLKOUT) FM(SCIF_CLK_A) F_(0, 0) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
174#define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(HRX0) F_(0, 0) FM(A19) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
175#define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
176#define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
177#define IP2_27_24 FM(IRQ0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
178#define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
179#define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
180#define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
181#define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
182#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N_TANS) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
183#define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
184#define IP3_23_20 FM(VI0_DATA2) FM(AVB0_AVTP_PPS) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
185#define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
186#define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
187#define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
188#define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
189#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
190#define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) FM(PWM0_A) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
191#define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) FM(A23) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
192#define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) FM(A24) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
193#define IP4_27_24 FM(VI0_DATA11) FM(HTX2) FM(PWM3_A) FM(A25) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
194#define IP4_31_28 FM(VI0_FIELD) FM(HRX2) FM(PWM4_A) FM(CS1_N) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
195#define IP5_3_0 FM(VI1_CLK) FM(MSIOF1_RXD) F_(0, 0) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
196#define IP5_7_4 FM(VI1_CLKENB) FM(MSIOF1_TXD) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
197#define IP5_11_8 FM(VI1_HSYNC_N) FM(MSIOF1_SCK) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
198#define IP5_15_12 FM(VI1_VSYNC_N) FM(MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
199#define IP5_19_16 FM(VI1_DATA0) FM(MSIOF1_SS1) F_(0, 0) FM(D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
200#define IP5_23_20 FM(VI1_DATA1) FM(MSIOF1_SS2) F_(0, 0) FM(D4) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
201#define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
202#define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
203#define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
204#define IP6_7_4 FM(VI1_DATA5) F_(0,0) FM(SCK4) FM(D8) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
205#define IP6_11_8 FM(VI1_DATA6) F_(0,0) FM(RX4) FM(D9) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
206#define IP6_15_12 FM(VI1_DATA7) F_(0,0) FM(TX4) FM(D10) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
207#define IP6_19_16 FM(VI1_DATA8) F_(0,0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208#define IP6_23_20 FM(VI1_DATA9) F_(0,0) FM(RTS4_N_TANS) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209#define IP6_27_24 FM(VI1_DATA10) F_(0,0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210#define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211#define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212#define IP7_7_4 FM(SCL0) FM(DU_DR0) FM(TPU0TO0) FM(CLKOUT) F_(0, 0) FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213#define IP7_11_8 FM(SDA0) FM(DU_DR1) FM(TPU0TO1) FM(BS_N) FM(SCK0) FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214#define IP7_15_12 FM(SCL1) FM(DU_DG0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215#define IP7_19_16 FM(SDA1) FM(DU_DG1) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N_TANS) FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216#define IP7_23_20 FM(SCL2) FM(DU_DB0) FM(TCLK1_A) FM(WE1_N) FM(RX0) FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217#define IP7_27_24 FM(SDA2) FM(DU_DB1) FM(TCLK2_A) FM(EX_WAIT0) FM(TX0) FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218#define IP7_31_28 FM(AVB0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSCLKST2_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP8_3_0 FM(CANFD0_TX_A) FM(FXR_TXDA) FM(PWM0_B) FM(DU_DISP) FM(FSCLKST2_N_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP8_7_4 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP8_11_8 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP8_15_12 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP8_19_16 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP8_23_20 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP8_27_24 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP8_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227
228#define PINMUX_GPSR \
229\
230 GPSR1_27 \
231 GPSR1_26 \
232 GPSR1_25 \
233 GPSR1_24 \
234 GPSR1_23 \
235 GPSR1_22 \
236GPSR0_21 GPSR1_21 \
237GPSR0_20 GPSR1_20 \
238GPSR0_19 GPSR1_19 \
239GPSR0_18 GPSR1_18 \
240GPSR0_17 GPSR1_17 \
241GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 \
242GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 \
243GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR5_14 \
244GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR5_13 \
245GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR5_12 \
246GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR5_11 \
247GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR5_10 \
248GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR5_9 \
249GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR5_8 \
250GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR5_7 \
251GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR5_6 \
252GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 \
253GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 \
254GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 \
255GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 \
256GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 \
257GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0
258
259#define PINMUX_IPSR \
260\
261FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
262FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
263FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
264FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
265FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
266FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
267FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
268FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
269\
270FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
271FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
272FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
273FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
274FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
275FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
276FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
277FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
278\
279FM(IP8_3_0) IP8_3_0 \
280FM(IP8_7_4) IP8_7_4 \
281FM(IP8_11_8) IP8_11_8 \
282FM(IP8_15_12) IP8_15_12 \
283FM(IP8_19_16) IP8_19_16 \
284FM(IP8_23_20) IP8_23_20 \
285FM(IP8_27_24) IP8_27_24 \
286FM(IP8_31_28) IP8_31_28
287
288/* MOD_SEL0 */ /* 0 */ /* 1 */
289#define MOD_SEL0_11 FM(SEL_I2C3_0) FM(SEL_I2C3_1)
290#define MOD_SEL0_10 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1)
291#define MOD_SEL0_9 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
292#define MOD_SEL0_8 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
293#define MOD_SEL0_7 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
294#define MOD_SEL0_6 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
295#define MOD_SEL0_5 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
296#define MOD_SEL0_4 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
297#define MOD_SEL0_3 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
298#define MOD_SEL0_2 FM(SEL_RFSO_0) FM(SEL_RFSO_1)
299#define MOD_SEL0_1 FM(SEL_RSP_0) FM(SEL_RSP_1)
300#define MOD_SEL0_0 FM(SEL_TMU_0) FM(SEL_TMU_1)
301
302#define PINMUX_MOD_SELS \
303\
304MOD_SEL0_11 \
305MOD_SEL0_10 \
306MOD_SEL0_9 \
307MOD_SEL0_8 \
308MOD_SEL0_7 \
309MOD_SEL0_6 \
310MOD_SEL0_5 \
311MOD_SEL0_4 \
312MOD_SEL0_3 \
313MOD_SEL0_2 \
314MOD_SEL0_1 \
315MOD_SEL0_0
316
317enum {
318 PINMUX_RESERVED = 0,
319
320 PINMUX_DATA_BEGIN,
321 GP_ALL(DATA),
322 PINMUX_DATA_END,
323
324#define F_(x, y)
325#define FM(x) FN_##x,
326 PINMUX_FUNCTION_BEGIN,
327 GP_ALL(FN),
328 PINMUX_GPSR
329 PINMUX_IPSR
330 PINMUX_MOD_SELS
331 PINMUX_FUNCTION_END,
332#undef F_
333#undef FM
334
335#define F_(x, y)
336#define FM(x) x##_MARK,
337 PINMUX_MARK_BEGIN,
338 PINMUX_GPSR
339 PINMUX_IPSR
340 PINMUX_MOD_SELS
341 PINMUX_MARK_END,
342#undef F_
343#undef FM
344};
345
346static const u16 pinmux_data[] = {
347 PINMUX_DATA_GP_ALL(),
348
349 PINMUX_SINGLE(AVB0_RX_CTL),
350 PINMUX_SINGLE(AVB0_RXC),
351 PINMUX_SINGLE(AVB0_RD0),
352 PINMUX_SINGLE(AVB0_RD1),
353 PINMUX_SINGLE(AVB0_RD2),
354 PINMUX_SINGLE(AVB0_RD3),
355 PINMUX_SINGLE(AVB0_TX_CTL),
356 PINMUX_SINGLE(AVB0_TXC),
357 PINMUX_SINGLE(AVB0_TD0),
358 PINMUX_SINGLE(AVB0_TD1),
359 PINMUX_SINGLE(AVB0_TD2),
360 PINMUX_SINGLE(AVB0_TD3),
361 PINMUX_SINGLE(AVB0_TXCREFCLK),
362 PINMUX_SINGLE(AVB0_MDIO),
363 PINMUX_SINGLE(AVB0_MDC),
364 PINMUX_SINGLE(AVB0_MAGIC),
365 PINMUX_SINGLE(AVB0_PHY_INT),
366 PINMUX_SINGLE(AVB0_LINK),
367 PINMUX_SINGLE(AVB0_AVTP_MATCH),
368
369 PINMUX_SINGLE(QSPI0_SPCLK),
370 PINMUX_SINGLE(QSPI0_MOSI_IO0),
371 PINMUX_SINGLE(QSPI0_MISO_IO1),
372 PINMUX_SINGLE(QSPI0_IO2),
373 PINMUX_SINGLE(QSPI0_IO3),
374 PINMUX_SINGLE(QSPI0_SSL),
375 PINMUX_SINGLE(QSPI1_SPCLK),
376 PINMUX_SINGLE(QSPI1_MOSI_IO0),
377 PINMUX_SINGLE(QSPI1_MISO_IO1),
378 PINMUX_SINGLE(QSPI1_IO2),
379 PINMUX_SINGLE(QSPI1_IO3),
380 PINMUX_SINGLE(QSPI1_SSL),
381 PINMUX_SINGLE(RPC_RESET_N),
382 PINMUX_SINGLE(RPC_WP_N),
383 PINMUX_SINGLE(RPC_INT_N),
384
385 /* IPSR0 */
386 PINMUX_IPSR_GPSR(IP0_3_0, DU_DR2),
387 PINMUX_IPSR_GPSR(IP0_3_0, HSCK0),
388 PINMUX_IPSR_GPSR(IP0_3_0, A0),
389
390 PINMUX_IPSR_GPSR(IP0_7_4, DU_DR3),
391 PINMUX_IPSR_GPSR(IP0_7_4, HRTS0_N),
392 PINMUX_IPSR_GPSR(IP0_7_4, A1),
393
394 PINMUX_IPSR_GPSR(IP0_11_8, DU_DR4),
395 PINMUX_IPSR_GPSR(IP0_11_8, HCTS0_N),
396 PINMUX_IPSR_GPSR(IP0_11_8, A2),
397
398 PINMUX_IPSR_GPSR(IP0_15_12, DU_DR5),
399 PINMUX_IPSR_GPSR(IP0_15_12, HTX0),
400 PINMUX_IPSR_GPSR(IP0_15_12, A3),
401
402 PINMUX_IPSR_GPSR(IP0_19_16, DU_DR6),
403 PINMUX_IPSR_GPSR(IP0_19_16, MSIOF3_RXD),
404 PINMUX_IPSR_GPSR(IP0_19_16, A4),
405
406 PINMUX_IPSR_GPSR(IP0_23_20, DU_DR7),
407 PINMUX_IPSR_GPSR(IP0_23_20, MSIOF3_TXD),
408 PINMUX_IPSR_GPSR(IP0_23_20, A5),
409
410 PINMUX_IPSR_GPSR(IP0_27_24, DU_DG2),
411 PINMUX_IPSR_GPSR(IP0_27_24, MSIOF3_SS1),
412 PINMUX_IPSR_GPSR(IP0_27_24, A6),
413
414 PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3),
415 PINMUX_IPSR_GPSR(IP0_31_28, MSIOF3_SS2),
416 PINMUX_IPSR_GPSR(IP0_31_28, A7),
417 PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0),
418
419 /* IPSR1 */
420 PINMUX_IPSR_GPSR(IP1_3_0, DU_DG4),
421 PINMUX_IPSR_GPSR(IP1_3_0, A8),
422 PINMUX_IPSR_MSEL(IP1_3_0, FSO_CFE_0_N_A, SEL_RFSO_0),
423
424 PINMUX_IPSR_GPSR(IP1_7_4, DU_DG5),
425 PINMUX_IPSR_GPSR(IP1_7_4, A9),
426 PINMUX_IPSR_MSEL(IP1_7_4, FSO_CFE_1_N_A, SEL_RFSO_0),
427
428 PINMUX_IPSR_GPSR(IP1_11_8, DU_DG6),
429 PINMUX_IPSR_GPSR(IP1_11_8, A10),
430 PINMUX_IPSR_MSEL(IP1_11_8, FSO_TOE_N_A, SEL_RFSO_0),
431
432 PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7),
433 PINMUX_IPSR_GPSR(IP1_15_12, A11),
434 PINMUX_IPSR_GPSR(IP1_15_12, IRQ1),
435
436 PINMUX_IPSR_GPSR(IP1_19_16, DU_DB2),
437 PINMUX_IPSR_GPSR(IP1_19_16, A12),
438 PINMUX_IPSR_GPSR(IP1_19_16, IRQ2),
439
440 PINMUX_IPSR_GPSR(IP1_23_20, DU_DB3),
441 PINMUX_IPSR_GPSR(IP1_23_20, A13),
442 PINMUX_IPSR_GPSR(IP1_23_20, FXR_CLKOUT1),
443
444 PINMUX_IPSR_GPSR(IP1_27_24, DU_DB4),
445 PINMUX_IPSR_GPSR(IP1_27_24, A14),
446 PINMUX_IPSR_GPSR(IP1_27_24, FXR_CLKOUT2),
447
448 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB5),
449 PINMUX_IPSR_GPSR(IP1_31_28, A15),
450 PINMUX_IPSR_GPSR(IP1_31_28, FXR_TXENA_N),
451
452 /* IPSR2 */
453 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB6),
454 PINMUX_IPSR_GPSR(IP2_3_0, A16),
455 PINMUX_IPSR_GPSR(IP2_3_0, FXR_TXENB_N),
456
457 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB7),
458 PINMUX_IPSR_GPSR(IP2_7_4, A17),
459
460 PINMUX_IPSR_GPSR(IP2_11_8, DU_DOTCLKOUT),
461 PINMUX_IPSR_MSEL(IP2_11_8, SCIF_CLK_A, SEL_HSCIF0_0),
462 PINMUX_IPSR_GPSR(IP2_11_8, A18),
463
464 PINMUX_IPSR_GPSR(IP2_15_12, DU_EXHSYNC_DU_HSYNC),
465 PINMUX_IPSR_GPSR(IP2_15_12, HRX0),
466 PINMUX_IPSR_GPSR(IP2_15_12, A19),
467 PINMUX_IPSR_GPSR(IP2_15_12, IRQ3),
468
469 PINMUX_IPSR_GPSR(IP2_19_16, DU_EXVSYNC_DU_VSYNC),
470 PINMUX_IPSR_GPSR(IP2_19_16, MSIOF3_SCK),
471
472 PINMUX_IPSR_GPSR(IP2_23_20, DU_EXODDF_DU_ODDF_DISP_CDE),
473 PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC),
474
475 PINMUX_IPSR_GPSR(IP2_27_24, IRQ0),
476 PINMUX_IPSR_GPSR(IP2_27_24, CC5_OSCOUT),
477
478 PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK),
479 PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK),
480 PINMUX_IPSR_GPSR(IP2_31_28, SCK3),
481 PINMUX_IPSR_GPSR(IP2_31_28, HSCK3),
482
483 /* IPSR3 */
484 PINMUX_IPSR_GPSR(IP3_3_0, VI0_CLKENB),
485 PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_RXD),
486 PINMUX_IPSR_GPSR(IP3_3_0, RX3),
487 PINMUX_IPSR_GPSR(IP3_3_0, RD_WR_N),
488 PINMUX_IPSR_GPSR(IP3_3_0, HCTS3_N),
489
490 PINMUX_IPSR_GPSR(IP3_7_4, VI0_HSYNC_N),
491 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
492 PINMUX_IPSR_GPSR(IP3_7_4, TX3),
493 PINMUX_IPSR_GPSR(IP3_7_4, HRTS3_N),
494
495 PINMUX_IPSR_GPSR(IP3_11_8, VI0_VSYNC_N),
496 PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_SYNC),
497 PINMUX_IPSR_GPSR(IP3_11_8, CTS3_N),
498 PINMUX_IPSR_GPSR(IP3_11_8, HTX3),
499
500 PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0),
501 PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1),
502 PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N_TANS),
503 PINMUX_IPSR_GPSR(IP3_15_12, HRX3),
504
505 PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1),
506 PINMUX_IPSR_GPSR(IP3_19_16, MSIOF2_SS2),
507 PINMUX_IPSR_GPSR(IP3_19_16, SCK1),
508 PINMUX_IPSR_MSEL(IP3_19_16, SPEEDIN_A, SEL_RSP_0),
509
510 PINMUX_IPSR_GPSR(IP3_23_20, VI0_DATA2),
511 PINMUX_IPSR_GPSR(IP3_23_20, AVB0_AVTP_PPS),
512 PINMUX_IPSR_MSEL(IP3_23_20, SDA3_A, SEL_I2C3_0),
513
514 PINMUX_IPSR_GPSR(IP3_27_24, VI0_DATA3),
515 PINMUX_IPSR_GPSR(IP3_27_24, HSCK1),
516 PINMUX_IPSR_MSEL(IP3_27_24, SCL3_A, SEL_I2C3_0),
517
518 PINMUX_IPSR_GPSR(IP3_31_28, VI0_DATA4),
519 PINMUX_IPSR_GPSR(IP3_31_28, HRTS1_N),
520 PINMUX_IPSR_MSEL(IP3_31_28, RX1_A, SEL_SCIF1_0),
521
522 /* IPSR4 */
523 PINMUX_IPSR_GPSR(IP4_3_0, VI0_DATA5),
524 PINMUX_IPSR_GPSR(IP4_3_0, HCTS1_N),
525 PINMUX_IPSR_MSEL(IP4_3_0, TX1_A, SEL_SCIF1_0),
526
527 PINMUX_IPSR_GPSR(IP4_7_4, VI0_DATA6),
528 PINMUX_IPSR_GPSR(IP4_7_4, HTX1),
529 PINMUX_IPSR_GPSR(IP4_7_4, CTS1_N),
530
531 PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7),
532 PINMUX_IPSR_GPSR(IP4_11_8, HRX1),
533 PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N_TANS),
534
535 PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8),
536 PINMUX_IPSR_GPSR(IP4_15_12, HSCK2),
537 PINMUX_IPSR_MSEL(IP4_15_12, PWM0_A, SEL_PWM0_0),
538
539 PINMUX_IPSR_GPSR(IP4_19_16, VI0_DATA9),
540 PINMUX_IPSR_GPSR(IP4_19_16, HCTS2_N),
541 PINMUX_IPSR_MSEL(IP4_19_16, PWM1_A, SEL_PWM1_0),
542 PINMUX_IPSR_MSEL(IP4_19_16, FSO_CFE_0_N_B, SEL_RFSO_1),
543
544 PINMUX_IPSR_GPSR(IP4_23_20, VI0_DATA10),
545 PINMUX_IPSR_GPSR(IP4_23_20, HRTS2_N),
546 PINMUX_IPSR_MSEL(IP4_23_20, PWM2_A, SEL_PWM2_0),
547 PINMUX_IPSR_MSEL(IP4_23_20, FSO_CFE_1_N_B, SEL_RFSO_1),
548
549 PINMUX_IPSR_GPSR(IP4_27_24, VI0_DATA11),
550 PINMUX_IPSR_GPSR(IP4_27_24, HTX2),
551 PINMUX_IPSR_MSEL(IP4_27_24, PWM3_A, SEL_PWM3_0),
552 PINMUX_IPSR_MSEL(IP4_27_24, FSO_TOE_N_B, SEL_RFSO_1),
553
554 PINMUX_IPSR_GPSR(IP4_31_28, VI0_FIELD),
555 PINMUX_IPSR_GPSR(IP4_31_28, HRX2),
556 PINMUX_IPSR_MSEL(IP4_31_28, PWM4_A, SEL_PWM4_0),
557 PINMUX_IPSR_GPSR(IP4_31_28, CS1_N),
558 PINMUX_IPSR_GPSR(IP4_31_28, FSCLKST2_N_A),
559
560 /* IPSR5 */
561 PINMUX_IPSR_GPSR(IP5_3_0, VI1_CLK),
562 PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD),
563 PINMUX_IPSR_GPSR(IP5_3_0, CS0_N),
564
565 PINMUX_IPSR_GPSR(IP5_7_4, VI1_CLKENB),
566 PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD),
567 PINMUX_IPSR_GPSR(IP5_7_4, D0),
568
569 PINMUX_IPSR_GPSR(IP5_11_8, VI1_HSYNC_N),
570 PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK),
571 PINMUX_IPSR_GPSR(IP5_11_8, D1),
572
573 PINMUX_IPSR_GPSR(IP5_15_12, VI1_VSYNC_N),
574 PINMUX_IPSR_GPSR(IP5_15_12, MSIOF1_SYNC),
575 PINMUX_IPSR_GPSR(IP5_15_12, D2),
576
577 PINMUX_IPSR_GPSR(IP5_19_16, VI1_DATA0),
578 PINMUX_IPSR_GPSR(IP5_19_16, MSIOF1_SS1),
579 PINMUX_IPSR_GPSR(IP5_19_16, D3),
580
581 PINMUX_IPSR_GPSR(IP5_23_20, VI1_DATA1),
582 PINMUX_IPSR_GPSR(IP5_23_20, MSIOF1_SS2),
583 PINMUX_IPSR_GPSR(IP5_23_20, D4),
584 PINMUX_IPSR_GPSR(IP5_23_20, MMC_CMD),
585
586 PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2),
587 PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1),
588 PINMUX_IPSR_GPSR(IP5_27_24, D5),
589 PINMUX_IPSR_GPSR(IP5_27_24, MMC_D0),
590
591 PINMUX_IPSR_GPSR(IP5_31_28, VI1_DATA3),
592 PINMUX_IPSR_MSEL(IP5_31_28, CANFD0_RX_B, SEL_CANFD0_1),
593 PINMUX_IPSR_GPSR(IP5_31_28, D6),
594 PINMUX_IPSR_GPSR(IP5_31_28, MMC_D1),
595
596 /* IPSR6 */
597 PINMUX_IPSR_GPSR(IP6_3_0, VI1_DATA4),
598 PINMUX_IPSR_MSEL(IP6_3_0, CANFD_CLK_B, SEL_CANFD0_1),
599 PINMUX_IPSR_GPSR(IP6_3_0, D7),
600 PINMUX_IPSR_GPSR(IP6_3_0, MMC_D2),
601
602 PINMUX_IPSR_GPSR(IP6_7_4, VI1_DATA5),
603 PINMUX_IPSR_GPSR(IP6_7_4, SCK4),
604 PINMUX_IPSR_GPSR(IP6_7_4, D8),
605 PINMUX_IPSR_GPSR(IP6_7_4, MMC_D3),
606
607 PINMUX_IPSR_GPSR(IP6_11_8, VI1_DATA6),
608 PINMUX_IPSR_GPSR(IP6_11_8, RX4),
609 PINMUX_IPSR_GPSR(IP6_11_8, D9),
610 PINMUX_IPSR_GPSR(IP6_11_8, MMC_CLK),
611
612 PINMUX_IPSR_GPSR(IP6_15_12, VI1_DATA7),
613 PINMUX_IPSR_GPSR(IP6_15_12, TX4),
614 PINMUX_IPSR_GPSR(IP6_15_12, D10),
615 PINMUX_IPSR_GPSR(IP6_15_12, MMC_D4),
616
617 PINMUX_IPSR_GPSR(IP6_19_16, VI1_DATA8),
618 PINMUX_IPSR_GPSR(IP6_19_16, CTS4_N),
619 PINMUX_IPSR_GPSR(IP6_19_16, D11),
620 PINMUX_IPSR_GPSR(IP6_19_16, MMC_D5),
621
622 PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9),
623 PINMUX_IPSR_GPSR(IP6_23_20, RTS4_N_TANS),
624 PINMUX_IPSR_GPSR(IP6_23_20, D12),
625 PINMUX_IPSR_GPSR(IP6_23_20, MMC_D6),
626 PINMUX_IPSR_MSEL(IP6_23_20, SCL3_B, SEL_I2C3_1),
627
628 PINMUX_IPSR_GPSR(IP6_27_24, VI1_DATA10),
629 PINMUX_IPSR_GPSR(IP6_27_24, D13),
630 PINMUX_IPSR_GPSR(IP6_27_24, MMC_D7),
631 PINMUX_IPSR_MSEL(IP6_27_24, SDA3_B, SEL_I2C3_1),
632
633 PINMUX_IPSR_GPSR(IP6_31_28, VI1_DATA11),
634 PINMUX_IPSR_GPSR(IP6_31_28, SCL4),
635 PINMUX_IPSR_GPSR(IP6_31_28, IRQ4),
636 PINMUX_IPSR_GPSR(IP6_31_28, D14),
637 PINMUX_IPSR_GPSR(IP6_31_28, MMC_WP),
638
639 /* IPSR7 */
640 PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD),
641 PINMUX_IPSR_GPSR(IP7_3_0, SDA4),
642 PINMUX_IPSR_GPSR(IP7_3_0, IRQ5),
643 PINMUX_IPSR_GPSR(IP7_3_0, D15),
644 PINMUX_IPSR_GPSR(IP7_3_0, MMC_CD),
645
646 PINMUX_IPSR_GPSR(IP7_7_4, SCL0),
647 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR0),
648 PINMUX_IPSR_GPSR(IP7_7_4, TPU0TO0),
649 PINMUX_IPSR_GPSR(IP7_7_4, CLKOUT),
650 PINMUX_IPSR_GPSR(IP7_7_4, MSIOF0_RXD),
651
652 PINMUX_IPSR_GPSR(IP7_11_8, SDA0),
653 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR1),
654 PINMUX_IPSR_GPSR(IP7_11_8, TPU0TO1),
655 PINMUX_IPSR_GPSR(IP7_11_8, BS_N),
656 PINMUX_IPSR_GPSR(IP7_11_8, SCK0),
657 PINMUX_IPSR_GPSR(IP7_11_8, MSIOF0_TXD),
658
659 PINMUX_IPSR_GPSR(IP7_15_12, SCL1),
660 PINMUX_IPSR_GPSR(IP7_15_12, DU_DG0),
661 PINMUX_IPSR_GPSR(IP7_15_12, TPU0TO2),
662 PINMUX_IPSR_GPSR(IP7_15_12, RD_N),
663 PINMUX_IPSR_GPSR(IP7_15_12, CTS0_N),
664 PINMUX_IPSR_GPSR(IP7_15_12, MSIOF0_SCK),
665
666 PINMUX_IPSR_GPSR(IP7_19_16, SDA1),
667 PINMUX_IPSR_GPSR(IP7_19_16, DU_DG1),
668 PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3),
669 PINMUX_IPSR_GPSR(IP7_19_16, WE0_N),
670 PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N_TANS),
671 PINMUX_IPSR_GPSR(IP7_19_16, MSIOF0_SYNC),
672
673 PINMUX_IPSR_GPSR(IP7_23_20, SCL2),
674 PINMUX_IPSR_GPSR(IP7_23_20, DU_DB0),
675 PINMUX_IPSR_MSEL(IP7_23_20, TCLK1_A, SEL_TMU_0),
676 PINMUX_IPSR_GPSR(IP7_23_20, WE1_N),
677 PINMUX_IPSR_GPSR(IP7_23_20, RX0),
678 PINMUX_IPSR_GPSR(IP7_23_20, MSIOF0_SS1),
679
680 PINMUX_IPSR_GPSR(IP7_27_24, SDA2),
681 PINMUX_IPSR_GPSR(IP7_27_24, DU_DB1),
682 PINMUX_IPSR_MSEL(IP7_27_24, TCLK2_A, SEL_TMU_0),
683 PINMUX_IPSR_GPSR(IP7_27_24, EX_WAIT0),
684 PINMUX_IPSR_GPSR(IP7_27_24, TX0),
685 PINMUX_IPSR_GPSR(IP7_27_24, MSIOF0_SS2),
686
687 PINMUX_IPSR_GPSR(IP7_31_28, AVB0_AVTP_CAPTURE),
688 PINMUX_IPSR_GPSR(IP7_31_28, FSCLKST2_N_B),
689
690 /* IPSR8 */
691 PINMUX_IPSR_MSEL(IP8_3_0, CANFD0_TX_A, SEL_CANFD0_0),
692 PINMUX_IPSR_GPSR(IP8_3_0, FXR_TXDA),
693 PINMUX_IPSR_MSEL(IP8_3_0, PWM0_B, SEL_PWM0_1),
694 PINMUX_IPSR_GPSR(IP8_3_0, DU_DISP),
695 PINMUX_IPSR_GPSR(IP8_3_0, FSCLKST2_N_C),
696
697 PINMUX_IPSR_MSEL(IP8_7_4, CANFD0_RX_A, SEL_CANFD0_0),
698 PINMUX_IPSR_GPSR(IP8_7_4, RXDA_EXTFXR),
699 PINMUX_IPSR_MSEL(IP8_7_4, PWM1_B, SEL_PWM1_1),
700 PINMUX_IPSR_GPSR(IP8_7_4, DU_CDE),
701
702 PINMUX_IPSR_GPSR(IP8_11_8, CANFD1_TX),
703 PINMUX_IPSR_GPSR(IP8_11_8, FXR_TXDB),
704 PINMUX_IPSR_MSEL(IP8_11_8, PWM2_B, SEL_PWM2_1),
705 PINMUX_IPSR_MSEL(IP8_11_8, TCLK1_B, SEL_TMU_1),
706 PINMUX_IPSR_MSEL(IP8_11_8, TX1_B, SEL_SCIF1_1),
707
708 PINMUX_IPSR_GPSR(IP8_15_12, CANFD1_RX),
709 PINMUX_IPSR_GPSR(IP8_15_12, RXDB_EXTFXR),
710 PINMUX_IPSR_MSEL(IP8_15_12, PWM3_B, SEL_PWM3_1),
711 PINMUX_IPSR_MSEL(IP8_15_12, TCLK2_B, SEL_TMU_1),
712 PINMUX_IPSR_MSEL(IP8_15_12, RX1_B, SEL_SCIF1_1),
713
714 PINMUX_IPSR_MSEL(IP8_19_16, CANFD_CLK_A, SEL_CANFD0_0),
715 PINMUX_IPSR_GPSR(IP8_19_16, CLK_EXTFXR),
716 PINMUX_IPSR_MSEL(IP8_19_16, PWM4_B, SEL_PWM4_1),
717 PINMUX_IPSR_MSEL(IP8_19_16, SPEEDIN_B, SEL_RSP_1),
718 PINMUX_IPSR_MSEL(IP8_19_16, SCIF_CLK_B, SEL_HSCIF0_1),
719
720 PINMUX_IPSR_GPSR(IP8_23_20, DIGRF_CLKIN),
721 PINMUX_IPSR_GPSR(IP8_23_20, DIGRF_CLKEN_IN),
722
723 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKOUT),
724 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_OUT),
725};
726
727static const struct sh_pfc_pin pinmux_pins[] = {
728 PINMUX_GPIO_GP_ALL(),
729};
730
731/* - CANFD Clock ------------------------------------------------------------ */
732static const unsigned int canfd_clk_a_pins[] = {
733 /* CANFD_CLK */
734 RCAR_GP_PIN(1, 25),
735};
736static const unsigned int canfd_clk_a_mux[] = {
737 CANFD_CLK_A_MARK,
738};
739static const unsigned int canfd_clk_b_pins[] = {
740 /* CANFD_CLK */
741 RCAR_GP_PIN(3, 8),
742};
743static const unsigned int canfd_clk_b_mux[] = {
744 CANFD_CLK_B_MARK,
745};
746
747/* - CANFD0 ----------------------------------------------------------------- */
748static const unsigned int canfd0_data_a_pins[] = {
749 /* TX, RX */
750 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
751};
752static const unsigned int canfd0_data_a_mux[] = {
753 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
754};
755static const unsigned int canfd0_data_b_pins[] = {
756 /* TX, RX */
757 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
758};
759static const unsigned int canfd0_data_b_mux[] = {
760 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
761};
762
763/* - CANFD1 ----------------------------------------------------------------- */
764static const unsigned int canfd1_data_pins[] = {
765 /* TX, RX */
766 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
767};
768static const unsigned int canfd1_data_mux[] = {
769 CANFD1_TX_MARK, CANFD1_RX_MARK,
770};
771
772/* - DU --------------------------------------------------------------------- */
773static const unsigned int du_rgb666_pins[] = {
774 /* R[7:2], G[7:2], B[7:2] */
775 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
776 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
777 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
778 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
779 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
780 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
781};
782static const unsigned int du_rgb666_mux[] = {
783 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
784 DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
785 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
786 DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
787 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
788 DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
789};
790static const unsigned int du_clk_out_pins[] = {
791 /* DOTCLKOUT */
792 RCAR_GP_PIN(0, 18),
793};
794static const unsigned int du_clk_out_mux[] = {
795 DU_DOTCLKOUT_MARK,
796};
797static const unsigned int du_sync_pins[] = {
798 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
799 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
800};
801static const unsigned int du_sync_mux[] = {
802 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
803};
804static const unsigned int du_oddf_pins[] = {
805 /* EXODDF/ODDF/DISP/CDE */
806 RCAR_GP_PIN(0, 21),
807};
808static const unsigned int du_oddf_mux[] = {
809 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
810};
811static const unsigned int du_cde_pins[] = {
812 /* CDE */
813 RCAR_GP_PIN(1, 22),
814};
815static const unsigned int du_cde_mux[] = {
816 DU_CDE_MARK,
817};
818static const unsigned int du_disp_pins[] = {
819 /* DISP */
820 RCAR_GP_PIN(1, 21),
821};
822static const unsigned int du_disp_mux[] = {
823 DU_DISP_MARK,
824};
825
826/* - HSCIF0 ----------------------------------------------------------------- */
827static const unsigned int hscif0_data_pins[] = {
828 /* HRX, HTX */
829 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 3),
830};
831static const unsigned int hscif0_data_mux[] = {
832 HRX0_MARK, HTX0_MARK,
833};
834static const unsigned int hscif0_clk_pins[] = {
835 /* HSCK */
836 RCAR_GP_PIN(0, 0),
837};
838static const unsigned int hscif0_clk_mux[] = {
839 HSCK0_MARK,
840};
841static const unsigned int hscif0_ctrl_pins[] = {
842 /* HRTS#, HCTS# */
843 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
844};
845static const unsigned int hscif0_ctrl_mux[] = {
846 HRTS0_N_MARK, HCTS0_N_MARK,
847};
848
849/* - HSCIF1 ----------------------------------------------------------------- */
850static const unsigned int hscif1_data_pins[] = {
851 /* HRX, HTX */
852 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
853};
854static const unsigned int hscif1_data_mux[] = {
855 HRX1_MARK, HTX1_MARK,
856};
857static const unsigned int hscif1_clk_pins[] = {
858 /* HSCK */
859 RCAR_GP_PIN(2, 7),
860};
861static const unsigned int hscif1_clk_mux[] = {
862 HSCK1_MARK,
863};
864static const unsigned int hscif1_ctrl_pins[] = {
865 /* HRTS#, HCTS# */
866 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
867};
868static const unsigned int hscif1_ctrl_mux[] = {
869 HRTS1_N_MARK, HCTS1_N_MARK,
870};
871
872/* - HSCIF2 ----------------------------------------------------------------- */
873static const unsigned int hscif2_data_pins[] = {
874 /* HRX, HTX */
875 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
876};
877static const unsigned int hscif2_data_mux[] = {
878 HRX2_MARK, HTX2_MARK,
879};
880static const unsigned int hscif2_clk_pins[] = {
881 /* HSCK */
882 RCAR_GP_PIN(2, 12),
883};
884static const unsigned int hscif2_clk_mux[] = {
885 HSCK2_MARK,
886};
887static const unsigned int hscif2_ctrl_pins[] = {
888 /* HRTS#, HCTS# */
889 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
890};
891static const unsigned int hscif2_ctrl_mux[] = {
892 HRTS2_N_MARK, HCTS2_N_MARK,
893};
894
895/* - HSCIF3 ----------------------------------------------------------------- */
896static const unsigned int hscif3_data_pins[] = {
897 /* HRX, HTX */
898 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
899};
900static const unsigned int hscif3_data_mux[] = {
901 HRX3_MARK, HTX3_MARK,
902};
903static const unsigned int hscif3_clk_pins[] = {
904 /* HSCK */
905 RCAR_GP_PIN(2, 0),
906};
907static const unsigned int hscif3_clk_mux[] = {
908 HSCK3_MARK,
909};
910static const unsigned int hscif3_ctrl_pins[] = {
911 /* HRTS#, HCTS# */
912 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
913};
914static const unsigned int hscif3_ctrl_mux[] = {
915 HRTS3_N_MARK, HCTS3_N_MARK,
916};
917
918/* - I2C0 ------------------------------------------------------------------- */
919static const unsigned int i2c0_pins[] = {
920 /* SDA, SCL */
921 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
922};
923static const unsigned int i2c0_mux[] = {
924 SDA0_MARK, SCL0_MARK,
925};
926
927/* - I2C1 ------------------------------------------------------------------- */
928static const unsigned int i2c1_pins[] = {
929 /* SDA, SCL */
930 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
931};
932static const unsigned int i2c1_mux[] = {
933 SDA1_MARK, SCL1_MARK,
934};
935
936/* - I2C2 ------------------------------------------------------------------- */
937static const unsigned int i2c2_pins[] = {
938 /* SDA, SCL */
939 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
940};
941static const unsigned int i2c2_mux[] = {
942 SDA2_MARK, SCL2_MARK,
943};
944
945/* - I2C3 ------------------------------------------------------------------- */
946static const unsigned int i2c3_a_pins[] = {
947 /* SDA, SCL */
948 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
949};
950static const unsigned int i2c3_a_mux[] = {
951 SDA3_A_MARK, SCL3_A_MARK,
952};
953static const unsigned int i2c3_b_pins[] = {
954 /* SDA, SCL */
955 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
956};
957static const unsigned int i2c3_b_mux[] = {
958 SDA3_B_MARK, SCL3_B_MARK,
959};
960
961/* - I2C4 ------------------------------------------------------------------- */
962static const unsigned int i2c4_pins[] = {
963 /* SDA, SCL */
964 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
965};
966static const unsigned int i2c4_mux[] = {
967 SDA4_MARK, SCL4_MARK,
968};
969
970/* - INTC-EX ---------------------------------------------------------------- */
971static const unsigned int intc_ex_irq0_pins[] = {
972 /* IRQ0 */
973 RCAR_GP_PIN(1, 0),
974};
975static const unsigned int intc_ex_irq0_mux[] = {
976 IRQ0_MARK,
977};
978static const unsigned int intc_ex_irq1_pins[] = {
979 /* IRQ1 */
980 RCAR_GP_PIN(0, 11),
981};
982static const unsigned int intc_ex_irq1_mux[] = {
983 IRQ1_MARK,
984};
985static const unsigned int intc_ex_irq2_pins[] = {
986 /* IRQ2 */
987 RCAR_GP_PIN(0, 12),
988};
989static const unsigned int intc_ex_irq2_mux[] = {
990 IRQ2_MARK,
991};
992static const unsigned int intc_ex_irq3_pins[] = {
993 /* IRQ3 */
994 RCAR_GP_PIN(0, 19),
995};
996static const unsigned int intc_ex_irq3_mux[] = {
997 IRQ3_MARK,
998};
999static const unsigned int intc_ex_irq4_pins[] = {
1000 /* IRQ4 */
1001 RCAR_GP_PIN(3, 15),
1002};
1003static const unsigned int intc_ex_irq4_mux[] = {
1004 IRQ4_MARK,
1005};
1006static const unsigned int intc_ex_irq5_pins[] = {
1007 /* IRQ5 */
1008 RCAR_GP_PIN(3, 16),
1009};
1010static const unsigned int intc_ex_irq5_mux[] = {
1011 IRQ5_MARK,
1012};
1013
1014/* - MMC -------------------------------------------------------------------- */
1015static const unsigned int mmc_data1_pins[] = {
1016 /* D0 */
1017 RCAR_GP_PIN(3, 6),
1018};
1019static const unsigned int mmc_data1_mux[] = {
1020 MMC_D0_MARK,
1021};
1022static const unsigned int mmc_data4_pins[] = {
1023 /* D[0:3] */
1024 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1025 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1026};
1027static const unsigned int mmc_data4_mux[] = {
1028 MMC_D0_MARK, MMC_D1_MARK,
1029 MMC_D2_MARK, MMC_D3_MARK,
1030};
1031static const unsigned int mmc_data8_pins[] = {
1032 /* D[0:7] */
1033 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1034 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1035 RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1036 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1037};
1038static const unsigned int mmc_data8_mux[] = {
1039 MMC_D0_MARK, MMC_D1_MARK,
1040 MMC_D2_MARK, MMC_D3_MARK,
1041 MMC_D4_MARK, MMC_D5_MARK,
1042 MMC_D6_MARK, MMC_D7_MARK,
1043};
1044static const unsigned int mmc_ctrl_pins[] = {
1045 /* CLK, CMD */
1046 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 5),
1047};
1048static const unsigned int mmc_ctrl_mux[] = {
1049 MMC_CLK_MARK, MMC_CMD_MARK,
1050};
1051static const unsigned int mmc_cd_pins[] = {
1052 /* CD */
1053 RCAR_GP_PIN(3, 16),
1054};
1055static const unsigned int mmc_cd_mux[] = {
1056 MMC_CD_MARK,
1057};
1058static const unsigned int mmc_wp_pins[] = {
1059 /* WP */
1060 RCAR_GP_PIN(3, 15),
1061};
1062static const unsigned int mmc_wp_mux[] = {
1063 MMC_WP_MARK,
1064};
1065
1066/* - MSIOF0 ----------------------------------------------------------------- */
1067static const unsigned int msiof0_clk_pins[] = {
1068 /* SCK */
1069 RCAR_GP_PIN(4, 2),
1070};
1071static const unsigned int msiof0_clk_mux[] = {
1072 MSIOF0_SCK_MARK,
1073};
1074static const unsigned int msiof0_sync_pins[] = {
1075 /* SYNC */
1076 RCAR_GP_PIN(4, 3),
1077};
1078static const unsigned int msiof0_sync_mux[] = {
1079 MSIOF0_SYNC_MARK,
1080};
1081static const unsigned int msiof0_ss1_pins[] = {
1082 /* SS1 */
1083 RCAR_GP_PIN(4, 4),
1084};
1085static const unsigned int msiof0_ss1_mux[] = {
1086 MSIOF0_SS1_MARK,
1087};
1088static const unsigned int msiof0_ss2_pins[] = {
1089 /* SS2 */
1090 RCAR_GP_PIN(4, 5),
1091};
1092static const unsigned int msiof0_ss2_mux[] = {
1093 MSIOF0_SS2_MARK,
1094};
1095static const unsigned int msiof0_txd_pins[] = {
1096 /* TXD */
1097 RCAR_GP_PIN(4, 1),
1098};
1099static const unsigned int msiof0_txd_mux[] = {
1100 MSIOF0_TXD_MARK,
1101};
1102static const unsigned int msiof0_rxd_pins[] = {
1103 /* RXD */
1104 RCAR_GP_PIN(4, 0),
1105};
1106static const unsigned int msiof0_rxd_mux[] = {
1107 MSIOF0_RXD_MARK,
1108};
1109
1110/* - MSIOF1 ----------------------------------------------------------------- */
1111static const unsigned int msiof1_clk_pins[] = {
1112 /* SCK */
1113 RCAR_GP_PIN(3, 2),
1114};
1115static const unsigned int msiof1_clk_mux[] = {
1116 MSIOF1_SCK_MARK,
1117};
1118static const unsigned int msiof1_sync_pins[] = {
1119 /* SYNC */
1120 RCAR_GP_PIN(3, 3),
1121};
1122static const unsigned int msiof1_sync_mux[] = {
1123 MSIOF1_SYNC_MARK,
1124};
1125static const unsigned int msiof1_ss1_pins[] = {
1126 /* SS1 */
1127 RCAR_GP_PIN(3, 4),
1128};
1129static const unsigned int msiof1_ss1_mux[] = {
1130 MSIOF1_SS1_MARK,
1131};
1132static const unsigned int msiof1_ss2_pins[] = {
1133 /* SS2 */
1134 RCAR_GP_PIN(3, 5),
1135};
1136static const unsigned int msiof1_ss2_mux[] = {
1137 MSIOF1_SS2_MARK,
1138};
1139static const unsigned int msiof1_txd_pins[] = {
1140 /* TXD */
1141 RCAR_GP_PIN(3, 1),
1142};
1143static const unsigned int msiof1_txd_mux[] = {
1144 MSIOF1_TXD_MARK,
1145};
1146static const unsigned int msiof1_rxd_pins[] = {
1147 /* RXD */
1148 RCAR_GP_PIN(3, 0),
1149};
1150static const unsigned int msiof1_rxd_mux[] = {
1151 MSIOF1_RXD_MARK,
1152};
1153
1154/* - MSIOF2 ----------------------------------------------------------------- */
1155static const unsigned int msiof2_clk_pins[] = {
1156 /* SCK */
1157 RCAR_GP_PIN(2, 0),
1158};
1159static const unsigned int msiof2_clk_mux[] = {
1160 MSIOF2_SCK_MARK,
1161};
1162static const unsigned int msiof2_sync_pins[] = {
1163 /* SYNC */
1164 RCAR_GP_PIN(2, 3),
1165};
1166static const unsigned int msiof2_sync_mux[] = {
1167 MSIOF2_SYNC_MARK,
1168};
1169static const unsigned int msiof2_ss1_pins[] = {
1170 /* SS1 */
1171 RCAR_GP_PIN(2, 4),
1172};
1173static const unsigned int msiof2_ss1_mux[] = {
1174 MSIOF2_SS1_MARK,
1175};
1176static const unsigned int msiof2_ss2_pins[] = {
1177 /* SS2 */
1178 RCAR_GP_PIN(2, 5),
1179};
1180static const unsigned int msiof2_ss2_mux[] = {
1181 MSIOF2_SS2_MARK,
1182};
1183static const unsigned int msiof2_txd_pins[] = {
1184 /* TXD */
1185 RCAR_GP_PIN(2, 2),
1186};
1187static const unsigned int msiof2_txd_mux[] = {
1188 MSIOF2_TXD_MARK,
1189};
1190static const unsigned int msiof2_rxd_pins[] = {
1191 /* RXD */
1192 RCAR_GP_PIN(2, 1),
1193};
1194static const unsigned int msiof2_rxd_mux[] = {
1195 MSIOF2_RXD_MARK,
1196};
1197
1198/* - MSIOF3 ----------------------------------------------------------------- */
1199static const unsigned int msiof3_clk_pins[] = {
1200 /* SCK */
1201 RCAR_GP_PIN(0, 20),
1202};
1203static const unsigned int msiof3_clk_mux[] = {
1204 MSIOF3_SCK_MARK,
1205};
1206static const unsigned int msiof3_sync_pins[] = {
1207 /* SYNC */
1208 RCAR_GP_PIN(0, 21),
1209};
1210static const unsigned int msiof3_sync_mux[] = {
1211 MSIOF3_SYNC_MARK,
1212};
1213static const unsigned int msiof3_ss1_pins[] = {
1214 /* SS1 */
1215 RCAR_GP_PIN(0, 6),
1216};
1217static const unsigned int msiof3_ss1_mux[] = {
1218 MSIOF3_SS1_MARK,
1219};
1220static const unsigned int msiof3_ss2_pins[] = {
1221 /* SS2 */
1222 RCAR_GP_PIN(0, 7),
1223};
1224static const unsigned int msiof3_ss2_mux[] = {
1225 MSIOF3_SS2_MARK,
1226};
1227static const unsigned int msiof3_txd_pins[] = {
1228 /* TXD */
1229 RCAR_GP_PIN(0, 5),
1230};
1231static const unsigned int msiof3_txd_mux[] = {
1232 MSIOF3_TXD_MARK,
1233};
1234static const unsigned int msiof3_rxd_pins[] = {
1235 /* RXD */
1236 RCAR_GP_PIN(0, 4),
1237};
1238static const unsigned int msiof3_rxd_mux[] = {
1239 MSIOF3_RXD_MARK,
1240};
1241
1242/* - PWM0 ------------------------------------------------------------------- */
1243static const unsigned int pwm0_a_pins[] = {
1244 RCAR_GP_PIN(2, 12),
1245};
1246static const unsigned int pwm0_a_mux[] = {
1247 PWM0_A_MARK,
1248};
1249static const unsigned int pwm0_b_pins[] = {
1250 RCAR_GP_PIN(1, 21),
1251};
1252static const unsigned int pwm0_b_mux[] = {
1253 PWM0_B_MARK,
1254};
1255
1256/* - PWM1 ------------------------------------------------------------------- */
1257static const unsigned int pwm1_a_pins[] = {
1258 RCAR_GP_PIN(2, 13),
1259};
1260static const unsigned int pwm1_a_mux[] = {
1261 PWM1_A_MARK,
1262};
1263static const unsigned int pwm1_b_pins[] = {
1264 RCAR_GP_PIN(1, 22),
1265};
1266static const unsigned int pwm1_b_mux[] = {
1267 PWM1_B_MARK,
1268};
1269
1270/* - PWM2 ------------------------------------------------------------------- */
1271static const unsigned int pwm2_a_pins[] = {
1272 RCAR_GP_PIN(2, 14),
1273};
1274static const unsigned int pwm2_a_mux[] = {
1275 PWM2_A_MARK,
1276};
1277static const unsigned int pwm2_b_pins[] = {
1278 RCAR_GP_PIN(1, 23),
1279};
1280static const unsigned int pwm2_b_mux[] = {
1281 PWM2_B_MARK,
1282};
1283
1284/* - PWM3 ------------------------------------------------------------------- */
1285static const unsigned int pwm3_a_pins[] = {
1286 RCAR_GP_PIN(2, 15),
1287};
1288static const unsigned int pwm3_a_mux[] = {
1289 PWM3_A_MARK,
1290};
1291static const unsigned int pwm3_b_pins[] = {
1292 RCAR_GP_PIN(1, 24),
1293};
1294static const unsigned int pwm3_b_mux[] = {
1295 PWM3_B_MARK,
1296};
1297
1298/* - PWM4 ------------------------------------------------------------------- */
1299static const unsigned int pwm4_a_pins[] = {
1300 RCAR_GP_PIN(2, 16),
1301};
1302static const unsigned int pwm4_a_mux[] = {
1303 PWM4_A_MARK,
1304};
1305static const unsigned int pwm4_b_pins[] = {
1306 RCAR_GP_PIN(1, 25),
1307};
1308static const unsigned int pwm4_b_mux[] = {
1309 PWM4_B_MARK,
1310};
1311
1312/* - SCIF Clock ------------------------------------------------------------- */
1313static const unsigned int scif_clk_a_pins[] = {
1314 /* SCIF_CLK */
1315 RCAR_GP_PIN(0, 18),
1316};
1317static const unsigned int scif_clk_a_mux[] = {
1318 SCIF_CLK_A_MARK,
1319};
1320static const unsigned int scif_clk_b_pins[] = {
1321 /* SCIF_CLK */
1322 RCAR_GP_PIN(1, 25),
1323};
1324static const unsigned int scif_clk_b_mux[] = {
1325 SCIF_CLK_B_MARK,
1326};
1327
1328/* - SCIF0 ------------------------------------------------------------------ */
1329static const unsigned int scif0_data_pins[] = {
1330 /* RX, TX */
1331 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1332};
1333static const unsigned int scif0_data_mux[] = {
1334 RX0_MARK, TX0_MARK,
1335};
1336static const unsigned int scif0_clk_pins[] = {
1337 /* SCK */
1338 RCAR_GP_PIN(4, 1),
1339};
1340static const unsigned int scif0_clk_mux[] = {
1341 SCK0_MARK,
1342};
1343static const unsigned int scif0_ctrl_pins[] = {
1344 /* RTS#, CTS# */
1345 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1346};
1347static const unsigned int scif0_ctrl_mux[] = {
1348 RTS0_N_TANS_MARK, CTS0_N_MARK,
1349};
1350
1351/* - SCIF1 ------------------------------------------------------------------ */
1352static const unsigned int scif1_data_a_pins[] = {
1353 /* RX, TX */
1354 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1355};
1356static const unsigned int scif1_data_a_mux[] = {
1357 RX1_A_MARK, TX1_A_MARK,
1358};
1359static const unsigned int scif1_clk_pins[] = {
1360 /* SCK */
1361 RCAR_GP_PIN(2, 5),
1362};
1363static const unsigned int scif1_clk_mux[] = {
1364 SCK1_MARK,
1365};
1366static const unsigned int scif1_ctrl_pins[] = {
1367 /* RTS#, CTS# */
1368 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1369};
1370static const unsigned int scif1_ctrl_mux[] = {
1371 RTS1_N_TANS_MARK, CTS1_N_MARK,
1372};
1373static const unsigned int scif1_data_b_pins[] = {
1374 /* RX, TX */
1375 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
1376};
1377static const unsigned int scif1_data_b_mux[] = {
1378 RX1_B_MARK, TX1_B_MARK,
1379};
1380
1381/* - SCIF3 ------------------------------------------------------------------ */
1382static const unsigned int scif3_data_pins[] = {
1383 /* RX, TX */
1384 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
1385};
1386static const unsigned int scif3_data_mux[] = {
1387 RX3_MARK, TX3_MARK,
1388};
1389static const unsigned int scif3_clk_pins[] = {
1390 /* SCK */
1391 RCAR_GP_PIN(2, 0),
1392};
1393static const unsigned int scif3_clk_mux[] = {
1394 SCK3_MARK,
1395};
1396static const unsigned int scif3_ctrl_pins[] = {
1397 /* RTS#, CTS# */
1398 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1399};
1400static const unsigned int scif3_ctrl_mux[] = {
1401 RTS3_N_TANS_MARK, CTS3_N_MARK,
1402};
1403
1404/* - SCIF4 ------------------------------------------------------------------ */
1405static const unsigned int scif4_data_pins[] = {
1406 /* RX, TX */
1407 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1408};
1409static const unsigned int scif4_data_mux[] = {
1410 RX4_MARK, TX4_MARK,
1411};
1412static const unsigned int scif4_clk_pins[] = {
1413 /* SCK */
1414 RCAR_GP_PIN(3, 9),
1415};
1416static const unsigned int scif4_clk_mux[] = {
1417 SCK4_MARK,
1418};
1419static const unsigned int scif4_ctrl_pins[] = {
1420 /* RTS#, CTS# */
1421 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
1422};
1423static const unsigned int scif4_ctrl_mux[] = {
1424 RTS4_N_TANS_MARK, CTS4_N_MARK,
1425};
1426
1427/* - TMU -------------------------------------------------------------------- */
1428static const unsigned int tmu_tclk1_a_pins[] = {
1429 /* TCLK1 */
1430 RCAR_GP_PIN(4, 4),
1431};
1432static const unsigned int tmu_tclk1_a_mux[] = {
1433 TCLK1_A_MARK,
1434};
1435static const unsigned int tmu_tclk1_b_pins[] = {
1436 /* TCLK1 */
1437 RCAR_GP_PIN(1, 23),
1438};
1439static const unsigned int tmu_tclk1_b_mux[] = {
1440 TCLK1_B_MARK,
1441};
1442static const unsigned int tmu_tclk2_a_pins[] = {
1443 /* TCLK2 */
1444 RCAR_GP_PIN(4, 5),
1445};
1446static const unsigned int tmu_tclk2_a_mux[] = {
1447 TCLK2_A_MARK,
1448};
1449static const unsigned int tmu_tclk2_b_pins[] = {
1450 /* TCLK2 */
1451 RCAR_GP_PIN(1, 24),
1452};
1453static const unsigned int tmu_tclk2_b_mux[] = {
1454 TCLK2_B_MARK,
1455};
1456
1457/* - VIN0 ------------------------------------------------------------------- */
1458static const unsigned int vin0_data8_pins[] = {
1459 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1460 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1461 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1462 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1463};
1464static const unsigned int vin0_data8_mux[] = {
1465 VI0_DATA0_MARK, VI0_DATA1_MARK,
1466 VI0_DATA2_MARK, VI0_DATA3_MARK,
1467 VI0_DATA4_MARK, VI0_DATA5_MARK,
1468 VI0_DATA6_MARK, VI0_DATA7_MARK,
1469};
1470static const unsigned int vin0_data10_pins[] = {
1471 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1472 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1473 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1474 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1475 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1476};
1477static const unsigned int vin0_data10_mux[] = {
1478 VI0_DATA0_MARK, VI0_DATA1_MARK,
1479 VI0_DATA2_MARK, VI0_DATA3_MARK,
1480 VI0_DATA4_MARK, VI0_DATA5_MARK,
1481 VI0_DATA6_MARK, VI0_DATA7_MARK,
1482 VI0_DATA8_MARK, VI0_DATA9_MARK,
1483};
1484static const unsigned int vin0_data12_pins[] = {
1485 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1486 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1487 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1488 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1489 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1490 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1491};
1492static const unsigned int vin0_data12_mux[] = {
1493 VI0_DATA0_MARK, VI0_DATA1_MARK,
1494 VI0_DATA2_MARK, VI0_DATA3_MARK,
1495 VI0_DATA4_MARK, VI0_DATA5_MARK,
1496 VI0_DATA6_MARK, VI0_DATA7_MARK,
1497 VI0_DATA8_MARK, VI0_DATA9_MARK,
1498 VI0_DATA10_MARK, VI0_DATA11_MARK,
1499};
1500static const unsigned int vin0_sync_pins[] = {
1501 /* HSYNC#, VSYNC# */
1502 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1503};
1504static const unsigned int vin0_sync_mux[] = {
1505 VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
1506};
1507static const unsigned int vin0_field_pins[] = {
1508 /* FIELD */
1509 RCAR_GP_PIN(2, 16),
1510};
1511static const unsigned int vin0_field_mux[] = {
1512 VI0_FIELD_MARK,
1513};
1514static const unsigned int vin0_clkenb_pins[] = {
1515 /* CLKENB */
1516 RCAR_GP_PIN(2, 1),
1517};
1518static const unsigned int vin0_clkenb_mux[] = {
1519 VI0_CLKENB_MARK,
1520};
1521static const unsigned int vin0_clk_pins[] = {
1522 /* CLK */
1523 RCAR_GP_PIN(2, 0),
1524};
1525static const unsigned int vin0_clk_mux[] = {
1526 VI0_CLK_MARK,
1527};
1528
1529/* - VIN1 ------------------------------------------------------------------- */
1530static const unsigned int vin1_data8_pins[] = {
1531 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1532 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1533 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1534 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1535};
1536static const unsigned int vin1_data8_mux[] = {
1537 VI1_DATA0_MARK, VI1_DATA1_MARK,
1538 VI1_DATA2_MARK, VI1_DATA3_MARK,
1539 VI1_DATA4_MARK, VI1_DATA5_MARK,
1540 VI1_DATA6_MARK, VI1_DATA7_MARK,
1541};
1542static const unsigned int vin1_data10_pins[] = {
1543 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1544 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1545 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1546 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1547 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1548};
1549static const unsigned int vin1_data10_mux[] = {
1550 VI1_DATA0_MARK, VI1_DATA1_MARK,
1551 VI1_DATA2_MARK, VI1_DATA3_MARK,
1552 VI1_DATA4_MARK, VI1_DATA5_MARK,
1553 VI1_DATA6_MARK, VI1_DATA7_MARK,
1554 VI1_DATA8_MARK, VI1_DATA9_MARK,
1555};
1556static const unsigned int vin1_data12_pins[] = {
1557 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1558 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1559 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1560 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1561 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1562 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
1563};
1564static const unsigned int vin1_data12_mux[] = {
1565 VI1_DATA0_MARK, VI1_DATA1_MARK,
1566 VI1_DATA2_MARK, VI1_DATA3_MARK,
1567 VI1_DATA4_MARK, VI1_DATA5_MARK,
1568 VI1_DATA6_MARK, VI1_DATA7_MARK,
1569 VI1_DATA8_MARK, VI1_DATA9_MARK,
1570 VI1_DATA10_MARK, VI1_DATA11_MARK,
1571};
1572static const unsigned int vin1_sync_pins[] = {
1573 /* HSYNC#, VSYNC# */
1574 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1575};
1576static const unsigned int vin1_sync_mux[] = {
1577 VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
1578};
1579static const unsigned int vin1_field_pins[] = {
1580 RCAR_GP_PIN(3, 16),
1581};
1582static const unsigned int vin1_field_mux[] = {
1583 /* FIELD */
1584 VI1_FIELD_MARK,
1585};
1586static const unsigned int vin1_clkenb_pins[] = {
1587 RCAR_GP_PIN(3, 1),
1588};
1589static const unsigned int vin1_clkenb_mux[] = {
1590 /* CLKENB */
1591 VI1_CLKENB_MARK,
1592};
1593static const unsigned int vin1_clk_pins[] = {
1594 RCAR_GP_PIN(3, 0),
1595};
1596static const unsigned int vin1_clk_mux[] = {
1597 /* CLK */
1598 VI1_CLK_MARK,
1599};
1600
1601static const struct sh_pfc_pin_group pinmux_groups[] = {
1602 SH_PFC_PIN_GROUP(canfd_clk_a),
1603 SH_PFC_PIN_GROUP(canfd_clk_b),
1604 SH_PFC_PIN_GROUP(canfd0_data_a),
1605 SH_PFC_PIN_GROUP(canfd0_data_b),
1606 SH_PFC_PIN_GROUP(canfd1_data),
1607 SH_PFC_PIN_GROUP(du_rgb666),
1608 SH_PFC_PIN_GROUP(du_clk_out),
1609 SH_PFC_PIN_GROUP(du_sync),
1610 SH_PFC_PIN_GROUP(du_oddf),
1611 SH_PFC_PIN_GROUP(du_cde),
1612 SH_PFC_PIN_GROUP(du_disp),
1613 SH_PFC_PIN_GROUP(hscif0_data),
1614 SH_PFC_PIN_GROUP(hscif0_clk),
1615 SH_PFC_PIN_GROUP(hscif0_ctrl),
1616 SH_PFC_PIN_GROUP(hscif1_data),
1617 SH_PFC_PIN_GROUP(hscif1_clk),
1618 SH_PFC_PIN_GROUP(hscif1_ctrl),
1619 SH_PFC_PIN_GROUP(hscif2_data),
1620 SH_PFC_PIN_GROUP(hscif2_clk),
1621 SH_PFC_PIN_GROUP(hscif2_ctrl),
1622 SH_PFC_PIN_GROUP(hscif3_data),
1623 SH_PFC_PIN_GROUP(hscif3_clk),
1624 SH_PFC_PIN_GROUP(hscif3_ctrl),
1625 SH_PFC_PIN_GROUP(i2c0),
1626 SH_PFC_PIN_GROUP(i2c1),
1627 SH_PFC_PIN_GROUP(i2c2),
1628 SH_PFC_PIN_GROUP(i2c3_a),
1629 SH_PFC_PIN_GROUP(i2c3_b),
1630 SH_PFC_PIN_GROUP(i2c4),
1631 SH_PFC_PIN_GROUP(intc_ex_irq0),
1632 SH_PFC_PIN_GROUP(intc_ex_irq1),
1633 SH_PFC_PIN_GROUP(intc_ex_irq2),
1634 SH_PFC_PIN_GROUP(intc_ex_irq3),
1635 SH_PFC_PIN_GROUP(intc_ex_irq4),
1636 SH_PFC_PIN_GROUP(intc_ex_irq5),
1637 SH_PFC_PIN_GROUP(mmc_data1),
1638 SH_PFC_PIN_GROUP(mmc_data4),
1639 SH_PFC_PIN_GROUP(mmc_data8),
1640 SH_PFC_PIN_GROUP(mmc_ctrl),
1641 SH_PFC_PIN_GROUP(mmc_cd),
1642 SH_PFC_PIN_GROUP(mmc_wp),
1643 SH_PFC_PIN_GROUP(msiof0_clk),
1644 SH_PFC_PIN_GROUP(msiof0_sync),
1645 SH_PFC_PIN_GROUP(msiof0_ss1),
1646 SH_PFC_PIN_GROUP(msiof0_ss2),
1647 SH_PFC_PIN_GROUP(msiof0_txd),
1648 SH_PFC_PIN_GROUP(msiof0_rxd),
1649 SH_PFC_PIN_GROUP(msiof1_clk),
1650 SH_PFC_PIN_GROUP(msiof1_sync),
1651 SH_PFC_PIN_GROUP(msiof1_ss1),
1652 SH_PFC_PIN_GROUP(msiof1_ss2),
1653 SH_PFC_PIN_GROUP(msiof1_txd),
1654 SH_PFC_PIN_GROUP(msiof1_rxd),
1655 SH_PFC_PIN_GROUP(msiof2_clk),
1656 SH_PFC_PIN_GROUP(msiof2_sync),
1657 SH_PFC_PIN_GROUP(msiof2_ss1),
1658 SH_PFC_PIN_GROUP(msiof2_ss2),
1659 SH_PFC_PIN_GROUP(msiof2_txd),
1660 SH_PFC_PIN_GROUP(msiof2_rxd),
1661 SH_PFC_PIN_GROUP(msiof3_clk),
1662 SH_PFC_PIN_GROUP(msiof3_sync),
1663 SH_PFC_PIN_GROUP(msiof3_ss1),
1664 SH_PFC_PIN_GROUP(msiof3_ss2),
1665 SH_PFC_PIN_GROUP(msiof3_txd),
1666 SH_PFC_PIN_GROUP(msiof3_rxd),
1667 SH_PFC_PIN_GROUP(pwm0_a),
1668 SH_PFC_PIN_GROUP(pwm0_b),
1669 SH_PFC_PIN_GROUP(pwm1_a),
1670 SH_PFC_PIN_GROUP(pwm1_b),
1671 SH_PFC_PIN_GROUP(pwm2_a),
1672 SH_PFC_PIN_GROUP(pwm2_b),
1673 SH_PFC_PIN_GROUP(pwm3_a),
1674 SH_PFC_PIN_GROUP(pwm3_b),
1675 SH_PFC_PIN_GROUP(pwm4_a),
1676 SH_PFC_PIN_GROUP(pwm4_b),
1677 SH_PFC_PIN_GROUP(scif_clk_a),
1678 SH_PFC_PIN_GROUP(scif_clk_b),
1679 SH_PFC_PIN_GROUP(scif0_data),
1680 SH_PFC_PIN_GROUP(scif0_clk),
1681 SH_PFC_PIN_GROUP(scif0_ctrl),
1682 SH_PFC_PIN_GROUP(scif1_data_a),
1683 SH_PFC_PIN_GROUP(scif1_clk),
1684 SH_PFC_PIN_GROUP(scif1_ctrl),
1685 SH_PFC_PIN_GROUP(scif1_data_b),
1686 SH_PFC_PIN_GROUP(scif3_data),
1687 SH_PFC_PIN_GROUP(scif3_clk),
1688 SH_PFC_PIN_GROUP(scif3_ctrl),
1689 SH_PFC_PIN_GROUP(scif4_data),
1690 SH_PFC_PIN_GROUP(scif4_clk),
1691 SH_PFC_PIN_GROUP(scif4_ctrl),
1692 SH_PFC_PIN_GROUP(tmu_tclk1_a),
1693 SH_PFC_PIN_GROUP(tmu_tclk1_b),
1694 SH_PFC_PIN_GROUP(tmu_tclk2_a),
1695 SH_PFC_PIN_GROUP(tmu_tclk2_b),
1696 SH_PFC_PIN_GROUP(vin0_data8),
1697 SH_PFC_PIN_GROUP(vin0_data10),
1698 SH_PFC_PIN_GROUP(vin0_data12),
1699 SH_PFC_PIN_GROUP(vin0_sync),
1700 SH_PFC_PIN_GROUP(vin0_field),
1701 SH_PFC_PIN_GROUP(vin0_clkenb),
1702 SH_PFC_PIN_GROUP(vin0_clk),
1703 SH_PFC_PIN_GROUP(vin1_data8),
1704 SH_PFC_PIN_GROUP(vin1_data10),
1705 SH_PFC_PIN_GROUP(vin1_data12),
1706 SH_PFC_PIN_GROUP(vin1_sync),
1707 SH_PFC_PIN_GROUP(vin1_field),
1708 SH_PFC_PIN_GROUP(vin1_clkenb),
1709 SH_PFC_PIN_GROUP(vin1_clk),
1710};
1711
1712static const char * const canfd_clk_groups[] = {
1713 "canfd_clk_a",
1714 "canfd_clk_b",
1715};
1716
1717static const char * const canfd0_groups[] = {
1718 "canfd0_data_a",
1719 "canfd0_data_b",
1720};
1721
1722static const char * const canfd1_groups[] = {
1723 "canfd1_data",
1724};
1725
1726static const char * const du_groups[] = {
1727 "du_rgb666",
1728 "du_clk_out",
1729 "du_sync",
1730 "du_oddf",
1731 "du_cde",
1732 "du_disp",
1733};
1734
1735static const char * const hscif0_groups[] = {
1736 "hscif0_data",
1737 "hscif0_clk",
1738 "hscif0_ctrl",
1739};
1740
1741static const char * const hscif1_groups[] = {
1742 "hscif1_data",
1743 "hscif1_clk",
1744 "hscif1_ctrl",
1745};
1746
1747static const char * const hscif2_groups[] = {
1748 "hscif2_data",
1749 "hscif2_clk",
1750 "hscif2_ctrl",
1751};
1752
1753static const char * const hscif3_groups[] = {
1754 "hscif3_data",
1755 "hscif3_clk",
1756 "hscif3_ctrl",
1757};
1758
1759static const char * const i2c0_groups[] = {
1760 "i2c0",
1761};
1762
1763static const char * const i2c1_groups[] = {
1764 "i2c1",
1765};
1766
1767static const char * const i2c2_groups[] = {
1768 "i2c2",
1769};
1770
1771static const char * const i2c3_groups[] = {
1772 "i2c3_a",
1773 "i2c3_b",
1774};
1775
1776static const char * const i2c4_groups[] = {
1777 "i2c4",
1778};
1779
1780static const char * const intc_ex_groups[] = {
1781 "intc_ex_irq0",
1782 "intc_ex_irq1",
1783 "intc_ex_irq2",
1784 "intc_ex_irq3",
1785 "intc_ex_irq4",
1786 "intc_ex_irq5",
1787};
1788
1789static const char * const mmc_groups[] = {
1790 "mmc_data1",
1791 "mmc_data4",
1792 "mmc_data8",
1793 "mmc_ctrl",
1794 "mmc_cd",
1795 "mmc_wp",
1796};
1797
1798static const char * const msiof0_groups[] = {
1799 "msiof0_clk",
1800 "msiof0_sync",
1801 "msiof0_ss1",
1802 "msiof0_ss2",
1803 "msiof0_txd",
1804 "msiof0_rxd",
1805};
1806
1807static const char * const msiof1_groups[] = {
1808 "msiof1_clk",
1809 "msiof1_sync",
1810 "msiof1_ss1",
1811 "msiof1_ss2",
1812 "msiof1_txd",
1813 "msiof1_rxd",
1814};
1815
1816static const char * const msiof2_groups[] = {
1817 "msiof2_clk",
1818 "msiof2_sync",
1819 "msiof2_ss1",
1820 "msiof2_ss2",
1821 "msiof2_txd",
1822 "msiof2_rxd",
1823};
1824
1825static const char * const msiof3_groups[] = {
1826 "msiof3_clk",
1827 "msiof3_sync",
1828 "msiof3_ss1",
1829 "msiof3_ss2",
1830 "msiof3_txd",
1831 "msiof3_rxd",
1832};
1833
1834static const char * const pwm0_groups[] = {
1835 "pwm0_a",
1836 "pwm0_b",
1837};
1838
1839static const char * const pwm1_groups[] = {
1840 "pwm1_a",
1841 "pwm1_b",
1842};
1843
1844static const char * const pwm2_groups[] = {
1845 "pwm2_a",
1846 "pwm2_b",
1847};
1848
1849static const char * const pwm3_groups[] = {
1850 "pwm3_a",
1851 "pwm3_b",
1852};
1853
1854static const char * const pwm4_groups[] = {
1855 "pwm4_a",
1856 "pwm4_b",
1857};
1858
1859static const char * const scif_clk_groups[] = {
1860 "scif_clk_a",
1861 "scif_clk_b",
1862};
1863
1864static const char * const scif0_groups[] = {
1865 "scif0_data",
1866 "scif0_clk",
1867 "scif0_ctrl",
1868};
1869
1870static const char * const scif1_groups[] = {
1871 "scif1_data_a",
1872 "scif1_clk",
1873 "scif1_ctrl",
1874 "scif1_data_b",
1875};
1876
1877static const char * const scif3_groups[] = {
1878 "scif3_data",
1879 "scif3_clk",
1880 "scif3_ctrl",
1881};
1882
1883static const char * const scif4_groups[] = {
1884 "scif4_data",
1885 "scif4_clk",
1886 "scif4_ctrl",
1887};
1888
1889static const char * const tmu_groups[] = {
1890 "tmu_tclk1_a",
1891 "tmu_tclk1_b",
1892 "tmu_tclk2_a",
1893 "tmu_tclk2_b",
1894};
1895
1896static const char * const vin0_groups[] = {
1897 "vin0_data8",
1898 "vin0_data10",
1899 "vin0_data12",
1900 "vin0_sync",
1901 "vin0_field",
1902 "vin0_clkenb",
1903 "vin0_clk",
1904};
1905
1906static const char * const vin1_groups[] = {
1907 "vin1_data8",
1908 "vin1_data10",
1909 "vin1_data12",
1910 "vin1_sync",
1911 "vin1_field",
1912 "vin1_clkenb",
1913 "vin1_clk",
1914};
1915
1916static const struct sh_pfc_function pinmux_functions[] = {
1917 SH_PFC_FUNCTION(canfd_clk),
1918 SH_PFC_FUNCTION(canfd0),
1919 SH_PFC_FUNCTION(canfd1),
1920 SH_PFC_FUNCTION(du),
1921 SH_PFC_FUNCTION(hscif0),
1922 SH_PFC_FUNCTION(hscif1),
1923 SH_PFC_FUNCTION(hscif2),
1924 SH_PFC_FUNCTION(hscif3),
1925 SH_PFC_FUNCTION(i2c0),
1926 SH_PFC_FUNCTION(i2c1),
1927 SH_PFC_FUNCTION(i2c2),
1928 SH_PFC_FUNCTION(i2c3),
1929 SH_PFC_FUNCTION(i2c4),
1930 SH_PFC_FUNCTION(intc_ex),
1931 SH_PFC_FUNCTION(mmc),
1932 SH_PFC_FUNCTION(msiof0),
1933 SH_PFC_FUNCTION(msiof1),
1934 SH_PFC_FUNCTION(msiof2),
1935 SH_PFC_FUNCTION(msiof3),
1936 SH_PFC_FUNCTION(pwm0),
1937 SH_PFC_FUNCTION(pwm1),
1938 SH_PFC_FUNCTION(pwm2),
1939 SH_PFC_FUNCTION(pwm3),
1940 SH_PFC_FUNCTION(pwm4),
1941 SH_PFC_FUNCTION(scif_clk),
1942 SH_PFC_FUNCTION(scif0),
1943 SH_PFC_FUNCTION(scif1),
1944 SH_PFC_FUNCTION(scif3),
1945 SH_PFC_FUNCTION(scif4),
1946 SH_PFC_FUNCTION(tmu),
1947 SH_PFC_FUNCTION(vin0),
1948 SH_PFC_FUNCTION(vin1),
1949};
1950
1951static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1952#define F_(x, y) FN_##y
1953#define FM(x) FN_##x
1954 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
1955 0, 0,
1956 0, 0,
1957 0, 0,
1958 0, 0,
1959 0, 0,
1960 0, 0,
1961 0, 0,
1962 0, 0,
1963 0, 0,
1964 0, 0,
1965 GP_0_21_FN, GPSR0_21,
1966 GP_0_20_FN, GPSR0_20,
1967 GP_0_19_FN, GPSR0_19,
1968 GP_0_18_FN, GPSR0_18,
1969 GP_0_17_FN, GPSR0_17,
1970 GP_0_16_FN, GPSR0_16,
1971 GP_0_15_FN, GPSR0_15,
1972 GP_0_14_FN, GPSR0_14,
1973 GP_0_13_FN, GPSR0_13,
1974 GP_0_12_FN, GPSR0_12,
1975 GP_0_11_FN, GPSR0_11,
1976 GP_0_10_FN, GPSR0_10,
1977 GP_0_9_FN, GPSR0_9,
1978 GP_0_8_FN, GPSR0_8,
1979 GP_0_7_FN, GPSR0_7,
1980 GP_0_6_FN, GPSR0_6,
1981 GP_0_5_FN, GPSR0_5,
1982 GP_0_4_FN, GPSR0_4,
1983 GP_0_3_FN, GPSR0_3,
1984 GP_0_2_FN, GPSR0_2,
1985 GP_0_1_FN, GPSR0_1,
1986 GP_0_0_FN, GPSR0_0, }
1987 },
1988 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
1989 0, 0,
1990 0, 0,
1991 0, 0,
1992 0, 0,
1993 GP_1_27_FN, GPSR1_27,
1994 GP_1_26_FN, GPSR1_26,
1995 GP_1_25_FN, GPSR1_25,
1996 GP_1_24_FN, GPSR1_24,
1997 GP_1_23_FN, GPSR1_23,
1998 GP_1_22_FN, GPSR1_22,
1999 GP_1_21_FN, GPSR1_21,
2000 GP_1_20_FN, GPSR1_20,
2001 GP_1_19_FN, GPSR1_19,
2002 GP_1_18_FN, GPSR1_18,
2003 GP_1_17_FN, GPSR1_17,
2004 GP_1_16_FN, GPSR1_16,
2005 GP_1_15_FN, GPSR1_15,
2006 GP_1_14_FN, GPSR1_14,
2007 GP_1_13_FN, GPSR1_13,
2008 GP_1_12_FN, GPSR1_12,
2009 GP_1_11_FN, GPSR1_11,
2010 GP_1_10_FN, GPSR1_10,
2011 GP_1_9_FN, GPSR1_9,
2012 GP_1_8_FN, GPSR1_8,
2013 GP_1_7_FN, GPSR1_7,
2014 GP_1_6_FN, GPSR1_6,
2015 GP_1_5_FN, GPSR1_5,
2016 GP_1_4_FN, GPSR1_4,
2017 GP_1_3_FN, GPSR1_3,
2018 GP_1_2_FN, GPSR1_2,
2019 GP_1_1_FN, GPSR1_1,
2020 GP_1_0_FN, GPSR1_0, }
2021 },
2022 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
2023 0, 0,
2024 0, 0,
2025 0, 0,
2026 0, 0,
2027 0, 0,
2028 0, 0,
2029 0, 0,
2030 0, 0,
2031 0, 0,
2032 0, 0,
2033 0, 0,
2034 0, 0,
2035 0, 0,
2036 0, 0,
2037 0, 0,
2038 GP_2_16_FN, GPSR2_16,
2039 GP_2_15_FN, GPSR2_15,
2040 GP_2_14_FN, GPSR2_14,
2041 GP_2_13_FN, GPSR2_13,
2042 GP_2_12_FN, GPSR2_12,
2043 GP_2_11_FN, GPSR2_11,
2044 GP_2_10_FN, GPSR2_10,
2045 GP_2_9_FN, GPSR2_9,
2046 GP_2_8_FN, GPSR2_8,
2047 GP_2_7_FN, GPSR2_7,
2048 GP_2_6_FN, GPSR2_6,
2049 GP_2_5_FN, GPSR2_5,
2050 GP_2_4_FN, GPSR2_4,
2051 GP_2_3_FN, GPSR2_3,
2052 GP_2_2_FN, GPSR2_2,
2053 GP_2_1_FN, GPSR2_1,
2054 GP_2_0_FN, GPSR2_0, }
2055 },
2056 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
2057 0, 0,
2058 0, 0,
2059 0, 0,
2060 0, 0,
2061 0, 0,
2062 0, 0,
2063 0, 0,
2064 0, 0,
2065 0, 0,
2066 0, 0,
2067 0, 0,
2068 0, 0,
2069 0, 0,
2070 0, 0,
2071 0, 0,
2072 GP_3_16_FN, GPSR3_16,
2073 GP_3_15_FN, GPSR3_15,
2074 GP_3_14_FN, GPSR3_14,
2075 GP_3_13_FN, GPSR3_13,
2076 GP_3_12_FN, GPSR3_12,
2077 GP_3_11_FN, GPSR3_11,
2078 GP_3_10_FN, GPSR3_10,
2079 GP_3_9_FN, GPSR3_9,
2080 GP_3_8_FN, GPSR3_8,
2081 GP_3_7_FN, GPSR3_7,
2082 GP_3_6_FN, GPSR3_6,
2083 GP_3_5_FN, GPSR3_5,
2084 GP_3_4_FN, GPSR3_4,
2085 GP_3_3_FN, GPSR3_3,
2086 GP_3_2_FN, GPSR3_2,
2087 GP_3_1_FN, GPSR3_1,
2088 GP_3_0_FN, GPSR3_0, }
2089 },
2090 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
2091 0, 0,
2092 0, 0,
2093 0, 0,
2094 0, 0,
2095 0, 0,
2096 0, 0,
2097 0, 0,
2098 0, 0,
2099 0, 0,
2100 0, 0,
2101 0, 0,
2102 0, 0,
2103 0, 0,
2104 0, 0,
2105 0, 0,
2106 0, 0,
2107 0, 0,
2108 0, 0,
2109 0, 0,
2110 0, 0,
2111 0, 0,
2112 0, 0,
2113 0, 0,
2114 0, 0,
2115 0, 0,
2116 0, 0,
2117 GP_4_5_FN, GPSR4_5,
2118 GP_4_4_FN, GPSR4_4,
2119 GP_4_3_FN, GPSR4_3,
2120 GP_4_2_FN, GPSR4_2,
2121 GP_4_1_FN, GPSR4_1,
2122 GP_4_0_FN, GPSR4_0, }
2123 },
2124 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
2125 0, 0,
2126 0, 0,
2127 0, 0,
2128 0, 0,
2129 0, 0,
2130 0, 0,
2131 0, 0,
2132 0, 0,
2133 0, 0,
2134 0, 0,
2135 0, 0,
2136 0, 0,
2137 0, 0,
2138 0, 0,
2139 0, 0,
2140 0, 0,
2141 0, 0,
2142 GP_5_14_FN, GPSR5_14,
2143 GP_5_13_FN, GPSR5_13,
2144 GP_5_12_FN, GPSR5_12,
2145 GP_5_11_FN, GPSR5_11,
2146 GP_5_10_FN, GPSR5_10,
2147 GP_5_9_FN, GPSR5_9,
2148 GP_5_8_FN, GPSR5_8,
2149 GP_5_7_FN, GPSR5_7,
2150 GP_5_6_FN, GPSR5_6,
2151 GP_5_5_FN, GPSR5_5,
2152 GP_5_4_FN, GPSR5_4,
2153 GP_5_3_FN, GPSR5_3,
2154 GP_5_2_FN, GPSR5_2,
2155 GP_5_1_FN, GPSR5_1,
2156 GP_5_0_FN, GPSR5_0, }
2157 },
2158#undef F_
2159#undef FM
2160
2161#define F_(x, y) x,
2162#define FM(x) FN_##x,
2163 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
2164 IP0_31_28
2165 IP0_27_24
2166 IP0_23_20
2167 IP0_19_16
2168 IP0_15_12
2169 IP0_11_8
2170 IP0_7_4
2171 IP0_3_0 }
2172 },
2173 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
2174 IP1_31_28
2175 IP1_27_24
2176 IP1_23_20
2177 IP1_19_16
2178 IP1_15_12
2179 IP1_11_8
2180 IP1_7_4
2181 IP1_3_0 }
2182 },
2183 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
2184 IP2_31_28
2185 IP2_27_24
2186 IP2_23_20
2187 IP2_19_16
2188 IP2_15_12
2189 IP2_11_8
2190 IP2_7_4
2191 IP2_3_0 }
2192 },
2193 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
2194 IP3_31_28
2195 IP3_27_24
2196 IP3_23_20
2197 IP3_19_16
2198 IP3_15_12
2199 IP3_11_8
2200 IP3_7_4
2201 IP3_3_0 }
2202 },
2203 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
2204 IP4_31_28
2205 IP4_27_24
2206 IP4_23_20
2207 IP4_19_16
2208 IP4_15_12
2209 IP4_11_8
2210 IP4_7_4
2211 IP4_3_0 }
2212 },
2213 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
2214 IP5_31_28
2215 IP5_27_24
2216 IP5_23_20
2217 IP5_19_16
2218 IP5_15_12
2219 IP5_11_8
2220 IP5_7_4
2221 IP5_3_0 }
2222 },
2223 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
2224 IP6_31_28
2225 IP6_27_24
2226 IP6_23_20
2227 IP6_19_16
2228 IP6_15_12
2229 IP6_11_8
2230 IP6_7_4
2231 IP6_3_0 }
2232 },
2233 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
2234 IP7_31_28
2235 IP7_27_24
2236 IP7_23_20
2237 IP7_19_16
2238 IP7_15_12
2239 IP7_11_8
2240 IP7_7_4
2241 IP7_3_0 }
2242 },
2243 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
2244 IP8_31_28
2245 IP8_27_24
2246 IP8_23_20
2247 IP8_19_16
2248 IP8_15_12
2249 IP8_11_8
2250 IP8_7_4
2251 IP8_3_0 }
2252 },
2253#undef F_
2254#undef FM
2255
2256#define F_(x, y) x,
2257#define FM(x) FN_##x,
2258 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2259 4, 4, 4, 4,
2260 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
2261 /* RESERVED 31, 30, 29, 28 */
2262 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2263 /* RESERVED 27, 26, 25, 24 */
2264 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2265 /* RESERVED 23, 22, 21, 20 */
2266 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2267 /* RESERVED 19, 18, 17, 16 */
2268 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2269 /* RESERVED 15, 14, 13, 12 */
2270 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2271 MOD_SEL0_11
2272 MOD_SEL0_10
2273 MOD_SEL0_9
2274 MOD_SEL0_8
2275 MOD_SEL0_7
2276 MOD_SEL0_6
2277 MOD_SEL0_5
2278 MOD_SEL0_4
2279 MOD_SEL0_3
2280 MOD_SEL0_2
2281 MOD_SEL0_1
2282 MOD_SEL0_0 }
2283 },
2284 { },
2285};
2286
2287static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
2288 u32 *pocctrl)
2289{
2290 int bit = pin & 0x1f;
2291
2292 *pocctrl = 0xe6060380;
2293 if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
2294 return bit;
2295 if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
2296 return bit + 22;
2297
2298 *pocctrl += 4;
2299 if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
2300 return bit - 10;
2301 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
2302 return bit + 7;
2303
2304 return -EINVAL;
2305}
2306
2307static const struct sh_pfc_soc_operations pinmux_ops = {
2308 .pin_to_pocctrl = r8a77970_pin_to_pocctrl,
2309};
2310
2311const struct sh_pfc_soc_info r8a77970_pinmux_info = {
2312 .name = "r8a77970_pfc",
2313 .ops = &pinmux_ops,
2314 .unlock_reg = 0xe6060000, /* PMMR */
2315
2316 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2317
2318 .pins = pinmux_pins,
2319 .nr_pins = ARRAY_SIZE(pinmux_pins),
2320 .groups = pinmux_groups,
2321 .nr_groups = ARRAY_SIZE(pinmux_groups),
2322 .functions = pinmux_functions,
2323 .nr_functions = ARRAY_SIZE(pinmux_functions),
2324
2325 .cfg_regs = pinmux_config_regs,
2326
2327 .pinmux_data = pinmux_data,
2328 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2329};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
index 89b7541ab1ed..a4927b78a17b 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
@@ -518,6 +518,8 @@ static const u16 pinmux_data[] = {
518 PINMUX_SINGLE(QSPI0_MISO_IO1), 518 PINMUX_SINGLE(QSPI0_MISO_IO1),
519 PINMUX_SINGLE(QSPI0_MOSI_IO0), 519 PINMUX_SINGLE(QSPI0_MOSI_IO0),
520 PINMUX_SINGLE(QSPI0_SPCLK), 520 PINMUX_SINGLE(QSPI0_SPCLK),
521 PINMUX_SINGLE(SCL0),
522 PINMUX_SINGLE(SDA0),
521 523
522 /* IPSR0 */ 524 /* IPSR0 */
523 PINMUX_IPSR_MSEL(IP0_3_0, IRQ0_A, SEL_IRQ_0_0), 525 PINMUX_IPSR_MSEL(IP0_3_0, IRQ0_A, SEL_IRQ_0_0),
@@ -1057,6 +1059,61 @@ static const unsigned int avb0_avtp_capture_b_mux[] = {
1057 AVB0_AVTP_CAPTURE_B_MARK, 1059 AVB0_AVTP_CAPTURE_B_MARK,
1058}; 1060};
1059 1061
1062/* - CAN ------------------------------------------------------------------ */
1063static const unsigned int can0_data_a_pins[] = {
1064 /* TX, RX */
1065 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31),
1066};
1067static const unsigned int can0_data_a_mux[] = {
1068 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1069};
1070static const unsigned int can0_data_b_pins[] = {
1071 /* TX, RX */
1072 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 5),
1073};
1074static const unsigned int can0_data_b_mux[] = {
1075 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1076};
1077static const unsigned int can1_data_a_pins[] = {
1078 /* TX, RX */
1079 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29),
1080};
1081static const unsigned int can1_data_a_mux[] = {
1082 CAN1_TX_A_MARK, CAN1_RX_A_MARK,
1083};
1084static const unsigned int can1_data_b_pins[] = {
1085 /* TX, RX */
1086 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6),
1087};
1088static const unsigned int can1_data_b_mux[] = {
1089 CAN1_TX_B_MARK, CAN1_RX_B_MARK,
1090};
1091
1092/* - CAN Clock -------------------------------------------------------------- */
1093static const unsigned int can_clk_pins[] = {
1094 /* CLK */
1095 RCAR_GP_PIN(5, 2),
1096};
1097static const unsigned int can_clk_mux[] = {
1098 CAN_CLK_MARK,
1099};
1100
1101/* - CAN FD ----------------------------------------------------------------- */
1102static const unsigned int canfd0_data_pins[] = {
1103 /* TX, RX */
1104 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31),
1105};
1106static const unsigned int canfd0_data_mux[] = {
1107 CANFD0_TX_MARK, CANFD0_RX_MARK,
1108};
1109static const unsigned int canfd1_data_pins[] = {
1110 /* TX, RX */
1111 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29),
1112};
1113static const unsigned int canfd1_data_mux[] = {
1114 CANFD1_TX_MARK, CANFD1_RX_MARK,
1115};
1116
1060/* - I2C -------------------------------------------------------------------- */ 1117/* - I2C -------------------------------------------------------------------- */
1061static const unsigned int i2c0_pins[] = { 1118static const unsigned int i2c0_pins[] = {
1062 /* SCL, SDA */ 1119 /* SCL, SDA */
@@ -1504,6 +1561,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
1504 SH_PFC_PIN_GROUP(avb0_avtp_pps_b), 1561 SH_PFC_PIN_GROUP(avb0_avtp_pps_b),
1505 SH_PFC_PIN_GROUP(avb0_avtp_match_b), 1562 SH_PFC_PIN_GROUP(avb0_avtp_match_b),
1506 SH_PFC_PIN_GROUP(avb0_avtp_capture_b), 1563 SH_PFC_PIN_GROUP(avb0_avtp_capture_b),
1564 SH_PFC_PIN_GROUP(can0_data_a),
1565 SH_PFC_PIN_GROUP(can0_data_b),
1566 SH_PFC_PIN_GROUP(can1_data_a),
1567 SH_PFC_PIN_GROUP(can1_data_b),
1568 SH_PFC_PIN_GROUP(can_clk),
1569 SH_PFC_PIN_GROUP(canfd0_data),
1570 SH_PFC_PIN_GROUP(canfd1_data),
1507 SH_PFC_PIN_GROUP(i2c0), 1571 SH_PFC_PIN_GROUP(i2c0),
1508 SH_PFC_PIN_GROUP(i2c1), 1572 SH_PFC_PIN_GROUP(i2c1),
1509 SH_PFC_PIN_GROUP(i2c2_a), 1573 SH_PFC_PIN_GROUP(i2c2_a),
@@ -1581,6 +1645,25 @@ static const char * const avb0_groups[] = {
1581 "avb0_avtp_capture_b", 1645 "avb0_avtp_capture_b",
1582}; 1646};
1583 1647
1648static const char * const can0_groups[] = {
1649 "can0_data_a",
1650 "can0_data_b",
1651};
1652static const char * const can1_groups[] = {
1653 "can1_data_a",
1654 "can1_data_b",
1655};
1656static const char * const can_clk_groups[] = {
1657 "can_clk",
1658};
1659
1660static const char * const canfd0_groups[] = {
1661 "canfd0_data",
1662};
1663static const char * const canfd1_groups[] = {
1664 "canfd1_data",
1665};
1666
1584static const char * const i2c0_groups[] = { 1667static const char * const i2c0_groups[] = {
1585 "i2c0", 1668 "i2c0",
1586}; 1669};
@@ -1691,6 +1774,11 @@ static const char * const usb0_groups[] = {
1691static const struct sh_pfc_function pinmux_functions[] = { 1774static const struct sh_pfc_function pinmux_functions[] = {
1692 SH_PFC_FUNCTION(audio_clk), 1775 SH_PFC_FUNCTION(audio_clk),
1693 SH_PFC_FUNCTION(avb0), 1776 SH_PFC_FUNCTION(avb0),
1777 SH_PFC_FUNCTION(can0),
1778 SH_PFC_FUNCTION(can1),
1779 SH_PFC_FUNCTION(can_clk),
1780 SH_PFC_FUNCTION(canfd0),
1781 SH_PFC_FUNCTION(canfd1),
1694 SH_PFC_FUNCTION(i2c0), 1782 SH_PFC_FUNCTION(i2c0),
1695 SH_PFC_FUNCTION(i2c1), 1783 SH_PFC_FUNCTION(i2c1),
1696 SH_PFC_FUNCTION(i2c2), 1784 SH_PFC_FUNCTION(i2c2),
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 213108a058fe..5747ab0472df 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -283,6 +283,7 @@ extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
283extern const struct sh_pfc_soc_info r8a7795_pinmux_info; 283extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
284extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info; 284extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info;
285extern const struct sh_pfc_soc_info r8a7796_pinmux_info; 285extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
286extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
286extern const struct sh_pfc_soc_info r8a77995_pinmux_info; 287extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
287extern const struct sh_pfc_soc_info sh7203_pinmux_info; 288extern const struct sh_pfc_soc_info sh7203_pinmux_info;
288extern const struct sh_pfc_soc_info sh7264_pinmux_info; 289extern const struct sh_pfc_soc_info sh7264_pinmux_info;
@@ -389,10 +390,14 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
389 PORT_GP_CFG_1(bank, 3, fn, sfx, cfg) 390 PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
390#define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0) 391#define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
391 392
392#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \ 393#define PORT_GP_CFG_6(bank, fn, sfx, cfg) \
393 PORT_GP_CFG_4(bank, fn, sfx, cfg), \ 394 PORT_GP_CFG_4(bank, fn, sfx, cfg), \
394 PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \ 395 PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \
395 PORT_GP_CFG_1(bank, 5, fn, sfx, cfg), \ 396 PORT_GP_CFG_1(bank, 5, fn, sfx, cfg)
397#define PORT_GP_6(bank, fn, sfx) PORT_GP_CFG_6(bank, fn, sfx, 0)
398
399#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
400 PORT_GP_CFG_6(bank, fn, sfx, cfg), \
396 PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), \ 401 PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), \
397 PORT_GP_CFG_1(bank, 7, fn, sfx, cfg) 402 PORT_GP_CFG_1(bank, 7, fn, sfx, cfg)
398#define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0) 403#define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0)
@@ -450,9 +455,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
450 PORT_GP_CFG_1(bank, 20, fn, sfx, cfg) 455 PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
451#define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0) 456#define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0)
452 457
453#define PORT_GP_CFG_23(bank, fn, sfx, cfg) \ 458#define PORT_GP_CFG_22(bank, fn, sfx, cfg) \
454 PORT_GP_CFG_21(bank, fn, sfx, cfg), \ 459 PORT_GP_CFG_21(bank, fn, sfx, cfg), \
455 PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \ 460 PORT_GP_CFG_1(bank, 21, fn, sfx, cfg)
461#define PORT_GP_22(bank, fn, sfx) PORT_GP_CFG_22(bank, fn, sfx, 0)
462
463#define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
464 PORT_GP_CFG_22(bank, fn, sfx, cfg), \
456 PORT_GP_CFG_1(bank, 22, fn, sfx, cfg) 465 PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
457#define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0) 466#define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0)
458 467
diff --git a/drivers/pinctrl/spear/pinctrl-plgpio.c b/drivers/pinctrl/spear/pinctrl-plgpio.c
index 6a0ed8ab33b9..d2123e396b29 100644
--- a/drivers/pinctrl/spear/pinctrl-plgpio.c
+++ b/drivers/pinctrl/spear/pinctrl-plgpio.c
@@ -519,10 +519,8 @@ static int plgpio_probe(struct platform_device *pdev)
519 int ret, irq; 519 int ret, irq;
520 520
521 plgpio = devm_kzalloc(&pdev->dev, sizeof(*plgpio), GFP_KERNEL); 521 plgpio = devm_kzalloc(&pdev->dev, sizeof(*plgpio), GFP_KERNEL);
522 if (!plgpio) { 522 if (!plgpio)
523 dev_err(&pdev->dev, "memory allocation fail\n");
524 return -ENOMEM; 523 return -ENOMEM;
525 }
526 524
527 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 525 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
528 plgpio->base = devm_ioremap_resource(&pdev->dev, res); 526 plgpio->base = devm_ioremap_resource(&pdev->dev, res);
@@ -544,10 +542,8 @@ static int plgpio_probe(struct platform_device *pdev)
544 sizeof(*plgpio->csave_regs) * 542 sizeof(*plgpio->csave_regs) *
545 DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG), 543 DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG),
546 GFP_KERNEL); 544 GFP_KERNEL);
547 if (!plgpio->csave_regs) { 545 if (!plgpio->csave_regs)
548 dev_err(&pdev->dev, "csave registers memory allocation fail\n");
549 return -ENOMEM; 546 return -ENOMEM;
550 }
551#endif 547#endif
552 548
553 platform_set_drvdata(pdev, plgpio); 549 platform_set_drvdata(pdev, plgpio);
diff --git a/drivers/pinctrl/spear/pinctrl-spear.c b/drivers/pinctrl/spear/pinctrl-spear.c
index 4db52ba38d8d..efe79d3f7659 100644
--- a/drivers/pinctrl/spear/pinctrl-spear.c
+++ b/drivers/pinctrl/spear/pinctrl-spear.c
@@ -361,10 +361,8 @@ int spear_pinctrl_probe(struct platform_device *pdev,
361 return -ENODEV; 361 return -ENODEV;
362 362
363 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); 363 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
364 if (!pmx) { 364 if (!pmx)
365 dev_err(&pdev->dev, "Can't alloc spear_pmx\n");
366 return -ENOMEM; 365 return -ENOMEM;
367 }
368 366
369 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 367 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
370 pmx->vbase = devm_ioremap_resource(&pdev->dev, res); 368 pmx->vbase = devm_ioremap_resource(&pdev->dev, res);
diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.c b/drivers/pinctrl/sprd/pinctrl-sprd.c
index 63529911445c..ba1c2ca406e4 100644
--- a/drivers/pinctrl/sprd/pinctrl-sprd.c
+++ b/drivers/pinctrl/sprd/pinctrl-sprd.c
@@ -818,7 +818,7 @@ static void sprd_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
818 818
819 grp = &info->groups[selector]; 819 grp = &info->groups[selector];
820 820
821 seq_printf(s, "\n"); 821 seq_putc(s, '\n');
822 for (i = 0; i < grp->npins; i++, config++) { 822 for (i = 0; i < grp->npins; i++, config++) {
823 unsigned int pin_id = grp->pins[i]; 823 unsigned int pin_id = grp->pins[i];
824 824
diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig
index 7e1fe39a56a5..1c4e00b2eb65 100644
--- a/drivers/pinctrl/stm32/Kconfig
+++ b/drivers/pinctrl/stm32/Kconfig
@@ -27,9 +27,21 @@ config PINCTRL_STM32F746
27 default MACH_STM32F746 27 default MACH_STM32F746
28 select PINCTRL_STM32 28 select PINCTRL_STM32
29 29
30config PINCTRL_STM32F769
31 bool "STMicroelectronics STM32F769 pin control" if COMPILE_TEST && !MACH_STM32F769
32 depends on OF
33 default MACH_STM32F769
34 select PINCTRL_STM32
35
30config PINCTRL_STM32H743 36config PINCTRL_STM32H743
31 bool "STMicroelectronics STM32H743 pin control" if COMPILE_TEST && !MACH_STM32H743 37 bool "STMicroelectronics STM32H743 pin control" if COMPILE_TEST && !MACH_STM32H743
32 depends on OF 38 depends on OF
33 default MACH_STM32H743 39 default MACH_STM32H743
34 select PINCTRL_STM32 40 select PINCTRL_STM32
41
42config PINCTRL_STM32MP157
43 bool "STMicroelectronics STM32MP157 pin control" if COMPILE_TEST && !MACH_STM32MP157
44 depends on OF
45 default MACH_STM32MP157
46 select PINCTRL_STM32
35endif 47endif
diff --git a/drivers/pinctrl/stm32/Makefile b/drivers/pinctrl/stm32/Makefile
index d13ca3573486..f7c56d4b941c 100644
--- a/drivers/pinctrl/stm32/Makefile
+++ b/drivers/pinctrl/stm32/Makefile
@@ -6,4 +6,6 @@ obj-$(CONFIG_PINCTRL_STM32) += pinctrl-stm32.o
6obj-$(CONFIG_PINCTRL_STM32F429) += pinctrl-stm32f429.o 6obj-$(CONFIG_PINCTRL_STM32F429) += pinctrl-stm32f429.o
7obj-$(CONFIG_PINCTRL_STM32F469) += pinctrl-stm32f469.o 7obj-$(CONFIG_PINCTRL_STM32F469) += pinctrl-stm32f469.o
8obj-$(CONFIG_PINCTRL_STM32F746) += pinctrl-stm32f746.o 8obj-$(CONFIG_PINCTRL_STM32F746) += pinctrl-stm32f746.o
9obj-$(CONFIG_PINCTRL_STM32F769) += pinctrl-stm32f769.o
9obj-$(CONFIG_PINCTRL_STM32H743) += pinctrl-stm32h743.o 10obj-$(CONFIG_PINCTRL_STM32H743) += pinctrl-stm32h743.o
11obj-$(CONFIG_PINCTRL_STM32MP157) += pinctrl-stm32mp157.o
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c
index e62ab087bfd8..617df163067f 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -1,7 +1,8 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Copyright (C) Maxime Coquelin 2015 3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics 2017
3 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> 5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * License terms: GNU General Public License (GPL), version 2
5 * 6 *
6 * Heavily based on Mediatek's pinctrl driver 7 * Heavily based on Mediatek's pinctrl driver
7 */ 8 */
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.h b/drivers/pinctrl/stm32/pinctrl-stm32.h
index 8702a9992ce5..473a6238a27b 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.h
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.h
@@ -1,7 +1,8 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Copyright (C) Maxime Coquelin 2015 3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics 2017
3 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> 5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * License terms: GNU General Public License (GPL), version 2
5 */ 6 */
6#ifndef __PINCTRL_STM32_H 7#ifndef __PINCTRL_STM32_H
7#define __PINCTRL_STM32_H 8#define __PINCTRL_STM32_H
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32f429.c b/drivers/pinctrl/stm32/pinctrl-stm32f429.c
index 4bbade25acc6..663a97113c51 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32f429.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32f429.c
@@ -1,7 +1,8 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Copyright (C) Maxime Coquelin 2015 3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics 2017
3 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> 5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * License terms: GNU General Public License (GPL), version 2
5 */ 6 */
6#include <linux/init.h> 7#include <linux/init.h>
7#include <linux/of.h> 8#include <linux/of.h>
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32f469.c b/drivers/pinctrl/stm32/pinctrl-stm32f469.c
index 86c8cebfa9b9..ed5397f6d7f2 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32f469.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32f469.c
@@ -1,7 +1,7 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Copyright (C) Alexandre Torgue 2016 3 * Copyright (C) STMicroelectronics 2017
3 * Author: Alexandre Torgue <alexandre.torgue@st.com> 4 * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
4 * License terms: GNU General Public License (GPL), version 2
5 */ 5 */
6#include <linux/init.h> 6#include <linux/init.h>
7#include <linux/of.h> 7#include <linux/of.h>
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32f746.c b/drivers/pinctrl/stm32/pinctrl-stm32f746.c
index a2fae7357c36..d832aab7ebe1 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32f746.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32f746.c
@@ -1,7 +1,8 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Copyright (C) Maxime Coquelin 2015 3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics 2017
3 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> 5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * License terms: GNU General Public License (GPL), version 2
5 */ 6 */
6#include <linux/init.h> 7#include <linux/init.h>
7#include <linux/of.h> 8#include <linux/of.h>
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32f769.c b/drivers/pinctrl/stm32/pinctrl-stm32f769.c
new file mode 100644
index 000000000000..f81c51c5aedf
--- /dev/null
+++ b/drivers/pinctrl/stm32/pinctrl-stm32f769.c
@@ -0,0 +1,1827 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) STMicroelectronics 2017
4 * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
5 */
6#include <linux/init.h>
7#include <linux/of.h>
8#include <linux/platform_device.h>
9
10#include "pinctrl-stm32.h"
11
12static const struct stm32_desc_pin stm32f769_pins[] = {
13 STM32_PIN(
14 PINCTRL_PIN(0, "PA0"),
15 STM32_FUNCTION(0, "GPIOA0"),
16 STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
17 STM32_FUNCTION(3, "TIM5_CH1"),
18 STM32_FUNCTION(4, "TIM8_ETR"),
19 STM32_FUNCTION(8, "USART2_CTS"),
20 STM32_FUNCTION(9, "UART4_TX"),
21 STM32_FUNCTION(11, "SAI2_SD_B"),
22 STM32_FUNCTION(12, "ETH_MII_CRS"),
23 STM32_FUNCTION(16, "EVENTOUT"),
24 STM32_FUNCTION(17, "ANALOG")
25 ),
26 STM32_PIN(
27 PINCTRL_PIN(1, "PA1"),
28 STM32_FUNCTION(0, "GPIOA1"),
29 STM32_FUNCTION(2, "TIM2_CH2"),
30 STM32_FUNCTION(3, "TIM5_CH2"),
31 STM32_FUNCTION(8, "USART2_RTS"),
32 STM32_FUNCTION(9, "UART4_RX"),
33 STM32_FUNCTION(10, "QUADSPI_BK1_IO3"),
34 STM32_FUNCTION(11, "SAI2_MCLK_B"),
35 STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"),
36 STM32_FUNCTION(15, "LCD_R2"),
37 STM32_FUNCTION(16, "EVENTOUT"),
38 STM32_FUNCTION(17, "ANALOG")
39 ),
40 STM32_PIN(
41 PINCTRL_PIN(2, "PA2"),
42 STM32_FUNCTION(0, "GPIOA2"),
43 STM32_FUNCTION(2, "TIM2_CH3"),
44 STM32_FUNCTION(3, "TIM5_CH3"),
45 STM32_FUNCTION(4, "TIM9_CH1"),
46 STM32_FUNCTION(8, "USART2_TX"),
47 STM32_FUNCTION(9, "SAI2_SCK_B"),
48 STM32_FUNCTION(12, "ETH_MDIO"),
49 STM32_FUNCTION(13, "MDIOS_MDIO"),
50 STM32_FUNCTION(15, "LCD_R1"),
51 STM32_FUNCTION(16, "EVENTOUT"),
52 STM32_FUNCTION(17, "ANALOG")
53 ),
54 STM32_PIN(
55 PINCTRL_PIN(3, "PA3"),
56 STM32_FUNCTION(0, "GPIOA3"),
57 STM32_FUNCTION(2, "TIM2_CH4"),
58 STM32_FUNCTION(3, "TIM5_CH4"),
59 STM32_FUNCTION(4, "TIM9_CH2"),
60 STM32_FUNCTION(8, "USART2_RX"),
61 STM32_FUNCTION(10, "LCD_B2"),
62 STM32_FUNCTION(11, "OTG_HS_ULPI_D0"),
63 STM32_FUNCTION(12, "ETH_MII_COL"),
64 STM32_FUNCTION(15, "LCD_B5"),
65 STM32_FUNCTION(16, "EVENTOUT"),
66 STM32_FUNCTION(17, "ANALOG")
67 ),
68 STM32_PIN(
69 PINCTRL_PIN(4, "PA4"),
70 STM32_FUNCTION(0, "GPIOA4"),
71 STM32_FUNCTION(6, "SPI1_NSS I2S1_WS"),
72 STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"),
73 STM32_FUNCTION(8, "USART2_CK"),
74 STM32_FUNCTION(9, "SPI6_NSS"),
75 STM32_FUNCTION(13, "OTG_HS_SOF"),
76 STM32_FUNCTION(14, "DCMI_HSYNC"),
77 STM32_FUNCTION(15, "LCD_VSYNC"),
78 STM32_FUNCTION(16, "EVENTOUT"),
79 STM32_FUNCTION(17, "ANALOG")
80 ),
81 STM32_PIN(
82 PINCTRL_PIN(5, "PA5"),
83 STM32_FUNCTION(0, "GPIOA5"),
84 STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
85 STM32_FUNCTION(4, "TIM8_CH1N"),
86 STM32_FUNCTION(6, "SPI1_SCK I2S1_CK"),
87 STM32_FUNCTION(9, "SPI6_SCK"),
88 STM32_FUNCTION(11, "OTG_HS_ULPI_CK"),
89 STM32_FUNCTION(15, "LCD_R4"),
90 STM32_FUNCTION(16, "EVENTOUT"),
91 STM32_FUNCTION(17, "ANALOG")
92 ),
93 STM32_PIN(
94 PINCTRL_PIN(6, "PA6"),
95 STM32_FUNCTION(0, "GPIOA6"),
96 STM32_FUNCTION(2, "TIM1_BKIN"),
97 STM32_FUNCTION(3, "TIM3_CH1"),
98 STM32_FUNCTION(4, "TIM8_BKIN"),
99 STM32_FUNCTION(6, "SPI1_MISO"),
100 STM32_FUNCTION(9, "SPI6_MISO"),
101 STM32_FUNCTION(10, "TIM13_CH1"),
102 STM32_FUNCTION(13, "MDIOS_MDC"),
103 STM32_FUNCTION(14, "DCMI_PIXCLK"),
104 STM32_FUNCTION(15, "LCD_G2"),
105 STM32_FUNCTION(16, "EVENTOUT"),
106 STM32_FUNCTION(17, "ANALOG")
107 ),
108 STM32_PIN(
109 PINCTRL_PIN(7, "PA7"),
110 STM32_FUNCTION(0, "GPIOA7"),
111 STM32_FUNCTION(2, "TIM1_CH1N"),
112 STM32_FUNCTION(3, "TIM3_CH2"),
113 STM32_FUNCTION(4, "TIM8_CH1N"),
114 STM32_FUNCTION(6, "SPI1_MOSI I2S1_SD"),
115 STM32_FUNCTION(9, "SPI6_MOSI"),
116 STM32_FUNCTION(10, "TIM14_CH1"),
117 STM32_FUNCTION(12, "ETH_MII_RX_DV ETH_RMII_CRS_DV"),
118 STM32_FUNCTION(13, "FMC_SDNWE"),
119 STM32_FUNCTION(16, "EVENTOUT"),
120 STM32_FUNCTION(17, "ANALOG")
121 ),
122 STM32_PIN(
123 PINCTRL_PIN(8, "PA8"),
124 STM32_FUNCTION(0, "GPIOA8"),
125 STM32_FUNCTION(1, "MCO1"),
126 STM32_FUNCTION(2, "TIM1_CH1"),
127 STM32_FUNCTION(4, "TIM8_BKIN2"),
128 STM32_FUNCTION(5, "I2C3_SCL"),
129 STM32_FUNCTION(8, "USART1_CK"),
130 STM32_FUNCTION(11, "OTG_FS_SOF"),
131 STM32_FUNCTION(12, "CAN3_RX"),
132 STM32_FUNCTION(13, "UART7_RX"),
133 STM32_FUNCTION(14, "LCD_B3"),
134 STM32_FUNCTION(15, "LCD_R6"),
135 STM32_FUNCTION(16, "EVENTOUT"),
136 STM32_FUNCTION(17, "ANALOG")
137 ),
138 STM32_PIN(
139 PINCTRL_PIN(9, "PA9"),
140 STM32_FUNCTION(0, "GPIOA9"),
141 STM32_FUNCTION(2, "TIM1_CH2"),
142 STM32_FUNCTION(5, "I2C3_SMBA"),
143 STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
144 STM32_FUNCTION(8, "USART1_TX"),
145 STM32_FUNCTION(14, "DCMI_D0"),
146 STM32_FUNCTION(15, "LCD_R5"),
147 STM32_FUNCTION(16, "EVENTOUT"),
148 STM32_FUNCTION(17, "ANALOG")
149 ),
150 STM32_PIN(
151 PINCTRL_PIN(10, "PA10"),
152 STM32_FUNCTION(0, "GPIOA10"),
153 STM32_FUNCTION(2, "TIM1_CH3"),
154 STM32_FUNCTION(8, "USART1_RX"),
155 STM32_FUNCTION(10, "LCD_B4"),
156 STM32_FUNCTION(11, "OTG_FS_ID"),
157 STM32_FUNCTION(13, "MDIOS_MDIO"),
158 STM32_FUNCTION(14, "DCMI_D1"),
159 STM32_FUNCTION(15, "LCD_B1"),
160 STM32_FUNCTION(16, "EVENTOUT"),
161 STM32_FUNCTION(17, "ANALOG")
162 ),
163 STM32_PIN(
164 PINCTRL_PIN(11, "PA11"),
165 STM32_FUNCTION(0, "GPIOA11"),
166 STM32_FUNCTION(2, "TIM1_CH4"),
167 STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
168 STM32_FUNCTION(7, "UART4_RX"),
169 STM32_FUNCTION(8, "USART1_CTS"),
170 STM32_FUNCTION(10, "CAN1_RX"),
171 STM32_FUNCTION(11, "OTG_FS_DM"),
172 STM32_FUNCTION(15, "LCD_R4"),
173 STM32_FUNCTION(16, "EVENTOUT"),
174 STM32_FUNCTION(17, "ANALOG")
175 ),
176 STM32_PIN(
177 PINCTRL_PIN(12, "PA12"),
178 STM32_FUNCTION(0, "GPIOA12"),
179 STM32_FUNCTION(2, "TIM1_ETR"),
180 STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
181 STM32_FUNCTION(7, "UART4_TX"),
182 STM32_FUNCTION(8, "USART1_RTS"),
183 STM32_FUNCTION(9, "SAI2_FS_B"),
184 STM32_FUNCTION(10, "CAN1_TX"),
185 STM32_FUNCTION(11, "OTG_FS_DP"),
186 STM32_FUNCTION(15, "LCD_R5"),
187 STM32_FUNCTION(16, "EVENTOUT"),
188 STM32_FUNCTION(17, "ANALOG")
189 ),
190 STM32_PIN(
191 PINCTRL_PIN(13, "PA13"),
192 STM32_FUNCTION(0, "GPIOA13"),
193 STM32_FUNCTION(1, "JTMS SWDIO"),
194 STM32_FUNCTION(16, "EVENTOUT"),
195 STM32_FUNCTION(17, "ANALOG")
196 ),
197 STM32_PIN(
198 PINCTRL_PIN(14, "PA14"),
199 STM32_FUNCTION(0, "GPIOA14"),
200 STM32_FUNCTION(1, "JTCK SWCLK"),
201 STM32_FUNCTION(16, "EVENTOUT"),
202 STM32_FUNCTION(17, "ANALOG")
203 ),
204 STM32_PIN(
205 PINCTRL_PIN(15, "PA15"),
206 STM32_FUNCTION(0, "GPIOA15"),
207 STM32_FUNCTION(1, "JTDI"),
208 STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
209 STM32_FUNCTION(5, "HDMI_CEC"),
210 STM32_FUNCTION(6, "SPI1_NSS I2S1_WS"),
211 STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"),
212 STM32_FUNCTION(8, "SPI6_NSS"),
213 STM32_FUNCTION(9, "UART4_RTS"),
214 STM32_FUNCTION(12, "CAN3_TX"),
215 STM32_FUNCTION(13, "UART7_TX"),
216 STM32_FUNCTION(16, "EVENTOUT"),
217 STM32_FUNCTION(17, "ANALOG")
218 ),
219 STM32_PIN(
220 PINCTRL_PIN(16, "PB0"),
221 STM32_FUNCTION(0, "GPIOB0"),
222 STM32_FUNCTION(2, "TIM1_CH2N"),
223 STM32_FUNCTION(3, "TIM3_CH3"),
224 STM32_FUNCTION(4, "TIM8_CH2N"),
225 STM32_FUNCTION(7, "DFSDM_CKOUT"),
226 STM32_FUNCTION(9, "UART4_CTS"),
227 STM32_FUNCTION(10, "LCD_R3"),
228 STM32_FUNCTION(11, "OTG_HS_ULPI_D1"),
229 STM32_FUNCTION(12, "ETH_MII_RXD2"),
230 STM32_FUNCTION(15, "LCD_G1"),
231 STM32_FUNCTION(16, "EVENTOUT"),
232 STM32_FUNCTION(17, "ANALOG")
233 ),
234 STM32_PIN(
235 PINCTRL_PIN(17, "PB1"),
236 STM32_FUNCTION(0, "GPIOB1"),
237 STM32_FUNCTION(2, "TIM1_CH3N"),
238 STM32_FUNCTION(3, "TIM3_CH4"),
239 STM32_FUNCTION(4, "TIM8_CH3N"),
240 STM32_FUNCTION(7, "DFSDM_DATIN1"),
241 STM32_FUNCTION(10, "LCD_R6"),
242 STM32_FUNCTION(11, "OTG_HS_ULPI_D2"),
243 STM32_FUNCTION(12, "ETH_MII_RXD3"),
244 STM32_FUNCTION(15, "LCD_G0"),
245 STM32_FUNCTION(16, "EVENTOUT"),
246 STM32_FUNCTION(17, "ANALOG")
247 ),
248 STM32_PIN(
249 PINCTRL_PIN(18, "PB2"),
250 STM32_FUNCTION(0, "GPIOB2"),
251 STM32_FUNCTION(7, "SAI1_SD_A"),
252 STM32_FUNCTION(8, "SPI3_MOSI I2S3_SD"),
253 STM32_FUNCTION(10, "QUADSPI_CLK"),
254 STM32_FUNCTION(11, "DFSDM_CKIN1"),
255 STM32_FUNCTION(16, "EVENTOUT"),
256 STM32_FUNCTION(17, "ANALOG")
257 ),
258 STM32_PIN(
259 PINCTRL_PIN(19, "PB3"),
260 STM32_FUNCTION(0, "GPIOB3"),
261 STM32_FUNCTION(1, "JTDO TRACESWO"),
262 STM32_FUNCTION(2, "TIM2_CH2"),
263 STM32_FUNCTION(6, "SPI1_SCK I2S1_CK"),
264 STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"),
265 STM32_FUNCTION(9, "SPI6_SCK"),
266 STM32_FUNCTION(11, "SDMMC2_D2"),
267 STM32_FUNCTION(12, "CAN3_RX"),
268 STM32_FUNCTION(13, "UART7_RX"),
269 STM32_FUNCTION(16, "EVENTOUT"),
270 STM32_FUNCTION(17, "ANALOG")
271 ),
272 STM32_PIN(
273 PINCTRL_PIN(20, "PB4"),
274 STM32_FUNCTION(0, "GPIOB4"),
275 STM32_FUNCTION(1, "NJTRST"),
276 STM32_FUNCTION(3, "TIM3_CH1"),
277 STM32_FUNCTION(6, "SPI1_MISO"),
278 STM32_FUNCTION(7, "SPI3_MISO"),
279 STM32_FUNCTION(8, "SPI2_NSS I2S2_WS"),
280 STM32_FUNCTION(9, "SPI6_MISO"),
281 STM32_FUNCTION(11, "SDMMC2_D3"),
282 STM32_FUNCTION(12, "CAN3_TX"),
283 STM32_FUNCTION(13, "UART7_TX"),
284 STM32_FUNCTION(16, "EVENTOUT"),
285 STM32_FUNCTION(17, "ANALOG")
286 ),
287 STM32_PIN(
288 PINCTRL_PIN(21, "PB5"),
289 STM32_FUNCTION(0, "GPIOB5"),
290 STM32_FUNCTION(2, "UART5_RX"),
291 STM32_FUNCTION(3, "TIM3_CH2"),
292 STM32_FUNCTION(5, "I2C1_SMBA"),
293 STM32_FUNCTION(6, "SPI1_MOSI I2S1_SD"),
294 STM32_FUNCTION(7, "SPI3_MOSI I2S3_SD"),
295 STM32_FUNCTION(9, "SPI6_MOSI"),
296 STM32_FUNCTION(10, "CAN2_RX"),
297 STM32_FUNCTION(11, "OTG_HS_ULPI_D7"),
298 STM32_FUNCTION(12, "ETH_PPS_OUT"),
299 STM32_FUNCTION(13, "FMC_SDCKE1"),
300 STM32_FUNCTION(14, "DCMI_D10"),
301 STM32_FUNCTION(15, "LCD_G7"),
302 STM32_FUNCTION(16, "EVENTOUT"),
303 STM32_FUNCTION(17, "ANALOG")
304 ),
305 STM32_PIN(
306 PINCTRL_PIN(22, "PB6"),
307 STM32_FUNCTION(0, "GPIOB6"),
308 STM32_FUNCTION(2, "UART5_TX"),
309 STM32_FUNCTION(3, "TIM4_CH1"),
310 STM32_FUNCTION(4, "HDMI_CEC"),
311 STM32_FUNCTION(5, "I2C1_SCL"),
312 STM32_FUNCTION(7, "DFSDM_DATIN5"),
313 STM32_FUNCTION(8, "USART1_TX"),
314 STM32_FUNCTION(10, "CAN2_TX"),
315 STM32_FUNCTION(11, "QUADSPI_BK1_NCS"),
316 STM32_FUNCTION(12, "I2C4_SCL"),
317 STM32_FUNCTION(13, "FMC_SDNE1"),
318 STM32_FUNCTION(14, "DCMI_D5"),
319 STM32_FUNCTION(16, "EVENTOUT"),
320 STM32_FUNCTION(17, "ANALOG")
321 ),
322 STM32_PIN(
323 PINCTRL_PIN(23, "PB7"),
324 STM32_FUNCTION(0, "GPIOB7"),
325 STM32_FUNCTION(3, "TIM4_CH2"),
326 STM32_FUNCTION(5, "I2C1_SDA"),
327 STM32_FUNCTION(7, "DFSDM_CKIN5"),
328 STM32_FUNCTION(8, "USART1_RX"),
329 STM32_FUNCTION(12, "I2C4_SDA"),
330 STM32_FUNCTION(13, "FMC_NL"),
331 STM32_FUNCTION(14, "DCMI_VSYNC"),
332 STM32_FUNCTION(16, "EVENTOUT"),
333 STM32_FUNCTION(17, "ANALOG")
334 ),
335 STM32_PIN(
336 PINCTRL_PIN(24, "PB8"),
337 STM32_FUNCTION(0, "GPIOB8"),
338 STM32_FUNCTION(2, "I2C4_SCL"),
339 STM32_FUNCTION(3, "TIM4_CH3"),
340 STM32_FUNCTION(4, "TIM10_CH1"),
341 STM32_FUNCTION(5, "I2C1_SCL"),
342 STM32_FUNCTION(7, "DFSDM_CKIN7"),
343 STM32_FUNCTION(8, "UART5_RX"),
344 STM32_FUNCTION(10, "CAN1_RX"),
345 STM32_FUNCTION(11, "SDMMC2_D4"),
346 STM32_FUNCTION(12, "ETH_MII_TXD3"),
347 STM32_FUNCTION(13, "SDMMC1_D4"),
348 STM32_FUNCTION(14, "DCMI_D6"),
349 STM32_FUNCTION(15, "LCD_B6"),
350 STM32_FUNCTION(16, "EVENTOUT"),
351 STM32_FUNCTION(17, "ANALOG")
352 ),
353 STM32_PIN(
354 PINCTRL_PIN(25, "PB9"),
355 STM32_FUNCTION(0, "GPIOB9"),
356 STM32_FUNCTION(2, "I2C4_SDA"),
357 STM32_FUNCTION(3, "TIM4_CH4"),
358 STM32_FUNCTION(4, "TIM11_CH1"),
359 STM32_FUNCTION(5, "I2C1_SDA"),
360 STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
361 STM32_FUNCTION(7, "DFSDM_DATIN7"),
362 STM32_FUNCTION(8, "UART5_TX"),
363 STM32_FUNCTION(10, "CAN1_TX"),
364 STM32_FUNCTION(11, "SDMMC2_D5"),
365 STM32_FUNCTION(12, "I2C4_SMBA"),
366 STM32_FUNCTION(13, "SDMMC1_D5"),
367 STM32_FUNCTION(14, "DCMI_D7"),
368 STM32_FUNCTION(15, "LCD_B7"),
369 STM32_FUNCTION(16, "EVENTOUT"),
370 STM32_FUNCTION(17, "ANALOG")
371 ),
372 STM32_PIN(
373 PINCTRL_PIN(26, "PB10"),
374 STM32_FUNCTION(0, "GPIOB10"),
375 STM32_FUNCTION(2, "TIM2_CH3"),
376 STM32_FUNCTION(5, "I2C2_SCL"),
377 STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
378 STM32_FUNCTION(7, "DFSDM_DATIN7"),
379 STM32_FUNCTION(8, "USART3_TX"),
380 STM32_FUNCTION(10, "QUADSPI_BK1_NCS"),
381 STM32_FUNCTION(11, "OTG_HS_ULPI_D3"),
382 STM32_FUNCTION(12, "ETH_MII_RX_ER"),
383 STM32_FUNCTION(15, "LCD_G4"),
384 STM32_FUNCTION(16, "EVENTOUT"),
385 STM32_FUNCTION(17, "ANALOG")
386 ),
387 STM32_PIN(
388 PINCTRL_PIN(27, "PB11"),
389 STM32_FUNCTION(0, "GPIOB11"),
390 STM32_FUNCTION(2, "TIM2_CH4"),
391 STM32_FUNCTION(5, "I2C2_SDA"),
392 STM32_FUNCTION(7, "DFSDM_CKIN7"),
393 STM32_FUNCTION(8, "USART3_RX"),
394 STM32_FUNCTION(11, "OTG_HS_ULPI_D4"),
395 STM32_FUNCTION(12, "ETH_MII_TX_EN ETH_RMII_TX_EN"),
396 STM32_FUNCTION(14, "DSI_TE"),
397 STM32_FUNCTION(15, "LCD_G5"),
398 STM32_FUNCTION(16, "EVENTOUT"),
399 STM32_FUNCTION(17, "ANALOG")
400 ),
401 STM32_PIN(
402 PINCTRL_PIN(28, "PB12"),
403 STM32_FUNCTION(0, "GPIOB12"),
404 STM32_FUNCTION(2, "TIM1_BKIN"),
405 STM32_FUNCTION(5, "I2C2_SMBA"),
406 STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
407 STM32_FUNCTION(7, "DFSDM_DATIN1"),
408 STM32_FUNCTION(8, "USART3_CK"),
409 STM32_FUNCTION(9, "UART5_RX"),
410 STM32_FUNCTION(10, "CAN2_RX"),
411 STM32_FUNCTION(11, "OTG_HS_ULPI_D5"),
412 STM32_FUNCTION(12, "ETH_MII_TXD0 ETH_RMII_TXD0"),
413 STM32_FUNCTION(13, "OTG_HS_ID"),
414 STM32_FUNCTION(16, "EVENTOUT"),
415 STM32_FUNCTION(17, "ANALOG")
416 ),
417 STM32_PIN(
418 PINCTRL_PIN(29, "PB13"),
419 STM32_FUNCTION(0, "GPIOB13"),
420 STM32_FUNCTION(2, "TIM1_CH1N"),
421 STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
422 STM32_FUNCTION(7, "DFSDM_CKIN1"),
423 STM32_FUNCTION(8, "USART3_CTS"),
424 STM32_FUNCTION(9, "UART5_TX"),
425 STM32_FUNCTION(10, "CAN2_TX"),
426 STM32_FUNCTION(11, "OTG_HS_ULPI_D6"),
427 STM32_FUNCTION(12, "ETH_MII_TXD1 ETH_RMII_TXD1"),
428 STM32_FUNCTION(16, "EVENTOUT"),
429 STM32_FUNCTION(17, "ANALOG")
430 ),
431 STM32_PIN(
432 PINCTRL_PIN(30, "PB14"),
433 STM32_FUNCTION(0, "GPIOB14"),
434 STM32_FUNCTION(2, "TIM1_CH2N"),
435 STM32_FUNCTION(4, "TIM8_CH2N"),
436 STM32_FUNCTION(5, "USART1_TX"),
437 STM32_FUNCTION(6, "SPI2_MISO"),
438 STM32_FUNCTION(7, "DFSDM_DATIN2"),
439 STM32_FUNCTION(8, "USART3_RTS"),
440 STM32_FUNCTION(9, "UART4_RTS"),
441 STM32_FUNCTION(10, "TIM12_CH1"),
442 STM32_FUNCTION(11, "SDMMC2_D0"),
443 STM32_FUNCTION(13, "OTG_HS_DM"),
444 STM32_FUNCTION(16, "EVENTOUT"),
445 STM32_FUNCTION(17, "ANALOG")
446 ),
447 STM32_PIN(
448 PINCTRL_PIN(31, "PB15"),
449 STM32_FUNCTION(0, "GPIOB15"),
450 STM32_FUNCTION(1, "RTC_REFIN"),
451 STM32_FUNCTION(2, "TIM1_CH3N"),
452 STM32_FUNCTION(4, "TIM8_CH3N"),
453 STM32_FUNCTION(5, "USART1_RX"),
454 STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"),
455 STM32_FUNCTION(7, "DFSDM_CKIN2"),
456 STM32_FUNCTION(9, "UART4_CTS"),
457 STM32_FUNCTION(10, "TIM12_CH2"),
458 STM32_FUNCTION(11, "SDMMC2_D1"),
459 STM32_FUNCTION(13, "OTG_HS_DP"),
460 STM32_FUNCTION(16, "EVENTOUT"),
461 STM32_FUNCTION(17, "ANALOG")
462 ),
463 STM32_PIN(
464 PINCTRL_PIN(32, "PC0"),
465 STM32_FUNCTION(0, "GPIOC0"),
466 STM32_FUNCTION(4, "DFSDM_CKIN0"),
467 STM32_FUNCTION(7, "DFSDM_DATIN4"),
468 STM32_FUNCTION(9, "SAI2_FS_B"),
469 STM32_FUNCTION(11, "OTG_HS_ULPI_STP"),
470 STM32_FUNCTION(13, "FMC_SDNWE"),
471 STM32_FUNCTION(15, "LCD_R5"),
472 STM32_FUNCTION(16, "EVENTOUT"),
473 STM32_FUNCTION(17, "ANALOG")
474 ),
475 STM32_PIN(
476 PINCTRL_PIN(33, "PC1"),
477 STM32_FUNCTION(0, "GPIOC1"),
478 STM32_FUNCTION(1, "TRACED0"),
479 STM32_FUNCTION(4, "DFSDM_DATIN0"),
480 STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"),
481 STM32_FUNCTION(7, "SAI1_SD_A"),
482 STM32_FUNCTION(11, "DFSDM_CKIN4"),
483 STM32_FUNCTION(12, "ETH_MDC"),
484 STM32_FUNCTION(13, "MDIOS_MDC"),
485 STM32_FUNCTION(16, "EVENTOUT"),
486 STM32_FUNCTION(17, "ANALOG")
487 ),
488 STM32_PIN(
489 PINCTRL_PIN(34, "PC2"),
490 STM32_FUNCTION(0, "GPIOC2"),
491 STM32_FUNCTION(4, "DFSDM_CKIN1"),
492 STM32_FUNCTION(6, "SPI2_MISO"),
493 STM32_FUNCTION(7, "DFSDM_CKOUT"),
494 STM32_FUNCTION(11, "OTG_HS_ULPI_DIR"),
495 STM32_FUNCTION(12, "ETH_MII_TXD2"),
496 STM32_FUNCTION(13, "FMC_SDNE0"),
497 STM32_FUNCTION(16, "EVENTOUT"),
498 STM32_FUNCTION(17, "ANALOG")
499 ),
500 STM32_PIN(
501 PINCTRL_PIN(35, "PC3"),
502 STM32_FUNCTION(0, "GPIOC3"),
503 STM32_FUNCTION(4, "DFSDM_DATIN1"),
504 STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"),
505 STM32_FUNCTION(11, "OTG_HS_ULPI_NXT"),
506 STM32_FUNCTION(12, "ETH_MII_TX_CLK"),
507 STM32_FUNCTION(13, "FMC_SDCKE0"),
508 STM32_FUNCTION(16, "EVENTOUT"),
509 STM32_FUNCTION(17, "ANALOG")
510 ),
511 STM32_PIN(
512 PINCTRL_PIN(36, "PC4"),
513 STM32_FUNCTION(0, "GPIOC4"),
514 STM32_FUNCTION(4, "DFSDM_CKIN2"),
515 STM32_FUNCTION(6, "I2S1_MCK"),
516 STM32_FUNCTION(9, "SPDIF_RX2"),
517 STM32_FUNCTION(12, "ETH_MII_RXD0 ETH_RMII_RXD0"),
518 STM32_FUNCTION(13, "FMC_SDNE0"),
519 STM32_FUNCTION(16, "EVENTOUT"),
520 STM32_FUNCTION(17, "ANALOG")
521 ),
522 STM32_PIN(
523 PINCTRL_PIN(37, "PC5"),
524 STM32_FUNCTION(0, "GPIOC5"),
525 STM32_FUNCTION(4, "DFSDM_DATIN2"),
526 STM32_FUNCTION(9, "SPDIF_RX3"),
527 STM32_FUNCTION(12, "ETH_MII_RXD1 ETH_RMII_RXD1"),
528 STM32_FUNCTION(13, "FMC_SDCKE0"),
529 STM32_FUNCTION(16, "EVENTOUT"),
530 STM32_FUNCTION(17, "ANALOG")
531 ),
532 STM32_PIN(
533 PINCTRL_PIN(38, "PC6"),
534 STM32_FUNCTION(0, "GPIOC6"),
535 STM32_FUNCTION(3, "TIM3_CH1"),
536 STM32_FUNCTION(4, "TIM8_CH1"),
537 STM32_FUNCTION(6, "I2S2_MCK"),
538 STM32_FUNCTION(8, "DFSDM_CKIN3"),
539 STM32_FUNCTION(9, "USART6_TX"),
540 STM32_FUNCTION(10, "FMC_NWAIT"),
541 STM32_FUNCTION(11, "SDMMC2_D6"),
542 STM32_FUNCTION(13, "SDMMC1_D6"),
543 STM32_FUNCTION(14, "DCMI_D0"),
544 STM32_FUNCTION(15, "LCD_HSYNC"),
545 STM32_FUNCTION(16, "EVENTOUT"),
546 STM32_FUNCTION(17, "ANALOG")
547 ),
548 STM32_PIN(
549 PINCTRL_PIN(39, "PC7"),
550 STM32_FUNCTION(0, "GPIOC7"),
551 STM32_FUNCTION(3, "TIM3_CH2"),
552 STM32_FUNCTION(4, "TIM8_CH2"),
553 STM32_FUNCTION(7, "I2S3_MCK"),
554 STM32_FUNCTION(8, "DFSDM_DATIN3"),
555 STM32_FUNCTION(9, "USART6_RX"),
556 STM32_FUNCTION(10, "FMC_NE1"),
557 STM32_FUNCTION(11, "SDMMC2_D7"),
558 STM32_FUNCTION(13, "SDMMC1_D7"),
559 STM32_FUNCTION(14, "DCMI_D1"),
560 STM32_FUNCTION(15, "LCD_G6"),
561 STM32_FUNCTION(16, "EVENTOUT"),
562 STM32_FUNCTION(17, "ANALOG")
563 ),
564 STM32_PIN(
565 PINCTRL_PIN(40, "PC8"),
566 STM32_FUNCTION(0, "GPIOC8"),
567 STM32_FUNCTION(1, "TRACED1"),
568 STM32_FUNCTION(3, "TIM3_CH3"),
569 STM32_FUNCTION(4, "TIM8_CH3"),
570 STM32_FUNCTION(8, "UART5_RTS"),
571 STM32_FUNCTION(9, "USART6_CK"),
572 STM32_FUNCTION(10, "FMC_NE2 FMC_NCE"),
573 STM32_FUNCTION(13, "SDMMC1_D0"),
574 STM32_FUNCTION(14, "DCMI_D2"),
575 STM32_FUNCTION(16, "EVENTOUT"),
576 STM32_FUNCTION(17, "ANALOG")
577 ),
578 STM32_PIN(
579 PINCTRL_PIN(41, "PC9"),
580 STM32_FUNCTION(0, "GPIOC9"),
581 STM32_FUNCTION(1, "MCO2"),
582 STM32_FUNCTION(3, "TIM3_CH4"),
583 STM32_FUNCTION(4, "TIM8_CH4"),
584 STM32_FUNCTION(5, "I2C3_SDA"),
585 STM32_FUNCTION(6, "I2S_CKIN"),
586 STM32_FUNCTION(8, "UART5_CTS"),
587 STM32_FUNCTION(10, "QUADSPI_BK1_IO0"),
588 STM32_FUNCTION(11, "LCD_G3"),
589 STM32_FUNCTION(13, "SDMMC1_D1"),
590 STM32_FUNCTION(14, "DCMI_D3"),
591 STM32_FUNCTION(15, "LCD_B2"),
592 STM32_FUNCTION(16, "EVENTOUT"),
593 STM32_FUNCTION(17, "ANALOG")
594 ),
595 STM32_PIN(
596 PINCTRL_PIN(42, "PC10"),
597 STM32_FUNCTION(0, "GPIOC10"),
598 STM32_FUNCTION(4, "DFSDM_CKIN5"),
599 STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"),
600 STM32_FUNCTION(8, "USART3_TX"),
601 STM32_FUNCTION(9, "UART4_TX"),
602 STM32_FUNCTION(10, "QUADSPI_BK1_IO1"),
603 STM32_FUNCTION(13, "SDMMC1_D2"),
604 STM32_FUNCTION(14, "DCMI_D8"),
605 STM32_FUNCTION(15, "LCD_R2"),
606 STM32_FUNCTION(16, "EVENTOUT"),
607 STM32_FUNCTION(17, "ANALOG")
608 ),
609 STM32_PIN(
610 PINCTRL_PIN(43, "PC11"),
611 STM32_FUNCTION(0, "GPIOC11"),
612 STM32_FUNCTION(4, "DFSDM_DATIN5"),
613 STM32_FUNCTION(7, "SPI3_MISO"),
614 STM32_FUNCTION(8, "USART3_RX"),
615 STM32_FUNCTION(9, "UART4_RX"),
616 STM32_FUNCTION(10, "QUADSPI_BK2_NCS"),
617 STM32_FUNCTION(13, "SDMMC1_D3"),
618 STM32_FUNCTION(14, "DCMI_D4"),
619 STM32_FUNCTION(16, "EVENTOUT"),
620 STM32_FUNCTION(17, "ANALOG")
621 ),
622 STM32_PIN(
623 PINCTRL_PIN(44, "PC12"),
624 STM32_FUNCTION(0, "GPIOC12"),
625 STM32_FUNCTION(1, "TRACED3"),
626 STM32_FUNCTION(7, "SPI3_MOSI I2S3_SD"),
627 STM32_FUNCTION(8, "USART3_CK"),
628 STM32_FUNCTION(9, "UART5_TX"),
629 STM32_FUNCTION(13, "SDMMC1_CK"),
630 STM32_FUNCTION(14, "DCMI_D9"),
631 STM32_FUNCTION(16, "EVENTOUT"),
632 STM32_FUNCTION(17, "ANALOG")
633 ),
634 STM32_PIN(
635 PINCTRL_PIN(45, "PC13"),
636 STM32_FUNCTION(0, "GPIOC13"),
637 STM32_FUNCTION(16, "EVENTOUT"),
638 STM32_FUNCTION(17, "ANALOG")
639 ),
640 STM32_PIN(
641 PINCTRL_PIN(46, "PC14"),
642 STM32_FUNCTION(0, "GPIOC14"),
643 STM32_FUNCTION(16, "EVENTOUT"),
644 STM32_FUNCTION(17, "ANALOG")
645 ),
646 STM32_PIN(
647 PINCTRL_PIN(47, "PC15"),
648 STM32_FUNCTION(0, "GPIOC15"),
649 STM32_FUNCTION(16, "EVENTOUT"),
650 STM32_FUNCTION(17, "ANALOG")
651 ),
652 STM32_PIN(
653 PINCTRL_PIN(48, "PD0"),
654 STM32_FUNCTION(0, "GPIOD0"),
655 STM32_FUNCTION(4, "DFSDM_CKIN6"),
656 STM32_FUNCTION(7, "DFSDM_DATIN7"),
657 STM32_FUNCTION(9, "UART4_RX"),
658 STM32_FUNCTION(10, "CAN1_RX"),
659 STM32_FUNCTION(13, "FMC_D2"),
660 STM32_FUNCTION(16, "EVENTOUT"),
661 STM32_FUNCTION(17, "ANALOG")
662 ),
663 STM32_PIN(
664 PINCTRL_PIN(49, "PD1"),
665 STM32_FUNCTION(0, "GPIOD1"),
666 STM32_FUNCTION(4, "DFSDM_DATIN6"),
667 STM32_FUNCTION(7, "DFSDM_CKIN7"),
668 STM32_FUNCTION(9, "UART4_TX"),
669 STM32_FUNCTION(10, "CAN1_TX"),
670 STM32_FUNCTION(13, "FMC_D3"),
671 STM32_FUNCTION(16, "EVENTOUT"),
672 STM32_FUNCTION(17, "ANALOG")
673 ),
674 STM32_PIN(
675 PINCTRL_PIN(50, "PD2"),
676 STM32_FUNCTION(0, "GPIOD2"),
677 STM32_FUNCTION(1, "TRACED2"),
678 STM32_FUNCTION(3, "TIM3_ETR"),
679 STM32_FUNCTION(9, "UART5_RX"),
680 STM32_FUNCTION(13, "SDMMC1_CMD"),
681 STM32_FUNCTION(14, "DCMI_D11"),
682 STM32_FUNCTION(16, "EVENTOUT"),
683 STM32_FUNCTION(17, "ANALOG")
684 ),
685 STM32_PIN(
686 PINCTRL_PIN(51, "PD3"),
687 STM32_FUNCTION(0, "GPIOD3"),
688 STM32_FUNCTION(4, "DFSDM_CKOUT"),
689 STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
690 STM32_FUNCTION(7, "DFSDM_DATIN0"),
691 STM32_FUNCTION(8, "USART2_CTS"),
692 STM32_FUNCTION(13, "FMC_CLK"),
693 STM32_FUNCTION(14, "DCMI_D5"),
694 STM32_FUNCTION(15, "LCD_G7"),
695 STM32_FUNCTION(16, "EVENTOUT"),
696 STM32_FUNCTION(17, "ANALOG")
697 ),
698 STM32_PIN(
699 PINCTRL_PIN(52, "PD4"),
700 STM32_FUNCTION(0, "GPIOD4"),
701 STM32_FUNCTION(7, "DFSDM_CKIN0"),
702 STM32_FUNCTION(8, "USART2_RTS"),
703 STM32_FUNCTION(13, "FMC_NOE"),
704 STM32_FUNCTION(16, "EVENTOUT"),
705 STM32_FUNCTION(17, "ANALOG")
706 ),
707 STM32_PIN(
708 PINCTRL_PIN(53, "PD5"),
709 STM32_FUNCTION(0, "GPIOD5"),
710 STM32_FUNCTION(8, "USART2_TX"),
711 STM32_FUNCTION(13, "FMC_NWE"),
712 STM32_FUNCTION(16, "EVENTOUT"),
713 STM32_FUNCTION(17, "ANALOG")
714 ),
715 STM32_PIN(
716 PINCTRL_PIN(54, "PD6"),
717 STM32_FUNCTION(0, "GPIOD6"),
718 STM32_FUNCTION(4, "DFSDM_CKIN4"),
719 STM32_FUNCTION(6, "SPI3_MOSI I2S3_SD"),
720 STM32_FUNCTION(7, "SAI1_SD_A"),
721 STM32_FUNCTION(8, "USART2_RX"),
722 STM32_FUNCTION(11, "DFSDM_DATIN1"),
723 STM32_FUNCTION(12, "SDMMC2_CK"),
724 STM32_FUNCTION(13, "FMC_NWAIT"),
725 STM32_FUNCTION(14, "DCMI_D10"),
726 STM32_FUNCTION(15, "LCD_B2"),
727 STM32_FUNCTION(16, "EVENTOUT"),
728 STM32_FUNCTION(17, "ANALOG")
729 ),
730 STM32_PIN(
731 PINCTRL_PIN(55, "PD7"),
732 STM32_FUNCTION(0, "GPIOD7"),
733 STM32_FUNCTION(4, "DFSDM_DATIN4"),
734 STM32_FUNCTION(6, "SPI1_MOSI I2S1_SD"),
735 STM32_FUNCTION(7, "DFSDM_CKIN1"),
736 STM32_FUNCTION(8, "USART2_CK"),
737 STM32_FUNCTION(9, "SPDIF_RX0"),
738 STM32_FUNCTION(12, "SDMMC2_CMD"),
739 STM32_FUNCTION(13, "FMC_NE1"),
740 STM32_FUNCTION(16, "EVENTOUT"),
741 STM32_FUNCTION(17, "ANALOG")
742 ),
743 STM32_PIN(
744 PINCTRL_PIN(56, "PD8"),
745 STM32_FUNCTION(0, "GPIOD8"),
746 STM32_FUNCTION(4, "DFSDM_CKIN3"),
747 STM32_FUNCTION(8, "USART3_TX"),
748 STM32_FUNCTION(9, "SPDIF_RX1"),
749 STM32_FUNCTION(13, "FMC_D13"),
750 STM32_FUNCTION(16, "EVENTOUT"),
751 STM32_FUNCTION(17, "ANALOG")
752 ),
753 STM32_PIN(
754 PINCTRL_PIN(57, "PD9"),
755 STM32_FUNCTION(0, "GPIOD9"),
756 STM32_FUNCTION(4, "DFSDM_DATIN3"),
757 STM32_FUNCTION(8, "USART3_RX"),
758 STM32_FUNCTION(13, "FMC_D14"),
759 STM32_FUNCTION(16, "EVENTOUT"),
760 STM32_FUNCTION(17, "ANALOG")
761 ),
762 STM32_PIN(
763 PINCTRL_PIN(58, "PD10"),
764 STM32_FUNCTION(0, "GPIOD10"),
765 STM32_FUNCTION(4, "DFSDM_CKOUT"),
766 STM32_FUNCTION(8, "USART3_CK"),
767 STM32_FUNCTION(13, "FMC_D15"),
768 STM32_FUNCTION(15, "LCD_B3"),
769 STM32_FUNCTION(16, "EVENTOUT"),
770 STM32_FUNCTION(17, "ANALOG")
771 ),
772 STM32_PIN(
773 PINCTRL_PIN(59, "PD11"),
774 STM32_FUNCTION(0, "GPIOD11"),
775 STM32_FUNCTION(5, "I2C4_SMBA"),
776 STM32_FUNCTION(8, "USART3_CTS"),
777 STM32_FUNCTION(10, "QUADSPI_BK1_IO0"),
778 STM32_FUNCTION(11, "SAI2_SD_A"),
779 STM32_FUNCTION(13, "FMC_A16 FMC_CLE"),
780 STM32_FUNCTION(16, "EVENTOUT"),
781 STM32_FUNCTION(17, "ANALOG")
782 ),
783 STM32_PIN(
784 PINCTRL_PIN(60, "PD12"),
785 STM32_FUNCTION(0, "GPIOD12"),
786 STM32_FUNCTION(3, "TIM4_CH1"),
787 STM32_FUNCTION(4, "LPTIM1_IN1"),
788 STM32_FUNCTION(5, "I2C4_SCL"),
789 STM32_FUNCTION(8, "USART3_RTS"),
790 STM32_FUNCTION(10, "QUADSPI_BK1_IO1"),
791 STM32_FUNCTION(11, "SAI2_FS_A"),
792 STM32_FUNCTION(13, "FMC_A17 FMC_ALE"),
793 STM32_FUNCTION(16, "EVENTOUT"),
794 STM32_FUNCTION(17, "ANALOG")
795 ),
796 STM32_PIN(
797 PINCTRL_PIN(61, "PD13"),
798 STM32_FUNCTION(0, "GPIOD13"),
799 STM32_FUNCTION(3, "TIM4_CH2"),
800 STM32_FUNCTION(4, "LPTIM1_OUT"),
801 STM32_FUNCTION(5, "I2C4_SDA"),
802 STM32_FUNCTION(10, "QUADSPI_BK1_IO3"),
803 STM32_FUNCTION(11, "SAI2_SCK_A"),
804 STM32_FUNCTION(13, "FMC_A18"),
805 STM32_FUNCTION(16, "EVENTOUT"),
806 STM32_FUNCTION(17, "ANALOG")
807 ),
808 STM32_PIN(
809 PINCTRL_PIN(62, "PD14"),
810 STM32_FUNCTION(0, "GPIOD14"),
811 STM32_FUNCTION(3, "TIM4_CH3"),
812 STM32_FUNCTION(9, "UART8_CTS"),
813 STM32_FUNCTION(13, "FMC_D0"),
814 STM32_FUNCTION(16, "EVENTOUT"),
815 STM32_FUNCTION(17, "ANALOG")
816 ),
817 STM32_PIN(
818 PINCTRL_PIN(63, "PD15"),
819 STM32_FUNCTION(0, "GPIOD15"),
820 STM32_FUNCTION(3, "TIM4_CH4"),
821 STM32_FUNCTION(9, "UART8_RTS"),
822 STM32_FUNCTION(13, "FMC_D1"),
823 STM32_FUNCTION(16, "EVENTOUT"),
824 STM32_FUNCTION(17, "ANALOG")
825 ),
826 STM32_PIN(
827 PINCTRL_PIN(64, "PE0"),
828 STM32_FUNCTION(0, "GPIOE0"),
829 STM32_FUNCTION(3, "TIM4_ETR"),
830 STM32_FUNCTION(4, "LPTIM1_ETR"),
831 STM32_FUNCTION(9, "UART8_RX"),
832 STM32_FUNCTION(11, "SAI2_MCLK_A"),
833 STM32_FUNCTION(13, "FMC_NBL0"),
834 STM32_FUNCTION(14, "DCMI_D2"),
835 STM32_FUNCTION(16, "EVENTOUT"),
836 STM32_FUNCTION(17, "ANALOG")
837 ),
838 STM32_PIN(
839 PINCTRL_PIN(65, "PE1"),
840 STM32_FUNCTION(0, "GPIOE1"),
841 STM32_FUNCTION(4, "LPTIM1_IN2"),
842 STM32_FUNCTION(9, "UART8_TX"),
843 STM32_FUNCTION(13, "FMC_NBL1"),
844 STM32_FUNCTION(14, "DCMI_D3"),
845 STM32_FUNCTION(16, "EVENTOUT"),
846 STM32_FUNCTION(17, "ANALOG")
847 ),
848 STM32_PIN(
849 PINCTRL_PIN(66, "PE2"),
850 STM32_FUNCTION(0, "GPIOE2"),
851 STM32_FUNCTION(1, "TRACECLK"),
852 STM32_FUNCTION(6, "SPI4_SCK"),
853 STM32_FUNCTION(7, "SAI1_MCLK_A"),
854 STM32_FUNCTION(10, "QUADSPI_BK1_IO2"),
855 STM32_FUNCTION(12, "ETH_MII_TXD3"),
856 STM32_FUNCTION(13, "FMC_A23"),
857 STM32_FUNCTION(16, "EVENTOUT"),
858 STM32_FUNCTION(17, "ANALOG")
859 ),
860 STM32_PIN(
861 PINCTRL_PIN(67, "PE3"),
862 STM32_FUNCTION(0, "GPIOE3"),
863 STM32_FUNCTION(1, "TRACED0"),
864 STM32_FUNCTION(7, "SAI1_SD_B"),
865 STM32_FUNCTION(13, "FMC_A19"),
866 STM32_FUNCTION(16, "EVENTOUT"),
867 STM32_FUNCTION(17, "ANALOG")
868 ),
869 STM32_PIN(
870 PINCTRL_PIN(68, "PE4"),
871 STM32_FUNCTION(0, "GPIOE4"),
872 STM32_FUNCTION(1, "TRACED1"),
873 STM32_FUNCTION(6, "SPI4_NSS"),
874 STM32_FUNCTION(7, "SAI1_FS_A"),
875 STM32_FUNCTION(11, "DFSDM_DATIN3"),
876 STM32_FUNCTION(13, "FMC_A20"),
877 STM32_FUNCTION(14, "DCMI_D4"),
878 STM32_FUNCTION(15, "LCD_B0"),
879 STM32_FUNCTION(16, "EVENTOUT"),
880 STM32_FUNCTION(17, "ANALOG")
881 ),
882 STM32_PIN(
883 PINCTRL_PIN(69, "PE5"),
884 STM32_FUNCTION(0, "GPIOE5"),
885 STM32_FUNCTION(1, "TRACED2"),
886 STM32_FUNCTION(4, "TIM9_CH1"),
887 STM32_FUNCTION(6, "SPI4_MISO"),
888 STM32_FUNCTION(7, "SAI1_SCK_A"),
889 STM32_FUNCTION(11, "DFSDM_CKIN3"),
890 STM32_FUNCTION(13, "FMC_A21"),
891 STM32_FUNCTION(14, "DCMI_D6"),
892 STM32_FUNCTION(15, "LCD_G0"),
893 STM32_FUNCTION(16, "EVENTOUT"),
894 STM32_FUNCTION(17, "ANALOG")
895 ),
896 STM32_PIN(
897 PINCTRL_PIN(70, "PE6"),
898 STM32_FUNCTION(0, "GPIOE6"),
899 STM32_FUNCTION(1, "TRACED3"),
900 STM32_FUNCTION(2, "TIM1_BKIN2"),
901 STM32_FUNCTION(4, "TIM9_CH2"),
902 STM32_FUNCTION(6, "SPI4_MOSI"),
903 STM32_FUNCTION(7, "SAI1_SD_A"),
904 STM32_FUNCTION(11, "SAI2_MCLK_B"),
905 STM32_FUNCTION(13, "FMC_A22"),
906 STM32_FUNCTION(14, "DCMI_D7"),
907 STM32_FUNCTION(15, "LCD_G1"),
908 STM32_FUNCTION(16, "EVENTOUT"),
909 STM32_FUNCTION(17, "ANALOG")
910 ),
911 STM32_PIN(
912 PINCTRL_PIN(71, "PE7"),
913 STM32_FUNCTION(0, "GPIOE7"),
914 STM32_FUNCTION(2, "TIM1_ETR"),
915 STM32_FUNCTION(7, "DFSDM_DATIN2"),
916 STM32_FUNCTION(9, "UART7_RX"),
917 STM32_FUNCTION(11, "QUADSPI_BK2_IO0"),
918 STM32_FUNCTION(13, "FMC_D4"),
919 STM32_FUNCTION(16, "EVENTOUT"),
920 STM32_FUNCTION(17, "ANALOG")
921 ),
922 STM32_PIN(
923 PINCTRL_PIN(72, "PE8"),
924 STM32_FUNCTION(0, "GPIOE8"),
925 STM32_FUNCTION(2, "TIM1_CH1N"),
926 STM32_FUNCTION(7, "DFSDM_CKIN2"),
927 STM32_FUNCTION(9, "UART7_TX"),
928 STM32_FUNCTION(11, "QUADSPI_BK2_IO1"),
929 STM32_FUNCTION(13, "FMC_D5"),
930 STM32_FUNCTION(16, "EVENTOUT"),
931 STM32_FUNCTION(17, "ANALOG")
932 ),
933 STM32_PIN(
934 PINCTRL_PIN(73, "PE9"),
935 STM32_FUNCTION(0, "GPIOE9"),
936 STM32_FUNCTION(2, "TIM1_CH1"),
937 STM32_FUNCTION(7, "DFSDM_CKOUT"),
938 STM32_FUNCTION(9, "UART7_RTS"),
939 STM32_FUNCTION(11, "QUADSPI_BK2_IO2"),
940 STM32_FUNCTION(13, "FMC_D6"),
941 STM32_FUNCTION(16, "EVENTOUT"),
942 STM32_FUNCTION(17, "ANALOG")
943 ),
944 STM32_PIN(
945 PINCTRL_PIN(74, "PE10"),
946 STM32_FUNCTION(0, "GPIOE10"),
947 STM32_FUNCTION(2, "TIM1_CH2N"),
948 STM32_FUNCTION(7, "DFSDM_DATIN4"),
949 STM32_FUNCTION(9, "UART7_CTS"),
950 STM32_FUNCTION(11, "QUADSPI_BK2_IO3"),
951 STM32_FUNCTION(13, "FMC_D7"),
952 STM32_FUNCTION(16, "EVENTOUT"),
953 STM32_FUNCTION(17, "ANALOG")
954 ),
955 STM32_PIN(
956 PINCTRL_PIN(75, "PE11"),
957 STM32_FUNCTION(0, "GPIOE11"),
958 STM32_FUNCTION(2, "TIM1_CH2"),
959 STM32_FUNCTION(6, "SPI4_NSS"),
960 STM32_FUNCTION(7, "DFSDM_CKIN4"),
961 STM32_FUNCTION(11, "SAI2_SD_B"),
962 STM32_FUNCTION(13, "FMC_D8"),
963 STM32_FUNCTION(15, "LCD_G3"),
964 STM32_FUNCTION(16, "EVENTOUT"),
965 STM32_FUNCTION(17, "ANALOG")
966 ),
967 STM32_PIN(
968 PINCTRL_PIN(76, "PE12"),
969 STM32_FUNCTION(0, "GPIOE12"),
970 STM32_FUNCTION(2, "TIM1_CH3N"),
971 STM32_FUNCTION(6, "SPI4_SCK"),
972 STM32_FUNCTION(7, "DFSDM_DATIN5"),
973 STM32_FUNCTION(11, "SAI2_SCK_B"),
974 STM32_FUNCTION(13, "FMC_D9"),
975 STM32_FUNCTION(15, "LCD_B4"),
976 STM32_FUNCTION(16, "EVENTOUT"),
977 STM32_FUNCTION(17, "ANALOG")
978 ),
979 STM32_PIN(
980 PINCTRL_PIN(77, "PE13"),
981 STM32_FUNCTION(0, "GPIOE13"),
982 STM32_FUNCTION(2, "TIM1_CH3"),
983 STM32_FUNCTION(6, "SPI4_MISO"),
984 STM32_FUNCTION(7, "DFSDM_CKIN5"),
985 STM32_FUNCTION(11, "SAI2_FS_B"),
986 STM32_FUNCTION(13, "FMC_D10"),
987 STM32_FUNCTION(15, "LCD_DE"),
988 STM32_FUNCTION(16, "EVENTOUT"),
989 STM32_FUNCTION(17, "ANALOG")
990 ),
991 STM32_PIN(
992 PINCTRL_PIN(78, "PE14"),
993 STM32_FUNCTION(0, "GPIOE14"),
994 STM32_FUNCTION(2, "TIM1_CH4"),
995 STM32_FUNCTION(6, "SPI4_MOSI"),
996 STM32_FUNCTION(11, "SAI2_MCLK_B"),
997 STM32_FUNCTION(13, "FMC_D11"),
998 STM32_FUNCTION(15, "LCD_CLK"),
999 STM32_FUNCTION(16, "EVENTOUT"),
1000 STM32_FUNCTION(17, "ANALOG")
1001 ),
1002 STM32_PIN(
1003 PINCTRL_PIN(79, "PE15"),
1004 STM32_FUNCTION(0, "GPIOE15"),
1005 STM32_FUNCTION(2, "TIM1_BKIN"),
1006 STM32_FUNCTION(13, "FMC_D12"),
1007 STM32_FUNCTION(15, "LCD_R7"),
1008 STM32_FUNCTION(16, "EVENTOUT"),
1009 STM32_FUNCTION(17, "ANALOG")
1010 ),
1011 STM32_PIN(
1012 PINCTRL_PIN(80, "PF0"),
1013 STM32_FUNCTION(0, "GPIOF0"),
1014 STM32_FUNCTION(5, "I2C2_SDA"),
1015 STM32_FUNCTION(13, "FMC_A0"),
1016 STM32_FUNCTION(16, "EVENTOUT"),
1017 STM32_FUNCTION(17, "ANALOG")
1018 ),
1019 STM32_PIN(
1020 PINCTRL_PIN(81, "PF1"),
1021 STM32_FUNCTION(0, "GPIOF1"),
1022 STM32_FUNCTION(5, "I2C2_SCL"),
1023 STM32_FUNCTION(13, "FMC_A1"),
1024 STM32_FUNCTION(16, "EVENTOUT"),
1025 STM32_FUNCTION(17, "ANALOG")
1026 ),
1027 STM32_PIN(
1028 PINCTRL_PIN(82, "PF2"),
1029 STM32_FUNCTION(0, "GPIOF2"),
1030 STM32_FUNCTION(5, "I2C2_SMBA"),
1031 STM32_FUNCTION(13, "FMC_A2"),
1032 STM32_FUNCTION(16, "EVENTOUT"),
1033 STM32_FUNCTION(17, "ANALOG")
1034 ),
1035 STM32_PIN(
1036 PINCTRL_PIN(83, "PF3"),
1037 STM32_FUNCTION(0, "GPIOF3"),
1038 STM32_FUNCTION(13, "FMC_A3"),
1039 STM32_FUNCTION(16, "EVENTOUT"),
1040 STM32_FUNCTION(17, "ANALOG")
1041 ),
1042 STM32_PIN(
1043 PINCTRL_PIN(84, "PF4"),
1044 STM32_FUNCTION(0, "GPIOF4"),
1045 STM32_FUNCTION(13, "FMC_A4"),
1046 STM32_FUNCTION(16, "EVENTOUT"),
1047 STM32_FUNCTION(17, "ANALOG")
1048 ),
1049 STM32_PIN(
1050 PINCTRL_PIN(85, "PF5"),
1051 STM32_FUNCTION(0, "GPIOF5"),
1052 STM32_FUNCTION(13, "FMC_A5"),
1053 STM32_FUNCTION(16, "EVENTOUT"),
1054 STM32_FUNCTION(17, "ANALOG")
1055 ),
1056 STM32_PIN(
1057 PINCTRL_PIN(86, "PF6"),
1058 STM32_FUNCTION(0, "GPIOF6"),
1059 STM32_FUNCTION(4, "TIM10_CH1"),
1060 STM32_FUNCTION(6, "SPI5_NSS"),
1061 STM32_FUNCTION(7, "SAI1_SD_B"),
1062 STM32_FUNCTION(9, "UART7_RX"),
1063 STM32_FUNCTION(10, "QUADSPI_BK1_IO3"),
1064 STM32_FUNCTION(16, "EVENTOUT"),
1065 STM32_FUNCTION(17, "ANALOG")
1066 ),
1067 STM32_PIN(
1068 PINCTRL_PIN(87, "PF7"),
1069 STM32_FUNCTION(0, "GPIOF7"),
1070 STM32_FUNCTION(4, "TIM11_CH1"),
1071 STM32_FUNCTION(6, "SPI5_SCK"),
1072 STM32_FUNCTION(7, "SAI1_MCLK_B"),
1073 STM32_FUNCTION(9, "UART7_TX"),
1074 STM32_FUNCTION(10, "QUADSPI_BK1_IO2"),
1075 STM32_FUNCTION(16, "EVENTOUT"),
1076 STM32_FUNCTION(17, "ANALOG")
1077 ),
1078 STM32_PIN(
1079 PINCTRL_PIN(88, "PF8"),
1080 STM32_FUNCTION(0, "GPIOF8"),
1081 STM32_FUNCTION(6, "SPI5_MISO"),
1082 STM32_FUNCTION(7, "SAI1_SCK_B"),
1083 STM32_FUNCTION(9, "UART7_RTS"),
1084 STM32_FUNCTION(10, "TIM13_CH1"),
1085 STM32_FUNCTION(11, "QUADSPI_BK1_IO0"),
1086 STM32_FUNCTION(16, "EVENTOUT"),
1087 STM32_FUNCTION(17, "ANALOG")
1088 ),
1089 STM32_PIN(
1090 PINCTRL_PIN(89, "PF9"),
1091 STM32_FUNCTION(0, "GPIOF9"),
1092 STM32_FUNCTION(6, "SPI5_MOSI"),
1093 STM32_FUNCTION(7, "SAI1_FS_B"),
1094 STM32_FUNCTION(9, "UART7_CTS"),
1095 STM32_FUNCTION(10, "TIM14_CH1"),
1096 STM32_FUNCTION(11, "QUADSPI_BK1_IO1"),
1097 STM32_FUNCTION(16, "EVENTOUT"),
1098 STM32_FUNCTION(17, "ANALOG")
1099 ),
1100 STM32_PIN(
1101 PINCTRL_PIN(90, "PF10"),
1102 STM32_FUNCTION(0, "GPIOF10"),
1103 STM32_FUNCTION(10, "QUADSPI_CLK"),
1104 STM32_FUNCTION(14, "DCMI_D11"),
1105 STM32_FUNCTION(15, "LCD_DE"),
1106 STM32_FUNCTION(16, "EVENTOUT"),
1107 STM32_FUNCTION(17, "ANALOG")
1108 ),
1109 STM32_PIN(
1110 PINCTRL_PIN(91, "PF11"),
1111 STM32_FUNCTION(0, "GPIOF11"),
1112 STM32_FUNCTION(6, "SPI5_MOSI"),
1113 STM32_FUNCTION(11, "SAI2_SD_B"),
1114 STM32_FUNCTION(13, "FMC_SDNRAS"),
1115 STM32_FUNCTION(14, "DCMI_D12"),
1116 STM32_FUNCTION(16, "EVENTOUT"),
1117 STM32_FUNCTION(17, "ANALOG")
1118 ),
1119 STM32_PIN(
1120 PINCTRL_PIN(92, "PF12"),
1121 STM32_FUNCTION(0, "GPIOF12"),
1122 STM32_FUNCTION(13, "FMC_A6"),
1123 STM32_FUNCTION(16, "EVENTOUT"),
1124 STM32_FUNCTION(17, "ANALOG")
1125 ),
1126 STM32_PIN(
1127 PINCTRL_PIN(93, "PF13"),
1128 STM32_FUNCTION(0, "GPIOF13"),
1129 STM32_FUNCTION(5, "I2C4_SMBA"),
1130 STM32_FUNCTION(7, "DFSDM_DATIN6"),
1131 STM32_FUNCTION(13, "FMC_A7"),
1132 STM32_FUNCTION(16, "EVENTOUT"),
1133 STM32_FUNCTION(17, "ANALOG")
1134 ),
1135 STM32_PIN(
1136 PINCTRL_PIN(94, "PF14"),
1137 STM32_FUNCTION(0, "GPIOF14"),
1138 STM32_FUNCTION(5, "I2C4_SCL"),
1139 STM32_FUNCTION(7, "DFSDM_CKIN6"),
1140 STM32_FUNCTION(13, "FMC_A8"),
1141 STM32_FUNCTION(16, "EVENTOUT"),
1142 STM32_FUNCTION(17, "ANALOG")
1143 ),
1144 STM32_PIN(
1145 PINCTRL_PIN(95, "PF15"),
1146 STM32_FUNCTION(0, "GPIOF15"),
1147 STM32_FUNCTION(5, "I2C4_SDA"),
1148 STM32_FUNCTION(13, "FMC_A9"),
1149 STM32_FUNCTION(16, "EVENTOUT"),
1150 STM32_FUNCTION(17, "ANALOG")
1151 ),
1152 STM32_PIN(
1153 PINCTRL_PIN(96, "PG0"),
1154 STM32_FUNCTION(0, "GPIOG0"),
1155 STM32_FUNCTION(13, "FMC_A10"),
1156 STM32_FUNCTION(16, "EVENTOUT"),
1157 STM32_FUNCTION(17, "ANALOG")
1158 ),
1159 STM32_PIN(
1160 PINCTRL_PIN(97, "PG1"),
1161 STM32_FUNCTION(0, "GPIOG1"),
1162 STM32_FUNCTION(13, "FMC_A11"),
1163 STM32_FUNCTION(16, "EVENTOUT"),
1164 STM32_FUNCTION(17, "ANALOG")
1165 ),
1166 STM32_PIN(
1167 PINCTRL_PIN(98, "PG2"),
1168 STM32_FUNCTION(0, "GPIOG2"),
1169 STM32_FUNCTION(13, "FMC_A12"),
1170 STM32_FUNCTION(16, "EVENTOUT"),
1171 STM32_FUNCTION(17, "ANALOG")
1172 ),
1173 STM32_PIN(
1174 PINCTRL_PIN(99, "PG3"),
1175 STM32_FUNCTION(0, "GPIOG3"),
1176 STM32_FUNCTION(13, "FMC_A13"),
1177 STM32_FUNCTION(16, "EVENTOUT"),
1178 STM32_FUNCTION(17, "ANALOG")
1179 ),
1180 STM32_PIN(
1181 PINCTRL_PIN(100, "PG4"),
1182 STM32_FUNCTION(0, "GPIOG4"),
1183 STM32_FUNCTION(13, "FMC_A14 FMC_BA0"),
1184 STM32_FUNCTION(16, "EVENTOUT"),
1185 STM32_FUNCTION(17, "ANALOG")
1186 ),
1187 STM32_PIN(
1188 PINCTRL_PIN(101, "PG5"),
1189 STM32_FUNCTION(0, "GPIOG5"),
1190 STM32_FUNCTION(13, "FMC_A15 FMC_BA1"),
1191 STM32_FUNCTION(16, "EVENTOUT"),
1192 STM32_FUNCTION(17, "ANALOG")
1193 ),
1194 STM32_PIN(
1195 PINCTRL_PIN(102, "PG6"),
1196 STM32_FUNCTION(0, "GPIOG6"),
1197 STM32_FUNCTION(13, "FMC_NE3"),
1198 STM32_FUNCTION(14, "DCMI_D12"),
1199 STM32_FUNCTION(15, "LCD_R7"),
1200 STM32_FUNCTION(16, "EVENTOUT"),
1201 STM32_FUNCTION(17, "ANALOG")
1202 ),
1203 STM32_PIN(
1204 PINCTRL_PIN(103, "PG7"),
1205 STM32_FUNCTION(0, "GPIOG7"),
1206 STM32_FUNCTION(7, "SAI1_MCLK_A"),
1207 STM32_FUNCTION(9, "USART6_CK"),
1208 STM32_FUNCTION(13, "FMC_INT"),
1209 STM32_FUNCTION(14, "DCMI_D13"),
1210 STM32_FUNCTION(15, "LCD_CLK"),
1211 STM32_FUNCTION(16, "EVENTOUT"),
1212 STM32_FUNCTION(17, "ANALOG")
1213 ),
1214 STM32_PIN(
1215 PINCTRL_PIN(104, "PG8"),
1216 STM32_FUNCTION(0, "GPIOG8"),
1217 STM32_FUNCTION(6, "SPI6_NSS"),
1218 STM32_FUNCTION(8, "SPDIF_RX2"),
1219 STM32_FUNCTION(9, "USART6_RTS"),
1220 STM32_FUNCTION(12, "ETH_PPS_OUT"),
1221 STM32_FUNCTION(13, "FMC_SDCLK"),
1222 STM32_FUNCTION(15, "LCD_G7"),
1223 STM32_FUNCTION(16, "EVENTOUT"),
1224 STM32_FUNCTION(17, "ANALOG")
1225 ),
1226 STM32_PIN(
1227 PINCTRL_PIN(105, "PG9"),
1228 STM32_FUNCTION(0, "GPIOG9"),
1229 STM32_FUNCTION(6, "SPI1_MISO"),
1230 STM32_FUNCTION(8, "SPDIF_RX3"),
1231 STM32_FUNCTION(9, "USART6_RX"),
1232 STM32_FUNCTION(10, "QUADSPI_BK2_IO2"),
1233 STM32_FUNCTION(11, "SAI2_FS_B"),
1234 STM32_FUNCTION(12, "SDMMC2_D0"),
1235 STM32_FUNCTION(13, "FMC_NE2 FMC_NCE"),
1236 STM32_FUNCTION(14, "DCMI_VSYNC"),
1237 STM32_FUNCTION(16, "EVENTOUT"),
1238 STM32_FUNCTION(17, "ANALOG")
1239 ),
1240 STM32_PIN(
1241 PINCTRL_PIN(106, "PG10"),
1242 STM32_FUNCTION(0, "GPIOG10"),
1243 STM32_FUNCTION(6, "SPI1_NSS I2S1_WS"),
1244 STM32_FUNCTION(10, "LCD_G3"),
1245 STM32_FUNCTION(11, "SAI2_SD_B"),
1246 STM32_FUNCTION(12, "SDMMC2_D1"),
1247 STM32_FUNCTION(13, "FMC_NE3"),
1248 STM32_FUNCTION(14, "DCMI_D2"),
1249 STM32_FUNCTION(15, "LCD_B2"),
1250 STM32_FUNCTION(16, "EVENTOUT"),
1251 STM32_FUNCTION(17, "ANALOG")
1252 ),
1253 STM32_PIN(
1254 PINCTRL_PIN(107, "PG11"),
1255 STM32_FUNCTION(0, "GPIOG11"),
1256 STM32_FUNCTION(6, "SPI1_SCK I2S1_CK"),
1257 STM32_FUNCTION(8, "SPDIF_RX0"),
1258 STM32_FUNCTION(11, "SDMMC2_D2"),
1259 STM32_FUNCTION(12, "ETH_MII_TX_EN ETH_RMII_TX_EN"),
1260 STM32_FUNCTION(14, "DCMI_D3"),
1261 STM32_FUNCTION(15, "LCD_B3"),
1262 STM32_FUNCTION(16, "EVENTOUT"),
1263 STM32_FUNCTION(17, "ANALOG")
1264 ),
1265 STM32_PIN(
1266 PINCTRL_PIN(108, "PG12"),
1267 STM32_FUNCTION(0, "GPIOG12"),
1268 STM32_FUNCTION(4, "LPTIM1_IN1"),
1269 STM32_FUNCTION(6, "SPI6_MISO"),
1270 STM32_FUNCTION(8, "SPDIF_RX1"),
1271 STM32_FUNCTION(9, "USART6_RTS"),
1272 STM32_FUNCTION(10, "LCD_B4"),
1273 STM32_FUNCTION(12, "SDMMC2_D3"),
1274 STM32_FUNCTION(13, "FMC_NE4"),
1275 STM32_FUNCTION(15, "LCD_B1"),
1276 STM32_FUNCTION(16, "EVENTOUT"),
1277 STM32_FUNCTION(17, "ANALOG")
1278 ),
1279 STM32_PIN(
1280 PINCTRL_PIN(109, "PG13"),
1281 STM32_FUNCTION(0, "GPIOG13"),
1282 STM32_FUNCTION(1, "TRACED0"),
1283 STM32_FUNCTION(4, "LPTIM1_OUT"),
1284 STM32_FUNCTION(6, "SPI6_SCK"),
1285 STM32_FUNCTION(9, "USART6_CTS"),
1286 STM32_FUNCTION(12, "ETH_MII_TXD0 ETH_RMII_TXD0"),
1287 STM32_FUNCTION(13, "FMC_A24"),
1288 STM32_FUNCTION(15, "LCD_R0"),
1289 STM32_FUNCTION(16, "EVENTOUT"),
1290 STM32_FUNCTION(17, "ANALOG")
1291 ),
1292 STM32_PIN(
1293 PINCTRL_PIN(110, "PG14"),
1294 STM32_FUNCTION(0, "GPIOG14"),
1295 STM32_FUNCTION(1, "TRACED1"),
1296 STM32_FUNCTION(4, "LPTIM1_ETR"),
1297 STM32_FUNCTION(6, "SPI6_MOSI"),
1298 STM32_FUNCTION(9, "USART6_TX"),
1299 STM32_FUNCTION(10, "QUADSPI_BK2_IO3"),
1300 STM32_FUNCTION(12, "ETH_MII_TXD1 ETH_RMII_TXD1"),
1301 STM32_FUNCTION(13, "FMC_A25"),
1302 STM32_FUNCTION(15, "LCD_B0"),
1303 STM32_FUNCTION(16, "EVENTOUT"),
1304 STM32_FUNCTION(17, "ANALOG")
1305 ),
1306 STM32_PIN(
1307 PINCTRL_PIN(111, "PG15"),
1308 STM32_FUNCTION(0, "GPIOG15"),
1309 STM32_FUNCTION(9, "USART6_CTS"),
1310 STM32_FUNCTION(13, "FMC_SDNCAS"),
1311 STM32_FUNCTION(14, "DCMI_D13"),
1312 STM32_FUNCTION(16, "EVENTOUT"),
1313 STM32_FUNCTION(17, "ANALOG")
1314 ),
1315 STM32_PIN(
1316 PINCTRL_PIN(112, "PH0"),
1317 STM32_FUNCTION(0, "GPIOH0"),
1318 STM32_FUNCTION(16, "EVENTOUT"),
1319 STM32_FUNCTION(17, "ANALOG")
1320 ),
1321 STM32_PIN(
1322 PINCTRL_PIN(113, "PH1"),
1323 STM32_FUNCTION(0, "GPIOH1"),
1324 STM32_FUNCTION(16, "EVENTOUT"),
1325 STM32_FUNCTION(17, "ANALOG")
1326 ),
1327 STM32_PIN(
1328 PINCTRL_PIN(114, "PH2"),
1329 STM32_FUNCTION(0, "GPIOH2"),
1330 STM32_FUNCTION(4, "LPTIM1_IN2"),
1331 STM32_FUNCTION(10, "QUADSPI_BK2_IO0"),
1332 STM32_FUNCTION(11, "SAI2_SCK_B"),
1333 STM32_FUNCTION(12, "ETH_MII_CRS"),
1334 STM32_FUNCTION(13, "FMC_SDCKE0"),
1335 STM32_FUNCTION(15, "LCD_R0"),
1336 STM32_FUNCTION(16, "EVENTOUT"),
1337 STM32_FUNCTION(17, "ANALOG")
1338 ),
1339 STM32_PIN(
1340 PINCTRL_PIN(115, "PH3"),
1341 STM32_FUNCTION(0, "GPIOH3"),
1342 STM32_FUNCTION(10, "QUADSPI_BK2_IO1"),
1343 STM32_FUNCTION(11, "SAI2_MCLK_B"),
1344 STM32_FUNCTION(12, "ETH_MII_COL"),
1345 STM32_FUNCTION(13, "FMC_SDNE0"),
1346 STM32_FUNCTION(15, "LCD_R1"),
1347 STM32_FUNCTION(16, "EVENTOUT"),
1348 STM32_FUNCTION(17, "ANALOG")
1349 ),
1350 STM32_PIN(
1351 PINCTRL_PIN(116, "PH4"),
1352 STM32_FUNCTION(0, "GPIOH4"),
1353 STM32_FUNCTION(5, "I2C2_SCL"),
1354 STM32_FUNCTION(10, "LCD_G5"),
1355 STM32_FUNCTION(11, "OTG_HS_ULPI_NXT"),
1356 STM32_FUNCTION(15, "LCD_G4"),
1357 STM32_FUNCTION(16, "EVENTOUT"),
1358 STM32_FUNCTION(17, "ANALOG")
1359 ),
1360 STM32_PIN(
1361 PINCTRL_PIN(117, "PH5"),
1362 STM32_FUNCTION(0, "GPIOH5"),
1363 STM32_FUNCTION(5, "I2C2_SDA"),
1364 STM32_FUNCTION(6, "SPI5_NSS"),
1365 STM32_FUNCTION(13, "FMC_SDNWE"),
1366 STM32_FUNCTION(16, "EVENTOUT"),
1367 STM32_FUNCTION(17, "ANALOG")
1368 ),
1369 STM32_PIN(
1370 PINCTRL_PIN(118, "PH6"),
1371 STM32_FUNCTION(0, "GPIOH6"),
1372 STM32_FUNCTION(5, "I2C2_SMBA"),
1373 STM32_FUNCTION(6, "SPI5_SCK"),
1374 STM32_FUNCTION(10, "TIM12_CH1"),
1375 STM32_FUNCTION(12, "ETH_MII_RXD2"),
1376 STM32_FUNCTION(13, "FMC_SDNE1"),
1377 STM32_FUNCTION(14, "DCMI_D8"),
1378 STM32_FUNCTION(16, "EVENTOUT"),
1379 STM32_FUNCTION(17, "ANALOG")
1380 ),
1381 STM32_PIN(
1382 PINCTRL_PIN(119, "PH7"),
1383 STM32_FUNCTION(0, "GPIOH7"),
1384 STM32_FUNCTION(5, "I2C3_SCL"),
1385 STM32_FUNCTION(6, "SPI5_MISO"),
1386 STM32_FUNCTION(12, "ETH_MII_RXD3"),
1387 STM32_FUNCTION(13, "FMC_SDCKE1"),
1388 STM32_FUNCTION(14, "DCMI_D9"),
1389 STM32_FUNCTION(16, "EVENTOUT"),
1390 STM32_FUNCTION(17, "ANALOG")
1391 ),
1392 STM32_PIN(
1393 PINCTRL_PIN(120, "PH8"),
1394 STM32_FUNCTION(0, "GPIOH8"),
1395 STM32_FUNCTION(5, "I2C3_SDA"),
1396 STM32_FUNCTION(13, "FMC_D16"),
1397 STM32_FUNCTION(14, "DCMI_HSYNC"),
1398 STM32_FUNCTION(15, "LCD_R2"),
1399 STM32_FUNCTION(16, "EVENTOUT"),
1400 STM32_FUNCTION(17, "ANALOG")
1401 ),
1402 STM32_PIN(
1403 PINCTRL_PIN(121, "PH9"),
1404 STM32_FUNCTION(0, "GPIOH9"),
1405 STM32_FUNCTION(5, "I2C3_SMBA"),
1406 STM32_FUNCTION(10, "TIM12_CH2"),
1407 STM32_FUNCTION(13, "FMC_D17"),
1408 STM32_FUNCTION(14, "DCMI_D0"),
1409 STM32_FUNCTION(15, "LCD_R3"),
1410 STM32_FUNCTION(16, "EVENTOUT"),
1411 STM32_FUNCTION(17, "ANALOG")
1412 ),
1413 STM32_PIN(
1414 PINCTRL_PIN(122, "PH10"),
1415 STM32_FUNCTION(0, "GPIOH10"),
1416 STM32_FUNCTION(3, "TIM5_CH1"),
1417 STM32_FUNCTION(5, "I2C4_SMBA"),
1418 STM32_FUNCTION(13, "FMC_D18"),
1419 STM32_FUNCTION(14, "DCMI_D1"),
1420 STM32_FUNCTION(15, "LCD_R4"),
1421 STM32_FUNCTION(16, "EVENTOUT"),
1422 STM32_FUNCTION(17, "ANALOG")
1423 ),
1424 STM32_PIN(
1425 PINCTRL_PIN(123, "PH11"),
1426 STM32_FUNCTION(0, "GPIOH11"),
1427 STM32_FUNCTION(3, "TIM5_CH2"),
1428 STM32_FUNCTION(5, "I2C4_SCL"),
1429 STM32_FUNCTION(13, "FMC_D19"),
1430 STM32_FUNCTION(14, "DCMI_D2"),
1431 STM32_FUNCTION(15, "LCD_R5"),
1432 STM32_FUNCTION(16, "EVENTOUT"),
1433 STM32_FUNCTION(17, "ANALOG")
1434 ),
1435 STM32_PIN(
1436 PINCTRL_PIN(124, "PH12"),
1437 STM32_FUNCTION(0, "GPIOH12"),
1438 STM32_FUNCTION(3, "TIM5_CH3"),
1439 STM32_FUNCTION(5, "I2C4_SDA"),
1440 STM32_FUNCTION(13, "FMC_D20"),
1441 STM32_FUNCTION(14, "DCMI_D3"),
1442 STM32_FUNCTION(15, "LCD_R6"),
1443 STM32_FUNCTION(16, "EVENTOUT"),
1444 STM32_FUNCTION(17, "ANALOG")
1445 ),
1446 STM32_PIN(
1447 PINCTRL_PIN(125, "PH13"),
1448 STM32_FUNCTION(0, "GPIOH13"),
1449 STM32_FUNCTION(4, "TIM8_CH1N"),
1450 STM32_FUNCTION(9, "UART4_TX"),
1451 STM32_FUNCTION(10, "CAN1_TX"),
1452 STM32_FUNCTION(13, "FMC_D21"),
1453 STM32_FUNCTION(15, "LCD_G2"),
1454 STM32_FUNCTION(16, "EVENTOUT"),
1455 STM32_FUNCTION(17, "ANALOG")
1456 ),
1457 STM32_PIN(
1458 PINCTRL_PIN(126, "PH14"),
1459 STM32_FUNCTION(0, "GPIOH14"),
1460 STM32_FUNCTION(4, "TIM8_CH2N"),
1461 STM32_FUNCTION(9, "UART4_RX"),
1462 STM32_FUNCTION(10, "CAN1_RX"),
1463 STM32_FUNCTION(13, "FMC_D22"),
1464 STM32_FUNCTION(14, "DCMI_D4"),
1465 STM32_FUNCTION(15, "LCD_G3"),
1466 STM32_FUNCTION(16, "EVENTOUT"),
1467 STM32_FUNCTION(17, "ANALOG")
1468 ),
1469 STM32_PIN(
1470 PINCTRL_PIN(127, "PH15"),
1471 STM32_FUNCTION(0, "GPIOH15"),
1472 STM32_FUNCTION(4, "TIM8_CH3N"),
1473 STM32_FUNCTION(13, "FMC_D23"),
1474 STM32_FUNCTION(14, "DCMI_D11"),
1475 STM32_FUNCTION(15, "LCD_G4"),
1476 STM32_FUNCTION(16, "EVENTOUT"),
1477 STM32_FUNCTION(17, "ANALOG")
1478 ),
1479 STM32_PIN(
1480 PINCTRL_PIN(128, "PI0"),
1481 STM32_FUNCTION(0, "GPIOI0"),
1482 STM32_FUNCTION(3, "TIM5_CH4"),
1483 STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
1484 STM32_FUNCTION(13, "FMC_D24"),
1485 STM32_FUNCTION(14, "DCMI_D13"),
1486 STM32_FUNCTION(15, "LCD_G5"),
1487 STM32_FUNCTION(16, "EVENTOUT"),
1488 STM32_FUNCTION(17, "ANALOG")
1489 ),
1490 STM32_PIN(
1491 PINCTRL_PIN(129, "PI1"),
1492 STM32_FUNCTION(0, "GPIOI1"),
1493 STM32_FUNCTION(4, "TIM8_BKIN2"),
1494 STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
1495 STM32_FUNCTION(13, "FMC_D25"),
1496 STM32_FUNCTION(14, "DCMI_D8"),
1497 STM32_FUNCTION(15, "LCD_G6"),
1498 STM32_FUNCTION(16, "EVENTOUT"),
1499 STM32_FUNCTION(17, "ANALOG")
1500 ),
1501 STM32_PIN(
1502 PINCTRL_PIN(130, "PI2"),
1503 STM32_FUNCTION(0, "GPIOI2"),
1504 STM32_FUNCTION(4, "TIM8_CH4"),
1505 STM32_FUNCTION(6, "SPI2_MISO"),
1506 STM32_FUNCTION(13, "FMC_D26"),
1507 STM32_FUNCTION(14, "DCMI_D9"),
1508 STM32_FUNCTION(15, "LCD_G7"),
1509 STM32_FUNCTION(16, "EVENTOUT"),
1510 STM32_FUNCTION(17, "ANALOG")
1511 ),
1512 STM32_PIN(
1513 PINCTRL_PIN(131, "PI3"),
1514 STM32_FUNCTION(0, "GPIOI3"),
1515 STM32_FUNCTION(4, "TIM8_ETR"),
1516 STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"),
1517 STM32_FUNCTION(13, "FMC_D27"),
1518 STM32_FUNCTION(14, "DCMI_D10"),
1519 STM32_FUNCTION(16, "EVENTOUT"),
1520 STM32_FUNCTION(17, "ANALOG")
1521 ),
1522 STM32_PIN(
1523 PINCTRL_PIN(132, "PI4"),
1524 STM32_FUNCTION(0, "GPIOI4"),
1525 STM32_FUNCTION(4, "TIM8_BKIN"),
1526 STM32_FUNCTION(11, "SAI2_MCLK_A"),
1527 STM32_FUNCTION(13, "FMC_NBL2"),
1528 STM32_FUNCTION(14, "DCMI_D5"),
1529 STM32_FUNCTION(15, "LCD_B4"),
1530 STM32_FUNCTION(16, "EVENTOUT"),
1531 STM32_FUNCTION(17, "ANALOG")
1532 ),
1533 STM32_PIN(
1534 PINCTRL_PIN(133, "PI5"),
1535 STM32_FUNCTION(0, "GPIOI5"),
1536 STM32_FUNCTION(4, "TIM8_CH1"),
1537 STM32_FUNCTION(11, "SAI2_SCK_A"),
1538 STM32_FUNCTION(13, "FMC_NBL3"),
1539 STM32_FUNCTION(14, "DCMI_VSYNC"),
1540 STM32_FUNCTION(15, "LCD_B5"),
1541 STM32_FUNCTION(16, "EVENTOUT"),
1542 STM32_FUNCTION(17, "ANALOG")
1543 ),
1544 STM32_PIN(
1545 PINCTRL_PIN(134, "PI6"),
1546 STM32_FUNCTION(0, "GPIOI6"),
1547 STM32_FUNCTION(4, "TIM8_CH2"),
1548 STM32_FUNCTION(11, "SAI2_SD_A"),
1549 STM32_FUNCTION(13, "FMC_D28"),
1550 STM32_FUNCTION(14, "DCMI_D6"),
1551 STM32_FUNCTION(15, "LCD_B6"),
1552 STM32_FUNCTION(16, "EVENTOUT"),
1553 STM32_FUNCTION(17, "ANALOG")
1554 ),
1555 STM32_PIN(
1556 PINCTRL_PIN(135, "PI7"),
1557 STM32_FUNCTION(0, "GPIOI7"),
1558 STM32_FUNCTION(4, "TIM8_CH3"),
1559 STM32_FUNCTION(11, "SAI2_FS_A"),
1560 STM32_FUNCTION(13, "FMC_D29"),
1561 STM32_FUNCTION(14, "DCMI_D7"),
1562 STM32_FUNCTION(15, "LCD_B7"),
1563 STM32_FUNCTION(16, "EVENTOUT"),
1564 STM32_FUNCTION(17, "ANALOG")
1565 ),
1566 STM32_PIN(
1567 PINCTRL_PIN(136, "PI8"),
1568 STM32_FUNCTION(0, "GPIOI8"),
1569 STM32_FUNCTION(16, "EVENTOUT"),
1570 STM32_FUNCTION(17, "ANALOG")
1571 ),
1572 STM32_PIN(
1573 PINCTRL_PIN(137, "PI9"),
1574 STM32_FUNCTION(0, "GPIOI9"),
1575 STM32_FUNCTION(9, "UART4_RX"),
1576 STM32_FUNCTION(10, "CAN1_RX"),
1577 STM32_FUNCTION(13, "FMC_D30"),
1578 STM32_FUNCTION(15, "LCD_VSYNC"),
1579 STM32_FUNCTION(16, "EVENTOUT"),
1580 STM32_FUNCTION(17, "ANALOG")
1581 ),
1582 STM32_PIN(
1583 PINCTRL_PIN(138, "PI10"),
1584 STM32_FUNCTION(0, "GPIOI10"),
1585 STM32_FUNCTION(12, "ETH_MII_RX_ER"),
1586 STM32_FUNCTION(13, "FMC_D31"),
1587 STM32_FUNCTION(15, "LCD_HSYNC"),
1588 STM32_FUNCTION(16, "EVENTOUT"),
1589 STM32_FUNCTION(17, "ANALOG")
1590 ),
1591 STM32_PIN(
1592 PINCTRL_PIN(139, "PI11"),
1593 STM32_FUNCTION(0, "GPIOI11"),
1594 STM32_FUNCTION(10, "LCD_G6"),
1595 STM32_FUNCTION(11, "OTG_HS_ULPI_DIR"),
1596 STM32_FUNCTION(16, "EVENTOUT"),
1597 STM32_FUNCTION(17, "ANALOG")
1598 ),
1599 STM32_PIN(
1600 PINCTRL_PIN(140, "PI12"),
1601 STM32_FUNCTION(0, "GPIOI12"),
1602 STM32_FUNCTION(15, "LCD_HSYNC"),
1603 STM32_FUNCTION(16, "EVENTOUT"),
1604 STM32_FUNCTION(17, "ANALOG")
1605 ),
1606 STM32_PIN(
1607 PINCTRL_PIN(141, "PI13"),
1608 STM32_FUNCTION(0, "GPIOI13"),
1609 STM32_FUNCTION(15, "LCD_VSYNC"),
1610 STM32_FUNCTION(16, "EVENTOUT"),
1611 STM32_FUNCTION(17, "ANALOG")
1612 ),
1613 STM32_PIN(
1614 PINCTRL_PIN(142, "PI14"),
1615 STM32_FUNCTION(0, "GPIOI14"),
1616 STM32_FUNCTION(15, "LCD_CLK"),
1617 STM32_FUNCTION(16, "EVENTOUT"),
1618 STM32_FUNCTION(17, "ANALOG")
1619 ),
1620 STM32_PIN(
1621 PINCTRL_PIN(143, "PI15"),
1622 STM32_FUNCTION(0, "GPIOI15"),
1623 STM32_FUNCTION(10, "LCD_G2"),
1624 STM32_FUNCTION(15, "LCD_R0"),
1625 STM32_FUNCTION(16, "EVENTOUT"),
1626 STM32_FUNCTION(17, "ANALOG")
1627 ),
1628 STM32_PIN(
1629 PINCTRL_PIN(144, "PJ0"),
1630 STM32_FUNCTION(0, "GPIOJ0"),
1631 STM32_FUNCTION(10, "LCD_R7"),
1632 STM32_FUNCTION(15, "LCD_R1"),
1633 STM32_FUNCTION(16, "EVENTOUT"),
1634 STM32_FUNCTION(17, "ANALOG")
1635 ),
1636 STM32_PIN(
1637 PINCTRL_PIN(145, "PJ1"),
1638 STM32_FUNCTION(0, "GPIOJ1"),
1639 STM32_FUNCTION(15, "LCD_R2"),
1640 STM32_FUNCTION(16, "EVENTOUT"),
1641 STM32_FUNCTION(17, "ANALOG")
1642 ),
1643 STM32_PIN(
1644 PINCTRL_PIN(146, "PJ2"),
1645 STM32_FUNCTION(0, "GPIOJ2"),
1646 STM32_FUNCTION(14, "DSI_TE"),
1647 STM32_FUNCTION(15, "LCD_R3"),
1648 STM32_FUNCTION(16, "EVENTOUT"),
1649 STM32_FUNCTION(17, "ANALOG")
1650 ),
1651 STM32_PIN(
1652 PINCTRL_PIN(147, "PJ3"),
1653 STM32_FUNCTION(0, "GPIOJ3"),
1654 STM32_FUNCTION(15, "LCD_R4"),
1655 STM32_FUNCTION(16, "EVENTOUT"),
1656 STM32_FUNCTION(17, "ANALOG")
1657 ),
1658 STM32_PIN(
1659 PINCTRL_PIN(148, "PJ4"),
1660 STM32_FUNCTION(0, "GPIOJ4"),
1661 STM32_FUNCTION(15, "LCD_R5"),
1662 STM32_FUNCTION(16, "EVENTOUT"),
1663 STM32_FUNCTION(17, "ANALOG")
1664 ),
1665 STM32_PIN(
1666 PINCTRL_PIN(149, "PJ5"),
1667 STM32_FUNCTION(0, "GPIOJ5"),
1668 STM32_FUNCTION(15, "LCD_R6"),
1669 STM32_FUNCTION(16, "EVENTOUT"),
1670 STM32_FUNCTION(17, "ANALOG")
1671 ),
1672 STM32_PIN(
1673 PINCTRL_PIN(150, "PJ6"),
1674 STM32_FUNCTION(0, "GPIOJ6"),
1675 STM32_FUNCTION(15, "LCD_R7"),
1676 STM32_FUNCTION(16, "EVENTOUT"),
1677 STM32_FUNCTION(17, "ANALOG")
1678 ),
1679 STM32_PIN(
1680 PINCTRL_PIN(151, "PJ7"),
1681 STM32_FUNCTION(0, "GPIOJ7"),
1682 STM32_FUNCTION(15, "LCD_G0"),
1683 STM32_FUNCTION(16, "EVENTOUT"),
1684 STM32_FUNCTION(17, "ANALOG")
1685 ),
1686 STM32_PIN(
1687 PINCTRL_PIN(152, "PJ8"),
1688 STM32_FUNCTION(0, "GPIOJ8"),
1689 STM32_FUNCTION(15, "LCD_G1"),
1690 STM32_FUNCTION(16, "EVENTOUT"),
1691 STM32_FUNCTION(17, "ANALOG")
1692 ),
1693 STM32_PIN(
1694 PINCTRL_PIN(153, "PJ9"),
1695 STM32_FUNCTION(0, "GPIOJ9"),
1696 STM32_FUNCTION(15, "LCD_G2"),
1697 STM32_FUNCTION(16, "EVENTOUT"),
1698 STM32_FUNCTION(17, "ANALOG")
1699 ),
1700 STM32_PIN(
1701 PINCTRL_PIN(154, "PJ10"),
1702 STM32_FUNCTION(0, "GPIOJ10"),
1703 STM32_FUNCTION(15, "LCD_G3"),
1704 STM32_FUNCTION(16, "EVENTOUT"),
1705 STM32_FUNCTION(17, "ANALOG")
1706 ),
1707 STM32_PIN(
1708 PINCTRL_PIN(155, "PJ11"),
1709 STM32_FUNCTION(0, "GPIOJ11"),
1710 STM32_FUNCTION(15, "LCD_G4"),
1711 STM32_FUNCTION(16, "EVENTOUT"),
1712 STM32_FUNCTION(17, "ANALOG")
1713 ),
1714 STM32_PIN(
1715 PINCTRL_PIN(156, "PJ12"),
1716 STM32_FUNCTION(0, "GPIOJ12"),
1717 STM32_FUNCTION(10, "LCD_G3"),
1718 STM32_FUNCTION(15, "LCD_B0"),
1719 STM32_FUNCTION(16, "EVENTOUT"),
1720 STM32_FUNCTION(17, "ANALOG")
1721 ),
1722 STM32_PIN(
1723 PINCTRL_PIN(157, "PJ13"),
1724 STM32_FUNCTION(0, "GPIOJ13"),
1725 STM32_FUNCTION(10, "LCD_G4"),
1726 STM32_FUNCTION(15, "LCD_B1"),
1727 STM32_FUNCTION(16, "EVENTOUT"),
1728 STM32_FUNCTION(17, "ANALOG")
1729 ),
1730 STM32_PIN(
1731 PINCTRL_PIN(158, "PJ14"),
1732 STM32_FUNCTION(0, "GPIOJ14"),
1733 STM32_FUNCTION(15, "LCD_B2"),
1734 STM32_FUNCTION(16, "EVENTOUT"),
1735 STM32_FUNCTION(17, "ANALOG")
1736 ),
1737 STM32_PIN(
1738 PINCTRL_PIN(159, "PJ15"),
1739 STM32_FUNCTION(0, "GPIOJ15"),
1740 STM32_FUNCTION(15, "LCD_B3"),
1741 STM32_FUNCTION(16, "EVENTOUT"),
1742 STM32_FUNCTION(17, "ANALOG")
1743 ),
1744 STM32_PIN(
1745 PINCTRL_PIN(160, "PK0"),
1746 STM32_FUNCTION(0, "GPIOK0"),
1747 STM32_FUNCTION(15, "LCD_G5"),
1748 STM32_FUNCTION(16, "EVENTOUT"),
1749 STM32_FUNCTION(17, "ANALOG")
1750 ),
1751 STM32_PIN(
1752 PINCTRL_PIN(161, "PK1"),
1753 STM32_FUNCTION(0, "GPIOK1"),
1754 STM32_FUNCTION(15, "LCD_G6"),
1755 STM32_FUNCTION(16, "EVENTOUT"),
1756 STM32_FUNCTION(17, "ANALOG")
1757 ),
1758 STM32_PIN(
1759 PINCTRL_PIN(162, "PK2"),
1760 STM32_FUNCTION(0, "GPIOK2"),
1761 STM32_FUNCTION(15, "LCD_G7"),
1762 STM32_FUNCTION(16, "EVENTOUT"),
1763 STM32_FUNCTION(17, "ANALOG")
1764 ),
1765 STM32_PIN(
1766 PINCTRL_PIN(163, "PK3"),
1767 STM32_FUNCTION(0, "GPIOK3"),
1768 STM32_FUNCTION(15, "LCD_B4"),
1769 STM32_FUNCTION(16, "EVENTOUT"),
1770 STM32_FUNCTION(17, "ANALOG")
1771 ),
1772 STM32_PIN(
1773 PINCTRL_PIN(164, "PK4"),
1774 STM32_FUNCTION(0, "GPIOK4"),
1775 STM32_FUNCTION(15, "LCD_B5"),
1776 STM32_FUNCTION(16, "EVENTOUT"),
1777 STM32_FUNCTION(17, "ANALOG")
1778 ),
1779 STM32_PIN(
1780 PINCTRL_PIN(165, "PK5"),
1781 STM32_FUNCTION(0, "GPIOK5"),
1782 STM32_FUNCTION(15, "LCD_B6"),
1783 STM32_FUNCTION(16, "EVENTOUT"),
1784 STM32_FUNCTION(17, "ANALOG")
1785 ),
1786 STM32_PIN(
1787 PINCTRL_PIN(166, "PK6"),
1788 STM32_FUNCTION(0, "GPIOK6"),
1789 STM32_FUNCTION(15, "LCD_B7"),
1790 STM32_FUNCTION(16, "EVENTOUT"),
1791 STM32_FUNCTION(17, "ANALOG")
1792 ),
1793 STM32_PIN(
1794 PINCTRL_PIN(167, "PK7"),
1795 STM32_FUNCTION(0, "GPIOK7"),
1796 STM32_FUNCTION(15, "LCD_DE"),
1797 STM32_FUNCTION(16, "EVENTOUT"),
1798 STM32_FUNCTION(17, "ANALOG")
1799 ),
1800};
1801
1802static struct stm32_pinctrl_match_data stm32f769_match_data = {
1803 .pins = stm32f769_pins,
1804 .npins = ARRAY_SIZE(stm32f769_pins),
1805};
1806
1807static const struct of_device_id stm32f769_pctrl_match[] = {
1808 {
1809 .compatible = "st,stm32f769-pinctrl",
1810 .data = &stm32f769_match_data,
1811 },
1812 { }
1813};
1814
1815static struct platform_driver stm32f769_pinctrl_driver = {
1816 .probe = stm32_pctl_probe,
1817 .driver = {
1818 .name = "stm32f769-pinctrl",
1819 .of_match_table = stm32f769_pctrl_match,
1820 },
1821};
1822
1823static int __init stm32f769_pinctrl_init(void)
1824{
1825 return platform_driver_register(&stm32f769_pinctrl_driver);
1826}
1827arch_initcall(stm32f769_pinctrl_init);
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32h743.c b/drivers/pinctrl/stm32/pinctrl-stm32h743.c
index e34b2b9217ce..ffe7b5271506 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32h743.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32h743.c
@@ -1,7 +1,7 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Copyright (C) Alexandre Torgue 2017 3 * Copyright (C) STMicroelectronics 2017
3 * Author: Alexandre Torgue <alexandre.torgue@st.com> 4 * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
4 * License terms: GNU General Public License (GPL), version 2
5 */ 5 */
6#include <linux/init.h> 6#include <linux/init.h>
7#include <linux/of.h> 7#include <linux/of.h>
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32mp157.c b/drivers/pinctrl/stm32/pinctrl-stm32mp157.c
new file mode 100644
index 000000000000..7c7d6284b23c
--- /dev/null
+++ b/drivers/pinctrl/stm32/pinctrl-stm32mp157.c
@@ -0,0 +1,2188 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
5 */
6#include <linux/init.h>
7#include <linux/of.h>
8#include <linux/platform_device.h>
9
10#include "pinctrl-stm32.h"
11
12static const struct stm32_desc_pin stm32mp157_pins[] = {
13 STM32_PIN(
14 PINCTRL_PIN(0, "PA0"),
15 STM32_FUNCTION(0, "GPIOA0"),
16 STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
17 STM32_FUNCTION(3, "TIM5_CH1"),
18 STM32_FUNCTION(4, "TIM8_ETR"),
19 STM32_FUNCTION(5, "TIM15_BKIN"),
20 STM32_FUNCTION(8, "USART2_CTS_NSS USART_BOOT2_CTS_NSS"),
21 STM32_FUNCTION(9, "UART4_TX"),
22 STM32_FUNCTION(10, "SDMMC2_CMD"),
23 STM32_FUNCTION(11, "SAI2_SD_B"),
24 STM32_FUNCTION(12, "ETH_GMII_CRS ETH_MII_CRS"),
25 STM32_FUNCTION(16, "EVENTOUT"),
26 STM32_FUNCTION(17, "ANALOG")
27 ),
28 STM32_PIN(
29 PINCTRL_PIN(1, "PA1"),
30 STM32_FUNCTION(0, "GPIOA1"),
31 STM32_FUNCTION(1, "ETH_CLK"),
32 STM32_FUNCTION(2, "TIM2_CH2"),
33 STM32_FUNCTION(3, "TIM5_CH2"),
34 STM32_FUNCTION(4, "LPTIM3_OUT"),
35 STM32_FUNCTION(5, "TIM15_CH1N"),
36 STM32_FUNCTION(8, "USART2_RTS USART_BOOT2_RTS"),
37 STM32_FUNCTION(9, "UART4_RX"),
38 STM32_FUNCTION(10, "QUADSPI_BK1_IO3 QUADSPI_BOOTBK1_IO3"),
39 STM32_FUNCTION(11, "SAI2_MCLK_B"),
40 STM32_FUNCTION(12, "ETH_GMII_RX_CLK ETH_MII_RX_CLK ETH_RGMII_RX_CLK ETH_RMII_REF_CLK"),
41 STM32_FUNCTION(15, "LCD_R2"),
42 STM32_FUNCTION(16, "EVENTOUT"),
43 STM32_FUNCTION(17, "ANALOG")
44 ),
45 STM32_PIN(
46 PINCTRL_PIN(2, "PA2"),
47 STM32_FUNCTION(0, "GPIOA2"),
48 STM32_FUNCTION(2, "TIM2_CH3"),
49 STM32_FUNCTION(3, "TIM5_CH3"),
50 STM32_FUNCTION(4, "LPTIM4_OUT"),
51 STM32_FUNCTION(5, "TIM15_CH1"),
52 STM32_FUNCTION(8, "USART2_TX USART_BOOT2_TX"),
53 STM32_FUNCTION(9, "SAI2_SCK_B"),
54 STM32_FUNCTION(11, "SDMMC2_D0DIR SDMMC_BOOT2_D0DIR"),
55 STM32_FUNCTION(12, "ETH_MDIO"),
56 STM32_FUNCTION(13, "MDIOS_MDIO"),
57 STM32_FUNCTION(15, "LCD_R1"),
58 STM32_FUNCTION(16, "EVENTOUT"),
59 STM32_FUNCTION(17, "ANALOG")
60 ),
61 STM32_PIN(
62 PINCTRL_PIN(3, "PA3"),
63 STM32_FUNCTION(0, "GPIOA3"),
64 STM32_FUNCTION(2, "TIM2_CH4"),
65 STM32_FUNCTION(3, "TIM5_CH4"),
66 STM32_FUNCTION(4, "LPTIM5_OUT"),
67 STM32_FUNCTION(5, "TIM15_CH2"),
68 STM32_FUNCTION(8, "USART2_RX USART_BOOT2_RX"),
69 STM32_FUNCTION(10, "LCD_B2"),
70 STM32_FUNCTION(12, "ETH_GMII_COL ETH_MII_COL"),
71 STM32_FUNCTION(15, "LCD_B5"),
72 STM32_FUNCTION(16, "EVENTOUT"),
73 STM32_FUNCTION(17, "ANALOG")
74 ),
75 STM32_PIN(
76 PINCTRL_PIN(4, "PA4"),
77 STM32_FUNCTION(0, "GPIOA4"),
78 STM32_FUNCTION(1, "HDP0"),
79 STM32_FUNCTION(3, "TIM5_ETR"),
80 STM32_FUNCTION(5, "SAI4_D2"),
81 STM32_FUNCTION(6, "SPI1_NSS I2S1_WS"),
82 STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"),
83 STM32_FUNCTION(8, "USART2_CK USART_BOOT2_CK"),
84 STM32_FUNCTION(9, "SPI6_NSS"),
85 STM32_FUNCTION(13, "SAI4_FS_A"),
86 STM32_FUNCTION(14, "DCMI_HSYNC"),
87 STM32_FUNCTION(15, "LCD_VSYNC"),
88 STM32_FUNCTION(16, "EVENTOUT"),
89 STM32_FUNCTION(17, "ANALOG")
90 ),
91 STM32_PIN(
92 PINCTRL_PIN(5, "PA5"),
93 STM32_FUNCTION(0, "GPIOA5"),
94 STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
95 STM32_FUNCTION(4, "TIM8_CH1N"),
96 STM32_FUNCTION(5, "SAI4_CK1"),
97 STM32_FUNCTION(6, "SPI1_SCK I2S1_CK"),
98 STM32_FUNCTION(9, "SPI6_SCK"),
99 STM32_FUNCTION(13, "SAI4_MCLK_A"),
100 STM32_FUNCTION(15, "LCD_R4"),
101 STM32_FUNCTION(16, "EVENTOUT"),
102 STM32_FUNCTION(17, "ANALOG")
103 ),
104 STM32_PIN(
105 PINCTRL_PIN(6, "PA6"),
106 STM32_FUNCTION(0, "GPIOA6"),
107 STM32_FUNCTION(2, "TIM1_BKIN"),
108 STM32_FUNCTION(3, "TIM3_CH1"),
109 STM32_FUNCTION(4, "TIM8_BKIN"),
110 STM32_FUNCTION(5, "SAI4_CK2"),
111 STM32_FUNCTION(6, "SPI1_MISO I2S1_SDI"),
112 STM32_FUNCTION(9, "SPI6_MISO"),
113 STM32_FUNCTION(10, "TIM13_CH1"),
114 STM32_FUNCTION(12, "MDIOS_MDC"),
115 STM32_FUNCTION(13, "SAI4_SCK_A"),
116 STM32_FUNCTION(14, "DCMI_PIXCLK"),
117 STM32_FUNCTION(15, "LCD_G2"),
118 STM32_FUNCTION(16, "EVENTOUT"),
119 STM32_FUNCTION(17, "ANALOG")
120 ),
121 STM32_PIN(
122 PINCTRL_PIN(7, "PA7"),
123 STM32_FUNCTION(0, "GPIOA7"),
124 STM32_FUNCTION(2, "TIM1_CH1N"),
125 STM32_FUNCTION(3, "TIM3_CH2"),
126 STM32_FUNCTION(4, "TIM8_CH1N"),
127 STM32_FUNCTION(5, "SAI4_D1"),
128 STM32_FUNCTION(6, "SPI1_MOSI I2S1_SDO"),
129 STM32_FUNCTION(9, "SPI6_MOSI"),
130 STM32_FUNCTION(10, "TIM14_CH1"),
131 STM32_FUNCTION(11, "QUADSPI_CLK"),
132 STM32_FUNCTION(12, "ETH_GMII_RX_DV ETH_MII_RX_DV ETH_RGMII_RX_CTL ETH_RMII_CRS_DV"),
133 STM32_FUNCTION(13, "SAI4_SD_A"),
134 STM32_FUNCTION(16, "EVENTOUT"),
135 STM32_FUNCTION(17, "ANALOG")
136 ),
137 STM32_PIN(
138 PINCTRL_PIN(8, "PA8"),
139 STM32_FUNCTION(0, "GPIOA8"),
140 STM32_FUNCTION(1, "MCO1"),
141 STM32_FUNCTION(2, "TIM1_CH1"),
142 STM32_FUNCTION(4, "TIM8_BKIN2"),
143 STM32_FUNCTION(5, "I2C3_SCL"),
144 STM32_FUNCTION(6, "SPI3_MOSI I2S3_SDO"),
145 STM32_FUNCTION(8, "USART1_CK"),
146 STM32_FUNCTION(9, "SDMMC2_CKIN SDMMC_BOOT2_CKIN"),
147 STM32_FUNCTION(10, "SDMMC2_D4 SDMMC_BOOT2_D4"),
148 STM32_FUNCTION(11, "USBO_SOF"),
149 STM32_FUNCTION(13, "SAI4_SD_B"),
150 STM32_FUNCTION(14, "UART7_RX"),
151 STM32_FUNCTION(15, "LCD_R6"),
152 STM32_FUNCTION(16, "EVENTOUT"),
153 STM32_FUNCTION(17, "ANALOG")
154 ),
155 STM32_PIN(
156 PINCTRL_PIN(9, "PA9"),
157 STM32_FUNCTION(0, "GPIOA9"),
158 STM32_FUNCTION(2, "TIM1_CH2"),
159 STM32_FUNCTION(5, "I2C3_SMBA"),
160 STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
161 STM32_FUNCTION(8, "USART1_TX"),
162 STM32_FUNCTION(9, "SDMMC2_CDIR SDMMC_BOOT2_CDIR"),
163 STM32_FUNCTION(10, "CAN1_RXFD"),
164 STM32_FUNCTION(11, "SDMMC2_D5 SDMMC_BOOT2_D5"),
165 STM32_FUNCTION(14, "DCMI_D0"),
166 STM32_FUNCTION(15, "LCD_R5"),
167 STM32_FUNCTION(16, "EVENTOUT"),
168 STM32_FUNCTION(17, "ANALOG")
169 ),
170 STM32_PIN(
171 PINCTRL_PIN(10, "PA10"),
172 STM32_FUNCTION(0, "GPIOA10"),
173 STM32_FUNCTION(2, "TIM1_CH3"),
174 STM32_FUNCTION(6, "SPI3_NSS I2S3_WS"),
175 STM32_FUNCTION(8, "USART1_RX"),
176 STM32_FUNCTION(10, "CAN1_TXFD"),
177 STM32_FUNCTION(12, "MDIOS_MDIO"),
178 STM32_FUNCTION(13, "SAI4_FS_B"),
179 STM32_FUNCTION(14, "DCMI_D1"),
180 STM32_FUNCTION(15, "LCD_B1"),
181 STM32_FUNCTION(16, "EVENTOUT"),
182 STM32_FUNCTION(17, "ANALOG")
183 ),
184 STM32_PIN(
185 PINCTRL_PIN(11, "PA11"),
186 STM32_FUNCTION(0, "GPIOA11"),
187 STM32_FUNCTION(2, "TIM1_CH4"),
188 STM32_FUNCTION(3, "I2C6_SCL"),
189 STM32_FUNCTION(5, "I2C5_SCL"),
190 STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
191 STM32_FUNCTION(7, "UART4_RX"),
192 STM32_FUNCTION(8, "USART1_CTS_NSS"),
193 STM32_FUNCTION(10, "CAN1_RX"),
194 STM32_FUNCTION(15, "LCD_R4"),
195 STM32_FUNCTION(16, "EVENTOUT"),
196 STM32_FUNCTION(17, "ANALOG")
197 ),
198 STM32_PIN(
199 PINCTRL_PIN(12, "PA12"),
200 STM32_FUNCTION(0, "GPIOA12"),
201 STM32_FUNCTION(2, "TIM1_ETR"),
202 STM32_FUNCTION(3, "I2C6_SDA"),
203 STM32_FUNCTION(5, "I2C5_SDA"),
204 STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
205 STM32_FUNCTION(7, "UART4_TX"),
206 STM32_FUNCTION(8, "USART1_RTS"),
207 STM32_FUNCTION(9, "SAI2_FS_B"),
208 STM32_FUNCTION(10, "CAN1_TX"),
209 STM32_FUNCTION(15, "LCD_R5"),
210 STM32_FUNCTION(16, "EVENTOUT"),
211 STM32_FUNCTION(17, "ANALOG")
212 ),
213 STM32_PIN(
214 PINCTRL_PIN(13, "PA13"),
215 STM32_FUNCTION(0, "GPIOA13"),
216 STM32_FUNCTION(1, "DBTRGO"),
217 STM32_FUNCTION(2, "DBTRGI"),
218 STM32_FUNCTION(3, "MCO1"),
219 STM32_FUNCTION(9, "UART4_TX"),
220 STM32_FUNCTION(16, "EVENTOUT"),
221 STM32_FUNCTION(17, "ANALOG")
222 ),
223 STM32_PIN(
224 PINCTRL_PIN(14, "PA14"),
225 STM32_FUNCTION(0, "GPIOA14"),
226 STM32_FUNCTION(1, "DBTRGO"),
227 STM32_FUNCTION(2, "DBTRGI"),
228 STM32_FUNCTION(3, "MCO2"),
229 STM32_FUNCTION(16, "EVENTOUT"),
230 STM32_FUNCTION(17, "ANALOG")
231 ),
232 STM32_PIN(
233 PINCTRL_PIN(15, "PA15"),
234 STM32_FUNCTION(0, "GPIOA15"),
235 STM32_FUNCTION(1, "DBTRGI"),
236 STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
237 STM32_FUNCTION(3, "SAI4_D2"),
238 STM32_FUNCTION(4, "SDMMC1_CDIR"),
239 STM32_FUNCTION(5, "HDMI_CEC"),
240 STM32_FUNCTION(6, "SPI1_NSS I2S1_WS"),
241 STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"),
242 STM32_FUNCTION(8, "SPI6_NSS"),
243 STM32_FUNCTION(9, "UART4_RTS UART_BOOT4_RTS"),
244 STM32_FUNCTION(10, "SDMMC2_D5 SDMMC_BOOT2_D5"),
245 STM32_FUNCTION(11, "SDMMC2_CDIR SDMMC_BOOT2_CDIR"),
246 STM32_FUNCTION(12, "SDMMC1_D5 SDMMC_BOOT1_D5"),
247 STM32_FUNCTION(13, "SAI4_FS_A"),
248 STM32_FUNCTION(14, "UART7_TX"),
249 STM32_FUNCTION(16, "EVENTOUT"),
250 STM32_FUNCTION(17, "ANALOG")
251 ),
252 STM32_PIN(
253 PINCTRL_PIN(16, "PB0"),
254 STM32_FUNCTION(0, "GPIOB0"),
255 STM32_FUNCTION(2, "TIM1_CH2N"),
256 STM32_FUNCTION(3, "TIM3_CH3"),
257 STM32_FUNCTION(4, "TIM8_CH2N"),
258 STM32_FUNCTION(7, "DFSDM_CKOUT"),
259 STM32_FUNCTION(9, "UART4_CTS UART_BOOT4_CTS"),
260 STM32_FUNCTION(10, "LCD_R3"),
261 STM32_FUNCTION(12, "ETH_GMII_RXD2 ETH_MII_RXD2 ETH_RGMII_RXD2"),
262 STM32_FUNCTION(13, "MDIOS_MDIO"),
263 STM32_FUNCTION(15, "LCD_G1"),
264 STM32_FUNCTION(16, "EVENTOUT"),
265 STM32_FUNCTION(17, "ANALOG")
266 ),
267 STM32_PIN(
268 PINCTRL_PIN(17, "PB1"),
269 STM32_FUNCTION(0, "GPIOB1"),
270 STM32_FUNCTION(2, "TIM1_CH3N"),
271 STM32_FUNCTION(3, "TIM3_CH4"),
272 STM32_FUNCTION(4, "TIM8_CH3N"),
273 STM32_FUNCTION(7, "DFSDM_DATA1"),
274 STM32_FUNCTION(10, "LCD_R6"),
275 STM32_FUNCTION(12, "ETH_GMII_RXD3 ETH_MII_RXD3 ETH_RGMII_RXD3"),
276 STM32_FUNCTION(13, "MDIOS_MDC"),
277 STM32_FUNCTION(15, "LCD_G0"),
278 STM32_FUNCTION(16, "EVENTOUT"),
279 STM32_FUNCTION(17, "ANALOG")
280 ),
281 STM32_PIN(
282 PINCTRL_PIN(18, "PB2"),
283 STM32_FUNCTION(0, "GPIOB2"),
284 STM32_FUNCTION(1, "TRACED4"),
285 STM32_FUNCTION(2, "RTC_OUT2"),
286 STM32_FUNCTION(3, "SAI1_D1"),
287 STM32_FUNCTION(4, "DFSDM_CK1"),
288 STM32_FUNCTION(5, "USART1_RX"),
289 STM32_FUNCTION(6, "I2S_CKIN"),
290 STM32_FUNCTION(7, "SAI1_SD_A"),
291 STM32_FUNCTION(8, "SPI3_MOSI I2S3_SDO"),
292 STM32_FUNCTION(9, "UART4_RX UART_BOOT4_RX"),
293 STM32_FUNCTION(10, "QUADSPI_CLK"),
294 STM32_FUNCTION(16, "EVENTOUT"),
295 STM32_FUNCTION(17, "ANALOG")
296 ),
297 STM32_PIN(
298 PINCTRL_PIN(19, "PB3"),
299 STM32_FUNCTION(0, "GPIOB3"),
300 STM32_FUNCTION(1, "TRACED9"),
301 STM32_FUNCTION(2, "TIM2_CH2"),
302 STM32_FUNCTION(5, "SAI4_CK1"),
303 STM32_FUNCTION(6, "SPI1_SCK I2S1_CK"),
304 STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"),
305 STM32_FUNCTION(9, "SPI6_SCK"),
306 STM32_FUNCTION(10, "SDMMC2_D2 SDMMC_BOOT2_D2"),
307 STM32_FUNCTION(13, "SAI4_MCLK_A"),
308 STM32_FUNCTION(14, "UART7_RX"),
309 STM32_FUNCTION(16, "EVENTOUT"),
310 STM32_FUNCTION(17, "ANALOG")
311 ),
312 STM32_PIN(
313 PINCTRL_PIN(20, "PB4"),
314 STM32_FUNCTION(0, "GPIOB4"),
315 STM32_FUNCTION(1, "TRACED8"),
316 STM32_FUNCTION(2, "TIM16_BKIN"),
317 STM32_FUNCTION(3, "TIM3_CH1"),
318 STM32_FUNCTION(5, "SAI4_CK2"),
319 STM32_FUNCTION(6, "SPI1_MISO I2S1_SDI"),
320 STM32_FUNCTION(7, "SPI3_MISO I2S3_SDI"),
321 STM32_FUNCTION(8, "SPI2_NSS I2S2_WS"),
322 STM32_FUNCTION(9, "SPI6_MISO"),
323 STM32_FUNCTION(10, "SDMMC2_D3 SDMMC_BOOT2_D3"),
324 STM32_FUNCTION(13, "SAI4_SCK_A"),
325 STM32_FUNCTION(14, "UART7_TX"),
326 STM32_FUNCTION(16, "EVENTOUT"),
327 STM32_FUNCTION(17, "ANALOG")
328 ),
329 STM32_PIN(
330 PINCTRL_PIN(21, "PB5"),
331 STM32_FUNCTION(0, "GPIOB5"),
332 STM32_FUNCTION(1, "ETH_CLK"),
333 STM32_FUNCTION(2, "TIM17_BKIN"),
334 STM32_FUNCTION(3, "TIM3_CH2"),
335 STM32_FUNCTION(4, "SAI4_D1"),
336 STM32_FUNCTION(5, "I2C1_SMBA"),
337 STM32_FUNCTION(6, "SPI1_MOSI I2S1_SDO"),
338 STM32_FUNCTION(7, "I2C4_SMBA"),
339 STM32_FUNCTION(8, "SPI3_MOSI I2S3_SDO"),
340 STM32_FUNCTION(9, "SPI6_MOSI"),
341 STM32_FUNCTION(10, "CAN2_RX"),
342 STM32_FUNCTION(11, "SAI4_SD_A"),
343 STM32_FUNCTION(12, "ETH_PPS_OUT"),
344 STM32_FUNCTION(13, "UART5_RX UART_BOOT5_RX"),
345 STM32_FUNCTION(14, "DCMI_D10"),
346 STM32_FUNCTION(15, "LCD_G7"),
347 STM32_FUNCTION(16, "EVENTOUT"),
348 STM32_FUNCTION(17, "ANALOG")
349 ),
350 STM32_PIN(
351 PINCTRL_PIN(22, "PB6"),
352 STM32_FUNCTION(0, "GPIOB6"),
353 STM32_FUNCTION(2, "TIM16_CH1N"),
354 STM32_FUNCTION(3, "TIM4_CH1"),
355 STM32_FUNCTION(5, "I2C1_SCL"),
356 STM32_FUNCTION(6, "HDMI_CEC"),
357 STM32_FUNCTION(7, "I2C4_SCL"),
358 STM32_FUNCTION(8, "USART1_TX"),
359 STM32_FUNCTION(10, "CAN2_TX"),
360 STM32_FUNCTION(11, "QUADSPI_BK1_NCS QUADSPI_BOOTBK1_NCS"),
361 STM32_FUNCTION(12, "DFSDM_DATA5"),
362 STM32_FUNCTION(13, "UART5_TX"),
363 STM32_FUNCTION(14, "DCMI_D5"),
364 STM32_FUNCTION(16, "EVENTOUT"),
365 STM32_FUNCTION(17, "ANALOG")
366 ),
367 STM32_PIN(
368 PINCTRL_PIN(23, "PB7"),
369 STM32_FUNCTION(0, "GPIOB7"),
370 STM32_FUNCTION(2, "TIM17_CH1N"),
371 STM32_FUNCTION(3, "TIM4_CH2"),
372 STM32_FUNCTION(5, "I2C1_SDA"),
373 STM32_FUNCTION(7, "I2C4_SDA"),
374 STM32_FUNCTION(8, "USART1_RX"),
375 STM32_FUNCTION(10, "CAN2_TXFD"),
376 STM32_FUNCTION(11, "SDMMC2_D1 SDMMC_BOOT2_D1"),
377 STM32_FUNCTION(12, "DFSDM_CK5"),
378 STM32_FUNCTION(13, "FMC_NL"),
379 STM32_FUNCTION(14, "DCMI_VSYNC"),
380 STM32_FUNCTION(16, "EVENTOUT"),
381 STM32_FUNCTION(17, "ANALOG")
382 ),
383 STM32_PIN(
384 PINCTRL_PIN(24, "PB8"),
385 STM32_FUNCTION(0, "GPIOB8"),
386 STM32_FUNCTION(1, "HDP6"),
387 STM32_FUNCTION(2, "TIM16_CH1"),
388 STM32_FUNCTION(3, "TIM4_CH3"),
389 STM32_FUNCTION(4, "DFSDM_CK7"),
390 STM32_FUNCTION(5, "I2C1_SCL"),
391 STM32_FUNCTION(6, "SDMMC1_CKIN SDMMC_BOOT1_CKIN"),
392 STM32_FUNCTION(7, "I2C4_SCL"),
393 STM32_FUNCTION(8, "SDMMC2_CKIN SDMMC_BOOT2_CKIN"),
394 STM32_FUNCTION(9, "UART4_RX"),
395 STM32_FUNCTION(10, "CAN1_RX"),
396 STM32_FUNCTION(11, "SDMMC2_D4 SDMMC_BOOT2_D4"),
397 STM32_FUNCTION(12, "ETH_GMII_TXD3 ETH_MII_TXD3 ETH_RGMII_TXD3"),
398 STM32_FUNCTION(13, "SDMMC1_D4 SDMMC_BOOT1_D4"),
399 STM32_FUNCTION(14, "DCMI_D6"),
400 STM32_FUNCTION(15, "LCD_B6"),
401 STM32_FUNCTION(16, "EVENTOUT"),
402 STM32_FUNCTION(17, "ANALOG")
403 ),
404 STM32_PIN(
405 PINCTRL_PIN(25, "PB9"),
406 STM32_FUNCTION(0, "GPIOB9"),
407 STM32_FUNCTION(1, "HDP7"),
408 STM32_FUNCTION(2, "TIM17_CH1"),
409 STM32_FUNCTION(3, "TIM4_CH4"),
410 STM32_FUNCTION(4, "DFSDM_DATA7"),
411 STM32_FUNCTION(5, "I2C1_SDA"),
412 STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
413 STM32_FUNCTION(7, "I2C4_SDA"),
414 STM32_FUNCTION(8, "SDMMC2_CDIR SDMMC_BOOT2_CDIR"),
415 STM32_FUNCTION(9, "UART4_TX"),
416 STM32_FUNCTION(10, "CAN1_TX"),
417 STM32_FUNCTION(11, "SDMMC2_D5 SDMMC_BOOT2_D5"),
418 STM32_FUNCTION(12, "SDMMC1_CDIR SDMMC_BOOT1_CDIR"),
419 STM32_FUNCTION(13, "SDMMC1_D5 SDMMC_BOOT1_D5"),
420 STM32_FUNCTION(14, "DCMI_D7"),
421 STM32_FUNCTION(15, "LCD_B7"),
422 STM32_FUNCTION(16, "EVENTOUT"),
423 STM32_FUNCTION(17, "ANALOG")
424 ),
425 STM32_PIN(
426 PINCTRL_PIN(26, "PB10"),
427 STM32_FUNCTION(0, "GPIOB10"),
428 STM32_FUNCTION(2, "TIM2_CH3"),
429 STM32_FUNCTION(4, "LPTIM2_IN1"),
430 STM32_FUNCTION(5, "I2C2_SCL"),
431 STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
432 STM32_FUNCTION(7, "DFSDM_DATA7"),
433 STM32_FUNCTION(8, "USART3_TX USART_BOOT3_TX"),
434 STM32_FUNCTION(10, "QUADSPI_BK1_NCS"),
435 STM32_FUNCTION(12, "ETH_GMII_RX_ER ETH_MII_RX_ER"),
436 STM32_FUNCTION(15, "LCD_G4"),
437 STM32_FUNCTION(16, "EVENTOUT"),
438 STM32_FUNCTION(17, "ANALOG")
439 ),
440 STM32_PIN(
441 PINCTRL_PIN(27, "PB11"),
442 STM32_FUNCTION(0, "GPIOB11"),
443 STM32_FUNCTION(2, "TIM2_CH4"),
444 STM32_FUNCTION(4, "LPTIM2_ETR"),
445 STM32_FUNCTION(5, "I2C2_SDA"),
446 STM32_FUNCTION(7, "DFSDM_CK7"),
447 STM32_FUNCTION(8, "USART3_RX"),
448 STM32_FUNCTION(12, "ETH_GMII_TX_EN ETH_MII_TX_EN ETH_RGMII_TX_CTL ETH_RMII_TX_EN"),
449 STM32_FUNCTION(14, "DSI_TE"),
450 STM32_FUNCTION(15, "LCD_G5"),
451 STM32_FUNCTION(16, "EVENTOUT"),
452 STM32_FUNCTION(17, "ANALOG")
453 ),
454 STM32_PIN(
455 PINCTRL_PIN(28, "PB12"),
456 STM32_FUNCTION(0, "GPIOB12"),
457 STM32_FUNCTION(2, "TIM1_BKIN"),
458 STM32_FUNCTION(3, "I2C6_SMBA"),
459 STM32_FUNCTION(5, "I2C2_SMBA"),
460 STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
461 STM32_FUNCTION(7, "DFSDM_DATA1"),
462 STM32_FUNCTION(8, "USART3_CK USART_BOOT3_CK"),
463 STM32_FUNCTION(9, "USART3_RX USART_BOOT3_RX"),
464 STM32_FUNCTION(10, "CAN2_RX"),
465 STM32_FUNCTION(12, "ETH_GMII_TXD0 ETH_MII_TXD0 ETH_RGMII_TXD0 ETH_RMII_TXD0"),
466 STM32_FUNCTION(15, "UART5_RX"),
467 STM32_FUNCTION(16, "EVENTOUT"),
468 STM32_FUNCTION(17, "ANALOG")
469 ),
470 STM32_PIN(
471 PINCTRL_PIN(29, "PB13"),
472 STM32_FUNCTION(0, "GPIOB13"),
473 STM32_FUNCTION(2, "TIM1_CH1N"),
474 STM32_FUNCTION(4, "DFSDM_CKOUT"),
475 STM32_FUNCTION(5, "LPTIM2_OUT"),
476 STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
477 STM32_FUNCTION(7, "DFSDM_CK1"),
478 STM32_FUNCTION(8, "USART3_CTS_NSS USART_BOOT3_CTS_NSS"),
479 STM32_FUNCTION(10, "CAN2_TX"),
480 STM32_FUNCTION(12, "ETH_GMII_TXD1 ETH_MII_TXD1 ETH_RGMII_TXD1 ETH_RMII_TXD1"),
481 STM32_FUNCTION(15, "UART5_TX UART_BOOT5_TX"),
482 STM32_FUNCTION(16, "EVENTOUT"),
483 STM32_FUNCTION(17, "ANALOG")
484 ),
485 STM32_PIN(
486 PINCTRL_PIN(30, "PB14"),
487 STM32_FUNCTION(0, "GPIOB14"),
488 STM32_FUNCTION(2, "TIM1_CH2N"),
489 STM32_FUNCTION(3, "TIM12_CH1"),
490 STM32_FUNCTION(4, "TIM8_CH2N"),
491 STM32_FUNCTION(5, "USART1_TX"),
492 STM32_FUNCTION(6, "SPI2_MISO I2S2_SDI"),
493 STM32_FUNCTION(7, "DFSDM_DATA2"),
494 STM32_FUNCTION(8, "USART3_RTS USART_BOOT3_RTS"),
495 STM32_FUNCTION(10, "SDMMC2_D0 SDMMC_BOOT2_D0"),
496 STM32_FUNCTION(16, "EVENTOUT"),
497 STM32_FUNCTION(17, "ANALOG")
498 ),
499 STM32_PIN(
500 PINCTRL_PIN(31, "PB15"),
501 STM32_FUNCTION(0, "GPIOB15"),
502 STM32_FUNCTION(1, "RTC_REFIN"),
503 STM32_FUNCTION(2, "TIM1_CH3N"),
504 STM32_FUNCTION(3, "TIM12_CH2"),
505 STM32_FUNCTION(4, "TIM8_CH3N"),
506 STM32_FUNCTION(5, "USART1_RX"),
507 STM32_FUNCTION(6, "SPI2_MOSI I2S2_SDO"),
508 STM32_FUNCTION(7, "DFSDM_CK2"),
509 STM32_FUNCTION(10, "SDMMC2_D1 SDMMC_BOOT2_D1"),
510 STM32_FUNCTION(16, "EVENTOUT"),
511 STM32_FUNCTION(17, "ANALOG")
512 ),
513 STM32_PIN(
514 PINCTRL_PIN(32, "PC0"),
515 STM32_FUNCTION(0, "GPIOC0"),
516 STM32_FUNCTION(4, "DFSDM_CK0"),
517 STM32_FUNCTION(5, "LPTIM2_IN2"),
518 STM32_FUNCTION(7, "DFSDM_DATA4"),
519 STM32_FUNCTION(9, "SAI2_FS_B"),
520 STM32_FUNCTION(11, "QUADSPI_BK2_NCS QUADSPI_BOOTBK2_NCS"),
521 STM32_FUNCTION(15, "LCD_R5"),
522 STM32_FUNCTION(16, "EVENTOUT"),
523 STM32_FUNCTION(17, "ANALOG")
524 ),
525 STM32_PIN(
526 PINCTRL_PIN(33, "PC1"),
527 STM32_FUNCTION(0, "GPIOC1"),
528 STM32_FUNCTION(1, "TRACED0"),
529 STM32_FUNCTION(3, "SAI1_D1"),
530 STM32_FUNCTION(4, "DFSDM_DATA0"),
531 STM32_FUNCTION(5, "DFSDM_CK4"),
532 STM32_FUNCTION(6, "SPI2_MOSI I2S2_SDO"),
533 STM32_FUNCTION(7, "SAI1_SD_A"),
534 STM32_FUNCTION(10, "SDMMC2_CK"),
535 STM32_FUNCTION(12, "ETH_MDC"),
536 STM32_FUNCTION(13, "MDIOS_MDC"),
537 STM32_FUNCTION(16, "EVENTOUT"),
538 STM32_FUNCTION(17, "ANALOG")
539 ),
540 STM32_PIN(
541 PINCTRL_PIN(34, "PC2"),
542 STM32_FUNCTION(0, "GPIOC2"),
543 STM32_FUNCTION(4, "DFSDM_CK1"),
544 STM32_FUNCTION(6, "SPI2_MISO I2S2_SDI"),
545 STM32_FUNCTION(7, "DFSDM_CKOUT"),
546 STM32_FUNCTION(12, "ETH_GMII_TXD2 ETH_MII_TXD2 ETH_RGMII_TXD2"),
547 STM32_FUNCTION(16, "EVENTOUT"),
548 STM32_FUNCTION(17, "ANALOG")
549 ),
550 STM32_PIN(
551 PINCTRL_PIN(35, "PC3"),
552 STM32_FUNCTION(0, "GPIOC3"),
553 STM32_FUNCTION(1, "TRACECLK"),
554 STM32_FUNCTION(4, "DFSDM_DATA1"),
555 STM32_FUNCTION(6, "SPI2_MOSI I2S2_SDO"),
556 STM32_FUNCTION(12, "ETH_GMII_TX_CLK ETH_MII_TX_CLK"),
557 STM32_FUNCTION(16, "EVENTOUT"),
558 STM32_FUNCTION(17, "ANALOG")
559 ),
560 STM32_PIN(
561 PINCTRL_PIN(36, "PC4"),
562 STM32_FUNCTION(0, "GPIOC4"),
563 STM32_FUNCTION(4, "DFSDM_CK2"),
564 STM32_FUNCTION(6, "I2S1_MCK"),
565 STM32_FUNCTION(10, "SPDIF_IN2"),
566 STM32_FUNCTION(12, "ETH_GMII_RXD0 ETH_MII_RXD0 ETH_RGMII_RXD0 ETH_RMII_RXD0"),
567 STM32_FUNCTION(16, "EVENTOUT"),
568 STM32_FUNCTION(17, "ANALOG")
569 ),
570 STM32_PIN(
571 PINCTRL_PIN(37, "PC5"),
572 STM32_FUNCTION(0, "GPIOC5"),
573 STM32_FUNCTION(3, "SAI1_D3"),
574 STM32_FUNCTION(4, "DFSDM_DATA2"),
575 STM32_FUNCTION(5, "SAI4_D4"),
576 STM32_FUNCTION(7, "SAI1_D4"),
577 STM32_FUNCTION(10, "SPDIF_IN3"),
578 STM32_FUNCTION(12, "ETH_GMII_RXD1 ETH_MII_RXD1 ETH_RGMII_RXD1 ETH_RMII_RXD1"),
579 STM32_FUNCTION(13, "SAI4_D3"),
580 STM32_FUNCTION(16, "EVENTOUT"),
581 STM32_FUNCTION(17, "ANALOG")
582 ),
583 STM32_PIN(
584 PINCTRL_PIN(38, "PC6"),
585 STM32_FUNCTION(0, "GPIOC6"),
586 STM32_FUNCTION(1, "HDP1"),
587 STM32_FUNCTION(3, "TIM3_CH1"),
588 STM32_FUNCTION(4, "TIM8_CH1"),
589 STM32_FUNCTION(5, "DFSDM_CK3"),
590 STM32_FUNCTION(6, "I2S2_MCK"),
591 STM32_FUNCTION(8, "USART6_TX USART_BOOT6_TX"),
592 STM32_FUNCTION(9, "SDMMC1_D0DIR SDMMC_BOOT1_D0DIR"),
593 STM32_FUNCTION(10, "SDMMC2_D0DIR SDMMC_BOOT2_D0DIR"),
594 STM32_FUNCTION(11, "SDMMC2_D6 SDMMC_BOOT2_D6"),
595 STM32_FUNCTION(12, "DSI_TE"),
596 STM32_FUNCTION(13, "SDMMC1_D6 SDMMC_BOOT1_D6"),
597 STM32_FUNCTION(14, "DCMI_D0"),
598 STM32_FUNCTION(15, "LCD_HSYNC"),
599 STM32_FUNCTION(16, "EVENTOUT"),
600 STM32_FUNCTION(17, "ANALOG")
601 ),
602 STM32_PIN(
603 PINCTRL_PIN(39, "PC7"),
604 STM32_FUNCTION(0, "GPIOC7"),
605 STM32_FUNCTION(1, "HDP4"),
606 STM32_FUNCTION(3, "TIM3_CH2"),
607 STM32_FUNCTION(4, "TIM8_CH2"),
608 STM32_FUNCTION(5, "DFSDM_DATA3"),
609 STM32_FUNCTION(7, "I2S3_MCK"),
610 STM32_FUNCTION(8, "USART6_RX USART_BOOT6_RX"),
611 STM32_FUNCTION(9, "SDMMC1_D123DIR SDMMC_BOOT1_D123DIR"),
612 STM32_FUNCTION(10, "SDMMC2_D123DIR SDMMC_BOOT2_D123DIR"),
613 STM32_FUNCTION(11, "SDMMC2_D7 SDMMC_BOOT2_D7"),
614 STM32_FUNCTION(13, "SDMMC1_D7 SDMMC_BOOT1_D7"),
615 STM32_FUNCTION(14, "DCMI_D1"),
616 STM32_FUNCTION(15, "LCD_G6"),
617 STM32_FUNCTION(16, "EVENTOUT"),
618 STM32_FUNCTION(17, "ANALOG")
619 ),
620 STM32_PIN(
621 PINCTRL_PIN(40, "PC8"),
622 STM32_FUNCTION(0, "GPIOC8"),
623 STM32_FUNCTION(1, "TRACED0"),
624 STM32_FUNCTION(3, "TIM3_CH3"),
625 STM32_FUNCTION(4, "TIM8_CH3"),
626 STM32_FUNCTION(7, "UART4_TX"),
627 STM32_FUNCTION(8, "USART6_CK USART_BOOT6_CK"),
628 STM32_FUNCTION(9, "UART5_RTS UART_BOOT5_RTS"),
629 STM32_FUNCTION(13, "SDMMC1_D0 SDMMC_BOOT1_D0"),
630 STM32_FUNCTION(14, "DCMI_D2"),
631 STM32_FUNCTION(16, "EVENTOUT"),
632 STM32_FUNCTION(17, "ANALOG")
633 ),
634 STM32_PIN(
635 PINCTRL_PIN(41, "PC9"),
636 STM32_FUNCTION(0, "GPIOC9"),
637 STM32_FUNCTION(1, "TRACED1"),
638 STM32_FUNCTION(3, "TIM3_CH4"),
639 STM32_FUNCTION(4, "TIM8_CH4"),
640 STM32_FUNCTION(5, "I2C3_SDA"),
641 STM32_FUNCTION(6, "I2S_CKIN"),
642 STM32_FUNCTION(9, "UART5_CTS UART_BOOT5_CTS"),
643 STM32_FUNCTION(10, "QUADSPI_BK1_IO0"),
644 STM32_FUNCTION(13, "SDMMC1_D1 SDMMC_BOOT1_D1"),
645 STM32_FUNCTION(14, "DCMI_D3"),
646 STM32_FUNCTION(15, "LCD_B2"),
647 STM32_FUNCTION(16, "EVENTOUT"),
648 STM32_FUNCTION(17, "ANALOG")
649 ),
650 STM32_PIN(
651 PINCTRL_PIN(42, "PC10"),
652 STM32_FUNCTION(0, "GPIOC10"),
653 STM32_FUNCTION(1, "TRACED2"),
654 STM32_FUNCTION(4, "DFSDM_CK5"),
655 STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"),
656 STM32_FUNCTION(8, "USART3_TX"),
657 STM32_FUNCTION(9, "UART4_TX"),
658 STM32_FUNCTION(10, "QUADSPI_BK1_IO1"),
659 STM32_FUNCTION(11, "SAI4_MCLK_B"),
660 STM32_FUNCTION(13, "SDMMC1_D2 SDMMC_BOOT1_D2"),
661 STM32_FUNCTION(14, "DCMI_D8"),
662 STM32_FUNCTION(15, "LCD_R2"),
663 STM32_FUNCTION(16, "EVENTOUT"),
664 STM32_FUNCTION(17, "ANALOG")
665 ),
666 STM32_PIN(
667 PINCTRL_PIN(43, "PC11"),
668 STM32_FUNCTION(0, "GPIOC11"),
669 STM32_FUNCTION(1, "TRACED3"),
670 STM32_FUNCTION(4, "DFSDM_DATA5"),
671 STM32_FUNCTION(7, "SPI3_MISO I2S3_SDI"),
672 STM32_FUNCTION(8, "USART3_RX"),
673 STM32_FUNCTION(9, "UART4_RX"),
674 STM32_FUNCTION(10, "QUADSPI_BK2_NCS QUADSPI_BOOTBK2_NCS"),
675 STM32_FUNCTION(11, "SAI4_SCK_B"),
676 STM32_FUNCTION(13, "SDMMC1_D3 SDMMC_BOOT1_D3"),
677 STM32_FUNCTION(14, "DCMI_D4"),
678 STM32_FUNCTION(16, "EVENTOUT"),
679 STM32_FUNCTION(17, "ANALOG")
680 ),
681 STM32_PIN(
682 PINCTRL_PIN(44, "PC12"),
683 STM32_FUNCTION(0, "GPIOC12"),
684 STM32_FUNCTION(1, "TRACECLK"),
685 STM32_FUNCTION(2, "MCO2"),
686 STM32_FUNCTION(3, "SAI4_D3"),
687 STM32_FUNCTION(7, "SPI3_MOSI I2S3_SDO"),
688 STM32_FUNCTION(8, "USART3_CK USART_BOOT3_CK"),
689 STM32_FUNCTION(9, "UART5_TX"),
690 STM32_FUNCTION(11, "SAI4_SD_B"),
691 STM32_FUNCTION(13, "SDMMC1_CK SDMMC_BOOT1_CK"),
692 STM32_FUNCTION(14, "DCMI_D9"),
693 STM32_FUNCTION(16, "EVENTOUT"),
694 STM32_FUNCTION(17, "ANALOG")
695 ),
696 STM32_PIN(
697 PINCTRL_PIN(45, "PC13"),
698 STM32_FUNCTION(0, "GPIOC13"),
699 STM32_FUNCTION(16, "EVENTOUT"),
700 STM32_FUNCTION(17, "ANALOG")
701 ),
702 STM32_PIN(
703 PINCTRL_PIN(46, "PC14"),
704 STM32_FUNCTION(0, "GPIOC14"),
705 STM32_FUNCTION(16, "EVENTOUT"),
706 STM32_FUNCTION(17, "ANALOG")
707 ),
708 STM32_PIN(
709 PINCTRL_PIN(47, "PC15"),
710 STM32_FUNCTION(0, "GPIOC15"),
711 STM32_FUNCTION(16, "EVENTOUT"),
712 STM32_FUNCTION(17, "ANALOG")
713 ),
714 STM32_PIN(
715 PINCTRL_PIN(48, "PD0"),
716 STM32_FUNCTION(0, "GPIOD0"),
717 STM32_FUNCTION(3, "I2C6_SDA"),
718 STM32_FUNCTION(4, "DFSDM_CK6"),
719 STM32_FUNCTION(5, "I2C5_SDA"),
720 STM32_FUNCTION(7, "SAI3_SCK_A"),
721 STM32_FUNCTION(9, "UART4_RX"),
722 STM32_FUNCTION(10, "CAN1_RX"),
723 STM32_FUNCTION(11, "SDMMC3_CMD"),
724 STM32_FUNCTION(12, "DFSDM_DATA7"),
725 STM32_FUNCTION(13, "FMC_D2"),
726 STM32_FUNCTION(16, "EVENTOUT"),
727 STM32_FUNCTION(17, "ANALOG")
728 ),
729 STM32_PIN(
730 PINCTRL_PIN(49, "PD1"),
731 STM32_FUNCTION(0, "GPIOD1"),
732 STM32_FUNCTION(3, "I2C6_SCL"),
733 STM32_FUNCTION(4, "DFSDM_DATA6"),
734 STM32_FUNCTION(5, "I2C5_SCL"),
735 STM32_FUNCTION(7, "SAI3_SD_A"),
736 STM32_FUNCTION(9, "UART4_TX"),
737 STM32_FUNCTION(10, "CAN1_TX"),
738 STM32_FUNCTION(11, "SDMMC3_D0"),
739 STM32_FUNCTION(12, "DFSDM_CK7"),
740 STM32_FUNCTION(13, "FMC_D3"),
741 STM32_FUNCTION(16, "EVENTOUT"),
742 STM32_FUNCTION(17, "ANALOG")
743 ),
744 STM32_PIN(
745 PINCTRL_PIN(50, "PD2"),
746 STM32_FUNCTION(0, "GPIOD2"),
747 STM32_FUNCTION(3, "TIM3_ETR"),
748 STM32_FUNCTION(5, "I2C5_SMBA"),
749 STM32_FUNCTION(7, "UART4_RX"),
750 STM32_FUNCTION(9, "UART5_RX"),
751 STM32_FUNCTION(13, "SDMMC1_CMD SDMMC_BOOT1_CMD"),
752 STM32_FUNCTION(14, "DCMI_D11"),
753 STM32_FUNCTION(16, "EVENTOUT"),
754 STM32_FUNCTION(17, "ANALOG")
755 ),
756 STM32_PIN(
757 PINCTRL_PIN(51, "PD3"),
758 STM32_FUNCTION(0, "GPIOD3"),
759 STM32_FUNCTION(1, "HDP5"),
760 STM32_FUNCTION(4, "DFSDM_CKOUT"),
761 STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
762 STM32_FUNCTION(7, "DFSDM_DATA0"),
763 STM32_FUNCTION(8, "USART2_CTS_NSS USART_BOOT2_CTS_NSS"),
764 STM32_FUNCTION(9, "SDMMC1_D123DIR SDMMC_BOOT1_D123DIR"),
765 STM32_FUNCTION(10, "SDMMC2_D7 SDMMC_BOOT2_D7"),
766 STM32_FUNCTION(11, "SDMMC2_D123DIR SDMMC_BOOT2_D123DIR"),
767 STM32_FUNCTION(12, "SDMMC1_D7 SDMMC_BOOT1_D7"),
768 STM32_FUNCTION(13, "FMC_CLK"),
769 STM32_FUNCTION(14, "DCMI_D5"),
770 STM32_FUNCTION(15, "LCD_G7"),
771 STM32_FUNCTION(16, "EVENTOUT"),
772 STM32_FUNCTION(17, "ANALOG")
773 ),
774 STM32_PIN(
775 PINCTRL_PIN(52, "PD4"),
776 STM32_FUNCTION(0, "GPIOD4"),
777 STM32_FUNCTION(7, "SAI3_FS_A"),
778 STM32_FUNCTION(8, "USART2_RTS USART_BOOT2_RTS"),
779 STM32_FUNCTION(10, "CAN1_RXFD"),
780 STM32_FUNCTION(11, "SDMMC3_D1"),
781 STM32_FUNCTION(12, "DFSDM_CK0"),
782 STM32_FUNCTION(13, "FMC_NOE"),
783 STM32_FUNCTION(16, "EVENTOUT"),
784 STM32_FUNCTION(17, "ANALOG")
785 ),
786 STM32_PIN(
787 PINCTRL_PIN(53, "PD5"),
788 STM32_FUNCTION(0, "GPIOD5"),
789 STM32_FUNCTION(8, "USART2_TX"),
790 STM32_FUNCTION(10, "CAN1_TXFD"),
791 STM32_FUNCTION(11, "SDMMC3_D2"),
792 STM32_FUNCTION(13, "FMC_NWE"),
793 STM32_FUNCTION(16, "EVENTOUT"),
794 STM32_FUNCTION(17, "ANALOG")
795 ),
796 STM32_PIN(
797 PINCTRL_PIN(54, "PD6"),
798 STM32_FUNCTION(0, "GPIOD6"),
799 STM32_FUNCTION(2, "TIM16_CH1N"),
800 STM32_FUNCTION(3, "SAI1_D1"),
801 STM32_FUNCTION(4, "DFSDM_CK4"),
802 STM32_FUNCTION(5, "DFSDM_DATA1"),
803 STM32_FUNCTION(6, "SPI3_MOSI I2S3_SDO"),
804 STM32_FUNCTION(7, "SAI1_SD_A"),
805 STM32_FUNCTION(8, "USART2_RX"),
806 STM32_FUNCTION(10, "CAN2_RXFD"),
807 STM32_FUNCTION(11, "FMC_INT"),
808 STM32_FUNCTION(13, "FMC_NWAIT"),
809 STM32_FUNCTION(14, "DCMI_D10"),
810 STM32_FUNCTION(15, "LCD_B2"),
811 STM32_FUNCTION(16, "EVENTOUT"),
812 STM32_FUNCTION(17, "ANALOG")
813 ),
814 STM32_PIN(
815 PINCTRL_PIN(55, "PD7"),
816 STM32_FUNCTION(0, "GPIOD7"),
817 STM32_FUNCTION(1, "TRACED6"),
818 STM32_FUNCTION(4, "DFSDM_DATA4"),
819 STM32_FUNCTION(5, "I2C2_SCL"),
820 STM32_FUNCTION(7, "DFSDM_CK1"),
821 STM32_FUNCTION(8, "USART2_CK USART_BOOT2_CK"),
822 STM32_FUNCTION(10, "SPDIF_IN0"),
823 STM32_FUNCTION(11, "SDMMC3_D3"),
824 STM32_FUNCTION(13, "FMC_NE1"),
825 STM32_FUNCTION(16, "EVENTOUT"),
826 STM32_FUNCTION(17, "ANALOG")
827 ),
828 STM32_PIN(
829 PINCTRL_PIN(56, "PD8"),
830 STM32_FUNCTION(0, "GPIOD8"),
831 STM32_FUNCTION(4, "DFSDM_CK3"),
832 STM32_FUNCTION(7, "SAI3_SCK_B"),
833 STM32_FUNCTION(8, "USART3_TX"),
834 STM32_FUNCTION(10, "SPDIF_IN1"),
835 STM32_FUNCTION(13, "FMC_D13"),
836 STM32_FUNCTION(15, "LCD_B7"),
837 STM32_FUNCTION(16, "EVENTOUT"),
838 STM32_FUNCTION(17, "ANALOG")
839 ),
840 STM32_PIN(
841 PINCTRL_PIN(57, "PD9"),
842 STM32_FUNCTION(0, "GPIOD9"),
843 STM32_FUNCTION(4, "DFSDM_DATA3"),
844 STM32_FUNCTION(7, "SAI3_SD_B"),
845 STM32_FUNCTION(8, "USART3_RX"),
846 STM32_FUNCTION(10, "CAN2_RXFD"),
847 STM32_FUNCTION(13, "FMC_D14"),
848 STM32_FUNCTION(15, "LCD_B0"),
849 STM32_FUNCTION(16, "EVENTOUT"),
850 STM32_FUNCTION(17, "ANALOG")
851 ),
852 STM32_PIN(
853 PINCTRL_PIN(58, "PD10"),
854 STM32_FUNCTION(0, "GPIOD10"),
855 STM32_FUNCTION(1, "RTC_REFIN"),
856 STM32_FUNCTION(2, "TIM16_BKIN"),
857 STM32_FUNCTION(4, "DFSDM_CKOUT"),
858 STM32_FUNCTION(5, "I2C5_SMBA"),
859 STM32_FUNCTION(6, "SPI3_MISO I2S3_SDI"),
860 STM32_FUNCTION(7, "SAI3_FS_B"),
861 STM32_FUNCTION(8, "USART3_CK USART_BOOT3_CK"),
862 STM32_FUNCTION(10, "CAN2_TXFD"),
863 STM32_FUNCTION(13, "FMC_D15"),
864 STM32_FUNCTION(15, "LCD_B3"),
865 STM32_FUNCTION(16, "EVENTOUT"),
866 STM32_FUNCTION(17, "ANALOG")
867 ),
868 STM32_PIN(
869 PINCTRL_PIN(59, "PD11"),
870 STM32_FUNCTION(0, "GPIOD11"),
871 STM32_FUNCTION(4, "LPTIM2_IN2"),
872 STM32_FUNCTION(5, "I2C4_SMBA"),
873 STM32_FUNCTION(6, "I2C1_SMBA"),
874 STM32_FUNCTION(8, "USART3_CTS_NSS USART_BOOT3_CTS_NSS"),
875 STM32_FUNCTION(10, "QUADSPI_BK1_IO0"),
876 STM32_FUNCTION(11, "SAI2_SD_A"),
877 STM32_FUNCTION(13, "FMC_A16 FMC_CLE"),
878 STM32_FUNCTION(16, "EVENTOUT"),
879 STM32_FUNCTION(17, "ANALOG")
880 ),
881 STM32_PIN(
882 PINCTRL_PIN(60, "PD12"),
883 STM32_FUNCTION(0, "GPIOD12"),
884 STM32_FUNCTION(2, "LPTIM1_IN1"),
885 STM32_FUNCTION(3, "TIM4_CH1"),
886 STM32_FUNCTION(4, "LPTIM2_IN1"),
887 STM32_FUNCTION(5, "I2C4_SCL"),
888 STM32_FUNCTION(6, "I2C1_SCL"),
889 STM32_FUNCTION(8, "USART3_RTS USART_BOOT3_RTS"),
890 STM32_FUNCTION(10, "QUADSPI_BK1_IO1"),
891 STM32_FUNCTION(11, "SAI2_FS_A"),
892 STM32_FUNCTION(13, "FMC_A17 FMC_ALE"),
893 STM32_FUNCTION(16, "EVENTOUT"),
894 STM32_FUNCTION(17, "ANALOG")
895 ),
896 STM32_PIN(
897 PINCTRL_PIN(61, "PD13"),
898 STM32_FUNCTION(0, "GPIOD13"),
899 STM32_FUNCTION(2, "LPTIM1_OUT"),
900 STM32_FUNCTION(3, "TIM4_CH2"),
901 STM32_FUNCTION(5, "I2C4_SDA"),
902 STM32_FUNCTION(6, "I2C1_SDA"),
903 STM32_FUNCTION(7, "I2S3_MCK"),
904 STM32_FUNCTION(10, "QUADSPI_BK1_IO3 QUADSPI_BOOTBK1_IO3"),
905 STM32_FUNCTION(11, "SAI2_SCK_A"),
906 STM32_FUNCTION(13, "FMC_A18"),
907 STM32_FUNCTION(14, "DSI_TE"),
908 STM32_FUNCTION(16, "EVENTOUT"),
909 STM32_FUNCTION(17, "ANALOG")
910 ),
911 STM32_PIN(
912 PINCTRL_PIN(62, "PD14"),
913 STM32_FUNCTION(0, "GPIOD14"),
914 STM32_FUNCTION(3, "TIM4_CH3"),
915 STM32_FUNCTION(7, "SAI3_MCLK_B"),
916 STM32_FUNCTION(9, "UART8_CTS UART_BOOT8_CTS"),
917 STM32_FUNCTION(13, "FMC_D0"),
918 STM32_FUNCTION(16, "EVENTOUT"),
919 STM32_FUNCTION(17, "ANALOG")
920 ),
921 STM32_PIN(
922 PINCTRL_PIN(63, "PD15"),
923 STM32_FUNCTION(0, "GPIOD15"),
924 STM32_FUNCTION(3, "TIM4_CH4"),
925 STM32_FUNCTION(7, "SAI3_MCLK_A"),
926 STM32_FUNCTION(9, "UART8_CTS UART_BOOT8_CTS"),
927 STM32_FUNCTION(13, "FMC_D1"),
928 STM32_FUNCTION(16, "EVENTOUT"),
929 STM32_FUNCTION(17, "ANALOG")
930 ),
931 STM32_PIN(
932 PINCTRL_PIN(64, "PE0"),
933 STM32_FUNCTION(0, "GPIOE0"),
934 STM32_FUNCTION(2, "LPTIM1_ETR"),
935 STM32_FUNCTION(3, "TIM4_ETR"),
936 STM32_FUNCTION(5, "LPTIM2_ETR"),
937 STM32_FUNCTION(6, "SPI3_SCK I2S3_CK"),
938 STM32_FUNCTION(7, "SAI4_MCLK_B"),
939 STM32_FUNCTION(9, "UART8_RX UART_BOOT8_RX"),
940 STM32_FUNCTION(10, "CAN1_RXFD"),
941 STM32_FUNCTION(11, "SAI2_MCLK_A"),
942 STM32_FUNCTION(13, "FMC_NBL0"),
943 STM32_FUNCTION(14, "DCMI_D2"),
944 STM32_FUNCTION(16, "EVENTOUT"),
945 STM32_FUNCTION(17, "ANALOG")
946 ),
947 STM32_PIN(
948 PINCTRL_PIN(65, "PE1"),
949 STM32_FUNCTION(0, "GPIOE1"),
950 STM32_FUNCTION(2, "LPTIM1_IN2"),
951 STM32_FUNCTION(6, "I2S2_MCK"),
952 STM32_FUNCTION(7, "SAI3_SD_B"),
953 STM32_FUNCTION(9, "UART8_TX UART_BOOT8_TX"),
954 STM32_FUNCTION(10, "CAN1_TXFD"),
955 STM32_FUNCTION(13, "FMC_NBL1"),
956 STM32_FUNCTION(14, "DCMI_D3"),
957 STM32_FUNCTION(16, "EVENTOUT"),
958 STM32_FUNCTION(17, "ANALOG")
959 ),
960 STM32_PIN(
961 PINCTRL_PIN(66, "PE2"),
962 STM32_FUNCTION(0, "GPIOE2"),
963 STM32_FUNCTION(1, "TRACECLK"),
964 STM32_FUNCTION(3, "SAI1_CK1"),
965 STM32_FUNCTION(5, "I2C4_SCL"),
966 STM32_FUNCTION(6, "SPI4_SCK"),
967 STM32_FUNCTION(7, "SAI1_MCLK_A"),
968 STM32_FUNCTION(10, "QUADSPI_BK1_IO2 QUADSPI_BOOTBK1_IO2"),
969 STM32_FUNCTION(12, "ETH_GMII_TXD3 ETH_MII_TXD3 ETH_RGMII_TXD3"),
970 STM32_FUNCTION(13, "FMC_A23"),
971 STM32_FUNCTION(16, "EVENTOUT"),
972 STM32_FUNCTION(17, "ANALOG")
973 ),
974 STM32_PIN(
975 PINCTRL_PIN(67, "PE3"),
976 STM32_FUNCTION(0, "GPIOE3"),
977 STM32_FUNCTION(1, "TRACED0"),
978 STM32_FUNCTION(5, "TIM15_BKIN"),
979 STM32_FUNCTION(7, "SAI1_SD_B"),
980 STM32_FUNCTION(10, "SDMMC2_CK SDMMC_BOOT2_CK"),
981 STM32_FUNCTION(13, "FMC_A19"),
982 STM32_FUNCTION(16, "EVENTOUT"),
983 STM32_FUNCTION(17, "ANALOG")
984 ),
985 STM32_PIN(
986 PINCTRL_PIN(68, "PE4"),
987 STM32_FUNCTION(0, "GPIOE4"),
988 STM32_FUNCTION(1, "TRACED1"),
989 STM32_FUNCTION(3, "SAI1_D2"),
990 STM32_FUNCTION(4, "DFSDM_DATA3"),
991 STM32_FUNCTION(5, "TIM15_CH1N"),
992 STM32_FUNCTION(6, "SPI4_NSS"),
993 STM32_FUNCTION(7, "SAI1_FS_A"),
994 STM32_FUNCTION(8, "SDMMC2_CKIN SDMMC_BOOT2_CKIN"),
995 STM32_FUNCTION(9, "SDMMC1_CKIN SDMMC_BOOT1_CKIN"),
996 STM32_FUNCTION(10, "SDMMC2_D4 SDMMC_BOOT2_D4"),
997 STM32_FUNCTION(12, "SDMMC1_D4 SDMMC_BOOT1_D4"),
998 STM32_FUNCTION(13, "FMC_A20"),
999 STM32_FUNCTION(14, "DCMI_D4"),
1000 STM32_FUNCTION(15, "LCD_B0"),
1001 STM32_FUNCTION(16, "EVENTOUT"),
1002 STM32_FUNCTION(17, "ANALOG")
1003 ),
1004 STM32_PIN(
1005 PINCTRL_PIN(69, "PE5"),
1006 STM32_FUNCTION(0, "GPIOE5"),
1007 STM32_FUNCTION(1, "TRACED3"),
1008 STM32_FUNCTION(3, "SAI1_CK2"),
1009 STM32_FUNCTION(4, "DFSDM_CK3"),
1010 STM32_FUNCTION(5, "TIM15_CH1"),
1011 STM32_FUNCTION(6, "SPI4_MISO"),
1012 STM32_FUNCTION(7, "SAI1_SCK_A"),
1013 STM32_FUNCTION(8, "SDMMC2_D0DIR SDMMC_BOOT2_D0DIR"),
1014 STM32_FUNCTION(9, "SDMMC1_D0DIR SDMMC_BOOT1_D0DIR"),
1015 STM32_FUNCTION(10, "SDMMC2_D6 SDMMC_BOOT2_D6"),
1016 STM32_FUNCTION(12, "SDMMC1_D6 SDMMC_BOOT1_D6"),
1017 STM32_FUNCTION(13, "FMC_A21"),
1018 STM32_FUNCTION(14, "DCMI_D6"),
1019 STM32_FUNCTION(15, "LCD_G0"),
1020 STM32_FUNCTION(16, "EVENTOUT"),
1021 STM32_FUNCTION(17, "ANALOG")
1022 ),
1023 STM32_PIN(
1024 PINCTRL_PIN(70, "PE6"),
1025 STM32_FUNCTION(0, "GPIOE6"),
1026 STM32_FUNCTION(1, "TRACED2"),
1027 STM32_FUNCTION(2, "TIM1_BKIN2"),
1028 STM32_FUNCTION(3, "SAI1_D1"),
1029 STM32_FUNCTION(5, "TIM15_CH2"),
1030 STM32_FUNCTION(6, "SPI4_MOSI"),
1031 STM32_FUNCTION(7, "SAI1_SD_A"),
1032 STM32_FUNCTION(8, "SDMMC2_D0"),
1033 STM32_FUNCTION(9, "SDMMC1_D2 SDMMC_BOOT1_D2"),
1034 STM32_FUNCTION(11, "SAI2_MCLK_B"),
1035 STM32_FUNCTION(13, "FMC_A22"),
1036 STM32_FUNCTION(14, "DCMI_D7"),
1037 STM32_FUNCTION(15, "LCD_G1"),
1038 STM32_FUNCTION(16, "EVENTOUT"),
1039 STM32_FUNCTION(17, "ANALOG")
1040 ),
1041 STM32_PIN(
1042 PINCTRL_PIN(71, "PE7"),
1043 STM32_FUNCTION(0, "GPIOE7"),
1044 STM32_FUNCTION(2, "TIM1_ETR"),
1045 STM32_FUNCTION(3, "TIM3_ETR"),
1046 STM32_FUNCTION(4, "DFSDM_DATA2"),
1047 STM32_FUNCTION(8, "UART7_RX"),
1048 STM32_FUNCTION(11, "QUADSPI_BK2_IO0 QUADSPI_BOOTBK2_IO0"),
1049 STM32_FUNCTION(13, "FMC_D4"),
1050 STM32_FUNCTION(16, "EVENTOUT"),
1051 STM32_FUNCTION(17, "ANALOG")
1052 ),
1053 STM32_PIN(
1054 PINCTRL_PIN(72, "PE8"),
1055 STM32_FUNCTION(0, "GPIOE8"),
1056 STM32_FUNCTION(2, "TIM1_CH1N"),
1057 STM32_FUNCTION(4, "DFSDM_CK2"),
1058 STM32_FUNCTION(8, "UART7_TX"),
1059 STM32_FUNCTION(11, "QUADSPI_BK2_IO1 QUADSPI_BOOTBK2_IO1"),
1060 STM32_FUNCTION(13, "FMC_D5"),
1061 STM32_FUNCTION(16, "EVENTOUT"),
1062 STM32_FUNCTION(17, "ANALOG")
1063 ),
1064 STM32_PIN(
1065 PINCTRL_PIN(73, "PE9"),
1066 STM32_FUNCTION(0, "GPIOE9"),
1067 STM32_FUNCTION(2, "TIM1_CH1"),
1068 STM32_FUNCTION(4, "DFSDM_CKOUT"),
1069 STM32_FUNCTION(8, "UART7_RTS UART_BOOT7_RTS"),
1070 STM32_FUNCTION(11, "QUADSPI_BK2_IO2 QUADSPI_BOOTBK2_IO2"),
1071 STM32_FUNCTION(13, "FMC_D6"),
1072 STM32_FUNCTION(16, "EVENTOUT"),
1073 STM32_FUNCTION(17, "ANALOG")
1074 ),
1075 STM32_PIN(
1076 PINCTRL_PIN(74, "PE10"),
1077 STM32_FUNCTION(0, "GPIOE10"),
1078 STM32_FUNCTION(2, "TIM1_CH2N"),
1079 STM32_FUNCTION(4, "DFSDM_DATA4"),
1080 STM32_FUNCTION(8, "UART7_CTS UART_BOOT7_CTS"),
1081 STM32_FUNCTION(11, "QUADSPI_BK2_IO3 QUADSPI_BOOTBK2_IO3"),
1082 STM32_FUNCTION(13, "FMC_D7"),
1083 STM32_FUNCTION(16, "EVENTOUT"),
1084 STM32_FUNCTION(17, "ANALOG")
1085 ),
1086 STM32_PIN(
1087 PINCTRL_PIN(75, "PE11"),
1088 STM32_FUNCTION(0, "GPIOE11"),
1089 STM32_FUNCTION(2, "TIM1_CH2"),
1090 STM32_FUNCTION(4, "DFSDM_CK4"),
1091 STM32_FUNCTION(6, "SPI4_NSS"),
1092 STM32_FUNCTION(8, "USART6_CK USART_BOOT6_CK"),
1093 STM32_FUNCTION(11, "SAI2_SD_B"),
1094 STM32_FUNCTION(13, "FMC_D8"),
1095 STM32_FUNCTION(15, "LCD_G3"),
1096 STM32_FUNCTION(16, "EVENTOUT"),
1097 STM32_FUNCTION(17, "ANALOG")
1098 ),
1099 STM32_PIN(
1100 PINCTRL_PIN(76, "PE12"),
1101 STM32_FUNCTION(0, "GPIOE12"),
1102 STM32_FUNCTION(2, "TIM1_CH3N"),
1103 STM32_FUNCTION(4, "DFSDM_DATA5"),
1104 STM32_FUNCTION(6, "SPI4_SCK"),
1105 STM32_FUNCTION(9, "SDMMC1_D0DIR SDMMC_BOOT1_D0DIR"),
1106 STM32_FUNCTION(11, "SAI2_SCK_B"),
1107 STM32_FUNCTION(13, "FMC_D9"),
1108 STM32_FUNCTION(15, "LCD_B4"),
1109 STM32_FUNCTION(16, "EVENTOUT"),
1110 STM32_FUNCTION(17, "ANALOG")
1111 ),
1112 STM32_PIN(
1113 PINCTRL_PIN(77, "PE13"),
1114 STM32_FUNCTION(0, "GPIOE13"),
1115 STM32_FUNCTION(1, "HDP2"),
1116 STM32_FUNCTION(2, "TIM1_CH3"),
1117 STM32_FUNCTION(4, "DFSDM_CK5"),
1118 STM32_FUNCTION(6, "SPI4_MISO"),
1119 STM32_FUNCTION(11, "SAI2_FS_B"),
1120 STM32_FUNCTION(13, "FMC_D10"),
1121 STM32_FUNCTION(15, "LCD_DE"),
1122 STM32_FUNCTION(16, "EVENTOUT"),
1123 STM32_FUNCTION(17, "ANALOG")
1124 ),
1125 STM32_PIN(
1126 PINCTRL_PIN(78, "PE14"),
1127 STM32_FUNCTION(0, "GPIOE14"),
1128 STM32_FUNCTION(2, "TIM1_CH4"),
1129 STM32_FUNCTION(6, "SPI4_MOSI"),
1130 STM32_FUNCTION(9, "UART8_RTS UART_BOOT8_RTS"),
1131 STM32_FUNCTION(11, "SAI2_MCLK_B"),
1132 STM32_FUNCTION(12, "SDMMC1_D123DIR SDMMC_BOOT1_D123DIR"),
1133 STM32_FUNCTION(13, "FMC_D11"),
1134 STM32_FUNCTION(14, "LCD_G0"),
1135 STM32_FUNCTION(15, "LCD_CLK"),
1136 STM32_FUNCTION(16, "EVENTOUT"),
1137 STM32_FUNCTION(17, "ANALOG")
1138 ),
1139 STM32_PIN(
1140 PINCTRL_PIN(79, "PE15"),
1141 STM32_FUNCTION(0, "GPIOE15"),
1142 STM32_FUNCTION(1, "HDP3"),
1143 STM32_FUNCTION(2, "TIM1_BKIN"),
1144 STM32_FUNCTION(5, "TIM15_BKIN"),
1145 STM32_FUNCTION(8, "USART2_CTS_NSS USART_BOOT2_CTS_NSS"),
1146 STM32_FUNCTION(9, "UART8_CTS UART_BOOT8_CTS"),
1147 STM32_FUNCTION(13, "FMC_D12"),
1148 STM32_FUNCTION(15, "LCD_R7"),
1149 STM32_FUNCTION(16, "EVENTOUT"),
1150 STM32_FUNCTION(17, "ANALOG")
1151 ),
1152 STM32_PIN(
1153 PINCTRL_PIN(80, "PF0"),
1154 STM32_FUNCTION(0, "GPIOF0"),
1155 STM32_FUNCTION(5, "I2C2_SDA"),
1156 STM32_FUNCTION(10, "SDMMC3_D0"),
1157 STM32_FUNCTION(11, "SDMMC3_CKIN"),
1158 STM32_FUNCTION(13, "FMC_A0"),
1159 STM32_FUNCTION(16, "EVENTOUT"),
1160 STM32_FUNCTION(17, "ANALOG")
1161 ),
1162 STM32_PIN(
1163 PINCTRL_PIN(81, "PF1"),
1164 STM32_FUNCTION(0, "GPIOF1"),
1165 STM32_FUNCTION(5, "I2C2_SCL"),
1166 STM32_FUNCTION(10, "SDMMC3_CMD"),
1167 STM32_FUNCTION(11, "SDMMC3_CDIR"),
1168 STM32_FUNCTION(13, "FMC_A1"),
1169 STM32_FUNCTION(16, "EVENTOUT"),
1170 STM32_FUNCTION(17, "ANALOG")
1171 ),
1172 STM32_PIN(
1173 PINCTRL_PIN(82, "PF2"),
1174 STM32_FUNCTION(0, "GPIOF2"),
1175 STM32_FUNCTION(5, "I2C2_SMBA"),
1176 STM32_FUNCTION(10, "SDMMC2_D0DIR SDMMC_BOOT2_D0DIR"),
1177 STM32_FUNCTION(11, "SDMMC3_D0DIR"),
1178 STM32_FUNCTION(12, "SDMMC1_D0DIR SDMMC_BOOT1_D0DIR"),
1179 STM32_FUNCTION(13, "FMC_A2"),
1180 STM32_FUNCTION(16, "EVENTOUT"),
1181 STM32_FUNCTION(17, "ANALOG")
1182 ),
1183 STM32_PIN(
1184 PINCTRL_PIN(83, "PF3"),
1185 STM32_FUNCTION(0, "GPIOF3"),
1186 STM32_FUNCTION(12, "ETH_GMII_TX_ER ETH_MII_TX_ER"),
1187 STM32_FUNCTION(13, "FMC_A3"),
1188 STM32_FUNCTION(16, "EVENTOUT"),
1189 STM32_FUNCTION(17, "ANALOG")
1190 ),
1191 STM32_PIN(
1192 PINCTRL_PIN(84, "PF4"),
1193 STM32_FUNCTION(0, "GPIOF4"),
1194 STM32_FUNCTION(8, "USART2_RX"),
1195 STM32_FUNCTION(10, "SDMMC3_D1"),
1196 STM32_FUNCTION(11, "SDMMC3_D123DIR"),
1197 STM32_FUNCTION(13, "FMC_A4"),
1198 STM32_FUNCTION(16, "EVENTOUT"),
1199 STM32_FUNCTION(17, "ANALOG")
1200 ),
1201 STM32_PIN(
1202 PINCTRL_PIN(85, "PF5"),
1203 STM32_FUNCTION(0, "GPIOF5"),
1204 STM32_FUNCTION(8, "USART2_TX"),
1205 STM32_FUNCTION(10, "SDMMC3_D2"),
1206 STM32_FUNCTION(13, "FMC_A5"),
1207 STM32_FUNCTION(16, "EVENTOUT"),
1208 STM32_FUNCTION(17, "ANALOG")
1209 ),
1210 STM32_PIN(
1211 PINCTRL_PIN(86, "PF6"),
1212 STM32_FUNCTION(0, "GPIOF6"),
1213 STM32_FUNCTION(2, "TIM16_CH1"),
1214 STM32_FUNCTION(6, "SPI5_NSS"),
1215 STM32_FUNCTION(7, "SAI1_SD_B"),
1216 STM32_FUNCTION(8, "UART7_RX UART_BOOT7_RX"),
1217 STM32_FUNCTION(10, "QUADSPI_BK1_IO3 QUADSPI_BOOTBK1_IO3"),
1218 STM32_FUNCTION(13, "SAI4_SCK_B"),
1219 STM32_FUNCTION(16, "EVENTOUT"),
1220 STM32_FUNCTION(17, "ANALOG")
1221 ),
1222 STM32_PIN(
1223 PINCTRL_PIN(87, "PF7"),
1224 STM32_FUNCTION(0, "GPIOF7"),
1225 STM32_FUNCTION(2, "TIM17_CH1"),
1226 STM32_FUNCTION(6, "SPI5_SCK"),
1227 STM32_FUNCTION(7, "SAI1_MCLK_B"),
1228 STM32_FUNCTION(8, "UART7_TX UART_BOOT7_TX"),
1229 STM32_FUNCTION(10, "QUADSPI_BK1_IO2 QUADSPI_BOOTBK1_IO2"),
1230 STM32_FUNCTION(16, "EVENTOUT"),
1231 STM32_FUNCTION(17, "ANALOG")
1232 ),
1233 STM32_PIN(
1234 PINCTRL_PIN(88, "PF8"),
1235 STM32_FUNCTION(0, "GPIOF8"),
1236 STM32_FUNCTION(1, "TRACED12"),
1237 STM32_FUNCTION(2, "TIM16_CH1N"),
1238 STM32_FUNCTION(6, "SPI5_MISO"),
1239 STM32_FUNCTION(7, "SAI1_SCK_B"),
1240 STM32_FUNCTION(8, "UART7_RTS UART_BOOT7_RTS"),
1241 STM32_FUNCTION(10, "TIM13_CH1"),
1242 STM32_FUNCTION(11, "QUADSPI_BK1_IO0 QUADSPI_BOOTBK1_IO0"),
1243 STM32_FUNCTION(16, "EVENTOUT"),
1244 STM32_FUNCTION(17, "ANALOG")
1245 ),
1246 STM32_PIN(
1247 PINCTRL_PIN(89, "PF9"),
1248 STM32_FUNCTION(0, "GPIOF9"),
1249 STM32_FUNCTION(1, "TRACED13"),
1250 STM32_FUNCTION(2, "TIM17_CH1N"),
1251 STM32_FUNCTION(6, "SPI5_MOSI"),
1252 STM32_FUNCTION(7, "SAI1_FS_B"),
1253 STM32_FUNCTION(8, "UART7_CTS UART_BOOT7_CTS"),
1254 STM32_FUNCTION(10, "TIM14_CH1"),
1255 STM32_FUNCTION(11, "QUADSPI_BK1_IO1 QUADSPI_BOOTBK1_IO1"),
1256 STM32_FUNCTION(16, "EVENTOUT"),
1257 STM32_FUNCTION(17, "ANALOG")
1258 ),
1259 STM32_PIN(
1260 PINCTRL_PIN(90, "PF10"),
1261 STM32_FUNCTION(0, "GPIOF10"),
1262 STM32_FUNCTION(2, "TIM16_BKIN"),
1263 STM32_FUNCTION(3, "SAI1_D3"),
1264 STM32_FUNCTION(4, "SAI4_D4"),
1265 STM32_FUNCTION(7, "SAI1_D4"),
1266 STM32_FUNCTION(10, "QUADSPI_CLK QUADSPI_BOOTCLK"),
1267 STM32_FUNCTION(13, "SAI4_D3"),
1268 STM32_FUNCTION(14, "DCMI_D11"),
1269 STM32_FUNCTION(15, "LCD_DE"),
1270 STM32_FUNCTION(16, "EVENTOUT"),
1271 STM32_FUNCTION(17, "ANALOG")
1272 ),
1273 STM32_PIN(
1274 PINCTRL_PIN(91, "PF11"),
1275 STM32_FUNCTION(0, "GPIOF11"),
1276 STM32_FUNCTION(6, "SPI5_MOSI"),
1277 STM32_FUNCTION(11, "SAI2_SD_B"),
1278 STM32_FUNCTION(14, "DCMI_D12"),
1279 STM32_FUNCTION(15, "LCD_G5"),
1280 STM32_FUNCTION(16, "EVENTOUT"),
1281 STM32_FUNCTION(17, "ANALOG")
1282 ),
1283 STM32_PIN(
1284 PINCTRL_PIN(92, "PF12"),
1285 STM32_FUNCTION(0, "GPIOF12"),
1286 STM32_FUNCTION(1, "TRACED4"),
1287 STM32_FUNCTION(12, "ETH_GMII_RXD4"),
1288 STM32_FUNCTION(13, "FMC_A6"),
1289 STM32_FUNCTION(16, "EVENTOUT"),
1290 STM32_FUNCTION(17, "ANALOG")
1291 ),
1292 STM32_PIN(
1293 PINCTRL_PIN(93, "PF13"),
1294 STM32_FUNCTION(0, "GPIOF13"),
1295 STM32_FUNCTION(1, "TRACED5"),
1296 STM32_FUNCTION(4, "DFSDM_DATA6"),
1297 STM32_FUNCTION(5, "I2C4_SMBA"),
1298 STM32_FUNCTION(6, "I2C1_SMBA"),
1299 STM32_FUNCTION(7, "DFSDM_DATA3"),
1300 STM32_FUNCTION(12, "ETH_GMII_RXD5"),
1301 STM32_FUNCTION(13, "FMC_A7"),
1302 STM32_FUNCTION(16, "EVENTOUT"),
1303 STM32_FUNCTION(17, "ANALOG")
1304 ),
1305 STM32_PIN(
1306 PINCTRL_PIN(94, "PF14"),
1307 STM32_FUNCTION(0, "GPIOF14"),
1308 STM32_FUNCTION(1, "TRACED6"),
1309 STM32_FUNCTION(4, "DFSDM_CK6"),
1310 STM32_FUNCTION(5, "I2C4_SCL"),
1311 STM32_FUNCTION(6, "I2C1_SCL"),
1312 STM32_FUNCTION(12, "ETH_GMII_RXD6"),
1313 STM32_FUNCTION(13, "FMC_A8"),
1314 STM32_FUNCTION(16, "EVENTOUT"),
1315 STM32_FUNCTION(17, "ANALOG")
1316 ),
1317 STM32_PIN(
1318 PINCTRL_PIN(95, "PF15"),
1319 STM32_FUNCTION(0, "GPIOF15"),
1320 STM32_FUNCTION(1, "TRACED7"),
1321 STM32_FUNCTION(5, "I2C4_SDA"),
1322 STM32_FUNCTION(6, "I2C1_SDA"),
1323 STM32_FUNCTION(12, "ETH_GMII_RXD7"),
1324 STM32_FUNCTION(13, "FMC_A9"),
1325 STM32_FUNCTION(16, "EVENTOUT"),
1326 STM32_FUNCTION(17, "ANALOG")
1327 ),
1328 STM32_PIN(
1329 PINCTRL_PIN(96, "PG0"),
1330 STM32_FUNCTION(0, "GPIOG0"),
1331 STM32_FUNCTION(1, "TRACED0"),
1332 STM32_FUNCTION(4, "DFSDM_DATA0"),
1333 STM32_FUNCTION(12, "ETH_GMII_TXD4"),
1334 STM32_FUNCTION(13, "FMC_A10"),
1335 STM32_FUNCTION(16, "EVENTOUT"),
1336 STM32_FUNCTION(17, "ANALOG")
1337 ),
1338 STM32_PIN(
1339 PINCTRL_PIN(97, "PG1"),
1340 STM32_FUNCTION(0, "GPIOG1"),
1341 STM32_FUNCTION(1, "TRACED1"),
1342 STM32_FUNCTION(12, "ETH_GMII_TXD5"),
1343 STM32_FUNCTION(13, "FMC_A11"),
1344 STM32_FUNCTION(16, "EVENTOUT"),
1345 STM32_FUNCTION(17, "ANALOG")
1346 ),
1347 STM32_PIN(
1348 PINCTRL_PIN(98, "PG2"),
1349 STM32_FUNCTION(0, "GPIOG2"),
1350 STM32_FUNCTION(1, "TRACED2"),
1351 STM32_FUNCTION(2, "MCO2"),
1352 STM32_FUNCTION(4, "TIM8_BKIN"),
1353 STM32_FUNCTION(12, "ETH_GMII_TXD6"),
1354 STM32_FUNCTION(13, "FMC_A12"),
1355 STM32_FUNCTION(16, "EVENTOUT"),
1356 STM32_FUNCTION(17, "ANALOG")
1357 ),
1358 STM32_PIN(
1359 PINCTRL_PIN(99, "PG3"),
1360 STM32_FUNCTION(0, "GPIOG3"),
1361 STM32_FUNCTION(1, "TRACED3"),
1362 STM32_FUNCTION(4, "TIM8_BKIN2"),
1363 STM32_FUNCTION(5, "DFSDM_CK1"),
1364 STM32_FUNCTION(12, "ETH_GMII_TXD7"),
1365 STM32_FUNCTION(13, "FMC_A13"),
1366 STM32_FUNCTION(16, "EVENTOUT"),
1367 STM32_FUNCTION(17, "ANALOG")
1368 ),
1369 STM32_PIN(
1370 PINCTRL_PIN(100, "PG4"),
1371 STM32_FUNCTION(0, "GPIOG4"),
1372 STM32_FUNCTION(2, "TIM1_BKIN2"),
1373 STM32_FUNCTION(12, "ETH_GMII_GTX_CLK ETH_RGMII_GTX_CLK"),
1374 STM32_FUNCTION(13, "FMC_A14"),
1375 STM32_FUNCTION(16, "EVENTOUT"),
1376 STM32_FUNCTION(17, "ANALOG")
1377 ),
1378 STM32_PIN(
1379 PINCTRL_PIN(101, "PG5"),
1380 STM32_FUNCTION(0, "GPIOG5"),
1381 STM32_FUNCTION(2, "TIM1_ETR"),
1382 STM32_FUNCTION(12, "ETH_GMII_CLK125 ETH_RGMII_CLK125"),
1383 STM32_FUNCTION(13, "FMC_A15"),
1384 STM32_FUNCTION(16, "EVENTOUT"),
1385 STM32_FUNCTION(17, "ANALOG")
1386 ),
1387 STM32_PIN(
1388 PINCTRL_PIN(102, "PG6"),
1389 STM32_FUNCTION(0, "GPIOG6"),
1390 STM32_FUNCTION(1, "TRACED14"),
1391 STM32_FUNCTION(2, "TIM17_BKIN"),
1392 STM32_FUNCTION(11, "SDMMC2_CMD SDMMC_BOOT2_CMD"),
1393 STM32_FUNCTION(14, "DCMI_D12"),
1394 STM32_FUNCTION(15, "LCD_R7"),
1395 STM32_FUNCTION(16, "EVENTOUT"),
1396 STM32_FUNCTION(17, "ANALOG")
1397 ),
1398 STM32_PIN(
1399 PINCTRL_PIN(103, "PG7"),
1400 STM32_FUNCTION(0, "GPIOG7"),
1401 STM32_FUNCTION(1, "TRACED5"),
1402 STM32_FUNCTION(7, "SAI1_MCLK_A"),
1403 STM32_FUNCTION(8, "USART6_CK USART_BOOT6_CK"),
1404 STM32_FUNCTION(9, "UART8_RTS UART_BOOT8_RTS"),
1405 STM32_FUNCTION(10, "QUADSPI_CLK"),
1406 STM32_FUNCTION(12, "QUADSPI_BK2_IO3 QUADSPI_BOOTBK2_IO3"),
1407 STM32_FUNCTION(13, "FMC_INT"),
1408 STM32_FUNCTION(14, "DCMI_D13"),
1409 STM32_FUNCTION(15, "LCD_CLK"),
1410 STM32_FUNCTION(16, "EVENTOUT"),
1411 STM32_FUNCTION(17, "ANALOG")
1412 ),
1413 STM32_PIN(
1414 PINCTRL_PIN(104, "PG8"),
1415 STM32_FUNCTION(0, "GPIOG8"),
1416 STM32_FUNCTION(1, "TRACED15"),
1417 STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
1418 STM32_FUNCTION(3, "ETH_CLK"),
1419 STM32_FUNCTION(4, "TIM8_ETR"),
1420 STM32_FUNCTION(6, "SPI6_NSS"),
1421 STM32_FUNCTION(7, "SAI4_D2"),
1422 STM32_FUNCTION(8, "USART6_RTS USART_BOOT6_RTS"),
1423 STM32_FUNCTION(9, "USART3_RTS"),
1424 STM32_FUNCTION(10, "SPDIF_IN2"),
1425 STM32_FUNCTION(11, "SAI4_FS_A"),
1426 STM32_FUNCTION(12, "ETH_PPS_OUT"),
1427 STM32_FUNCTION(15, "LCD_G7"),
1428 STM32_FUNCTION(16, "EVENTOUT"),
1429 STM32_FUNCTION(17, "ANALOG")
1430 ),
1431 STM32_PIN(
1432 PINCTRL_PIN(105, "PG9"),
1433 STM32_FUNCTION(0, "GPIOG9"),
1434 STM32_FUNCTION(1, "DBTRGO"),
1435 STM32_FUNCTION(8, "USART6_RX"),
1436 STM32_FUNCTION(9, "SPDIF_IN3"),
1437 STM32_FUNCTION(10, "QUADSPI_BK2_IO2 QUADSPI_BOOTBK2_IO2"),
1438 STM32_FUNCTION(11, "SAI2_FS_B"),
1439 STM32_FUNCTION(13, "FMC_NE2 FMC_NCE"),
1440 STM32_FUNCTION(14, "DCMI_VSYNC"),
1441 STM32_FUNCTION(16, "EVENTOUT"),
1442 STM32_FUNCTION(17, "ANALOG")
1443 ),
1444 STM32_PIN(
1445 PINCTRL_PIN(106, "PG10"),
1446 STM32_FUNCTION(0, "GPIOG10"),
1447 STM32_FUNCTION(1, "TRACED10"),
1448 STM32_FUNCTION(9, "UART8_CTS UART_BOOT8_CTS"),
1449 STM32_FUNCTION(10, "LCD_G3"),
1450 STM32_FUNCTION(11, "SAI2_SD_B"),
1451 STM32_FUNCTION(12, "QUADSPI_BK2_IO2 QUADSPI_BOOTBK2_IO2"),
1452 STM32_FUNCTION(13, "FMC_NE3"),
1453 STM32_FUNCTION(14, "DCMI_D2"),
1454 STM32_FUNCTION(15, "LCD_B2"),
1455 STM32_FUNCTION(16, "EVENTOUT"),
1456 STM32_FUNCTION(17, "ANALOG")
1457 ),
1458 STM32_PIN(
1459 PINCTRL_PIN(107, "PG11"),
1460 STM32_FUNCTION(0, "GPIOG11"),
1461 STM32_FUNCTION(1, "TRACED11"),
1462 STM32_FUNCTION(5, "USART1_TX"),
1463 STM32_FUNCTION(7, "UART4_TX UART_BOOT4_TX"),
1464 STM32_FUNCTION(9, "SPDIF_IN0"),
1465 STM32_FUNCTION(12, "ETH_GMII_TX_EN ETH_MII_TX_EN ETH_RGMII_TX_CTL ETH_RMII_TX_EN"),
1466 STM32_FUNCTION(14, "DCMI_D3"),
1467 STM32_FUNCTION(15, "LCD_B3"),
1468 STM32_FUNCTION(16, "EVENTOUT"),
1469 STM32_FUNCTION(17, "ANALOG")
1470 ),
1471 STM32_PIN(
1472 PINCTRL_PIN(108, "PG12"),
1473 STM32_FUNCTION(0, "GPIOG12"),
1474 STM32_FUNCTION(2, "LPTIM1_IN1"),
1475 STM32_FUNCTION(6, "SPI6_MISO"),
1476 STM32_FUNCTION(7, "SAI4_CK2"),
1477 STM32_FUNCTION(8, "USART6_RTS USART_BOOT6_RTS"),
1478 STM32_FUNCTION(9, "SPDIF_IN1"),
1479 STM32_FUNCTION(10, "LCD_B4"),
1480 STM32_FUNCTION(11, "SAI4_SCK_A"),
1481 STM32_FUNCTION(12, "ETH_PHY_INTN"),
1482 STM32_FUNCTION(13, "FMC_NE4"),
1483 STM32_FUNCTION(15, "LCD_B1"),
1484 STM32_FUNCTION(16, "EVENTOUT"),
1485 STM32_FUNCTION(17, "ANALOG")
1486 ),
1487 STM32_PIN(
1488 PINCTRL_PIN(109, "PG13"),
1489 STM32_FUNCTION(0, "GPIOG13"),
1490 STM32_FUNCTION(1, "TRACED0"),
1491 STM32_FUNCTION(2, "LPTIM1_OUT"),
1492 STM32_FUNCTION(3, "SAI1_CK2"),
1493 STM32_FUNCTION(5, "SAI4_CK1"),
1494 STM32_FUNCTION(6, "SPI6_SCK"),
1495 STM32_FUNCTION(7, "SAI1_SCK_A"),
1496 STM32_FUNCTION(8, "USART6_CTS_NSS USART_BOOT6_CTS_NSS"),
1497 STM32_FUNCTION(11, "SAI4_MCLK_A"),
1498 STM32_FUNCTION(12, "ETH_GMII_TXD0 ETH_MII_TXD0 ETH_RGMII_TXD0 ETH_RMII_TXD0"),
1499 STM32_FUNCTION(13, "FMC_A24"),
1500 STM32_FUNCTION(15, "LCD_R0"),
1501 STM32_FUNCTION(16, "EVENTOUT"),
1502 STM32_FUNCTION(17, "ANALOG")
1503 ),
1504 STM32_PIN(
1505 PINCTRL_PIN(110, "PG14"),
1506 STM32_FUNCTION(0, "GPIOG14"),
1507 STM32_FUNCTION(1, "TRACED1"),
1508 STM32_FUNCTION(2, "LPTIM1_ETR"),
1509 STM32_FUNCTION(6, "SPI6_MOSI"),
1510 STM32_FUNCTION(7, "SAI4_D1"),
1511 STM32_FUNCTION(8, "USART6_TX"),
1512 STM32_FUNCTION(10, "QUADSPI_BK2_IO3 QUADSPI_BOOTBK2_IO3"),
1513 STM32_FUNCTION(11, "SAI4_SD_A"),
1514 STM32_FUNCTION(12, "ETH_GMII_TXD1 ETH_MII_TXD1 ETH_RGMII_TXD1 ETH_RMII_TXD1"),
1515 STM32_FUNCTION(13, "FMC_A25"),
1516 STM32_FUNCTION(15, "LCD_B0"),
1517 STM32_FUNCTION(16, "EVENTOUT"),
1518 STM32_FUNCTION(17, "ANALOG")
1519 ),
1520 STM32_PIN(
1521 PINCTRL_PIN(111, "PG15"),
1522 STM32_FUNCTION(0, "GPIOG15"),
1523 STM32_FUNCTION(1, "TRACED7"),
1524 STM32_FUNCTION(3, "SAI1_D2"),
1525 STM32_FUNCTION(5, "I2C2_SDA"),
1526 STM32_FUNCTION(7, "SAI1_FS_A"),
1527 STM32_FUNCTION(8, "USART6_CTS_NSS USART_BOOT6_CTS_NSS"),
1528 STM32_FUNCTION(11, "SDMMC3_CK"),
1529 STM32_FUNCTION(14, "DCMI_D13"),
1530 STM32_FUNCTION(16, "EVENTOUT"),
1531 STM32_FUNCTION(17, "ANALOG")
1532 ),
1533 STM32_PIN(
1534 PINCTRL_PIN(112, "PH0"),
1535 STM32_FUNCTION(0, "GPIOH0"),
1536 STM32_FUNCTION(16, "EVENTOUT"),
1537 STM32_FUNCTION(17, "ANALOG")
1538 ),
1539 STM32_PIN(
1540 PINCTRL_PIN(113, "PH1"),
1541 STM32_FUNCTION(0, "GPIOH1"),
1542 STM32_FUNCTION(16, "EVENTOUT"),
1543 STM32_FUNCTION(17, "ANALOG")
1544 ),
1545 STM32_PIN(
1546 PINCTRL_PIN(114, "PH2"),
1547 STM32_FUNCTION(0, "GPIOH2"),
1548 STM32_FUNCTION(2, "LPTIM1_IN2"),
1549 STM32_FUNCTION(10, "QUADSPI_BK2_IO0 QUADSPI_BOOTBK2_IO0"),
1550 STM32_FUNCTION(11, "SAI2_SCK_B"),
1551 STM32_FUNCTION(12, "ETH_GMII_CRS ETH_MII_CRS"),
1552 STM32_FUNCTION(15, "LCD_R0"),
1553 STM32_FUNCTION(16, "EVENTOUT"),
1554 STM32_FUNCTION(17, "ANALOG")
1555 ),
1556 STM32_PIN(
1557 PINCTRL_PIN(115, "PH3"),
1558 STM32_FUNCTION(0, "GPIOH3"),
1559 STM32_FUNCTION(4, "DFSDM_CK4"),
1560 STM32_FUNCTION(10, "QUADSPI_BK2_IO1 QUADSPI_BOOTBK2_IO1"),
1561 STM32_FUNCTION(11, "SAI2_MCLK_B"),
1562 STM32_FUNCTION(12, "ETH_GMII_COL ETH_MII_COL"),
1563 STM32_FUNCTION(15, "LCD_R1"),
1564 STM32_FUNCTION(16, "EVENTOUT"),
1565 STM32_FUNCTION(17, "ANALOG")
1566 ),
1567 STM32_PIN(
1568 PINCTRL_PIN(116, "PH4"),
1569 STM32_FUNCTION(0, "GPIOH4"),
1570 STM32_FUNCTION(5, "I2C2_SCL"),
1571 STM32_FUNCTION(10, "LCD_G5"),
1572 STM32_FUNCTION(15, "LCD_G4"),
1573 STM32_FUNCTION(16, "EVENTOUT"),
1574 STM32_FUNCTION(17, "ANALOG")
1575 ),
1576 STM32_PIN(
1577 PINCTRL_PIN(117, "PH5"),
1578 STM32_FUNCTION(0, "GPIOH5"),
1579 STM32_FUNCTION(5, "I2C2_SDA"),
1580 STM32_FUNCTION(6, "SPI5_NSS"),
1581 STM32_FUNCTION(13, "SAI4_SD_B"),
1582 STM32_FUNCTION(16, "EVENTOUT"),
1583 STM32_FUNCTION(17, "ANALOG")
1584 ),
1585 STM32_PIN(
1586 PINCTRL_PIN(118, "PH6"),
1587 STM32_FUNCTION(0, "GPIOH6"),
1588 STM32_FUNCTION(3, "TIM12_CH1"),
1589 STM32_FUNCTION(5, "I2C2_SMBA"),
1590 STM32_FUNCTION(6, "SPI5_SCK"),
1591 STM32_FUNCTION(12, "ETH_GMII_RXD2 ETH_MII_RXD2 ETH_RGMII_RXD2"),
1592 STM32_FUNCTION(13, "MDIOS_MDIO"),
1593 STM32_FUNCTION(14, "DCMI_D8"),
1594 STM32_FUNCTION(16, "EVENTOUT"),
1595 STM32_FUNCTION(17, "ANALOG")
1596 ),
1597 STM32_PIN(
1598 PINCTRL_PIN(119, "PH7"),
1599 STM32_FUNCTION(0, "GPIOH7"),
1600 STM32_FUNCTION(5, "I2C3_SCL"),
1601 STM32_FUNCTION(6, "SPI5_MISO"),
1602 STM32_FUNCTION(12, "ETH_GMII_RXD3 ETH_MII_RXD3 ETH_RGMII_RXD3"),
1603 STM32_FUNCTION(13, "MDIOS_MDC"),
1604 STM32_FUNCTION(14, "DCMI_D9"),
1605 STM32_FUNCTION(16, "EVENTOUT"),
1606 STM32_FUNCTION(17, "ANALOG")
1607 ),
1608 STM32_PIN(
1609 PINCTRL_PIN(120, "PH8"),
1610 STM32_FUNCTION(0, "GPIOH8"),
1611 STM32_FUNCTION(3, "TIM5_ETR"),
1612 STM32_FUNCTION(5, "I2C3_SDA"),
1613 STM32_FUNCTION(14, "DCMI_HSYNC"),
1614 STM32_FUNCTION(15, "LCD_R2"),
1615 STM32_FUNCTION(16, "EVENTOUT"),
1616 STM32_FUNCTION(17, "ANALOG")
1617 ),
1618 STM32_PIN(
1619 PINCTRL_PIN(121, "PH9"),
1620 STM32_FUNCTION(0, "GPIOH9"),
1621 STM32_FUNCTION(3, "TIM12_CH2"),
1622 STM32_FUNCTION(5, "I2C3_SMBA"),
1623 STM32_FUNCTION(14, "DCMI_D0"),
1624 STM32_FUNCTION(15, "LCD_R3"),
1625 STM32_FUNCTION(16, "EVENTOUT"),
1626 STM32_FUNCTION(17, "ANALOG")
1627 ),
1628 STM32_PIN(
1629 PINCTRL_PIN(122, "PH10"),
1630 STM32_FUNCTION(0, "GPIOH10"),
1631 STM32_FUNCTION(3, "TIM5_CH1"),
1632 STM32_FUNCTION(5, "I2C4_SMBA"),
1633 STM32_FUNCTION(6, "I2C1_SMBA"),
1634 STM32_FUNCTION(14, "DCMI_D1"),
1635 STM32_FUNCTION(15, "LCD_R4"),
1636 STM32_FUNCTION(16, "EVENTOUT"),
1637 STM32_FUNCTION(17, "ANALOG")
1638 ),
1639 STM32_PIN(
1640 PINCTRL_PIN(123, "PH11"),
1641 STM32_FUNCTION(0, "GPIOH11"),
1642 STM32_FUNCTION(3, "TIM5_CH2"),
1643 STM32_FUNCTION(5, "I2C4_SCL"),
1644 STM32_FUNCTION(6, "I2C1_SCL"),
1645 STM32_FUNCTION(14, "DCMI_D2"),
1646 STM32_FUNCTION(15, "LCD_R5"),
1647 STM32_FUNCTION(16, "EVENTOUT"),
1648 STM32_FUNCTION(17, "ANALOG")
1649 ),
1650 STM32_PIN(
1651 PINCTRL_PIN(124, "PH12"),
1652 STM32_FUNCTION(0, "GPIOH12"),
1653 STM32_FUNCTION(1, "HDP2"),
1654 STM32_FUNCTION(3, "TIM5_CH3"),
1655 STM32_FUNCTION(5, "I2C4_SDA"),
1656 STM32_FUNCTION(6, "I2C1_SDA"),
1657 STM32_FUNCTION(14, "DCMI_D3"),
1658 STM32_FUNCTION(15, "LCD_R6"),
1659 STM32_FUNCTION(16, "EVENTOUT"),
1660 STM32_FUNCTION(17, "ANALOG")
1661 ),
1662 STM32_PIN(
1663 PINCTRL_PIN(125, "PH13"),
1664 STM32_FUNCTION(0, "GPIOH13"),
1665 STM32_FUNCTION(4, "TIM8_CH1N"),
1666 STM32_FUNCTION(9, "UART4_TX"),
1667 STM32_FUNCTION(10, "CAN1_TX"),
1668 STM32_FUNCTION(15, "LCD_G2"),
1669 STM32_FUNCTION(16, "EVENTOUT"),
1670 STM32_FUNCTION(17, "ANALOG")
1671 ),
1672 STM32_PIN(
1673 PINCTRL_PIN(126, "PH14"),
1674 STM32_FUNCTION(0, "GPIOH14"),
1675 STM32_FUNCTION(4, "TIM8_CH2N"),
1676 STM32_FUNCTION(9, "UART4_RX"),
1677 STM32_FUNCTION(10, "CAN1_RX"),
1678 STM32_FUNCTION(14, "DCMI_D4"),
1679 STM32_FUNCTION(15, "LCD_G3"),
1680 STM32_FUNCTION(16, "EVENTOUT"),
1681 STM32_FUNCTION(17, "ANALOG")
1682 ),
1683 STM32_PIN(
1684 PINCTRL_PIN(127, "PH15"),
1685 STM32_FUNCTION(0, "GPIOH15"),
1686 STM32_FUNCTION(4, "TIM8_CH3N"),
1687 STM32_FUNCTION(10, "CAN1_TXFD"),
1688 STM32_FUNCTION(14, "DCMI_D11"),
1689 STM32_FUNCTION(15, "LCD_G4"),
1690 STM32_FUNCTION(16, "EVENTOUT"),
1691 STM32_FUNCTION(17, "ANALOG")
1692 ),
1693 STM32_PIN(
1694 PINCTRL_PIN(128, "PI0"),
1695 STM32_FUNCTION(0, "GPIOI0"),
1696 STM32_FUNCTION(3, "TIM5_CH4"),
1697 STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
1698 STM32_FUNCTION(10, "CAN1_RXFD"),
1699 STM32_FUNCTION(14, "DCMI_D13"),
1700 STM32_FUNCTION(15, "LCD_G5"),
1701 STM32_FUNCTION(16, "EVENTOUT"),
1702 STM32_FUNCTION(17, "ANALOG")
1703 ),
1704 STM32_PIN(
1705 PINCTRL_PIN(129, "PI1"),
1706 STM32_FUNCTION(0, "GPIOI1"),
1707 STM32_FUNCTION(4, "TIM8_BKIN2"),
1708 STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
1709 STM32_FUNCTION(14, "DCMI_D8"),
1710 STM32_FUNCTION(15, "LCD_G6"),
1711 STM32_FUNCTION(16, "EVENTOUT"),
1712 STM32_FUNCTION(17, "ANALOG")
1713 ),
1714 STM32_PIN(
1715 PINCTRL_PIN(130, "PI2"),
1716 STM32_FUNCTION(0, "GPIOI2"),
1717 STM32_FUNCTION(4, "TIM8_CH4"),
1718 STM32_FUNCTION(6, "SPI2_MISO I2S2_SDI"),
1719 STM32_FUNCTION(14, "DCMI_D9"),
1720 STM32_FUNCTION(15, "LCD_G7"),
1721 STM32_FUNCTION(16, "EVENTOUT"),
1722 STM32_FUNCTION(17, "ANALOG")
1723 ),
1724 STM32_PIN(
1725 PINCTRL_PIN(131, "PI3"),
1726 STM32_FUNCTION(0, "GPIOI3"),
1727 STM32_FUNCTION(4, "TIM8_ETR"),
1728 STM32_FUNCTION(6, "SPI2_MOSI I2S2_SDO"),
1729 STM32_FUNCTION(14, "DCMI_D10"),
1730 STM32_FUNCTION(16, "EVENTOUT"),
1731 STM32_FUNCTION(17, "ANALOG")
1732 ),
1733 STM32_PIN(
1734 PINCTRL_PIN(132, "PI4"),
1735 STM32_FUNCTION(0, "GPIOI4"),
1736 STM32_FUNCTION(4, "TIM8_BKIN"),
1737 STM32_FUNCTION(11, "SAI2_MCLK_A"),
1738 STM32_FUNCTION(14, "DCMI_D5"),
1739 STM32_FUNCTION(15, "LCD_B4"),
1740 STM32_FUNCTION(16, "EVENTOUT"),
1741 STM32_FUNCTION(17, "ANALOG")
1742 ),
1743 STM32_PIN(
1744 PINCTRL_PIN(133, "PI5"),
1745 STM32_FUNCTION(0, "GPIOI5"),
1746 STM32_FUNCTION(4, "TIM8_CH1"),
1747 STM32_FUNCTION(11, "SAI2_SCK_A"),
1748 STM32_FUNCTION(14, "DCMI_VSYNC"),
1749 STM32_FUNCTION(15, "LCD_B5"),
1750 STM32_FUNCTION(16, "EVENTOUT"),
1751 STM32_FUNCTION(17, "ANALOG")
1752 ),
1753 STM32_PIN(
1754 PINCTRL_PIN(134, "PI6"),
1755 STM32_FUNCTION(0, "GPIOI6"),
1756 STM32_FUNCTION(4, "TIM8_CH2"),
1757 STM32_FUNCTION(11, "SAI2_SD_A"),
1758 STM32_FUNCTION(14, "DCMI_D6"),
1759 STM32_FUNCTION(15, "LCD_B6"),
1760 STM32_FUNCTION(16, "EVENTOUT"),
1761 STM32_FUNCTION(17, "ANALOG")
1762 ),
1763 STM32_PIN(
1764 PINCTRL_PIN(135, "PI7"),
1765 STM32_FUNCTION(0, "GPIOI7"),
1766 STM32_FUNCTION(4, "TIM8_CH3"),
1767 STM32_FUNCTION(11, "SAI2_FS_A"),
1768 STM32_FUNCTION(14, "DCMI_D7"),
1769 STM32_FUNCTION(15, "LCD_B7"),
1770 STM32_FUNCTION(16, "EVENTOUT"),
1771 STM32_FUNCTION(17, "ANALOG")
1772 ),
1773 STM32_PIN(
1774 PINCTRL_PIN(136, "PI8"),
1775 STM32_FUNCTION(0, "GPIOI8"),
1776 STM32_FUNCTION(16, "EVENTOUT"),
1777 STM32_FUNCTION(17, "ANALOG")
1778 ),
1779 STM32_PIN(
1780 PINCTRL_PIN(137, "PI9"),
1781 STM32_FUNCTION(0, "GPIOI9"),
1782 STM32_FUNCTION(1, "HDP1"),
1783 STM32_FUNCTION(9, "UART4_RX"),
1784 STM32_FUNCTION(10, "CAN1_RX"),
1785 STM32_FUNCTION(15, "LCD_VSYNC"),
1786 STM32_FUNCTION(16, "EVENTOUT"),
1787 STM32_FUNCTION(17, "ANALOG")
1788 ),
1789 STM32_PIN(
1790 PINCTRL_PIN(138, "PI10"),
1791 STM32_FUNCTION(0, "GPIOI10"),
1792 STM32_FUNCTION(1, "HDP0"),
1793 STM32_FUNCTION(9, "USART3_CTS_NSS USART_BOOT3_CTS_NSS"),
1794 STM32_FUNCTION(10, "CAN1_RXFD"),
1795 STM32_FUNCTION(12, "ETH_GMII_RX_ER ETH_MII_RX_ER"),
1796 STM32_FUNCTION(15, "LCD_HSYNC"),
1797 STM32_FUNCTION(16, "EVENTOUT"),
1798 STM32_FUNCTION(17, "ANALOG")
1799 ),
1800 STM32_PIN(
1801 PINCTRL_PIN(139, "PI11"),
1802 STM32_FUNCTION(0, "GPIOI11"),
1803 STM32_FUNCTION(1, "MCO1"),
1804 STM32_FUNCTION(6, "I2S_CKIN"),
1805 STM32_FUNCTION(10, "LCD_G6"),
1806 STM32_FUNCTION(16, "EVENTOUT"),
1807 STM32_FUNCTION(17, "ANALOG")
1808 ),
1809 STM32_PIN(
1810 PINCTRL_PIN(140, "PI12"),
1811 STM32_FUNCTION(0, "GPIOI12"),
1812 STM32_FUNCTION(1, "TRACED0"),
1813 STM32_FUNCTION(3, "HDP0"),
1814 STM32_FUNCTION(15, "LCD_HSYNC"),
1815 STM32_FUNCTION(16, "EVENTOUT"),
1816 STM32_FUNCTION(17, "ANALOG")
1817 ),
1818 STM32_PIN(
1819 PINCTRL_PIN(141, "PI13"),
1820 STM32_FUNCTION(0, "GPIOI13"),
1821 STM32_FUNCTION(1, "TRACED1"),
1822 STM32_FUNCTION(3, "HDP1"),
1823 STM32_FUNCTION(15, "LCD_VSYNC"),
1824 STM32_FUNCTION(16, "EVENTOUT"),
1825 STM32_FUNCTION(17, "ANALOG")
1826 ),
1827 STM32_PIN(
1828 PINCTRL_PIN(142, "PI14"),
1829 STM32_FUNCTION(0, "GPIOI14"),
1830 STM32_FUNCTION(1, "TRACECLK"),
1831 STM32_FUNCTION(15, "LCD_CLK"),
1832 STM32_FUNCTION(16, "EVENTOUT"),
1833 STM32_FUNCTION(17, "ANALOG")
1834 ),
1835 STM32_PIN(
1836 PINCTRL_PIN(143, "PI15"),
1837 STM32_FUNCTION(0, "GPIOI15"),
1838 STM32_FUNCTION(10, "LCD_G2"),
1839 STM32_FUNCTION(15, "LCD_R0"),
1840 STM32_FUNCTION(16, "EVENTOUT"),
1841 STM32_FUNCTION(17, "ANALOG")
1842 ),
1843 STM32_PIN(
1844 PINCTRL_PIN(144, "PJ0"),
1845 STM32_FUNCTION(0, "GPIOJ0"),
1846 STM32_FUNCTION(1, "TRACED8"),
1847 STM32_FUNCTION(10, "LCD_R7"),
1848 STM32_FUNCTION(15, "LCD_R1"),
1849 STM32_FUNCTION(16, "EVENTOUT"),
1850 STM32_FUNCTION(17, "ANALOG")
1851 ),
1852 STM32_PIN(
1853 PINCTRL_PIN(145, "PJ1"),
1854 STM32_FUNCTION(0, "GPIOJ1"),
1855 STM32_FUNCTION(1, "TRACED9"),
1856 STM32_FUNCTION(15, "LCD_R2"),
1857 STM32_FUNCTION(16, "EVENTOUT"),
1858 STM32_FUNCTION(17, "ANALOG")
1859 ),
1860 STM32_PIN(
1861 PINCTRL_PIN(146, "PJ2"),
1862 STM32_FUNCTION(0, "GPIOJ2"),
1863 STM32_FUNCTION(1, "TRACED10"),
1864 STM32_FUNCTION(14, "DSI_TE"),
1865 STM32_FUNCTION(15, "LCD_R3"),
1866 STM32_FUNCTION(16, "EVENTOUT"),
1867 STM32_FUNCTION(17, "ANALOG")
1868 ),
1869 STM32_PIN(
1870 PINCTRL_PIN(147, "PJ3"),
1871 STM32_FUNCTION(0, "GPIOJ3"),
1872 STM32_FUNCTION(1, "TRACED11"),
1873 STM32_FUNCTION(15, "LCD_R4"),
1874 STM32_FUNCTION(16, "EVENTOUT"),
1875 STM32_FUNCTION(17, "ANALOG")
1876 ),
1877 STM32_PIN(
1878 PINCTRL_PIN(148, "PJ4"),
1879 STM32_FUNCTION(0, "GPIOJ4"),
1880 STM32_FUNCTION(1, "TRACED12"),
1881 STM32_FUNCTION(15, "LCD_R5"),
1882 STM32_FUNCTION(16, "EVENTOUT"),
1883 STM32_FUNCTION(17, "ANALOG")
1884 ),
1885 STM32_PIN(
1886 PINCTRL_PIN(149, "PJ5"),
1887 STM32_FUNCTION(0, "GPIOJ5"),
1888 STM32_FUNCTION(1, "TRACED2"),
1889 STM32_FUNCTION(3, "HDP2"),
1890 STM32_FUNCTION(15, "LCD_R6"),
1891 STM32_FUNCTION(16, "EVENTOUT"),
1892 STM32_FUNCTION(17, "ANALOG")
1893 ),
1894 STM32_PIN(
1895 PINCTRL_PIN(150, "PJ6"),
1896 STM32_FUNCTION(0, "GPIOJ6"),
1897 STM32_FUNCTION(1, "TRACED3"),
1898 STM32_FUNCTION(3, "HDP3"),
1899 STM32_FUNCTION(4, "TIM8_CH2"),
1900 STM32_FUNCTION(15, "LCD_R7"),
1901 STM32_FUNCTION(16, "EVENTOUT"),
1902 STM32_FUNCTION(17, "ANALOG")
1903 ),
1904 STM32_PIN(
1905 PINCTRL_PIN(151, "PJ7"),
1906 STM32_FUNCTION(0, "GPIOJ7"),
1907 STM32_FUNCTION(1, "TRACED13"),
1908 STM32_FUNCTION(4, "TIM8_CH2N"),
1909 STM32_FUNCTION(15, "LCD_G0"),
1910 STM32_FUNCTION(16, "EVENTOUT"),
1911 STM32_FUNCTION(17, "ANALOG")
1912 ),
1913 STM32_PIN(
1914 PINCTRL_PIN(152, "PJ8"),
1915 STM32_FUNCTION(0, "GPIOJ8"),
1916 STM32_FUNCTION(1, "TRACED14"),
1917 STM32_FUNCTION(2, "TIM1_CH3N"),
1918 STM32_FUNCTION(4, "TIM8_CH1"),
1919 STM32_FUNCTION(9, "UART8_TX"),
1920 STM32_FUNCTION(15, "LCD_G1"),
1921 STM32_FUNCTION(16, "EVENTOUT"),
1922 STM32_FUNCTION(17, "ANALOG")
1923 ),
1924 STM32_PIN(
1925 PINCTRL_PIN(153, "PJ9"),
1926 STM32_FUNCTION(0, "GPIOJ9"),
1927 STM32_FUNCTION(1, "TRACED15"),
1928 STM32_FUNCTION(2, "TIM1_CH3"),
1929 STM32_FUNCTION(4, "TIM8_CH1N"),
1930 STM32_FUNCTION(9, "UART8_RX"),
1931 STM32_FUNCTION(15, "LCD_G2"),
1932 STM32_FUNCTION(16, "EVENTOUT"),
1933 STM32_FUNCTION(17, "ANALOG")
1934 ),
1935 STM32_PIN(
1936 PINCTRL_PIN(154, "PJ10"),
1937 STM32_FUNCTION(0, "GPIOJ10"),
1938 STM32_FUNCTION(2, "TIM1_CH2N"),
1939 STM32_FUNCTION(4, "TIM8_CH2"),
1940 STM32_FUNCTION(6, "SPI5_MOSI"),
1941 STM32_FUNCTION(15, "LCD_G3"),
1942 STM32_FUNCTION(16, "EVENTOUT"),
1943 STM32_FUNCTION(17, "ANALOG")
1944 ),
1945 STM32_PIN(
1946 PINCTRL_PIN(155, "PJ11"),
1947 STM32_FUNCTION(0, "GPIOJ11"),
1948 STM32_FUNCTION(2, "TIM1_CH2"),
1949 STM32_FUNCTION(4, "TIM8_CH2N"),
1950 STM32_FUNCTION(6, "SPI5_MISO"),
1951 STM32_FUNCTION(15, "LCD_G4"),
1952 STM32_FUNCTION(16, "EVENTOUT"),
1953 STM32_FUNCTION(17, "ANALOG")
1954 ),
1955 STM32_PIN(
1956 PINCTRL_PIN(156, "PJ12"),
1957 STM32_FUNCTION(0, "GPIOJ12"),
1958 STM32_FUNCTION(10, "LCD_G3"),
1959 STM32_FUNCTION(15, "LCD_B0"),
1960 STM32_FUNCTION(16, "EVENTOUT"),
1961 STM32_FUNCTION(17, "ANALOG")
1962 ),
1963 STM32_PIN(
1964 PINCTRL_PIN(157, "PJ13"),
1965 STM32_FUNCTION(0, "GPIOJ13"),
1966 STM32_FUNCTION(10, "LCD_G4"),
1967 STM32_FUNCTION(15, "LCD_B1"),
1968 STM32_FUNCTION(16, "EVENTOUT"),
1969 STM32_FUNCTION(17, "ANALOG")
1970 ),
1971 STM32_PIN(
1972 PINCTRL_PIN(158, "PJ14"),
1973 STM32_FUNCTION(0, "GPIOJ14"),
1974 STM32_FUNCTION(15, "LCD_B2"),
1975 STM32_FUNCTION(16, "EVENTOUT"),
1976 STM32_FUNCTION(17, "ANALOG")
1977 ),
1978 STM32_PIN(
1979 PINCTRL_PIN(159, "PJ15"),
1980 STM32_FUNCTION(0, "GPIOJ15"),
1981 STM32_FUNCTION(15, "LCD_B3"),
1982 STM32_FUNCTION(16, "EVENTOUT"),
1983 STM32_FUNCTION(17, "ANALOG")
1984 ),
1985 STM32_PIN(
1986 PINCTRL_PIN(160, "PK0"),
1987 STM32_FUNCTION(0, "GPIOK0"),
1988 STM32_FUNCTION(2, "TIM1_CH1N"),
1989 STM32_FUNCTION(4, "TIM8_CH3"),
1990 STM32_FUNCTION(6, "SPI5_SCK"),
1991 STM32_FUNCTION(15, "LCD_G5"),
1992 STM32_FUNCTION(16, "EVENTOUT"),
1993 STM32_FUNCTION(17, "ANALOG")
1994 ),
1995 STM32_PIN(
1996 PINCTRL_PIN(161, "PK1"),
1997 STM32_FUNCTION(0, "GPIOK1"),
1998 STM32_FUNCTION(1, "TRACED4"),
1999 STM32_FUNCTION(2, "TIM1_CH1"),
2000 STM32_FUNCTION(3, "HDP4"),
2001 STM32_FUNCTION(4, "TIM8_CH3N"),
2002 STM32_FUNCTION(6, "SPI5_NSS"),
2003 STM32_FUNCTION(15, "LCD_G6"),
2004 STM32_FUNCTION(16, "EVENTOUT"),
2005 STM32_FUNCTION(17, "ANALOG")
2006 ),
2007 STM32_PIN(
2008 PINCTRL_PIN(162, "PK2"),
2009 STM32_FUNCTION(0, "GPIOK2"),
2010 STM32_FUNCTION(1, "TRACED5"),
2011 STM32_FUNCTION(2, "TIM1_BKIN"),
2012 STM32_FUNCTION(3, "HDP5"),
2013 STM32_FUNCTION(4, "TIM8_BKIN"),
2014 STM32_FUNCTION(15, "LCD_G7"),
2015 STM32_FUNCTION(16, "EVENTOUT"),
2016 STM32_FUNCTION(17, "ANALOG")
2017 ),
2018 STM32_PIN(
2019 PINCTRL_PIN(163, "PK3"),
2020 STM32_FUNCTION(0, "GPIOK3"),
2021 STM32_FUNCTION(15, "LCD_B4"),
2022 STM32_FUNCTION(16, "EVENTOUT"),
2023 STM32_FUNCTION(17, "ANALOG")
2024 ),
2025 STM32_PIN(
2026 PINCTRL_PIN(164, "PK4"),
2027 STM32_FUNCTION(0, "GPIOK4"),
2028 STM32_FUNCTION(15, "LCD_B5"),
2029 STM32_FUNCTION(16, "EVENTOUT"),
2030 STM32_FUNCTION(17, "ANALOG")
2031 ),
2032 STM32_PIN(
2033 PINCTRL_PIN(165, "PK5"),
2034 STM32_FUNCTION(0, "GPIOK5"),
2035 STM32_FUNCTION(1, "TRACED6"),
2036 STM32_FUNCTION(3, "HDP6"),
2037 STM32_FUNCTION(15, "LCD_B6"),
2038 STM32_FUNCTION(16, "EVENTOUT"),
2039 STM32_FUNCTION(17, "ANALOG")
2040 ),
2041 STM32_PIN(
2042 PINCTRL_PIN(166, "PK6"),
2043 STM32_FUNCTION(0, "GPIOK6"),
2044 STM32_FUNCTION(1, "TRACED7"),
2045 STM32_FUNCTION(3, "HDP7"),
2046 STM32_FUNCTION(15, "LCD_B7"),
2047 STM32_FUNCTION(16, "EVENTOUT"),
2048 STM32_FUNCTION(17, "ANALOG")
2049 ),
2050 STM32_PIN(
2051 PINCTRL_PIN(167, "PK7"),
2052 STM32_FUNCTION(0, "GPIOK7"),
2053 STM32_FUNCTION(15, "LCD_DE"),
2054 STM32_FUNCTION(16, "EVENTOUT"),
2055 STM32_FUNCTION(17, "ANALOG")
2056 ),
2057};
2058
2059static const struct stm32_desc_pin stm32mp157_z_pins[] = {
2060 STM32_PIN(
2061 PINCTRL_PIN(400, "PZ0"),
2062 STM32_FUNCTION(0, "GPIOZ0"),
2063 STM32_FUNCTION(3, "I2C6_SCL"),
2064 STM32_FUNCTION(4, "I2C2_SCL"),
2065 STM32_FUNCTION(6, "SPI1_SCK I2S1_CK"),
2066 STM32_FUNCTION(8, "USART1_CK"),
2067 STM32_FUNCTION(9, "SPI6_SCK"),
2068 STM32_FUNCTION(16, "EVENTOUT"),
2069 STM32_FUNCTION(17, "ANALOG")
2070 ),
2071 STM32_PIN(
2072 PINCTRL_PIN(401, "PZ1"),
2073 STM32_FUNCTION(0, "GPIOZ1"),
2074 STM32_FUNCTION(3, "I2C6_SDA"),
2075 STM32_FUNCTION(4, "I2C2_SDA"),
2076 STM32_FUNCTION(5, "I2C5_SDA"),
2077 STM32_FUNCTION(6, "SPI1_MISO I2S1_SDI"),
2078 STM32_FUNCTION(7, "I2C4_SDA"),
2079 STM32_FUNCTION(8, "USART1_RX"),
2080 STM32_FUNCTION(9, "SPI6_MISO"),
2081 STM32_FUNCTION(16, "EVENTOUT"),
2082 STM32_FUNCTION(17, "ANALOG")
2083 ),
2084 STM32_PIN(
2085 PINCTRL_PIN(402, "PZ2"),
2086 STM32_FUNCTION(0, "GPIOZ2"),
2087 STM32_FUNCTION(3, "I2C6_SCL"),
2088 STM32_FUNCTION(4, "I2C2_SCL"),
2089 STM32_FUNCTION(5, "I2C5_SMBA"),
2090 STM32_FUNCTION(6, "SPI1_MOSI I2S1_SDO"),
2091 STM32_FUNCTION(7, "I2C4_SMBA"),
2092 STM32_FUNCTION(8, "USART1_TX"),
2093 STM32_FUNCTION(9, "SPI6_MOSI"),
2094 STM32_FUNCTION(16, "EVENTOUT"),
2095 STM32_FUNCTION(17, "ANALOG")
2096 ),
2097 STM32_PIN(
2098 PINCTRL_PIN(403, "PZ3"),
2099 STM32_FUNCTION(0, "GPIOZ3"),
2100 STM32_FUNCTION(3, "I2C6_SDA"),
2101 STM32_FUNCTION(4, "I2C2_SDA"),
2102 STM32_FUNCTION(5, "I2C5_SDA"),
2103 STM32_FUNCTION(6, "SPI1_NSS I2S1_WS"),
2104 STM32_FUNCTION(7, "I2C4_SDA"),
2105 STM32_FUNCTION(8, "USART1_CTS_NSS"),
2106 STM32_FUNCTION(9, "SPI6_NSS"),
2107 STM32_FUNCTION(16, "EVENTOUT"),
2108 STM32_FUNCTION(17, "ANALOG")
2109 ),
2110 STM32_PIN(
2111 PINCTRL_PIN(404, "PZ4"),
2112 STM32_FUNCTION(0, "GPIOZ4"),
2113 STM32_FUNCTION(3, "I2C6_SCL"),
2114 STM32_FUNCTION(4, "I2C2_SCL"),
2115 STM32_FUNCTION(5, "I2C5_SCL"),
2116 STM32_FUNCTION(7, "I2C4_SCL"),
2117 STM32_FUNCTION(16, "EVENTOUT"),
2118 STM32_FUNCTION(17, "ANALOG")
2119 ),
2120 STM32_PIN(
2121 PINCTRL_PIN(405, "PZ5"),
2122 STM32_FUNCTION(0, "GPIOZ5"),
2123 STM32_FUNCTION(3, "I2C6_SDA"),
2124 STM32_FUNCTION(4, "I2C2_SDA"),
2125 STM32_FUNCTION(5, "I2C5_SDA"),
2126 STM32_FUNCTION(7, "I2C4_SDA"),
2127 STM32_FUNCTION(8, "USART1_RTS"),
2128 STM32_FUNCTION(16, "EVENTOUT"),
2129 STM32_FUNCTION(17, "ANALOG")
2130 ),
2131 STM32_PIN(
2132 PINCTRL_PIN(406, "PZ6"),
2133 STM32_FUNCTION(0, "GPIOZ6"),
2134 STM32_FUNCTION(3, "I2C6_SCL"),
2135 STM32_FUNCTION(4, "I2C2_SCL"),
2136 STM32_FUNCTION(5, "USART1_CK"),
2137 STM32_FUNCTION(6, "I2S1_MCK"),
2138 STM32_FUNCTION(7, "I2C4_SMBA"),
2139 STM32_FUNCTION(8, "USART1_RX"),
2140 STM32_FUNCTION(16, "EVENTOUT"),
2141 STM32_FUNCTION(17, "ANALOG")
2142 ),
2143 STM32_PIN(
2144 PINCTRL_PIN(407, "PZ7"),
2145 STM32_FUNCTION(0, "GPIOZ7"),
2146 STM32_FUNCTION(3, "I2C6_SDA"),
2147 STM32_FUNCTION(4, "I2C2_SDA"),
2148 STM32_FUNCTION(8, "USART1_TX"),
2149 STM32_FUNCTION(16, "EVENTOUT"),
2150 STM32_FUNCTION(17, "ANALOG")
2151 ),
2152};
2153
2154static struct stm32_pinctrl_match_data stm32mp157_match_data = {
2155 .pins = stm32mp157_pins,
2156 .npins = ARRAY_SIZE(stm32mp157_pins),
2157};
2158
2159static struct stm32_pinctrl_match_data stm32mp157_z_match_data = {
2160 .pins = stm32mp157_z_pins,
2161 .npins = ARRAY_SIZE(stm32mp157_z_pins),
2162};
2163
2164static const struct of_device_id stm32mp157_pctrl_match[] = {
2165 {
2166 .compatible = "st,stm32mp157-pinctrl",
2167 .data = &stm32mp157_match_data,
2168 },
2169 {
2170 .compatible = "st,stm32mp157-z-pinctrl",
2171 .data = &stm32mp157_z_match_data,
2172 },
2173 { }
2174};
2175
2176static struct platform_driver stm32mp157_pinctrl_driver = {
2177 .probe = stm32_pctl_probe,
2178 .driver = {
2179 .name = "stm32mp157-pinctrl",
2180 .of_match_table = stm32mp157_pctrl_match,
2181 },
2182};
2183
2184static int __init stm32mp157_pinctrl_init(void)
2185{
2186 return platform_driver_register(&stm32mp157_pinctrl_driver);
2187}
2188arch_initcall(stm32mp157_pinctrl_init);
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
index 295e48fc94bc..0c7c361ebac5 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
@@ -1167,7 +1167,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
1167 SUNXI_FUNCTION(0x0, "gpio_in"), 1167 SUNXI_FUNCTION(0x0, "gpio_in"),
1168 SUNXI_FUNCTION(0x1, "gpio_out"), 1168 SUNXI_FUNCTION(0x1, "gpio_out"),
1169 SUNXI_FUNCTION(0x2, "pwm"), /* PWM1 */ 1169 SUNXI_FUNCTION(0x2, "pwm"), /* PWM1 */
1170 SUNXI_FUNCTION_VARIANT(0x3, "i2c3", /* SDA */ 1170 SUNXI_FUNCTION_VARIANT(0x3, "i2c4", /* SDA */
1171 PINCTRL_SUN7I_A20 | 1171 PINCTRL_SUN7I_A20 |
1172 PINCTRL_SUN8I_R40)), 1172 PINCTRL_SUN8I_R40)),
1173 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 4), 1173 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 4),
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 4b6cb25bc796..341312d66512 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -12,6 +12,7 @@
12 12
13#include <linux/io.h> 13#include <linux/io.h>
14#include <linux/clk.h> 14#include <linux/clk.h>
15#include <linux/clk-provider.h>
15#include <linux/gpio/driver.h> 16#include <linux/gpio/driver.h>
16#include <linux/irqdomain.h> 17#include <linux/irqdomain.h>
17#include <linux/irqchip/chained_irq.h> 18#include <linux/irqchip/chained_irq.h>
@@ -83,7 +84,9 @@ sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
83 struct sunxi_desc_function *func = pin->functions; 84 struct sunxi_desc_function *func = pin->functions;
84 85
85 while (func->name) { 86 while (func->name) {
86 if (!strcmp(func->name, func_name)) 87 if (!strcmp(func->name, func_name) &&
88 (!func->variant ||
89 func->variant & pctl->variant))
87 return func; 90 return func;
88 91
89 func++; 92 func++;
@@ -1185,7 +1188,7 @@ static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl,
1185 int i, ret; 1188 int i, ret;
1186 1189
1187 /* Deal with old DTs that didn't have the oscillators */ 1190 /* Deal with old DTs that didn't have the oscillators */
1188 if (of_count_phandle_with_args(node, "clocks", "#clock-cells") != 3) 1191 if (of_clk_get_parent_count(node) != 3)
1189 return 0; 1192 return 0;
1190 1193
1191 /* If we don't have any setup, bail out */ 1194 /* If we don't have any setup, bail out */
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
index 51716819129d..72c718e66ebb 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
@@ -666,10 +666,9 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
666 int fn, gn, gfn; 666 int fn, gn, gfn;
667 667
668 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); 668 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
669 if (!pmx) { 669 if (!pmx)
670 dev_err(&pdev->dev, "Can't alloc tegra_pmx\n");
671 return -ENOMEM; 670 return -ENOMEM;
672 } 671
673 pmx->dev = &pdev->dev; 672 pmx->dev = &pdev->dev;
674 pmx->soc = soc_data; 673 pmx->soc = soc_data;
675 674
@@ -722,10 +721,8 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
722 721
723 pmx->regs = devm_kzalloc(&pdev->dev, pmx->nbanks * sizeof(*pmx->regs), 722 pmx->regs = devm_kzalloc(&pdev->dev, pmx->nbanks * sizeof(*pmx->regs),
724 GFP_KERNEL); 723 GFP_KERNEL);
725 if (!pmx->regs) { 724 if (!pmx->regs)
726 dev_err(&pdev->dev, "Can't alloc regs pointer\n");
727 return -ENOMEM; 725 return -ENOMEM;
728 }
729 726
730 for (i = 0; i < pmx->nbanks; i++) { 727 for (i = 0; i < pmx->nbanks; i++) {
731 res = platform_get_resource(pdev, IORESOURCE_MEM, i); 728 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
index 26fda5c53e65..ec0f77afeaa4 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
@@ -146,6 +146,71 @@ static const struct pinctrl_ops uniphier_pctlops = {
146 .dt_free_map = pinctrl_utils_free_map, 146 .dt_free_map = pinctrl_utils_free_map,
147}; 147};
148 148
149static const unsigned int uniphier_conf_drv_strengths_1bit[] = {4, 8};
150static const unsigned int uniphier_conf_drv_strengths_2bit[] = {8, 12, 16, 20};
151static const unsigned int uniphier_conf_drv_strengths_3bit[] = {4, 5, 7, 9, 11,
152 12, 14, 16};
153static const unsigned int uniphier_conf_drv_strengths_fixed4[] = {4};
154static const unsigned int uniphier_conf_drv_strengths_fixed5[] = {5};
155static const unsigned int uniphier_conf_drv_strengths_fixed8[] = {8};
156
157static int uniphier_conf_get_drvctrl_data(struct pinctrl_dev *pctldev,
158 unsigned int pin, unsigned int *reg,
159 unsigned int *shift,
160 unsigned int *mask,
161 const unsigned int **strengths)
162{
163 const struct pin_desc *desc = pin_desc_get(pctldev, pin);
164 enum uniphier_pin_drv_type type =
165 uniphier_pin_get_drv_type(desc->drv_data);
166 unsigned int base = 0;
167 unsigned int stride = 0;
168 unsigned int width = 0;
169 unsigned int drvctrl;
170
171 switch (type) {
172 case UNIPHIER_PIN_DRV_1BIT:
173 *strengths = uniphier_conf_drv_strengths_1bit;
174 base = UNIPHIER_PINCTRL_DRVCTRL_BASE;
175 stride = 1;
176 width = 1;
177 break;
178 case UNIPHIER_PIN_DRV_2BIT:
179 *strengths = uniphier_conf_drv_strengths_2bit;
180 base = UNIPHIER_PINCTRL_DRV2CTRL_BASE;
181 stride = 2;
182 width = 2;
183 break;
184 case UNIPHIER_PIN_DRV_3BIT:
185 *strengths = uniphier_conf_drv_strengths_3bit;
186 base = UNIPHIER_PINCTRL_DRV3CTRL_BASE;
187 stride = 4;
188 width = 3;
189 break;
190 case UNIPHIER_PIN_DRV_FIXED4:
191 *strengths = uniphier_conf_drv_strengths_fixed4;
192 break;
193 case UNIPHIER_PIN_DRV_FIXED5:
194 *strengths = uniphier_conf_drv_strengths_fixed5;
195 break;
196 case UNIPHIER_PIN_DRV_FIXED8:
197 *strengths = uniphier_conf_drv_strengths_fixed8;
198 break;
199 default:
200 /* drive strength control is not supported for this pin */
201 return -EINVAL;
202 }
203
204 drvctrl = uniphier_pin_get_drvctrl(desc->drv_data);
205 drvctrl *= stride;
206
207 *reg = base + drvctrl / 32 * 4;
208 *shift = drvctrl % 32;
209 *mask = (1U << width) - 1;
210
211 return 0;
212}
213
149static int uniphier_conf_pin_bias_get(struct pinctrl_dev *pctldev, 214static int uniphier_conf_pin_bias_get(struct pinctrl_dev *pctldev,
150 unsigned int pin, 215 unsigned int pin,
151 enum pin_config_param param) 216 enum pin_config_param param)
@@ -201,59 +266,24 @@ static int uniphier_conf_pin_drive_get(struct pinctrl_dev *pctldev,
201 unsigned int pin, u32 *strength) 266 unsigned int pin, u32 *strength)
202{ 267{
203 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 268 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
204 const struct pin_desc *desc = pin_desc_get(pctldev, pin); 269 unsigned int reg, shift, mask, val;
205 enum uniphier_pin_drv_type type = 270 const unsigned int *strengths;
206 uniphier_pin_get_drv_type(desc->drv_data);
207 static const unsigned int strength_1bit[] = {4, 8};
208 static const unsigned int strength_2bit[] = {8, 12, 16, 20};
209 static const unsigned int strength_3bit[] = {4, 5, 7, 9, 11, 12,
210 14, 16};
211 const unsigned int *supported_strength;
212 unsigned int drvctrl, reg, shift, mask, width, val;
213 int ret; 271 int ret;
214 272
215 switch (type) { 273 ret = uniphier_conf_get_drvctrl_data(pctldev, pin, &reg, &shift,
216 case UNIPHIER_PIN_DRV_1BIT: 274 &mask, &strengths);
217 supported_strength = strength_1bit;
218 reg = UNIPHIER_PINCTRL_DRVCTRL_BASE;
219 width = 1;
220 break;
221 case UNIPHIER_PIN_DRV_2BIT:
222 supported_strength = strength_2bit;
223 reg = UNIPHIER_PINCTRL_DRV2CTRL_BASE;
224 width = 2;
225 break;
226 case UNIPHIER_PIN_DRV_3BIT:
227 supported_strength = strength_3bit;
228 reg = UNIPHIER_PINCTRL_DRV3CTRL_BASE;
229 width = 4;
230 break;
231 case UNIPHIER_PIN_DRV_FIXED4:
232 *strength = 4;
233 return 0;
234 case UNIPHIER_PIN_DRV_FIXED5:
235 *strength = 5;
236 return 0;
237 case UNIPHIER_PIN_DRV_FIXED8:
238 *strength = 8;
239 return 0;
240 default:
241 /* drive strength control is not supported for this pin */
242 return -EINVAL;
243 }
244
245 drvctrl = uniphier_pin_get_drvctrl(desc->drv_data);
246 drvctrl *= width;
247
248 reg += drvctrl / 32 * 4;
249 shift = drvctrl % 32;
250 mask = (1U << width) - 1;
251
252 ret = regmap_read(priv->regmap, reg, &val);
253 if (ret) 275 if (ret)
254 return ret; 276 return ret;
255 277
256 *strength = supported_strength[(val >> shift) & mask]; 278 if (mask) {
279 ret = regmap_read(priv->regmap, reg, &val);
280 if (ret)
281 return ret;
282 } else {
283 val = 0;
284 }
285
286 *strength = strengths[(val >> shift) & mask];
257 287
258 return 0; 288 return 0;
259} 289}
@@ -398,40 +428,20 @@ static int uniphier_conf_pin_drive_set(struct pinctrl_dev *pctldev,
398{ 428{
399 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 429 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
400 const struct pin_desc *desc = pin_desc_get(pctldev, pin); 430 const struct pin_desc *desc = pin_desc_get(pctldev, pin);
401 enum uniphier_pin_drv_type type = 431 unsigned int reg, shift, mask, val;
402 uniphier_pin_get_drv_type(desc->drv_data); 432 const unsigned int *strengths;
403 static const unsigned int strength_1bit[] = {4, 8, -1}; 433 int ret;
404 static const unsigned int strength_2bit[] = {8, 12, 16, 20, -1};
405 static const unsigned int strength_3bit[] = {4, 5, 7, 9, 11, 12, 14,
406 16, -1};
407 const unsigned int *supported_strength;
408 unsigned int drvctrl, reg, shift, mask, width, val;
409 434
410 switch (type) { 435 ret = uniphier_conf_get_drvctrl_data(pctldev, pin, &reg, &shift,
411 case UNIPHIER_PIN_DRV_1BIT: 436 &mask, &strengths);
412 supported_strength = strength_1bit; 437 if (ret) {
413 reg = UNIPHIER_PINCTRL_DRVCTRL_BASE; 438 dev_err(pctldev->dev, "cannot set drive strength for pin %s\n",
414 width = 1;
415 break;
416 case UNIPHIER_PIN_DRV_2BIT:
417 supported_strength = strength_2bit;
418 reg = UNIPHIER_PINCTRL_DRV2CTRL_BASE;
419 width = 2;
420 break;
421 case UNIPHIER_PIN_DRV_3BIT:
422 supported_strength = strength_3bit;
423 reg = UNIPHIER_PINCTRL_DRV3CTRL_BASE;
424 width = 4;
425 break;
426 default:
427 dev_err(pctldev->dev,
428 "cannot change drive strength for pin %s\n",
429 desc->name); 439 desc->name);
430 return -EINVAL; 440 return ret;
431 } 441 }
432 442
433 for (val = 0; supported_strength[val] > 0; val++) { 443 for (val = 0; val <= mask; val++) {
434 if (supported_strength[val] > strength) 444 if (strengths[val] > strength)
435 break; 445 break;
436 } 446 }
437 447
@@ -442,14 +452,10 @@ static int uniphier_conf_pin_drive_set(struct pinctrl_dev *pctldev,
442 return -EINVAL; 452 return -EINVAL;
443 } 453 }
444 454
445 val--; 455 if (!mask)
446 456 return 0;
447 drvctrl = uniphier_pin_get_drvctrl(desc->drv_data);
448 drvctrl *= width;
449 457
450 reg += drvctrl / 32 * 4; 458 val--;
451 shift = drvctrl % 32;
452 mask = (1U << width) - 1;
453 459
454 return regmap_update_bits(priv->regmap, reg, 460 return regmap_update_bits(priv->regmap, reg,
455 mask << shift, val << shift); 461 mask << shift, val << shift);
diff --git a/drivers/pinctrl/vt8500/pinctrl-vt8500.c b/drivers/pinctrl/vt8500/pinctrl-vt8500.c
index 767f340d6b11..9086a3758eee 100644
--- a/drivers/pinctrl/vt8500/pinctrl-vt8500.c
+++ b/drivers/pinctrl/vt8500/pinctrl-vt8500.c
@@ -458,10 +458,8 @@ static int vt8500_pinctrl_probe(struct platform_device *pdev)
458 struct wmt_pinctrl_data *data; 458 struct wmt_pinctrl_data *data;
459 459
460 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 460 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
461 if (!data) { 461 if (!data)
462 dev_err(&pdev->dev, "failed to allocate data\n");
463 return -ENOMEM; 462 return -ENOMEM;
464 }
465 463
466 data->banks = vt8500_banks; 464 data->banks = vt8500_banks;
467 data->nbanks = ARRAY_SIZE(vt8500_banks); 465 data->nbanks = ARRAY_SIZE(vt8500_banks);
diff --git a/drivers/pinctrl/vt8500/pinctrl-wm8505.c b/drivers/pinctrl/vt8500/pinctrl-wm8505.c
index a56fdbd87e42..e1aae1d4b0b1 100644
--- a/drivers/pinctrl/vt8500/pinctrl-wm8505.c
+++ b/drivers/pinctrl/vt8500/pinctrl-wm8505.c
@@ -489,10 +489,8 @@ static int wm8505_pinctrl_probe(struct platform_device *pdev)
489 struct wmt_pinctrl_data *data; 489 struct wmt_pinctrl_data *data;
490 490
491 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 491 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
492 if (!data) { 492 if (!data)
493 dev_err(&pdev->dev, "failed to allocate data\n");
494 return -ENOMEM; 493 return -ENOMEM;
495 }
496 494
497 data->banks = wm8505_banks; 495 data->banks = wm8505_banks;
498 data->nbanks = ARRAY_SIZE(wm8505_banks); 496 data->nbanks = ARRAY_SIZE(wm8505_banks);
diff --git a/drivers/pinctrl/vt8500/pinctrl-wm8650.c b/drivers/pinctrl/vt8500/pinctrl-wm8650.c
index 270dd491f5a1..4678227d4001 100644
--- a/drivers/pinctrl/vt8500/pinctrl-wm8650.c
+++ b/drivers/pinctrl/vt8500/pinctrl-wm8650.c
@@ -327,10 +327,8 @@ static int wm8650_pinctrl_probe(struct platform_device *pdev)
327 struct wmt_pinctrl_data *data; 327 struct wmt_pinctrl_data *data;
328 328
329 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 329 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
330 if (!data) { 330 if (!data)
331 dev_err(&pdev->dev, "failed to allocate data\n");
332 return -ENOMEM; 331 return -ENOMEM;
333 }
334 332
335 data->banks = wm8650_banks; 333 data->banks = wm8650_banks;
336 data->nbanks = ARRAY_SIZE(wm8650_banks); 334 data->nbanks = ARRAY_SIZE(wm8650_banks);
diff --git a/drivers/pinctrl/vt8500/pinctrl-wm8750.c b/drivers/pinctrl/vt8500/pinctrl-wm8750.c
index 74f7b3a18f3a..c46d6946c8f5 100644
--- a/drivers/pinctrl/vt8500/pinctrl-wm8750.c
+++ b/drivers/pinctrl/vt8500/pinctrl-wm8750.c
@@ -366,10 +366,8 @@ static int wm8750_pinctrl_probe(struct platform_device *pdev)
366 struct wmt_pinctrl_data *data; 366 struct wmt_pinctrl_data *data;
367 367
368 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 368 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
369 if (!data) { 369 if (!data)
370 dev_err(&pdev->dev, "failed to allocate data\n");
371 return -ENOMEM; 370 return -ENOMEM;
372 }
373 371
374 data->banks = wm8750_banks; 372 data->banks = wm8750_banks;
375 data->nbanks = ARRAY_SIZE(wm8750_banks); 373 data->nbanks = ARRAY_SIZE(wm8750_banks);
diff --git a/drivers/pinctrl/vt8500/pinctrl-wm8850.c b/drivers/pinctrl/vt8500/pinctrl-wm8850.c
index 45792aa7a06e..e2e85316a65e 100644
--- a/drivers/pinctrl/vt8500/pinctrl-wm8850.c
+++ b/drivers/pinctrl/vt8500/pinctrl-wm8850.c
@@ -345,10 +345,8 @@ static int wm8850_pinctrl_probe(struct platform_device *pdev)
345 struct wmt_pinctrl_data *data; 345 struct wmt_pinctrl_data *data;
346 346
347 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 347 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
348 if (!data) { 348 if (!data)
349 dev_err(&pdev->dev, "failed to allocate data\n");
350 return -ENOMEM; 349 return -ENOMEM;
351 }
352 350
353 data->banks = wm8850_banks; 351 data->banks = wm8850_banks;
354 data->nbanks = ARRAY_SIZE(wm8850_banks); 352 data->nbanks = ARRAY_SIZE(wm8850_banks);
diff --git a/include/dt-bindings/gpio/meson-axg-gpio.h b/include/dt-bindings/gpio/meson-axg-gpio.h
new file mode 100644
index 000000000000..25bb1fffa97a
--- /dev/null
+++ b/include/dt-bindings/gpio/meson-axg-gpio.h
@@ -0,0 +1,116 @@
1/*
2 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
3 * Author: Xingyu Chen <xingyu.chen@amlogic.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#ifndef _DT_BINDINGS_MESON_AXG_GPIO_H
9#define _DT_BINDINGS_MESON_AXG_GPIO_H
10
11/* First GPIO chip */
12#define GPIOAO_0 0
13#define GPIOAO_1 1
14#define GPIOAO_2 2
15#define GPIOAO_3 3
16#define GPIOAO_4 4
17#define GPIOAO_5 5
18#define GPIOAO_6 6
19#define GPIOAO_7 7
20#define GPIOAO_8 8
21#define GPIOAO_9 9
22#define GPIOAO_10 10
23#define GPIOAO_11 11
24#define GPIOAO_12 12
25#define GPIOAO_13 13
26#define GPIO_TEST_N 14
27
28/* Second GPIO chip */
29#define GPIOZ_0 0
30#define GPIOZ_1 1
31#define GPIOZ_2 2
32#define GPIOZ_3 3
33#define GPIOZ_4 4
34#define GPIOZ_5 5
35#define GPIOZ_6 6
36#define GPIOZ_7 7
37#define GPIOZ_8 8
38#define GPIOZ_9 9
39#define GPIOZ_10 10
40#define BOOT_0 11
41#define BOOT_1 12
42#define BOOT_2 13
43#define BOOT_3 14
44#define BOOT_4 15
45#define BOOT_5 16
46#define BOOT_6 17
47#define BOOT_7 18
48#define BOOT_8 19
49#define BOOT_9 20
50#define BOOT_10 21
51#define BOOT_11 22
52#define BOOT_12 23
53#define BOOT_13 24
54#define BOOT_14 25
55#define GPIOA_0 26
56#define GPIOA_1 27
57#define GPIOA_2 28
58#define GPIOA_3 29
59#define GPIOA_4 30
60#define GPIOA_5 31
61#define GPIOA_6 32
62#define GPIOA_7 33
63#define GPIOA_8 34
64#define GPIOA_9 35
65#define GPIOA_10 36
66#define GPIOA_11 37
67#define GPIOA_12 38
68#define GPIOA_13 39
69#define GPIOA_14 40
70#define GPIOA_15 41
71#define GPIOA_16 42
72#define GPIOA_17 43
73#define GPIOA_18 44
74#define GPIOA_19 45
75#define GPIOA_20 46
76#define GPIOX_0 47
77#define GPIOX_1 48
78#define GPIOX_2 49
79#define GPIOX_3 50
80#define GPIOX_4 51
81#define GPIOX_5 52
82#define GPIOX_6 53
83#define GPIOX_7 54
84#define GPIOX_8 55
85#define GPIOX_9 56
86#define GPIOX_10 57
87#define GPIOX_11 58
88#define GPIOX_12 59
89#define GPIOX_13 60
90#define GPIOX_14 61
91#define GPIOX_15 62
92#define GPIOX_16 63
93#define GPIOX_17 64
94#define GPIOX_18 65
95#define GPIOX_19 66
96#define GPIOX_20 67
97#define GPIOX_21 68
98#define GPIOX_22 69
99#define GPIOY_0 70
100#define GPIOY_1 71
101#define GPIOY_2 72
102#define GPIOY_3 73
103#define GPIOY_4 74
104#define GPIOY_5 75
105#define GPIOY_6 76
106#define GPIOY_7 77
107#define GPIOY_8 78
108#define GPIOY_9 79
109#define GPIOY_10 80
110#define GPIOY_11 81
111#define GPIOY_12 82
112#define GPIOY_13 83
113#define GPIOY_14 84
114#define GPIOY_15 85
115
116#endif /* _DT_BINDINGS_MESON_AXG_GPIO_H */
diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h
index b8dfe31821e6..b5a2174a6386 100644
--- a/include/dt-bindings/pinctrl/stm32-pinfunc.h
+++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h
@@ -1,3 +1,9 @@
1/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Torgue Alexandre <alexandre.torgue@st.com> for STMicroelectronics.
5 */
6
1#ifndef _DT_BINDINGS_STM32_PINFUNC_H 7#ifndef _DT_BINDINGS_STM32_PINFUNC_H
2#define _DT_BINDINGS_STM32_PINFUNC_H 8#define _DT_BINDINGS_STM32_PINFUNC_H
3 9
diff --git a/include/linux/pinctrl/devinfo.h b/include/linux/pinctrl/devinfo.h
index 05082e407c4a..d01a8638bb45 100644
--- a/include/linux/pinctrl/devinfo.h
+++ b/include/linux/pinctrl/devinfo.h
@@ -43,6 +43,8 @@ extern int pinctrl_init_done(struct device *dev);
43 43
44#else 44#else
45 45
46struct device;
47
46/* Stubs if we're not using pinctrl */ 48/* Stubs if we're not using pinctrl */
47 49
48static inline int pinctrl_bind_pins(struct device *dev) 50static inline int pinctrl_bind_pins(struct device *dev)
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-27 10:31:17 -0400