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authorPaul Mundt <lethal@linux-sh.org>2011-01-13 01:21:27 -0500
committerPaul Mundt <lethal@linux-sh.org>2011-01-13 01:21:27 -0500
commitef7fc9026fe6adef13870c6b2cb4642b6193af67 (patch)
tree6f41f996de6e76161fdfc60a197ec42f0aa0ec7d
parentfac6c2a891a3e7255e4440f09a4c7da954043ba9 (diff)
parentf43dc23d5ea91fca257be02138a255f02d98e806 (diff)
Merge branch 'common/serial-rework' into sh-latest
Diffstat
-rw-r--r--arch/arm/mach-shmobile/setup-sh7367.c14
-rw-r--r--arch/arm/mach-shmobile/setup-sh7372.c14
-rw-r--r--arch/arm/mach-shmobile/setup-sh7377.c16
-rw-r--r--arch/arm/mach-shmobile/setup-sh73a0.c18
-rw-r--r--arch/sh/kernel/cpu/sh2/setup-sh7619.c6
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-mxg.c2
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7201.c16
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7203.c8
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7206.c8
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7705.c5
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh770x.c6
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7710.c6
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7720.c6
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh4-202.c2
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7750.c36
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7760.c8
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7343.c8
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7366.c2
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7722.c6
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7723.c12
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7724.c12
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7757.c6
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7763.c6
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7770.c20
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7780.c12
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7785.c12
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7786.c12
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-shx3.c6
-rw-r--r--arch/sh/kernel/cpu/sh5/setup-sh5.c2
-rw-r--r--drivers/serial/sh-sci.c100
-rw-r--r--drivers/serial/sh-sci.h153
-rw-r--r--include/linux/serial_sci.h22
32 files changed, 374 insertions, 188 deletions
diff --git a/arch/arm/mach-shmobile/setup-sh7367.c b/arch/arm/mach-shmobile/setup-sh7367.c
index 003008c18360..ce28141662da 100644
--- a/arch/arm/mach-shmobile/setup-sh7367.c
+++ b/arch/arm/mach-shmobile/setup-sh7367.c
@@ -35,6 +35,8 @@
35static struct plat_sci_port scif0_platform_data = { 35static struct plat_sci_port scif0_platform_data = {
36 .mapbase = 0xe6c40000, 36 .mapbase = 0xe6c40000,
37 .flags = UPF_BOOT_AUTOCONF, 37 .flags = UPF_BOOT_AUTOCONF,
38 .scscr = SCSCR_RE | SCSCR_TE,
39 .scbrr_algo_id = SCBRR_ALGO_4,
38 .type = PORT_SCIF, 40 .type = PORT_SCIF,
39 .irqs = { evt2irq(0xc00), evt2irq(0xc00), 41 .irqs = { evt2irq(0xc00), evt2irq(0xc00),
40 evt2irq(0xc00), evt2irq(0xc00) }, 42 evt2irq(0xc00), evt2irq(0xc00) },
@@ -52,6 +54,8 @@ static struct platform_device scif0_device = {
52static struct plat_sci_port scif1_platform_data = { 54static struct plat_sci_port scif1_platform_data = {
53 .mapbase = 0xe6c50000, 55 .mapbase = 0xe6c50000,
54 .flags = UPF_BOOT_AUTOCONF, 56 .flags = UPF_BOOT_AUTOCONF,
57 .scscr = SCSCR_RE | SCSCR_TE,
58 .scbrr_algo_id = SCBRR_ALGO_4,
55 .type = PORT_SCIF, 59 .type = PORT_SCIF,
56 .irqs = { evt2irq(0xc20), evt2irq(0xc20), 60 .irqs = { evt2irq(0xc20), evt2irq(0xc20),
57 evt2irq(0xc20), evt2irq(0xc20) }, 61 evt2irq(0xc20), evt2irq(0xc20) },
@@ -69,6 +73,8 @@ static struct platform_device scif1_device = {
69static struct plat_sci_port scif2_platform_data = { 73static struct plat_sci_port scif2_platform_data = {
70 .mapbase = 0xe6c60000, 74 .mapbase = 0xe6c60000,
71 .flags = UPF_BOOT_AUTOCONF, 75 .flags = UPF_BOOT_AUTOCONF,
76 .scscr = SCSCR_RE | SCSCR_TE,
77 .scbrr_algo_id = SCBRR_ALGO_4,
72 .type = PORT_SCIF, 78 .type = PORT_SCIF,
73 .irqs = { evt2irq(0xc40), evt2irq(0xc40), 79 .irqs = { evt2irq(0xc40), evt2irq(0xc40),
74 evt2irq(0xc40), evt2irq(0xc40) }, 80 evt2irq(0xc40), evt2irq(0xc40) },
@@ -86,6 +92,8 @@ static struct platform_device scif2_device = {
86static struct plat_sci_port scif3_platform_data = { 92static struct plat_sci_port scif3_platform_data = {
87 .mapbase = 0xe6c70000, 93 .mapbase = 0xe6c70000,
88 .flags = UPF_BOOT_AUTOCONF, 94 .flags = UPF_BOOT_AUTOCONF,
95 .scscr = SCSCR_RE | SCSCR_TE,
96 .scbrr_algo_id = SCBRR_ALGO_4,
89 .type = PORT_SCIF, 97 .type = PORT_SCIF,
90 .irqs = { evt2irq(0xc60), evt2irq(0xc60), 98 .irqs = { evt2irq(0xc60), evt2irq(0xc60),
91 evt2irq(0xc60), evt2irq(0xc60) }, 99 evt2irq(0xc60), evt2irq(0xc60) },
@@ -103,6 +111,8 @@ static struct platform_device scif3_device = {
103static struct plat_sci_port scif4_platform_data = { 111static struct plat_sci_port scif4_platform_data = {
104 .mapbase = 0xe6c80000, 112 .mapbase = 0xe6c80000,
105 .flags = UPF_BOOT_AUTOCONF, 113 .flags = UPF_BOOT_AUTOCONF,
114 .scscr = SCSCR_RE | SCSCR_TE,
115 .scbrr_algo_id = SCBRR_ALGO_4,
106 .type = PORT_SCIF, 116 .type = PORT_SCIF,
107 .irqs = { evt2irq(0xd20), evt2irq(0xd20), 117 .irqs = { evt2irq(0xd20), evt2irq(0xd20),
108 evt2irq(0xd20), evt2irq(0xd20) }, 118 evt2irq(0xd20), evt2irq(0xd20) },
@@ -120,6 +130,8 @@ static struct platform_device scif4_device = {
120static struct plat_sci_port scif5_platform_data = { 130static struct plat_sci_port scif5_platform_data = {
121 .mapbase = 0xe6cb0000, 131 .mapbase = 0xe6cb0000,
122 .flags = UPF_BOOT_AUTOCONF, 132 .flags = UPF_BOOT_AUTOCONF,
133 .scscr = SCSCR_RE | SCSCR_TE,
134 .scbrr_algo_id = SCBRR_ALGO_4,
123 .type = PORT_SCIF, 135 .type = PORT_SCIF,
124 .irqs = { evt2irq(0xd40), evt2irq(0xd40), 136 .irqs = { evt2irq(0xd40), evt2irq(0xd40),
125 evt2irq(0xd40), evt2irq(0xd40) }, 137 evt2irq(0xd40), evt2irq(0xd40) },
@@ -137,6 +149,8 @@ static struct platform_device scif5_device = {
137static struct plat_sci_port scif6_platform_data = { 149static struct plat_sci_port scif6_platform_data = {
138 .mapbase = 0xe6c30000, 150 .mapbase = 0xe6c30000,
139 .flags = UPF_BOOT_AUTOCONF, 151 .flags = UPF_BOOT_AUTOCONF,
152 .scscr = SCSCR_RE | SCSCR_TE,
153 .scbrr_algo_id = SCBRR_ALGO_4,
140 .type = PORT_SCIF, 154 .type = PORT_SCIF,
141 .irqs = { evt2irq(0xd60), evt2irq(0xd60), 155 .irqs = { evt2irq(0xd60), evt2irq(0xd60),
142 evt2irq(0xd60), evt2irq(0xd60) }, 156 evt2irq(0xd60), evt2irq(0xd60) },
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 2e3e11ee7c43..ff0494f3d00c 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -38,6 +38,8 @@
38static struct plat_sci_port scif0_platform_data = { 38static struct plat_sci_port scif0_platform_data = {
39 .mapbase = 0xe6c40000, 39 .mapbase = 0xe6c40000,
40 .flags = UPF_BOOT_AUTOCONF, 40 .flags = UPF_BOOT_AUTOCONF,
41 .scscr = SCSCR_RE | SCSCR_TE,
42 .scbrr_algo_id = SCBRR_ALGO_4,
41 .type = PORT_SCIFA, 43 .type = PORT_SCIFA,
42 .irqs = { evt2irq(0x0c00), evt2irq(0x0c00), 44 .irqs = { evt2irq(0x0c00), evt2irq(0x0c00),
43 evt2irq(0x0c00), evt2irq(0x0c00) }, 45 evt2irq(0x0c00), evt2irq(0x0c00) },
@@ -55,6 +57,8 @@ static struct platform_device scif0_device = {
55static struct plat_sci_port scif1_platform_data = { 57static struct plat_sci_port scif1_platform_data = {
56 .mapbase = 0xe6c50000, 58 .mapbase = 0xe6c50000,
57 .flags = UPF_BOOT_AUTOCONF, 59 .flags = UPF_BOOT_AUTOCONF,
60 .scscr = SCSCR_RE | SCSCR_TE,
61 .scbrr_algo_id = SCBRR_ALGO_4,
58 .type = PORT_SCIFA, 62 .type = PORT_SCIFA,
59 .irqs = { evt2irq(0x0c20), evt2irq(0x0c20), 63 .irqs = { evt2irq(0x0c20), evt2irq(0x0c20),
60 evt2irq(0x0c20), evt2irq(0x0c20) }, 64 evt2irq(0x0c20), evt2irq(0x0c20) },
@@ -72,6 +76,8 @@ static struct platform_device scif1_device = {
72static struct plat_sci_port scif2_platform_data = { 76static struct plat_sci_port scif2_platform_data = {
73 .mapbase = 0xe6c60000, 77 .mapbase = 0xe6c60000,
74 .flags = UPF_BOOT_AUTOCONF, 78 .flags = UPF_BOOT_AUTOCONF,
79 .scscr = SCSCR_RE | SCSCR_TE,
80 .scbrr_algo_id = SCBRR_ALGO_4,
75 .type = PORT_SCIFA, 81 .type = PORT_SCIFA,
76 .irqs = { evt2irq(0x0c40), evt2irq(0x0c40), 82 .irqs = { evt2irq(0x0c40), evt2irq(0x0c40),
77 evt2irq(0x0c40), evt2irq(0x0c40) }, 83 evt2irq(0x0c40), evt2irq(0x0c40) },
@@ -89,6 +95,8 @@ static struct platform_device scif2_device = {
89static struct plat_sci_port scif3_platform_data = { 95static struct plat_sci_port scif3_platform_data = {
90 .mapbase = 0xe6c70000, 96 .mapbase = 0xe6c70000,
91 .flags = UPF_BOOT_AUTOCONF, 97 .flags = UPF_BOOT_AUTOCONF,
98 .scscr = SCSCR_RE | SCSCR_TE,
99 .scbrr_algo_id = SCBRR_ALGO_4,
92 .type = PORT_SCIFA, 100 .type = PORT_SCIFA,
93 .irqs = { evt2irq(0x0c60), evt2irq(0x0c60), 101 .irqs = { evt2irq(0x0c60), evt2irq(0x0c60),
94 evt2irq(0x0c60), evt2irq(0x0c60) }, 102 evt2irq(0x0c60), evt2irq(0x0c60) },
@@ -106,6 +114,8 @@ static struct platform_device scif3_device = {
106static struct plat_sci_port scif4_platform_data = { 114static struct plat_sci_port scif4_platform_data = {
107 .mapbase = 0xe6c80000, 115 .mapbase = 0xe6c80000,
108 .flags = UPF_BOOT_AUTOCONF, 116 .flags = UPF_BOOT_AUTOCONF,
117 .scscr = SCSCR_RE | SCSCR_TE,
118 .scbrr_algo_id = SCBRR_ALGO_4,
109 .type = PORT_SCIFA, 119 .type = PORT_SCIFA,
110 .irqs = { evt2irq(0x0d20), evt2irq(0x0d20), 120 .irqs = { evt2irq(0x0d20), evt2irq(0x0d20),
111 evt2irq(0x0d20), evt2irq(0x0d20) }, 121 evt2irq(0x0d20), evt2irq(0x0d20) },
@@ -123,6 +133,8 @@ static struct platform_device scif4_device = {
123static struct plat_sci_port scif5_platform_data = { 133static struct plat_sci_port scif5_platform_data = {
124 .mapbase = 0xe6cb0000, 134 .mapbase = 0xe6cb0000,
125 .flags = UPF_BOOT_AUTOCONF, 135 .flags = UPF_BOOT_AUTOCONF,
136 .scscr = SCSCR_RE | SCSCR_TE,
137 .scbrr_algo_id = SCBRR_ALGO_4,
126 .type = PORT_SCIFA, 138 .type = PORT_SCIFA,
127 .irqs = { evt2irq(0x0d40), evt2irq(0x0d40), 139 .irqs = { evt2irq(0x0d40), evt2irq(0x0d40),
128 evt2irq(0x0d40), evt2irq(0x0d40) }, 140 evt2irq(0x0d40), evt2irq(0x0d40) },
@@ -140,6 +152,8 @@ static struct platform_device scif5_device = {
140static struct plat_sci_port scif6_platform_data = { 152static struct plat_sci_port scif6_platform_data = {
141 .mapbase = 0xe6c30000, 153 .mapbase = 0xe6c30000,
142 .flags = UPF_BOOT_AUTOCONF, 154 .flags = UPF_BOOT_AUTOCONF,
155 .scscr = SCSCR_RE | SCSCR_TE,
156 .scbrr_algo_id = SCBRR_ALGO_4,
143 .type = PORT_SCIFB, 157 .type = PORT_SCIFB,
144 .irqs = { evt2irq(0x0d60), evt2irq(0x0d60), 158 .irqs = { evt2irq(0x0d60), evt2irq(0x0d60),
145 evt2irq(0x0d60), evt2irq(0x0d60) }, 159 evt2irq(0x0d60), evt2irq(0x0d60) },
diff --git a/arch/arm/mach-shmobile/setup-sh7377.c b/arch/arm/mach-shmobile/setup-sh7377.c
index 575dbd6c2f1d..8099b0b8a934 100644
--- a/arch/arm/mach-shmobile/setup-sh7377.c
+++ b/arch/arm/mach-shmobile/setup-sh7377.c
@@ -36,6 +36,8 @@
36static struct plat_sci_port scif0_platform_data = { 36static struct plat_sci_port scif0_platform_data = {
37 .mapbase = 0xe6c40000, 37 .mapbase = 0xe6c40000,
38 .flags = UPF_BOOT_AUTOCONF, 38 .flags = UPF_BOOT_AUTOCONF,
39 .scscr = SCSCR_RE | SCSCR_TE,
40 .scbrr_algo_id = SCBRR_ALGO_4,
39 .type = PORT_SCIF, 41 .type = PORT_SCIF,
40 .irqs = { evt2irq(0xc00), evt2irq(0xc00), 42 .irqs = { evt2irq(0xc00), evt2irq(0xc00),
41 evt2irq(0xc00), evt2irq(0xc00) }, 43 evt2irq(0xc00), evt2irq(0xc00) },
@@ -53,6 +55,8 @@ static struct platform_device scif0_device = {
53static struct plat_sci_port scif1_platform_data = { 55static struct plat_sci_port scif1_platform_data = {
54 .mapbase = 0xe6c50000, 56 .mapbase = 0xe6c50000,
55 .flags = UPF_BOOT_AUTOCONF, 57 .flags = UPF_BOOT_AUTOCONF,
58 .scscr = SCSCR_RE | SCSCR_TE,
59 .scbrr_algo_id = SCBRR_ALGO_4,
56 .type = PORT_SCIF, 60 .type = PORT_SCIF,
57 .irqs = { evt2irq(0xc20), evt2irq(0xc20), 61 .irqs = { evt2irq(0xc20), evt2irq(0xc20),
58 evt2irq(0xc20), evt2irq(0xc20) }, 62 evt2irq(0xc20), evt2irq(0xc20) },
@@ -70,6 +74,8 @@ static struct platform_device scif1_device = {
70static struct plat_sci_port scif2_platform_data = { 74static struct plat_sci_port scif2_platform_data = {
71 .mapbase = 0xe6c60000, 75 .mapbase = 0xe6c60000,
72 .flags = UPF_BOOT_AUTOCONF, 76 .flags = UPF_BOOT_AUTOCONF,
77 .scscr = SCSCR_RE | SCSCR_TE,
78 .scbrr_algo_id = SCBRR_ALGO_4,
73 .type = PORT_SCIF, 79 .type = PORT_SCIF,
74 .irqs = { evt2irq(0xc40), evt2irq(0xc40), 80 .irqs = { evt2irq(0xc40), evt2irq(0xc40),
75 evt2irq(0xc40), evt2irq(0xc40) }, 81 evt2irq(0xc40), evt2irq(0xc40) },
@@ -87,6 +93,8 @@ static struct platform_device scif2_device = {
87static struct plat_sci_port scif3_platform_data = { 93static struct plat_sci_port scif3_platform_data = {
88 .mapbase = 0xe6c70000, 94 .mapbase = 0xe6c70000,
89 .flags = UPF_BOOT_AUTOCONF, 95 .flags = UPF_BOOT_AUTOCONF,
96 .scscr = SCSCR_RE | SCSCR_TE,
97 .scbrr_algo_id = SCBRR_ALGO_4,
90 .type = PORT_SCIF, 98 .type = PORT_SCIF,
91 .irqs = { evt2irq(0xc60), evt2irq(0xc60), 99 .irqs = { evt2irq(0xc60), evt2irq(0xc60),
92 evt2irq(0xc60), evt2irq(0xc60) }, 100 evt2irq(0xc60), evt2irq(0xc60) },
@@ -104,6 +112,8 @@ static struct platform_device scif3_device = {
104static struct plat_sci_port scif4_platform_data = { 112static struct plat_sci_port scif4_platform_data = {
105 .mapbase = 0xe6c80000, 113 .mapbase = 0xe6c80000,
106 .flags = UPF_BOOT_AUTOCONF, 114 .flags = UPF_BOOT_AUTOCONF,
115 .scscr = SCSCR_RE | SCSCR_TE,
116 .scbrr_algo_id = SCBRR_ALGO_4,
107 .type = PORT_SCIF, 117 .type = PORT_SCIF,
108 .irqs = { evt2irq(0xd20), evt2irq(0xd20), 118 .irqs = { evt2irq(0xd20), evt2irq(0xd20),
109 evt2irq(0xd20), evt2irq(0xd20) }, 119 evt2irq(0xd20), evt2irq(0xd20) },
@@ -121,6 +131,8 @@ static struct platform_device scif4_device = {
121static struct plat_sci_port scif5_platform_data = { 131static struct plat_sci_port scif5_platform_data = {
122 .mapbase = 0xe6cb0000, 132 .mapbase = 0xe6cb0000,
123 .flags = UPF_BOOT_AUTOCONF, 133 .flags = UPF_BOOT_AUTOCONF,
134 .scscr = SCSCR_RE | SCSCR_TE,
135 .scbrr_algo_id = SCBRR_ALGO_4,
124 .type = PORT_SCIF, 136 .type = PORT_SCIF,
125 .irqs = { evt2irq(0xd40), evt2irq(0xd40), 137 .irqs = { evt2irq(0xd40), evt2irq(0xd40),
126 evt2irq(0xd40), evt2irq(0xd40) }, 138 evt2irq(0xd40), evt2irq(0xd40) },
@@ -138,6 +150,8 @@ static struct platform_device scif5_device = {
138static struct plat_sci_port scif6_platform_data = { 150static struct plat_sci_port scif6_platform_data = {
139 .mapbase = 0xe6cc0000, 151 .mapbase = 0xe6cc0000,
140 .flags = UPF_BOOT_AUTOCONF, 152 .flags = UPF_BOOT_AUTOCONF,
153 .scscr = SCSCR_RE | SCSCR_TE,
154 .scbrr_algo_id = SCBRR_ALGO_4,
141 .type = PORT_SCIF, 155 .type = PORT_SCIF,
142 .irqs = { intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80), 156 .irqs = { intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80),
143 intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80) }, 157 intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80) },
@@ -155,6 +169,8 @@ static struct platform_device scif6_device = {
155static struct plat_sci_port scif7_platform_data = { 169static struct plat_sci_port scif7_platform_data = {
156 .mapbase = 0xe6c30000, 170 .mapbase = 0xe6c30000,
157 .flags = UPF_BOOT_AUTOCONF, 171 .flags = UPF_BOOT_AUTOCONF,
172 .scscr = SCSCR_RE | SCSCR_TE,
173 .scbrr_algo_id = SCBRR_ALGO_4,
158 .type = PORT_SCIF, 174 .type = PORT_SCIF,
159 .irqs = { evt2irq(0xd60), evt2irq(0xd60), 175 .irqs = { evt2irq(0xd60), evt2irq(0xd60),
160 evt2irq(0xd60), evt2irq(0xd60) }, 176 evt2irq(0xd60), evt2irq(0xd60) },
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index f1eff8b37bd6..685c40a2f5e6 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -36,6 +36,8 @@
36static struct plat_sci_port scif0_platform_data = { 36static struct plat_sci_port scif0_platform_data = {
37 .mapbase = 0xe6c40000, 37 .mapbase = 0xe6c40000,
38 .flags = UPF_BOOT_AUTOCONF, 38 .flags = UPF_BOOT_AUTOCONF,
39 .scscr = SCSCR_RE | SCSCR_TE,
40 .scbrr_algo_id = SCBRR_ALGO_4,
39 .type = PORT_SCIFA, 41 .type = PORT_SCIFA,
40 .irqs = { gic_spi(72), gic_spi(72), 42 .irqs = { gic_spi(72), gic_spi(72),
41 gic_spi(72), gic_spi(72) }, 43 gic_spi(72), gic_spi(72) },
@@ -52,6 +54,8 @@ static struct platform_device scif0_device = {
52static struct plat_sci_port scif1_platform_data = { 54static struct plat_sci_port scif1_platform_data = {
53 .mapbase = 0xe6c50000, 55 .mapbase = 0xe6c50000,
54 .flags = UPF_BOOT_AUTOCONF, 56 .flags = UPF_BOOT_AUTOCONF,
57 .scscr = SCSCR_RE | SCSCR_TE,
58 .scbrr_algo_id = SCBRR_ALGO_4,
55 .type = PORT_SCIFA, 59 .type = PORT_SCIFA,
56 .irqs = { gic_spi(73), gic_spi(73), 60 .irqs = { gic_spi(73), gic_spi(73),
57 gic_spi(73), gic_spi(73) }, 61 gic_spi(73), gic_spi(73) },
@@ -68,6 +72,8 @@ static struct platform_device scif1_device = {
68static struct plat_sci_port scif2_platform_data = { 72static struct plat_sci_port scif2_platform_data = {
69 .mapbase = 0xe6c60000, 73 .mapbase = 0xe6c60000,
70 .flags = UPF_BOOT_AUTOCONF, 74 .flags = UPF_BOOT_AUTOCONF,
75 .scscr = SCSCR_RE | SCSCR_TE,
76 .scbrr_algo_id = SCBRR_ALGO_4,
71 .type = PORT_SCIFA, 77 .type = PORT_SCIFA,
72 .irqs = { gic_spi(74), gic_spi(74), 78 .irqs = { gic_spi(74), gic_spi(74),
73 gic_spi(74), gic_spi(74) }, 79 gic_spi(74), gic_spi(74) },
@@ -84,6 +90,8 @@ static struct platform_device scif2_device = {
84static struct plat_sci_port scif3_platform_data = { 90static struct plat_sci_port scif3_platform_data = {
85 .mapbase = 0xe6c70000, 91 .mapbase = 0xe6c70000,
86 .flags = UPF_BOOT_AUTOCONF, 92 .flags = UPF_BOOT_AUTOCONF,
93 .scscr = SCSCR_RE | SCSCR_TE,
94 .scbrr_algo_id = SCBRR_ALGO_4,
87 .type = PORT_SCIFA, 95 .type = PORT_SCIFA,
88 .irqs = { gic_spi(75), gic_spi(75), 96 .irqs = { gic_spi(75), gic_spi(75),
89 gic_spi(75), gic_spi(75) }, 97 gic_spi(75), gic_spi(75) },
@@ -100,6 +108,8 @@ static struct platform_device scif3_device = {
100static struct plat_sci_port scif4_platform_data = { 108static struct plat_sci_port scif4_platform_data = {
101 .mapbase = 0xe6c80000, 109 .mapbase = 0xe6c80000,
102 .flags = UPF_BOOT_AUTOCONF, 110 .flags = UPF_BOOT_AUTOCONF,
111 .scscr = SCSCR_RE | SCSCR_TE,
112 .scbrr_algo_id = SCBRR_ALGO_4,
103 .type = PORT_SCIFA, 113 .type = PORT_SCIFA,
104 .irqs = { gic_spi(78), gic_spi(78), 114 .irqs = { gic_spi(78), gic_spi(78),
105 gic_spi(78), gic_spi(78) }, 115 gic_spi(78), gic_spi(78) },
@@ -116,6 +126,8 @@ static struct platform_device scif4_device = {
116static struct plat_sci_port scif5_platform_data = { 126static struct plat_sci_port scif5_platform_data = {
117 .mapbase = 0xe6cb0000, 127 .mapbase = 0xe6cb0000,
118 .flags = UPF_BOOT_AUTOCONF, 128 .flags = UPF_BOOT_AUTOCONF,
129 .scscr = SCSCR_RE | SCSCR_TE,
130 .scbrr_algo_id = SCBRR_ALGO_4,
119 .type = PORT_SCIFA, 131 .type = PORT_SCIFA,
120 .irqs = { gic_spi(79), gic_spi(79), 132 .irqs = { gic_spi(79), gic_spi(79),
121 gic_spi(79), gic_spi(79) }, 133 gic_spi(79), gic_spi(79) },
@@ -132,6 +144,8 @@ static struct platform_device scif5_device = {
132static struct plat_sci_port scif6_platform_data = { 144static struct plat_sci_port scif6_platform_data = {
133 .mapbase = 0xe6cc0000, 145 .mapbase = 0xe6cc0000,
134 .flags = UPF_BOOT_AUTOCONF, 146 .flags = UPF_BOOT_AUTOCONF,
147 .scscr = SCSCR_RE | SCSCR_TE,
148 .scbrr_algo_id = SCBRR_ALGO_4,
135 .type = PORT_SCIFA, 149 .type = PORT_SCIFA,
136 .irqs = { gic_spi(156), gic_spi(156), 150 .irqs = { gic_spi(156), gic_spi(156),
137 gic_spi(156), gic_spi(156) }, 151 gic_spi(156), gic_spi(156) },
@@ -148,6 +162,8 @@ static struct platform_device scif6_device = {
148static struct plat_sci_port scif7_platform_data = { 162static struct plat_sci_port scif7_platform_data = {
149 .mapbase = 0xe6cd0000, 163 .mapbase = 0xe6cd0000,
150 .flags = UPF_BOOT_AUTOCONF, 164 .flags = UPF_BOOT_AUTOCONF,
165 .scscr = SCSCR_RE | SCSCR_TE,
166 .scbrr_algo_id = SCBRR_ALGO_4,
151 .type = PORT_SCIFA, 167 .type = PORT_SCIFA,
152 .irqs = { gic_spi(143), gic_spi(143), 168 .irqs = { gic_spi(143), gic_spi(143),
153 gic_spi(143), gic_spi(143) }, 169 gic_spi(143), gic_spi(143) },
@@ -164,6 +180,8 @@ static struct platform_device scif7_device = {
164static struct plat_sci_port scif8_platform_data = { 180static struct plat_sci_port scif8_platform_data = {
165 .mapbase = 0xe6c30000, 181 .mapbase = 0xe6c30000,
166 .flags = UPF_BOOT_AUTOCONF, 182 .flags = UPF_BOOT_AUTOCONF,
183 .scscr = SCSCR_RE | SCSCR_TE,
184 .scbrr_algo_id = SCBRR_ALGO_4,
167 .type = PORT_SCIFB, 185 .type = PORT_SCIFB,
168 .irqs = { gic_spi(80), gic_spi(80), 186 .irqs = { gic_spi(80), gic_spi(80),
169 gic_spi(80), gic_spi(80) }, 187 gic_spi(80), gic_spi(80) },
diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
index c3638516bffc..0f8befccf9fa 100644
--- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
@@ -62,6 +62,8 @@ static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, NULL,
62static struct plat_sci_port scif0_platform_data = { 62static struct plat_sci_port scif0_platform_data = {
63 .mapbase = 0xf8400000, 63 .mapbase = 0xf8400000,
64 .flags = UPF_BOOT_AUTOCONF, 64 .flags = UPF_BOOT_AUTOCONF,
65 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
66 .scbrr_algo_id = SCBRR_ALGO_2,
65 .type = PORT_SCIF, 67 .type = PORT_SCIF,
66 .irqs = { 88, 88, 88, 88 }, 68 .irqs = { 88, 88, 88, 88 },
67}; 69};
@@ -77,6 +79,8 @@ static struct platform_device scif0_device = {
77static struct plat_sci_port scif1_platform_data = { 79static struct plat_sci_port scif1_platform_data = {
78 .mapbase = 0xf8410000, 80 .mapbase = 0xf8410000,
79 .flags = UPF_BOOT_AUTOCONF, 81 .flags = UPF_BOOT_AUTOCONF,
82 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
83 .scbrr_algo_id = SCBRR_ALGO_2,
80 .type = PORT_SCIF, 84 .type = PORT_SCIF,
81 .irqs = { 92, 92, 92, 92 }, 85 .irqs = { 92, 92, 92, 92 },
82}; 86};
@@ -92,6 +96,8 @@ static struct platform_device scif1_device = {
92static struct plat_sci_port scif2_platform_data = { 96static struct plat_sci_port scif2_platform_data = {
93 .mapbase = 0xf8420000, 97 .mapbase = 0xf8420000,
94 .flags = UPF_BOOT_AUTOCONF, 98 .flags = UPF_BOOT_AUTOCONF,
99 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
100 .scbrr_algo_id = SCBRR_ALGO_2,
95 .type = PORT_SCIF, 101 .type = PORT_SCIF,
96 .irqs = { 96, 96, 96, 96 }, 102 .irqs = { 96, 96, 96, 96 },
97}; 103};
diff --git a/arch/sh/kernel/cpu/sh2a/setup-mxg.c b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
index 6c96ea02bf8d..949bf2bac28c 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-mxg.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
@@ -201,6 +201,8 @@ static struct platform_device mtu2_2_device = {
201static struct plat_sci_port scif0_platform_data = { 201static struct plat_sci_port scif0_platform_data = {
202 .mapbase = 0xff804000, 202 .mapbase = 0xff804000,
203 .flags = UPF_BOOT_AUTOCONF, 203 .flags = UPF_BOOT_AUTOCONF,
204 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
205 .scbrr_algo_id = SCBRR_ALGO_2,
204 .type = PORT_SCIF, 206 .type = PORT_SCIF,
205 .irqs = { 220, 220, 220, 220 }, 207 .irqs = { 220, 220, 220, 220 },
206}; 208};
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
index d08bf4c07d60..9df558dcdb86 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
@@ -180,6 +180,8 @@ static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups,
180static struct plat_sci_port scif0_platform_data = { 180static struct plat_sci_port scif0_platform_data = {
181 .mapbase = 0xfffe8000, 181 .mapbase = 0xfffe8000,
182 .flags = UPF_BOOT_AUTOCONF, 182 .flags = UPF_BOOT_AUTOCONF,
183 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
184 .scbrr_algo_id = SCBRR_ALGO_2,
183 .type = PORT_SCIF, 185 .type = PORT_SCIF,
184 .irqs = { 180, 180, 180, 180 } 186 .irqs = { 180, 180, 180, 180 }
185}; 187};
@@ -195,6 +197,8 @@ static struct platform_device scif0_device = {
195static struct plat_sci_port scif1_platform_data = { 197static struct plat_sci_port scif1_platform_data = {
196 .mapbase = 0xfffe8800, 198 .mapbase = 0xfffe8800,
197 .flags = UPF_BOOT_AUTOCONF, 199 .flags = UPF_BOOT_AUTOCONF,
200 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
201 .scbrr_algo_id = SCBRR_ALGO_2,
198 .type = PORT_SCIF, 202 .type = PORT_SCIF,
199 .irqs = { 184, 184, 184, 184 } 203 .irqs = { 184, 184, 184, 184 }
200}; 204};
@@ -210,6 +214,8 @@ static struct platform_device scif1_device = {
210static struct plat_sci_port scif2_platform_data = { 214static struct plat_sci_port scif2_platform_data = {
211 .mapbase = 0xfffe9000, 215 .mapbase = 0xfffe9000,
212 .flags = UPF_BOOT_AUTOCONF, 216 .flags = UPF_BOOT_AUTOCONF,
217 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
218 .scbrr_algo_id = SCBRR_ALGO_2,
213 .type = PORT_SCIF, 219 .type = PORT_SCIF,
214 .irqs = { 188, 188, 188, 188 } 220 .irqs = { 188, 188, 188, 188 }
215}; 221};
@@ -225,6 +231,8 @@ static struct platform_device scif2_device = {
225static struct plat_sci_port scif3_platform_data = { 231static struct plat_sci_port scif3_platform_data = {
226 .mapbase = 0xfffe9800, 232 .mapbase = 0xfffe9800,
227 .flags = UPF_BOOT_AUTOCONF, 233 .flags = UPF_BOOT_AUTOCONF,
234 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
235 .scbrr_algo_id = SCBRR_ALGO_2,
228 .type = PORT_SCIF, 236 .type = PORT_SCIF,
229 .irqs = { 192, 192, 192, 192 } 237 .irqs = { 192, 192, 192, 192 }
230}; 238};
@@ -240,6 +248,8 @@ static struct platform_device scif3_device = {
240static struct plat_sci_port scif4_platform_data = { 248static struct plat_sci_port scif4_platform_data = {
241 .mapbase = 0xfffea000, 249 .mapbase = 0xfffea000,
242 .flags = UPF_BOOT_AUTOCONF, 250 .flags = UPF_BOOT_AUTOCONF,
251 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
252 .scbrr_algo_id = SCBRR_ALGO_2,
243 .type = PORT_SCIF, 253 .type = PORT_SCIF,
244 .irqs = { 196, 196, 196, 196 } 254 .irqs = { 196, 196, 196, 196 }
245}; 255};
@@ -255,6 +265,8 @@ static struct platform_device scif4_device = {
255static struct plat_sci_port scif5_platform_data = { 265static struct plat_sci_port scif5_platform_data = {
256 .mapbase = 0xfffea800, 266 .mapbase = 0xfffea800,
257 .flags = UPF_BOOT_AUTOCONF, 267 .flags = UPF_BOOT_AUTOCONF,
268 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
269 .scbrr_algo_id = SCBRR_ALGO_2,
258 .type = PORT_SCIF, 270 .type = PORT_SCIF,
259 .irqs = { 200, 200, 200, 200 } 271 .irqs = { 200, 200, 200, 200 }
260}; 272};
@@ -270,6 +282,8 @@ static struct platform_device scif5_device = {
270static struct plat_sci_port scif6_platform_data = { 282static struct plat_sci_port scif6_platform_data = {
271 .mapbase = 0xfffeb000, 283 .mapbase = 0xfffeb000,
272 .flags = UPF_BOOT_AUTOCONF, 284 .flags = UPF_BOOT_AUTOCONF,
285 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
286 .scbrr_algo_id = SCBRR_ALGO_2,
273 .type = PORT_SCIF, 287 .type = PORT_SCIF,
274 .irqs = { 204, 204, 204, 204 } 288 .irqs = { 204, 204, 204, 204 }
275}; 289};
@@ -285,6 +299,8 @@ static struct platform_device scif6_device = {
285static struct plat_sci_port scif7_platform_data = { 299static struct plat_sci_port scif7_platform_data = {
286 .mapbase = 0xfffeb800, 300 .mapbase = 0xfffeb800,
287 .flags = UPF_BOOT_AUTOCONF, 301 .flags = UPF_BOOT_AUTOCONF,
302 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
303 .scbrr_algo_id = SCBRR_ALGO_2,
288 .type = PORT_SCIF, 304 .type = PORT_SCIF,
289 .irqs = { 208, 208, 208, 208 } 305 .irqs = { 208, 208, 208, 208 }
290}; 306};
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
index 832f401b5860..a43124e608c3 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
@@ -176,6 +176,8 @@ static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups,
176static struct plat_sci_port scif0_platform_data = { 176static struct plat_sci_port scif0_platform_data = {
177 .mapbase = 0xfffe8000, 177 .mapbase = 0xfffe8000,
178 .flags = UPF_BOOT_AUTOCONF, 178 .flags = UPF_BOOT_AUTOCONF,
179 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
180 .scbrr_algo_id = SCBRR_ALGO_2,
179 .type = PORT_SCIF, 181 .type = PORT_SCIF,
180 .irqs = { 192, 192, 192, 192 }, 182 .irqs = { 192, 192, 192, 192 },
181}; 183};
@@ -191,6 +193,8 @@ static struct platform_device scif0_device = {
191static struct plat_sci_port scif1_platform_data = { 193static struct plat_sci_port scif1_platform_data = {
192 .mapbase = 0xfffe8800, 194 .mapbase = 0xfffe8800,
193 .flags = UPF_BOOT_AUTOCONF, 195 .flags = UPF_BOOT_AUTOCONF,
196 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
197 .scbrr_algo_id = SCBRR_ALGO_2,
194 .type = PORT_SCIF, 198 .type = PORT_SCIF,
195 .irqs = { 196, 196, 196, 196 }, 199 .irqs = { 196, 196, 196, 196 },
196}; 200};
@@ -206,6 +210,8 @@ static struct platform_device scif1_device = {
206static struct plat_sci_port scif2_platform_data = { 210static struct plat_sci_port scif2_platform_data = {
207 .mapbase = 0xfffe9000, 211 .mapbase = 0xfffe9000,
208 .flags = UPF_BOOT_AUTOCONF, 212 .flags = UPF_BOOT_AUTOCONF,
213 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
214 .scbrr_algo_id = SCBRR_ALGO_2,
209 .type = PORT_SCIF, 215 .type = PORT_SCIF,
210 .irqs = { 200, 200, 200, 200 }, 216 .irqs = { 200, 200, 200, 200 },
211}; 217};
@@ -221,6 +227,8 @@ static struct platform_device scif2_device = {
221static struct plat_sci_port scif3_platform_data = { 227static struct plat_sci_port scif3_platform_data = {
222 .mapbase = 0xfffe9800, 228 .mapbase = 0xfffe9800,
223 .flags = UPF_BOOT_AUTOCONF, 229 .flags = UPF_BOOT_AUTOCONF,
230 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
231 .scbrr_algo_id = SCBRR_ALGO_2,
224 .type = PORT_SCIF, 232 .type = PORT_SCIF,
225 .irqs = { 204, 204, 204, 204 }, 233 .irqs = { 204, 204, 204, 204 },
226}; 234};
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
index dc47b04e1049..5d14f849aea3 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
@@ -136,6 +136,8 @@ static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups,
136static struct plat_sci_port scif0_platform_data = { 136static struct plat_sci_port scif0_platform_data = {
137 .mapbase = 0xfffe8000, 137 .mapbase = 0xfffe8000,
138 .flags = UPF_BOOT_AUTOCONF, 138 .flags = UPF_BOOT_AUTOCONF,
139 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
140 .scbrr_algo_id = SCBRR_ALGO_2,
139 .type = PORT_SCIF, 141 .type = PORT_SCIF,
140 .irqs = { 240, 240, 240, 240 }, 142 .irqs = { 240, 240, 240, 240 },
141}; 143};
@@ -151,6 +153,8 @@ static struct platform_device scif0_device = {
151static struct plat_sci_port scif1_platform_data = { 153static struct plat_sci_port scif1_platform_data = {
152 .mapbase = 0xfffe8800, 154 .mapbase = 0xfffe8800,
153 .flags = UPF_BOOT_AUTOCONF, 155 .flags = UPF_BOOT_AUTOCONF,
156 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
157 .scbrr_algo_id = SCBRR_ALGO_2,
154 .type = PORT_SCIF, 158 .type = PORT_SCIF,
155 .irqs = { 244, 244, 244, 244 }, 159 .irqs = { 244, 244, 244, 244 },
156}; 160};
@@ -166,6 +170,8 @@ static struct platform_device scif1_device = {
166static struct plat_sci_port scif2_platform_data = { 170static struct plat_sci_port scif2_platform_data = {
167 .mapbase = 0xfffe9000, 171 .mapbase = 0xfffe9000,
168 .flags = UPF_BOOT_AUTOCONF, 172 .flags = UPF_BOOT_AUTOCONF,
173 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
174 .scbrr_algo_id = SCBRR_ALGO_2,
169 .type = PORT_SCIF, 175 .type = PORT_SCIF,
170 .irqs = { 248, 248, 248, 248 }, 176 .irqs = { 248, 248, 248, 248 },
171}; 177};
@@ -181,6 +187,8 @@ static struct platform_device scif2_device = {
181static struct plat_sci_port scif3_platform_data = { 187static struct plat_sci_port scif3_platform_data = {
182 .mapbase = 0xfffe9800, 188 .mapbase = 0xfffe9800,
183 .flags = UPF_BOOT_AUTOCONF, 189 .flags = UPF_BOOT_AUTOCONF,
190 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
191 .scbrr_algo_id = SCBRR_ALGO_2,
184 .type = PORT_SCIF, 192 .type = PORT_SCIF,
185 .irqs = { 252, 252, 252, 252 }, 193 .irqs = { 252, 252, 252, 252 },
186}; 194};
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
index baadd7f54d94..cd2e702feb7e 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
@@ -70,6 +70,9 @@ static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, NULL,
70static struct plat_sci_port scif0_platform_data = { 70static struct plat_sci_port scif0_platform_data = {
71 .mapbase = 0xa4410000, 71 .mapbase = 0xa4410000,
72 .flags = UPF_BOOT_AUTOCONF, 72 .flags = UPF_BOOT_AUTOCONF,
73 .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE |
74 SCSCR_RE | SCSCR_CKE1 | SCSCR_CKE0,
75 .scbrr_algo_id = SCBRR_ALGO_4,
73 .type = PORT_SCIF, 76 .type = PORT_SCIF,
74 .irqs = { 56, 56, 56 }, 77 .irqs = { 56, 56, 56 },
75}; 78};
@@ -85,6 +88,8 @@ static struct platform_device scif0_device = {
85static struct plat_sci_port scif1_platform_data = { 88static struct plat_sci_port scif1_platform_data = {
86 .mapbase = 0xa4400000, 89 .mapbase = 0xa4400000,
87 .flags = UPF_BOOT_AUTOCONF, 90 .flags = UPF_BOOT_AUTOCONF,
91 .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE,
92 .scbrr_algo_id = SCBRR_ALGO_4,
88 .type = PORT_SCIF, 93 .type = PORT_SCIF,
89 .irqs = { 52, 52, 52 }, 94 .irqs = { 52, 52, 52 },
90}; 95};
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
index 3cf8c8ef7b32..4551ad647c2c 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
@@ -109,6 +109,8 @@ static struct platform_device rtc_device = {
109static struct plat_sci_port scif0_platform_data = { 109static struct plat_sci_port scif0_platform_data = {
110 .mapbase = 0xfffffe80, 110 .mapbase = 0xfffffe80,
111 .flags = UPF_BOOT_AUTOCONF, 111 .flags = UPF_BOOT_AUTOCONF,
112 .scscr = SCSCR_TE | SCSCR_RE,
113 .scbrr_algo_id = SCBRR_ALGO_2,
112 .type = PORT_SCI, 114 .type = PORT_SCI,
113 .irqs = { 23, 23, 23, 0 }, 115 .irqs = { 23, 23, 23, 0 },
114}; 116};
@@ -126,6 +128,8 @@ static struct platform_device scif0_device = {
126static struct plat_sci_port scif1_platform_data = { 128static struct plat_sci_port scif1_platform_data = {
127 .mapbase = 0xa4000150, 129 .mapbase = 0xa4000150,
128 .flags = UPF_BOOT_AUTOCONF, 130 .flags = UPF_BOOT_AUTOCONF,
131 .scscr = SCSCR_TE | SCSCR_RE,
132 .scbrr_algo_id = SCBRR_ALGO_2,
129 .type = PORT_SCIF, 133 .type = PORT_SCIF,
130 .irqs = { 56, 56, 56, 56 }, 134 .irqs = { 56, 56, 56, 56 },
131}; 135};
@@ -143,6 +147,8 @@ static struct platform_device scif1_device = {
143static struct plat_sci_port scif2_platform_data = { 147static struct plat_sci_port scif2_platform_data = {
144 .mapbase = 0xa4000140, 148 .mapbase = 0xa4000140,
145 .flags = UPF_BOOT_AUTOCONF, 149 .flags = UPF_BOOT_AUTOCONF,
150 .scscr = SCSCR_TE | SCSCR_RE,
151 .scbrr_algo_id = SCBRR_ALGO_2,
146 .type = PORT_IRDA, 152 .type = PORT_IRDA,
147 .irqs = { 52, 52, 52, 52 }, 153 .irqs = { 52, 52, 52, 52 },
148}; 154};
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
index b0c2fb4ab479..78f6b01d42c3 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
@@ -99,6 +99,9 @@ static struct platform_device rtc_device = {
99static struct plat_sci_port scif0_platform_data = { 99static struct plat_sci_port scif0_platform_data = {
100 .mapbase = 0xa4400000, 100 .mapbase = 0xa4400000,
101 .flags = UPF_BOOT_AUTOCONF, 101 .flags = UPF_BOOT_AUTOCONF,
102 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
103 SCSCR_CKE1 | SCSCR_CKE0,
104 .scbrr_algo_id = SCBRR_ALGO_2,
102 .type = PORT_SCIF, 105 .type = PORT_SCIF,
103 .irqs = { 52, 52, 52, 52 }, 106 .irqs = { 52, 52, 52, 52 },
104}; 107};
@@ -114,6 +117,9 @@ static struct platform_device scif0_device = {
114static struct plat_sci_port scif1_platform_data = { 117static struct plat_sci_port scif1_platform_data = {
115 .mapbase = 0xa4410000, 118 .mapbase = 0xa4410000,
116 .flags = UPF_BOOT_AUTOCONF, 119 .flags = UPF_BOOT_AUTOCONF,
120 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
121 SCSCR_CKE1 | SCSCR_CKE0,
122 .scbrr_algo_id = SCBRR_ALGO_2,
117 .type = PORT_SCIF, 123 .type = PORT_SCIF,
118 .irqs = { 56, 56, 56, 56 }, 124 .irqs = { 56, 56, 56, 56 },
119}; 125};
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
index 24b17135d5d2..365b94a6fcb7 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * SH7720 Setup 2 * Setup code for SH7720, SH7721.
3 * 3 *
4 * Copyright (C) 2007 Markus Brunner, Mark Jonas 4 * Copyright (C) 2007 Markus Brunner, Mark Jonas
5 * Copyright (C) 2009 Paul Mundt 5 * Copyright (C) 2009 Paul Mundt
@@ -51,6 +51,8 @@ static struct platform_device rtc_device = {
51static struct plat_sci_port scif0_platform_data = { 51static struct plat_sci_port scif0_platform_data = {
52 .mapbase = 0xa4430000, 52 .mapbase = 0xa4430000,
53 .flags = UPF_BOOT_AUTOCONF, 53 .flags = UPF_BOOT_AUTOCONF,
54 .scscr = SCSCR_RE | SCSCR_TE,
55 .scbrr_algo_id = SCBRR_ALGO_4,
54 .type = PORT_SCIF, 56 .type = PORT_SCIF,
55 .irqs = { 80, 80, 80, 80 }, 57 .irqs = { 80, 80, 80, 80 },
56}; 58};
@@ -66,6 +68,8 @@ static struct platform_device scif0_device = {
66static struct plat_sci_port scif1_platform_data = { 68static struct plat_sci_port scif1_platform_data = {
67 .mapbase = 0xa4438000, 69 .mapbase = 0xa4438000,
68 .flags = UPF_BOOT_AUTOCONF, 70 .flags = UPF_BOOT_AUTOCONF,
71 .scscr = SCSCR_RE | SCSCR_TE,
72 .scbrr_algo_id = SCBRR_ALGO_4,
69 .type = PORT_SCIF, 73 .type = PORT_SCIF,
70 .irqs = { 81, 81, 81, 81 }, 74 .irqs = { 81, 81, 81, 81 },
71}; 75};
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
index e916b18e1f7c..5b2833159b7d 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
@@ -18,6 +18,8 @@
18static struct plat_sci_port scif0_platform_data = { 18static struct plat_sci_port scif0_platform_data = {
19 .mapbase = 0xffe80000, 19 .mapbase = 0xffe80000,
20 .flags = UPF_BOOT_AUTOCONF, 20 .flags = UPF_BOOT_AUTOCONF,
21 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
22 .scbrr_algo_id = SCBRR_ALGO_2,
21 .type = PORT_SCIF, 23 .type = PORT_SCIF,
22 .irqs = { 40, 41, 43, 42 }, 24 .irqs = { 40, 41, 43, 42 },
23}; 25};
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
index 911d196e86b5..c2b0aaaedcae 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
@@ -14,6 +14,7 @@
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/sh_timer.h> 15#include <linux/sh_timer.h>
16#include <linux/serial_sci.h> 16#include <linux/serial_sci.h>
17#include <asm/machtypes.h>
17 18
18static struct resource rtc_resources[] = { 19static struct resource rtc_resources[] = {
19 [0] = { 20 [0] = {
@@ -35,33 +36,37 @@ static struct platform_device rtc_device = {
35 .resource = rtc_resources, 36 .resource = rtc_resources,
36}; 37};
37 38
38static struct plat_sci_port scif0_platform_data = { 39static struct plat_sci_port sci_platform_data = {
39 .mapbase = 0xffe00000, 40 .mapbase = 0xffe00000,
40 .flags = UPF_BOOT_AUTOCONF, 41 .flags = UPF_BOOT_AUTOCONF,
42 .scscr = SCSCR_TE | SCSCR_RE,
43 .scbrr_algo_id = SCBRR_ALGO_2,
41 .type = PORT_SCI, 44 .type = PORT_SCI,
42 .irqs = { 23, 23, 23, 0 }, 45 .irqs = { 23, 23, 23, 0 },
43}; 46};
44 47
45static struct platform_device scif0_device = { 48static struct platform_device sci_device = {
46 .name = "sh-sci", 49 .name = "sh-sci",
47 .id = 0, 50 .id = 0,
48 .dev = { 51 .dev = {
49 .platform_data = &scif0_platform_data, 52 .platform_data = &sci_platform_data,
50 }, 53 },
51}; 54};
52 55
53static struct plat_sci_port scif1_platform_data = { 56static struct plat_sci_port scif_platform_data = {
54 .mapbase = 0xffe80000, 57 .mapbase = 0xffe80000,
55 .flags = UPF_BOOT_AUTOCONF, 58 .flags = UPF_BOOT_AUTOCONF,
59 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE,
60 .scbrr_algo_id = SCBRR_ALGO_2,
56 .type = PORT_SCIF, 61 .type = PORT_SCIF,
57 .irqs = { 40, 40, 40, 40 }, 62 .irqs = { 40, 40, 40, 40 },
58}; 63};
59 64
60static struct platform_device scif1_device = { 65static struct platform_device scif_device = {
61 .name = "sh-sci", 66 .name = "sh-sci",
62 .id = 1, 67 .id = 1,
63 .dev = { 68 .dev = {
64 .platform_data = &scif1_platform_data, 69 .platform_data = &scif_platform_data,
65 }, 70 },
66}; 71};
67 72
@@ -210,8 +215,6 @@ static struct platform_device tmu4_device = {
210#endif 215#endif
211 216
212static struct platform_device *sh7750_devices[] __initdata = { 217static struct platform_device *sh7750_devices[] __initdata = {
213 &scif0_device,
214 &scif1_device,
215 &rtc_device, 218 &rtc_device,
216 &tmu0_device, 219 &tmu0_device,
217 &tmu1_device, 220 &tmu1_device,
@@ -226,14 +229,19 @@ static struct platform_device *sh7750_devices[] __initdata = {
226 229
227static int __init sh7750_devices_setup(void) 230static int __init sh7750_devices_setup(void)
228{ 231{
232 if (mach_is_rts7751r2d()) {
233 platform_register_device(&scif_device);
234 } else {
235 platform_register_device(&sci_device);
236 platform_register_device(&scif_device);
237 }
238
229 return platform_add_devices(sh7750_devices, 239 return platform_add_devices(sh7750_devices,
230 ARRAY_SIZE(sh7750_devices)); 240 ARRAY_SIZE(sh7750_devices));
231} 241}
232arch_initcall(sh7750_devices_setup); 242arch_initcall(sh7750_devices_setup);
233 243
234static struct platform_device *sh7750_early_devices[] __initdata = { 244static struct platform_device *sh7750_early_devices[] __initdata = {
235 &scif0_device,
236 &scif1_device,
237 &tmu0_device, 245 &tmu0_device,
238 &tmu1_device, 246 &tmu1_device,
239 &tmu2_device, 247 &tmu2_device,
@@ -247,6 +255,14 @@ static struct platform_device *sh7750_early_devices[] __initdata = {
247 255
248void __init plat_early_device_setup(void) 256void __init plat_early_device_setup(void)
249{ 257{
258 if (mach_is_rts7751r2d()) {
259 scif_platform_data.scscr |= SCSCR_CKE1;
260 early_platform_add_devices(&scif_device, 1);
261 } else {
262 early_platform_add_devices(&sci_device, 1);
263 early_platform_add_devices(&scif_device, 1);
264 }
265
250 early_platform_add_devices(sh7750_early_devices, 266 early_platform_add_devices(sh7750_early_devices,
251 ARRAY_SIZE(sh7750_early_devices)); 267 ARRAY_SIZE(sh7750_early_devices));
252} 268}
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
index 48ea8fe85dc5..78bbf232e391 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
@@ -129,6 +129,8 @@ static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups,
129static struct plat_sci_port scif0_platform_data = { 129static struct plat_sci_port scif0_platform_data = {
130 .mapbase = 0xfe600000, 130 .mapbase = 0xfe600000,
131 .flags = UPF_BOOT_AUTOCONF, 131 .flags = UPF_BOOT_AUTOCONF,
132 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
133 .scbrr_algo_id = SCBRR_ALGO_2,
132 .type = PORT_SCIF, 134 .type = PORT_SCIF,
133 .irqs = { 52, 53, 55, 54 }, 135 .irqs = { 52, 53, 55, 54 },
134}; 136};
@@ -145,6 +147,8 @@ static struct plat_sci_port scif1_platform_data = {
145 .mapbase = 0xfe610000, 147 .mapbase = 0xfe610000,
146 .flags = UPF_BOOT_AUTOCONF, 148 .flags = UPF_BOOT_AUTOCONF,
147 .type = PORT_SCIF, 149 .type = PORT_SCIF,
150 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
151 .scbrr_algo_id = SCBRR_ALGO_2,
148 .irqs = { 72, 73, 75, 74 }, 152 .irqs = { 72, 73, 75, 74 },
149}; 153};
150 154
@@ -159,6 +163,8 @@ static struct platform_device scif1_device = {
159static struct plat_sci_port scif2_platform_data = { 163static struct plat_sci_port scif2_platform_data = {
160 .mapbase = 0xfe620000, 164 .mapbase = 0xfe620000,
161 .flags = UPF_BOOT_AUTOCONF, 165 .flags = UPF_BOOT_AUTOCONF,
166 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
167 .scbrr_algo_id = SCBRR_ALGO_2,
162 .type = PORT_SCIF, 168 .type = PORT_SCIF,
163 .irqs = { 76, 77, 79, 78 }, 169 .irqs = { 76, 77, 79, 78 },
164}; 170};
@@ -174,6 +180,8 @@ static struct platform_device scif2_device = {
174static struct plat_sci_port scif3_platform_data = { 180static struct plat_sci_port scif3_platform_data = {
175 .mapbase = 0xfe480000, 181 .mapbase = 0xfe480000,
176 .flags = UPF_BOOT_AUTOCONF, 182 .flags = UPF_BOOT_AUTOCONF,
183 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
184 .scbrr_algo_id = SCBRR_ALGO_2,
177 .type = PORT_SCI, 185 .type = PORT_SCI,
178 .irqs = { 80, 81, 82, 0 }, 186 .irqs = { 80, 81, 82, 0 },
179}; 187};
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
index b8e5bc80aa4a..1b8848317e9c 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
@@ -19,6 +19,8 @@
19static struct plat_sci_port scif0_platform_data = { 19static struct plat_sci_port scif0_platform_data = {
20 .mapbase = 0xffe00000, 20 .mapbase = 0xffe00000,
21 .flags = UPF_BOOT_AUTOCONF, 21 .flags = UPF_BOOT_AUTOCONF,
22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
23 .scbrr_algo_id = SCBRR_ALGO_2,
22 .type = PORT_SCIF, 24 .type = PORT_SCIF,
23 .irqs = { 80, 80, 80, 80 }, 25 .irqs = { 80, 80, 80, 80 },
24}; 26};
@@ -34,6 +36,8 @@ static struct platform_device scif0_device = {
34static struct plat_sci_port scif1_platform_data = { 36static struct plat_sci_port scif1_platform_data = {
35 .mapbase = 0xffe10000, 37 .mapbase = 0xffe10000,
36 .flags = UPF_BOOT_AUTOCONF, 38 .flags = UPF_BOOT_AUTOCONF,
39 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
40 .scbrr_algo_id = SCBRR_ALGO_2,
37 .type = PORT_SCIF, 41 .type = PORT_SCIF,
38 .irqs = { 81, 81, 81, 81 }, 42 .irqs = { 81, 81, 81, 81 },
39}; 43};
@@ -49,6 +53,8 @@ static struct platform_device scif1_device = {
49static struct plat_sci_port scif2_platform_data = { 53static struct plat_sci_port scif2_platform_data = {
50 .mapbase = 0xffe20000, 54 .mapbase = 0xffe20000,
51 .flags = UPF_BOOT_AUTOCONF, 55 .flags = UPF_BOOT_AUTOCONF,
56 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
57 .scbrr_algo_id = SCBRR_ALGO_2,
52 .type = PORT_SCIF, 58 .type = PORT_SCIF,
53 .irqs = { 82, 82, 82, 82 }, 59 .irqs = { 82, 82, 82, 82 },
54}; 60};
@@ -64,6 +70,8 @@ static struct platform_device scif2_device = {
64static struct plat_sci_port scif3_platform_data = { 70static struct plat_sci_port scif3_platform_data = {
65 .mapbase = 0xffe30000, 71 .mapbase = 0xffe30000,
66 .flags = UPF_BOOT_AUTOCONF, 72 .flags = UPF_BOOT_AUTOCONF,
73 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
74 .scbrr_algo_id = SCBRR_ALGO_2,
67 .type = PORT_SCIF, 75 .type = PORT_SCIF,
68 .irqs = { 83, 83, 83, 83 }, 76 .irqs = { 83, 83, 83, 83 },
69}; 77};
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index 9b3a6aa9081c..82616af64d62 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -21,6 +21,8 @@
21static struct plat_sci_port scif0_platform_data = { 21static struct plat_sci_port scif0_platform_data = {
22 .mapbase = 0xffe00000, 22 .mapbase = 0xffe00000,
23 .flags = UPF_BOOT_AUTOCONF, 23 .flags = UPF_BOOT_AUTOCONF,
24 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
25 .scbrr_algo_id = SCBRR_ALGO_2,
24 .type = PORT_SCIF, 26 .type = PORT_SCIF,
25 .irqs = { 80, 80, 80, 80 }, 27 .irqs = { 80, 80, 80, 80 },
26}; 28};
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index a164f8924258..5813d8023619 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -181,6 +181,8 @@ struct platform_device dma_device = {
181static struct plat_sci_port scif0_platform_data = { 181static struct plat_sci_port scif0_platform_data = {
182 .mapbase = 0xffe00000, 182 .mapbase = 0xffe00000,
183 .flags = UPF_BOOT_AUTOCONF, 183 .flags = UPF_BOOT_AUTOCONF,
184 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
185 .scbrr_algo_id = SCBRR_ALGO_2,
184 .type = PORT_SCIF, 186 .type = PORT_SCIF,
185 .irqs = { 80, 80, 80, 80 }, 187 .irqs = { 80, 80, 80, 80 },
186}; 188};
@@ -196,6 +198,8 @@ static struct platform_device scif0_device = {
196static struct plat_sci_port scif1_platform_data = { 198static struct plat_sci_port scif1_platform_data = {
197 .mapbase = 0xffe10000, 199 .mapbase = 0xffe10000,
198 .flags = UPF_BOOT_AUTOCONF, 200 .flags = UPF_BOOT_AUTOCONF,
201 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
202 .scbrr_algo_id = SCBRR_ALGO_2,
199 .type = PORT_SCIF, 203 .type = PORT_SCIF,
200 .irqs = { 81, 81, 81, 81 }, 204 .irqs = { 81, 81, 81, 81 },
201}; 205};
@@ -211,6 +215,8 @@ static struct platform_device scif1_device = {
211static struct plat_sci_port scif2_platform_data = { 215static struct plat_sci_port scif2_platform_data = {
212 .mapbase = 0xffe20000, 216 .mapbase = 0xffe20000,
213 .flags = UPF_BOOT_AUTOCONF, 217 .flags = UPF_BOOT_AUTOCONF,
218 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
219 .scbrr_algo_id = SCBRR_ALGO_2,
214 .type = PORT_SCIF, 220 .type = PORT_SCIF,
215 .irqs = { 82, 82, 82, 82 }, 221 .irqs = { 82, 82, 82, 82 },
216}; 222};
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index d7641221ee42..072382280f96 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -24,6 +24,8 @@
24static struct plat_sci_port scif0_platform_data = { 24static struct plat_sci_port scif0_platform_data = {
25 .mapbase = 0xffe00000, 25 .mapbase = 0xffe00000,
26 .flags = UPF_BOOT_AUTOCONF, 26 .flags = UPF_BOOT_AUTOCONF,
27 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
28 .scbrr_algo_id = SCBRR_ALGO_2,
27 .type = PORT_SCIF, 29 .type = PORT_SCIF,
28 .irqs = { 80, 80, 80, 80 }, 30 .irqs = { 80, 80, 80, 80 },
29}; 31};
@@ -39,6 +41,8 @@ static struct platform_device scif0_device = {
39static struct plat_sci_port scif1_platform_data = { 41static struct plat_sci_port scif1_platform_data = {
40 .mapbase = 0xffe10000, 42 .mapbase = 0xffe10000,
41 .flags = UPF_BOOT_AUTOCONF, 43 .flags = UPF_BOOT_AUTOCONF,
44 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
45 .scbrr_algo_id = SCBRR_ALGO_2,
42 .type = PORT_SCIF, 46 .type = PORT_SCIF,
43 .irqs = { 81, 81, 81, 81 }, 47 .irqs = { 81, 81, 81, 81 },
44}; 48};
@@ -54,6 +58,8 @@ static struct platform_device scif1_device = {
54static struct plat_sci_port scif2_platform_data = { 58static struct plat_sci_port scif2_platform_data = {
55 .mapbase = 0xffe20000, 59 .mapbase = 0xffe20000,
56 .flags = UPF_BOOT_AUTOCONF, 60 .flags = UPF_BOOT_AUTOCONF,
61 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
62 .scbrr_algo_id = SCBRR_ALGO_2,
57 .type = PORT_SCIF, 63 .type = PORT_SCIF,
58 .irqs = { 82, 82, 82, 82 }, 64 .irqs = { 82, 82, 82, 82 },
59}; 65};
@@ -69,6 +75,8 @@ static struct platform_device scif2_device = {
69static struct plat_sci_port scif3_platform_data = { 75static struct plat_sci_port scif3_platform_data = {
70 .mapbase = 0xa4e30000, 76 .mapbase = 0xa4e30000,
71 .flags = UPF_BOOT_AUTOCONF, 77 .flags = UPF_BOOT_AUTOCONF,
78 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
79 .scbrr_algo_id = SCBRR_ALGO_3,
72 .type = PORT_SCIFA, 80 .type = PORT_SCIFA,
73 .irqs = { 56, 56, 56, 56 }, 81 .irqs = { 56, 56, 56, 56 },
74}; 82};
@@ -84,6 +92,8 @@ static struct platform_device scif3_device = {
84static struct plat_sci_port scif4_platform_data = { 92static struct plat_sci_port scif4_platform_data = {
85 .mapbase = 0xa4e40000, 93 .mapbase = 0xa4e40000,
86 .flags = UPF_BOOT_AUTOCONF, 94 .flags = UPF_BOOT_AUTOCONF,
95 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
96 .scbrr_algo_id = SCBRR_ALGO_3,
87 .type = PORT_SCIFA, 97 .type = PORT_SCIFA,
88 .irqs = { 88, 88, 88, 88 }, 98 .irqs = { 88, 88, 88, 88 },
89}; 99};
@@ -99,6 +109,8 @@ static struct platform_device scif4_device = {
99static struct plat_sci_port scif5_platform_data = { 109static struct plat_sci_port scif5_platform_data = {
100 .mapbase = 0xa4e50000, 110 .mapbase = 0xa4e50000,
101 .flags = UPF_BOOT_AUTOCONF, 111 .flags = UPF_BOOT_AUTOCONF,
112 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
113 .scbrr_algo_id = SCBRR_ALGO_3,
102 .type = PORT_SCIFA, 114 .type = PORT_SCIFA,
103 .irqs = { 109, 109, 109, 109 }, 115 .irqs = { 109, 109, 109, 109 },
104}; 116};
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index c598a7f61b7f..0333fe9e3881 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -257,6 +257,8 @@ static struct platform_device dma1_device = {
257static struct plat_sci_port scif0_platform_data = { 257static struct plat_sci_port scif0_platform_data = {
258 .mapbase = 0xffe00000, 258 .mapbase = 0xffe00000,
259 .flags = UPF_BOOT_AUTOCONF, 259 .flags = UPF_BOOT_AUTOCONF,
260 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
261 .scbrr_algo_id = SCBRR_ALGO_2,
260 .type = PORT_SCIF, 262 .type = PORT_SCIF,
261 .irqs = { 80, 80, 80, 80 }, 263 .irqs = { 80, 80, 80, 80 },
262}; 264};
@@ -272,6 +274,8 @@ static struct platform_device scif0_device = {
272static struct plat_sci_port scif1_platform_data = { 274static struct plat_sci_port scif1_platform_data = {
273 .mapbase = 0xffe10000, 275 .mapbase = 0xffe10000,
274 .flags = UPF_BOOT_AUTOCONF, 276 .flags = UPF_BOOT_AUTOCONF,
277 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
278 .scbrr_algo_id = SCBRR_ALGO_2,
275 .type = PORT_SCIF, 279 .type = PORT_SCIF,
276 .irqs = { 81, 81, 81, 81 }, 280 .irqs = { 81, 81, 81, 81 },
277}; 281};
@@ -287,6 +291,8 @@ static struct platform_device scif1_device = {
287static struct plat_sci_port scif2_platform_data = { 291static struct plat_sci_port scif2_platform_data = {
288 .mapbase = 0xffe20000, 292 .mapbase = 0xffe20000,
289 .flags = UPF_BOOT_AUTOCONF, 293 .flags = UPF_BOOT_AUTOCONF,
294 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
295 .scbrr_algo_id = SCBRR_ALGO_2,
290 .type = PORT_SCIF, 296 .type = PORT_SCIF,
291 .irqs = { 82, 82, 82, 82 }, 297 .irqs = { 82, 82, 82, 82 },
292}; 298};
@@ -302,6 +308,8 @@ static struct platform_device scif2_device = {
302static struct plat_sci_port scif3_platform_data = { 308static struct plat_sci_port scif3_platform_data = {
303 .mapbase = 0xa4e30000, 309 .mapbase = 0xa4e30000,
304 .flags = UPF_BOOT_AUTOCONF, 310 .flags = UPF_BOOT_AUTOCONF,
311 .scscr = SCSCR_RE | SCSCR_TE,
312 .scbrr_algo_id = SCBRR_ALGO_3,
305 .type = PORT_SCIFA, 313 .type = PORT_SCIFA,
306 .irqs = { 56, 56, 56, 56 }, 314 .irqs = { 56, 56, 56, 56 },
307}; 315};
@@ -317,6 +325,8 @@ static struct platform_device scif3_device = {
317static struct plat_sci_port scif4_platform_data = { 325static struct plat_sci_port scif4_platform_data = {
318 .mapbase = 0xa4e40000, 326 .mapbase = 0xa4e40000,
319 .flags = UPF_BOOT_AUTOCONF, 327 .flags = UPF_BOOT_AUTOCONF,
328 .scscr = SCSCR_RE | SCSCR_TE,
329 .scbrr_algo_id = SCBRR_ALGO_3,
320 .type = PORT_SCIFA, 330 .type = PORT_SCIFA,
321 .irqs = { 88, 88, 88, 88 }, 331 .irqs = { 88, 88, 88, 88 },
322}; 332};
@@ -332,6 +342,8 @@ static struct platform_device scif4_device = {
332static struct plat_sci_port scif5_platform_data = { 342static struct plat_sci_port scif5_platform_data = {
333 .mapbase = 0xa4e50000, 343 .mapbase = 0xa4e50000,
334 .flags = UPF_BOOT_AUTOCONF, 344 .flags = UPF_BOOT_AUTOCONF,
345 .scscr = SCSCR_RE | SCSCR_TE,
346 .scbrr_algo_id = SCBRR_ALGO_3,
335 .type = PORT_SCIFA, 347 .type = PORT_SCIFA,
336 .irqs = { 109, 109, 109, 109 }, 348 .irqs = { 109, 109, 109, 109 },
337}; 349};
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
index 749c6388d5a5..9c1de2633ac3 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
@@ -20,6 +20,8 @@
20static struct plat_sci_port scif2_platform_data = { 20static struct plat_sci_port scif2_platform_data = {
21 .mapbase = 0xfe4b0000, /* SCIF2 */ 21 .mapbase = 0xfe4b0000, /* SCIF2 */
22 .flags = UPF_BOOT_AUTOCONF, 22 .flags = UPF_BOOT_AUTOCONF,
23 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
24 .scbrr_algo_id = SCBRR_ALGO_2,
23 .type = PORT_SCIF, 25 .type = PORT_SCIF,
24 .irqs = { 40, 40, 40, 40 }, 26 .irqs = { 40, 40, 40, 40 },
25}; 27};
@@ -35,6 +37,8 @@ static struct platform_device scif2_device = {
35static struct plat_sci_port scif3_platform_data = { 37static struct plat_sci_port scif3_platform_data = {
36 .mapbase = 0xfe4c0000, /* SCIF3 */ 38 .mapbase = 0xfe4c0000, /* SCIF3 */
37 .flags = UPF_BOOT_AUTOCONF, 39 .flags = UPF_BOOT_AUTOCONF,
40 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
41 .scbrr_algo_id = SCBRR_ALGO_2,
38 .type = PORT_SCIF, 42 .type = PORT_SCIF,
39 .irqs = { 76, 76, 76, 76 }, 43 .irqs = { 76, 76, 76, 76 },
40}; 44};
@@ -50,6 +54,8 @@ static struct platform_device scif3_device = {
50static struct plat_sci_port scif4_platform_data = { 54static struct plat_sci_port scif4_platform_data = {
51 .mapbase = 0xfe4d0000, /* SCIF4 */ 55 .mapbase = 0xfe4d0000, /* SCIF4 */
52 .flags = UPF_BOOT_AUTOCONF, 56 .flags = UPF_BOOT_AUTOCONF,
57 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
58 .scbrr_algo_id = SCBRR_ALGO_2,
53 .type = PORT_SCIF, 59 .type = PORT_SCIF,
54 .irqs = { 104, 104, 104, 104 }, 60 .irqs = { 104, 104, 104, 104 },
55}; 61};
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
index 5b5f6b005fc5..593eca6509b5 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
@@ -19,6 +19,8 @@
19static struct plat_sci_port scif0_platform_data = { 19static struct plat_sci_port scif0_platform_data = {
20 .mapbase = 0xffe00000, 20 .mapbase = 0xffe00000,
21 .flags = UPF_BOOT_AUTOCONF, 21 .flags = UPF_BOOT_AUTOCONF,
22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
23 .scbrr_algo_id = SCBRR_ALGO_2,
22 .type = PORT_SCIF, 24 .type = PORT_SCIF,
23 .irqs = { 40, 40, 40, 40 }, 25 .irqs = { 40, 40, 40, 40 },
24}; 26};
@@ -34,6 +36,8 @@ static struct platform_device scif0_device = {
34static struct plat_sci_port scif1_platform_data = { 36static struct plat_sci_port scif1_platform_data = {
35 .mapbase = 0xffe08000, 37 .mapbase = 0xffe08000,
36 .flags = UPF_BOOT_AUTOCONF, 38 .flags = UPF_BOOT_AUTOCONF,
39 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
40 .scbrr_algo_id = SCBRR_ALGO_2,
37 .type = PORT_SCIF, 41 .type = PORT_SCIF,
38 .irqs = { 76, 76, 76, 76 }, 42 .irqs = { 76, 76, 76, 76 },
39}; 43};
@@ -49,6 +53,8 @@ static struct platform_device scif1_device = {
49static struct plat_sci_port scif2_platform_data = { 53static struct plat_sci_port scif2_platform_data = {
50 .mapbase = 0xffe10000, 54 .mapbase = 0xffe10000,
51 .flags = UPF_BOOT_AUTOCONF, 55 .flags = UPF_BOOT_AUTOCONF,
56 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
57 .scbrr_algo_id = SCBRR_ALGO_2,
52 .type = PORT_SCIF, 58 .type = PORT_SCIF,
53 .irqs = { 104, 104, 104, 104 }, 59 .irqs = { 104, 104, 104, 104 },
54}; 60};
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
index 7270d7fd6761..2c6aa22cf5f6 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
@@ -17,6 +17,8 @@
17static struct plat_sci_port scif0_platform_data = { 17static struct plat_sci_port scif0_platform_data = {
18 .mapbase = 0xff923000, 18 .mapbase = 0xff923000,
19 .flags = UPF_BOOT_AUTOCONF, 19 .flags = UPF_BOOT_AUTOCONF,
20 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
21 .scbrr_algo_id = SCBRR_ALGO_2,
20 .type = PORT_SCIF, 22 .type = PORT_SCIF,
21 .irqs = { 61, 61, 61, 61 }, 23 .irqs = { 61, 61, 61, 61 },
22}; 24};
@@ -32,6 +34,8 @@ static struct platform_device scif0_device = {
32static struct plat_sci_port scif1_platform_data = { 34static struct plat_sci_port scif1_platform_data = {
33 .mapbase = 0xff924000, 35 .mapbase = 0xff924000,
34 .flags = UPF_BOOT_AUTOCONF, 36 .flags = UPF_BOOT_AUTOCONF,
37 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
38 .scbrr_algo_id = SCBRR_ALGO_2,
35 .type = PORT_SCIF, 39 .type = PORT_SCIF,
36 .irqs = { 62, 62, 62, 62 }, 40 .irqs = { 62, 62, 62, 62 },
37}; 41};
@@ -47,6 +51,8 @@ static struct platform_device scif1_device = {
47static struct plat_sci_port scif2_platform_data = { 51static struct plat_sci_port scif2_platform_data = {
48 .mapbase = 0xff925000, 52 .mapbase = 0xff925000,
49 .flags = UPF_BOOT_AUTOCONF, 53 .flags = UPF_BOOT_AUTOCONF,
54 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
55 .scbrr_algo_id = SCBRR_ALGO_2,
50 .type = PORT_SCIF, 56 .type = PORT_SCIF,
51 .irqs = { 63, 63, 63, 63 }, 57 .irqs = { 63, 63, 63, 63 },
52}; 58};
@@ -62,6 +68,8 @@ static struct platform_device scif2_device = {
62static struct plat_sci_port scif3_platform_data = { 68static struct plat_sci_port scif3_platform_data = {
63 .mapbase = 0xff926000, 69 .mapbase = 0xff926000,
64 .flags = UPF_BOOT_AUTOCONF, 70 .flags = UPF_BOOT_AUTOCONF,
71 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
72 .scbrr_algo_id = SCBRR_ALGO_2,
65 .type = PORT_SCIF, 73 .type = PORT_SCIF,
66 .irqs = { 64, 64, 64, 64 }, 74 .irqs = { 64, 64, 64, 64 },
67}; 75};
@@ -77,6 +85,8 @@ static struct platform_device scif3_device = {
77static struct plat_sci_port scif4_platform_data = { 85static struct plat_sci_port scif4_platform_data = {
78 .mapbase = 0xff927000, 86 .mapbase = 0xff927000,
79 .flags = UPF_BOOT_AUTOCONF, 87 .flags = UPF_BOOT_AUTOCONF,
88 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
89 .scbrr_algo_id = SCBRR_ALGO_2,
80 .type = PORT_SCIF, 90 .type = PORT_SCIF,
81 .irqs = { 65, 65, 65, 65 }, 91 .irqs = { 65, 65, 65, 65 },
82}; 92};
@@ -92,6 +102,8 @@ static struct platform_device scif4_device = {
92static struct plat_sci_port scif5_platform_data = { 102static struct plat_sci_port scif5_platform_data = {
93 .mapbase = 0xff928000, 103 .mapbase = 0xff928000,
94 .flags = UPF_BOOT_AUTOCONF, 104 .flags = UPF_BOOT_AUTOCONF,
105 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
106 .scbrr_algo_id = SCBRR_ALGO_2,
95 .type = PORT_SCIF, 107 .type = PORT_SCIF,
96 .irqs = { 66, 66, 66, 66 }, 108 .irqs = { 66, 66, 66, 66 },
97}; 109};
@@ -107,6 +119,8 @@ static struct platform_device scif5_device = {
107static struct plat_sci_port scif6_platform_data = { 119static struct plat_sci_port scif6_platform_data = {
108 .mapbase = 0xff929000, 120 .mapbase = 0xff929000,
109 .flags = UPF_BOOT_AUTOCONF, 121 .flags = UPF_BOOT_AUTOCONF,
122 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
123 .scbrr_algo_id = SCBRR_ALGO_2,
110 .type = PORT_SCIF, 124 .type = PORT_SCIF,
111 .irqs = { 67, 67, 67, 67 }, 125 .irqs = { 67, 67, 67, 67 },
112}; 126};
@@ -122,6 +136,8 @@ static struct platform_device scif6_device = {
122static struct plat_sci_port scif7_platform_data = { 136static struct plat_sci_port scif7_platform_data = {
123 .mapbase = 0xff92a000, 137 .mapbase = 0xff92a000,
124 .flags = UPF_BOOT_AUTOCONF, 138 .flags = UPF_BOOT_AUTOCONF,
139 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
140 .scbrr_algo_id = SCBRR_ALGO_2,
125 .type = PORT_SCIF, 141 .type = PORT_SCIF,
126 .irqs = { 68, 68, 68, 68 }, 142 .irqs = { 68, 68, 68, 68 },
127}; 143};
@@ -137,6 +153,8 @@ static struct platform_device scif7_device = {
137static struct plat_sci_port scif8_platform_data = { 153static struct plat_sci_port scif8_platform_data = {
138 .mapbase = 0xff92b000, 154 .mapbase = 0xff92b000,
139 .flags = UPF_BOOT_AUTOCONF, 155 .flags = UPF_BOOT_AUTOCONF,
156 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
157 .scbrr_algo_id = SCBRR_ALGO_2,
140 .type = PORT_SCIF, 158 .type = PORT_SCIF,
141 .irqs = { 69, 69, 69, 69 }, 159 .irqs = { 69, 69, 69, 69 },
142}; 160};
@@ -152,6 +170,8 @@ static struct platform_device scif8_device = {
152static struct plat_sci_port scif9_platform_data = { 170static struct plat_sci_port scif9_platform_data = {
153 .mapbase = 0xff92c000, 171 .mapbase = 0xff92c000,
154 .flags = UPF_BOOT_AUTOCONF, 172 .flags = UPF_BOOT_AUTOCONF,
173 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
174 .scbrr_algo_id = SCBRR_ALGO_2,
155 .type = PORT_SCIF, 175 .type = PORT_SCIF,
156 .irqs = { 70, 70, 70, 70 }, 176 .irqs = { 70, 70, 70, 70 },
157}; 177};
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index 0f414864f76b..08add7fa6849 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -20,6 +20,8 @@
20static struct plat_sci_port scif0_platform_data = { 20static struct plat_sci_port scif0_platform_data = {
21 .mapbase = 0xffe00000, 21 .mapbase = 0xffe00000,
22 .flags = UPF_BOOT_AUTOCONF, 22 .flags = UPF_BOOT_AUTOCONF,
23 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
24 .scbrr_algo_id = SCBRR_ALGO_1,
23 .type = PORT_SCIF, 25 .type = PORT_SCIF,
24 .irqs = { 40, 40, 40, 40 }, 26 .irqs = { 40, 40, 40, 40 },
25}; 27};
@@ -35,6 +37,8 @@ static struct platform_device scif0_device = {
35static struct plat_sci_port scif1_platform_data = { 37static struct plat_sci_port scif1_platform_data = {
36 .mapbase = 0xffe10000, 38 .mapbase = 0xffe10000,
37 .flags = UPF_BOOT_AUTOCONF, 39 .flags = UPF_BOOT_AUTOCONF,
40 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
41 .scbrr_algo_id = SCBRR_ALGO_1,
38 .type = PORT_SCIF, 42 .type = PORT_SCIF,
39 .irqs = { 76, 76, 76, 76 }, 43 .irqs = { 76, 76, 76, 76 },
40}; 44};
@@ -379,6 +383,7 @@ static int __init sh7780_devices_setup(void)
379 ARRAY_SIZE(sh7780_devices)); 383 ARRAY_SIZE(sh7780_devices));
380} 384}
381arch_initcall(sh7780_devices_setup); 385arch_initcall(sh7780_devices_setup);
386
382static struct platform_device *sh7780_early_devices[] __initdata = { 387static struct platform_device *sh7780_early_devices[] __initdata = {
383 &scif0_device, 388 &scif0_device,
384 &scif1_device, 389 &scif1_device,
@@ -392,6 +397,13 @@ static struct platform_device *sh7780_early_devices[] __initdata = {
392 397
393void __init plat_early_device_setup(void) 398void __init plat_early_device_setup(void)
394{ 399{
400 if (mach_is_sh2007()) {
401 scif0_platform_data.scscr &= ~SCSCR_CKE1;
402 scif0_platform_data.scbrr_algo_id = SCBRR_ALGO_2;
403 scif1_platform_data.scscr &= ~SCSCR_CKE1;
404 scif1_platform_data.scbrr_algo_id = SCBRR_ALGO_2;
405 }
406
395 early_platform_add_devices(sh7780_early_devices, 407 early_platform_add_devices(sh7780_early_devices,
396 ARRAY_SIZE(sh7780_early_devices)); 408 ARRAY_SIZE(sh7780_early_devices));
397} 409}
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index c9a572bc6dc8..18d8fc136fb2 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -23,6 +23,8 @@
23static struct plat_sci_port scif0_platform_data = { 23static struct plat_sci_port scif0_platform_data = {
24 .mapbase = 0xffea0000, 24 .mapbase = 0xffea0000,
25 .flags = UPF_BOOT_AUTOCONF, 25 .flags = UPF_BOOT_AUTOCONF,
26 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
27 .scbrr_algo_id = SCBRR_ALGO_1,
26 .type = PORT_SCIF, 28 .type = PORT_SCIF,
27 .irqs = { 40, 40, 40, 40 }, 29 .irqs = { 40, 40, 40, 40 },
28}; 30};
@@ -38,6 +40,8 @@ static struct platform_device scif0_device = {
38static struct plat_sci_port scif1_platform_data = { 40static struct plat_sci_port scif1_platform_data = {
39 .mapbase = 0xffeb0000, 41 .mapbase = 0xffeb0000,
40 .flags = UPF_BOOT_AUTOCONF, 42 .flags = UPF_BOOT_AUTOCONF,
43 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
44 .scbrr_algo_id = SCBRR_ALGO_1,
41 .type = PORT_SCIF, 45 .type = PORT_SCIF,
42 .irqs = { 44, 44, 44, 44 }, 46 .irqs = { 44, 44, 44, 44 },
43}; 47};
@@ -53,6 +57,8 @@ static struct platform_device scif1_device = {
53static struct plat_sci_port scif2_platform_data = { 57static struct plat_sci_port scif2_platform_data = {
54 .mapbase = 0xffec0000, 58 .mapbase = 0xffec0000,
55 .flags = UPF_BOOT_AUTOCONF, 59 .flags = UPF_BOOT_AUTOCONF,
60 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
61 .scbrr_algo_id = SCBRR_ALGO_1,
56 .type = PORT_SCIF, 62 .type = PORT_SCIF,
57 .irqs = { 60, 60, 60, 60 }, 63 .irqs = { 60, 60, 60, 60 },
58}; 64};
@@ -68,6 +74,8 @@ static struct platform_device scif2_device = {
68static struct plat_sci_port scif3_platform_data = { 74static struct plat_sci_port scif3_platform_data = {
69 .mapbase = 0xffed0000, 75 .mapbase = 0xffed0000,
70 .flags = UPF_BOOT_AUTOCONF, 76 .flags = UPF_BOOT_AUTOCONF,
77 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
78 .scbrr_algo_id = SCBRR_ALGO_1,
71 .type = PORT_SCIF, 79 .type = PORT_SCIF,
72 .irqs = { 61, 61, 61, 61 }, 80 .irqs = { 61, 61, 61, 61 },
73}; 81};
@@ -83,6 +91,8 @@ static struct platform_device scif3_device = {
83static struct plat_sci_port scif4_platform_data = { 91static struct plat_sci_port scif4_platform_data = {
84 .mapbase = 0xffee0000, 92 .mapbase = 0xffee0000,
85 .flags = UPF_BOOT_AUTOCONF, 93 .flags = UPF_BOOT_AUTOCONF,
94 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
95 .scbrr_algo_id = SCBRR_ALGO_1,
86 .type = PORT_SCIF, 96 .type = PORT_SCIF,
87 .irqs = { 62, 62, 62, 62 }, 97 .irqs = { 62, 62, 62, 62 },
88}; 98};
@@ -98,6 +108,8 @@ static struct platform_device scif4_device = {
98static struct plat_sci_port scif5_platform_data = { 108static struct plat_sci_port scif5_platform_data = {
99 .mapbase = 0xffef0000, 109 .mapbase = 0xffef0000,
100 .flags = UPF_BOOT_AUTOCONF, 110 .flags = UPF_BOOT_AUTOCONF,
111 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
112 .scbrr_algo_id = SCBRR_ALGO_1,
101 .type = PORT_SCIF, 113 .type = PORT_SCIF,
102 .irqs = { 63, 63, 63, 63 }, 114 .irqs = { 63, 63, 63, 63 },
103}; 115};
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
index 0170dbda1d00..1656b8c91faf 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -29,6 +29,8 @@
29static struct plat_sci_port scif0_platform_data = { 29static struct plat_sci_port scif0_platform_data = {
30 .mapbase = 0xffea0000, 30 .mapbase = 0xffea0000,
31 .flags = UPF_BOOT_AUTOCONF, 31 .flags = UPF_BOOT_AUTOCONF,
32 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
33 .scbrr_algo_id = SCBRR_ALGO_1,
32 .type = PORT_SCIF, 34 .type = PORT_SCIF,
33 .irqs = { 40, 41, 43, 42 }, 35 .irqs = { 40, 41, 43, 42 },
34}; 36};
@@ -47,6 +49,8 @@ static struct platform_device scif0_device = {
47static struct plat_sci_port scif1_platform_data = { 49static struct plat_sci_port scif1_platform_data = {
48 .mapbase = 0xffeb0000, 50 .mapbase = 0xffeb0000,
49 .flags = UPF_BOOT_AUTOCONF, 51 .flags = UPF_BOOT_AUTOCONF,
52 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
53 .scbrr_algo_id = SCBRR_ALGO_1,
50 .type = PORT_SCIF, 54 .type = PORT_SCIF,
51 .irqs = { 44, 44, 44, 44 }, 55 .irqs = { 44, 44, 44, 44 },
52}; 56};
@@ -62,6 +66,8 @@ static struct platform_device scif1_device = {
62static struct plat_sci_port scif2_platform_data = { 66static struct plat_sci_port scif2_platform_data = {
63 .mapbase = 0xffec0000, 67 .mapbase = 0xffec0000,
64 .flags = UPF_BOOT_AUTOCONF, 68 .flags = UPF_BOOT_AUTOCONF,
69 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
70 .scbrr_algo_id = SCBRR_ALGO_1,
65 .type = PORT_SCIF, 71 .type = PORT_SCIF,
66 .irqs = { 50, 50, 50, 50 }, 72 .irqs = { 50, 50, 50, 50 },
67}; 73};
@@ -77,6 +83,8 @@ static struct platform_device scif2_device = {
77static struct plat_sci_port scif3_platform_data = { 83static struct plat_sci_port scif3_platform_data = {
78 .mapbase = 0xffed0000, 84 .mapbase = 0xffed0000,
79 .flags = UPF_BOOT_AUTOCONF, 85 .flags = UPF_BOOT_AUTOCONF,
86 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
87 .scbrr_algo_id = SCBRR_ALGO_1,
80 .type = PORT_SCIF, 88 .type = PORT_SCIF,
81 .irqs = { 51, 51, 51, 51 }, 89 .irqs = { 51, 51, 51, 51 },
82}; 90};
@@ -92,6 +100,8 @@ static struct platform_device scif3_device = {
92static struct plat_sci_port scif4_platform_data = { 100static struct plat_sci_port scif4_platform_data = {
93 .mapbase = 0xffee0000, 101 .mapbase = 0xffee0000,
94 .flags = UPF_BOOT_AUTOCONF, 102 .flags = UPF_BOOT_AUTOCONF,
103 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
104 .scbrr_algo_id = SCBRR_ALGO_1,
95 .type = PORT_SCIF, 105 .type = PORT_SCIF,
96 .irqs = { 52, 52, 52, 52 }, 106 .irqs = { 52, 52, 52, 52 },
97}; 107};
@@ -107,6 +117,8 @@ static struct platform_device scif4_device = {
107static struct plat_sci_port scif5_platform_data = { 117static struct plat_sci_port scif5_platform_data = {
108 .mapbase = 0xffef0000, 118 .mapbase = 0xffef0000,
109 .flags = UPF_BOOT_AUTOCONF, 119 .flags = UPF_BOOT_AUTOCONF,
120 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
121 .scbrr_algo_id = SCBRR_ALGO_1,
110 .type = PORT_SCIF, 122 .type = PORT_SCIF,
111 .irqs = { 53, 53, 53, 53 }, 123 .irqs = { 53, 53, 53, 53 },
112}; 124};
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
index 013f0b144489..bb208806dc1a 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
@@ -29,6 +29,8 @@
29static struct plat_sci_port scif0_platform_data = { 29static struct plat_sci_port scif0_platform_data = {
30 .mapbase = 0xffc30000, 30 .mapbase = 0xffc30000,
31 .flags = UPF_BOOT_AUTOCONF, 31 .flags = UPF_BOOT_AUTOCONF,
32 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
33 .scbrr_algo_id = SCBRR_ALGO_2,
32 .type = PORT_SCIF, 34 .type = PORT_SCIF,
33 .irqs = { 40, 41, 43, 42 }, 35 .irqs = { 40, 41, 43, 42 },
34}; 36};
@@ -44,6 +46,8 @@ static struct platform_device scif0_device = {
44static struct plat_sci_port scif1_platform_data = { 46static struct plat_sci_port scif1_platform_data = {
45 .mapbase = 0xffc40000, 47 .mapbase = 0xffc40000,
46 .flags = UPF_BOOT_AUTOCONF, 48 .flags = UPF_BOOT_AUTOCONF,
49 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
50 .scbrr_algo_id = SCBRR_ALGO_2,
47 .type = PORT_SCIF, 51 .type = PORT_SCIF,
48 .irqs = { 44, 45, 47, 46 }, 52 .irqs = { 44, 45, 47, 46 },
49}; 53};
@@ -59,6 +63,8 @@ static struct platform_device scif1_device = {
59static struct plat_sci_port scif2_platform_data = { 63static struct plat_sci_port scif2_platform_data = {
60 .mapbase = 0xffc60000, 64 .mapbase = 0xffc60000,
61 .flags = UPF_BOOT_AUTOCONF, 65 .flags = UPF_BOOT_AUTOCONF,
66 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
67 .scbrr_algo_id = SCBRR_ALGO_2,
62 .type = PORT_SCIF, 68 .type = PORT_SCIF,
63 .irqs = { 52, 53, 55, 54 }, 69 .irqs = { 52, 53, 55, 54 },
64}; 70};
diff --git a/arch/sh/kernel/cpu/sh5/setup-sh5.c b/arch/sh/kernel/cpu/sh5/setup-sh5.c
index d910666142b1..18419f1de963 100644
--- a/arch/sh/kernel/cpu/sh5/setup-sh5.c
+++ b/arch/sh/kernel/cpu/sh5/setup-sh5.c
@@ -19,6 +19,8 @@
19static struct plat_sci_port scif0_platform_data = { 19static struct plat_sci_port scif0_platform_data = {
20 .mapbase = PHYS_PERIPHERAL_BLOCK + 0x01030000, 20 .mapbase = PHYS_PERIPHERAL_BLOCK + 0x01030000,
21 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, 21 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
23 .scbrr_algo_id = SCBRR_ALGO_2,
22 .type = PORT_SCIF, 24 .type = PORT_SCIF,
23 .irqs = { 39, 40, 42, 0 }, 25 .irqs = { 39, 40, 42, 0 },
24}; 26};
diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c
index c291b3add1d2..251c08c55ae0 100644
--- a/drivers/serial/sh-sci.c
+++ b/drivers/serial/sh-sci.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 * 5 *
6 * Copyright (C) 2002 - 2008 Paul Mundt 6 * Copyright (C) 2002 - 2011 Paul Mundt
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 * 8 *
9 * based off of the old drivers/char/sh-sci.c by: 9 * based off of the old drivers/char/sh-sci.c by:
@@ -81,14 +81,22 @@ struct sci_port {
81 struct timer_list break_timer; 81 struct timer_list break_timer;
82 int break_flag; 82 int break_flag;
83 83
84 /* SCSCR initialization */
85 unsigned int scscr;
86
87 /* SCBRR calculation algo */
88 unsigned int scbrr_algo_id;
89
84 /* Interface clock */ 90 /* Interface clock */
85 struct clk *iclk; 91 struct clk *iclk;
86 /* Function clock */ 92 /* Function clock */
87 struct clk *fclk; 93 struct clk *fclk;
88 94
89 struct list_head node; 95 struct list_head node;
96
90 struct dma_chan *chan_tx; 97 struct dma_chan *chan_tx;
91 struct dma_chan *chan_rx; 98 struct dma_chan *chan_rx;
99
92#ifdef CONFIG_SERIAL_SH_SCI_DMA 100#ifdef CONFIG_SERIAL_SH_SCI_DMA
93 struct device *dma_dev; 101 struct device *dma_dev;
94 unsigned int slave_tx; 102 unsigned int slave_tx;
@@ -415,9 +423,9 @@ static void sci_transmit_chars(struct uart_port *port)
415 if (!(status & SCxSR_TDxE(port))) { 423 if (!(status & SCxSR_TDxE(port))) {
416 ctrl = sci_in(port, SCSCR); 424 ctrl = sci_in(port, SCSCR);
417 if (uart_circ_empty(xmit)) 425 if (uart_circ_empty(xmit))
418 ctrl &= ~SCI_CTRL_FLAGS_TIE; 426 ctrl &= ~SCSCR_TIE;
419 else 427 else
420 ctrl |= SCI_CTRL_FLAGS_TIE; 428 ctrl |= SCSCR_TIE;
421 sci_out(port, SCSCR, ctrl); 429 sci_out(port, SCSCR, ctrl);
422 return; 430 return;
423 } 431 }
@@ -459,7 +467,7 @@ static void sci_transmit_chars(struct uart_port *port)
459 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); 467 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
460 } 468 }
461 469
462 ctrl |= SCI_CTRL_FLAGS_TIE; 470 ctrl |= SCSCR_TIE;
463 sci_out(port, SCSCR, ctrl); 471 sci_out(port, SCSCR, ctrl);
464 } 472 }
465} 473}
@@ -708,7 +716,7 @@ static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
708 disable_irq_nosync(irq); 716 disable_irq_nosync(irq);
709 scr |= 0x4000; 717 scr |= 0x4000;
710 } else { 718 } else {
711 scr &= ~SCI_CTRL_FLAGS_RIE; 719 scr &= ~SCSCR_RIE;
712 } 720 }
713 sci_out(port, SCSCR, scr); 721 sci_out(port, SCSCR, scr);
714 /* Clear current interrupt */ 722 /* Clear current interrupt */
@@ -777,6 +785,18 @@ static irqreturn_t sci_br_interrupt(int irq, void *ptr)
777 return IRQ_HANDLED; 785 return IRQ_HANDLED;
778} 786}
779 787
788static inline unsigned long port_rx_irq_mask(struct uart_port *port)
789{
790 /*
791 * Not all ports (such as SCIFA) will support REIE. Rather than
792 * special-casing the port type, we check the port initialization
793 * IRQ enable mask to see whether the IRQ is desired at all. If
794 * it's unset, it's logically inferred that there's no point in
795 * testing for it.
796 */
797 return SCSCR_RIE | (to_sci_port(port)->scscr & SCSR_REIE);
798}
799
780static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 800static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
781{ 801{
782 unsigned short ssr_status, scr_status, err_enabled; 802 unsigned short ssr_status, scr_status, err_enabled;
@@ -786,22 +806,25 @@ static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
786 806
787 ssr_status = sci_in(port, SCxSR); 807 ssr_status = sci_in(port, SCxSR);
788 scr_status = sci_in(port, SCSCR); 808 scr_status = sci_in(port, SCSCR);
789 err_enabled = scr_status & (SCI_CTRL_FLAGS_REIE | SCI_CTRL_FLAGS_RIE); 809 err_enabled = scr_status & port_rx_irq_mask(port);
790 810
791 /* Tx Interrupt */ 811 /* Tx Interrupt */
792 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCI_CTRL_FLAGS_TIE) && 812 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
793 !s->chan_tx) 813 !s->chan_tx)
794 ret = sci_tx_interrupt(irq, ptr); 814 ret = sci_tx_interrupt(irq, ptr);
815
795 /* 816 /*
796 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 817 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
797 * DR flags 818 * DR flags
798 */ 819 */
799 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 820 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
800 (scr_status & SCI_CTRL_FLAGS_RIE)) 821 (scr_status & SCSCR_RIE))
801 ret = sci_rx_interrupt(irq, ptr); 822 ret = sci_rx_interrupt(irq, ptr);
823
802 /* Error Interrupt */ 824 /* Error Interrupt */
803 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 825 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
804 ret = sci_er_interrupt(irq, ptr); 826 ret = sci_er_interrupt(irq, ptr);
827
805 /* Break Interrupt */ 828 /* Break Interrupt */
806 if ((ssr_status & SCxSR_BRK(port)) && err_enabled) 829 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
807 ret = sci_br_interrupt(irq, ptr); 830 ret = sci_br_interrupt(irq, ptr);
@@ -951,7 +974,7 @@ static void sci_dma_tx_complete(void *arg)
951 schedule_work(&s->work_tx); 974 schedule_work(&s->work_tx);
952 } else if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 975 } else if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
953 u16 ctrl = sci_in(port, SCSCR); 976 u16 ctrl = sci_in(port, SCSCR);
954 sci_out(port, SCSCR, ctrl & ~SCI_CTRL_FLAGS_TIE); 977 sci_out(port, SCSCR, ctrl & ~SCSCR_TIE);
955 } 978 }
956 979
957 spin_unlock_irqrestore(&port->lock, flags); 980 spin_unlock_irqrestore(&port->lock, flags);
@@ -1214,14 +1237,16 @@ static void sci_start_tx(struct uart_port *port)
1214 if (new != scr) 1237 if (new != scr)
1215 sci_out(port, SCSCR, new); 1238 sci_out(port, SCSCR, new);
1216 } 1239 }
1240
1217 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && 1241 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1218 s->cookie_tx < 0) 1242 s->cookie_tx < 0)
1219 schedule_work(&s->work_tx); 1243 schedule_work(&s->work_tx);
1220#endif 1244#endif
1245
1221 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1246 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1222 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 1247 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1223 ctrl = sci_in(port, SCSCR); 1248 ctrl = sci_in(port, SCSCR);
1224 sci_out(port, SCSCR, ctrl | SCI_CTRL_FLAGS_TIE); 1249 sci_out(port, SCSCR, ctrl | SCSCR_TIE);
1225 } 1250 }
1226} 1251}
1227 1252
@@ -1231,20 +1256,24 @@ static void sci_stop_tx(struct uart_port *port)
1231 1256
1232 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 1257 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1233 ctrl = sci_in(port, SCSCR); 1258 ctrl = sci_in(port, SCSCR);
1259
1234 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1260 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1235 ctrl &= ~0x8000; 1261 ctrl &= ~0x8000;
1236 ctrl &= ~SCI_CTRL_FLAGS_TIE; 1262
1263 ctrl &= ~SCSCR_TIE;
1264
1237 sci_out(port, SCSCR, ctrl); 1265 sci_out(port, SCSCR, ctrl);
1238} 1266}
1239 1267
1240static void sci_start_rx(struct uart_port *port) 1268static void sci_start_rx(struct uart_port *port)
1241{ 1269{
1242 unsigned short ctrl = SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE; 1270 unsigned short ctrl;
1271
1272 ctrl = sci_in(port, SCSCR) | port_rx_irq_mask(port);
1243 1273
1244 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
1245 ctrl |= sci_in(port, SCSCR);
1246 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1274 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1247 ctrl &= ~0x4000; 1275 ctrl &= ~0x4000;
1276
1248 sci_out(port, SCSCR, ctrl); 1277 sci_out(port, SCSCR, ctrl);
1249} 1278}
1250 1279
@@ -1252,11 +1281,13 @@ static void sci_stop_rx(struct uart_port *port)
1252{ 1281{
1253 unsigned short ctrl; 1282 unsigned short ctrl;
1254 1283
1255 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
1256 ctrl = sci_in(port, SCSCR); 1284 ctrl = sci_in(port, SCSCR);
1285
1257 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1286 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1258 ctrl &= ~0x4000; 1287 ctrl &= ~0x4000;
1259 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE); 1288
1289 ctrl &= ~port_rx_irq_mask(port);
1290
1260 sci_out(port, SCSCR, ctrl); 1291 sci_out(port, SCSCR, ctrl);
1261} 1292}
1262 1293
@@ -1296,7 +1327,7 @@ static void rx_timer_fn(unsigned long arg)
1296 scr &= ~0x4000; 1327 scr &= ~0x4000;
1297 enable_irq(s->irqs[1]); 1328 enable_irq(s->irqs[1]);
1298 } 1329 }
1299 sci_out(port, SCSCR, scr | SCI_CTRL_FLAGS_RIE); 1330 sci_out(port, SCSCR, scr | SCSCR_RIE);
1300 dev_dbg(port->dev, "DMA Rx timed out\n"); 1331 dev_dbg(port->dev, "DMA Rx timed out\n");
1301 schedule_work(&s->work_rx); 1332 schedule_work(&s->work_rx);
1302} 1333}
@@ -1442,12 +1473,31 @@ static void sci_shutdown(struct uart_port *port)
1442 s->disable(port); 1473 s->disable(port);
1443} 1474}
1444 1475
1476static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
1477 unsigned long freq)
1478{
1479 switch (algo_id) {
1480 case SCBRR_ALGO_1:
1481 return ((freq + 16 * bps) / (16 * bps) - 1);
1482 case SCBRR_ALGO_2:
1483 return ((freq + 16 * bps) / (32 * bps) - 1);
1484 case SCBRR_ALGO_3:
1485 return (((freq * 2) + 16 * bps) / (16 * bps) - 1);
1486 case SCBRR_ALGO_4:
1487 return (((freq * 2) + 16 * bps) / (32 * bps) - 1);
1488 case SCBRR_ALGO_5:
1489 return (((freq * 1000 / 32) / bps) - 1);
1490 }
1491
1492 /* Warn, but use a safe default */
1493 WARN_ON(1);
1494 return ((freq + 16 * bps) / (32 * bps) - 1);
1495}
1496
1445static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 1497static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1446 struct ktermios *old) 1498 struct ktermios *old)
1447{ 1499{
1448#ifdef CONFIG_SERIAL_SH_SCI_DMA
1449 struct sci_port *s = to_sci_port(port); 1500 struct sci_port *s = to_sci_port(port);
1450#endif
1451 unsigned int status, baud, smr_val, max_baud; 1501 unsigned int status, baud, smr_val, max_baud;
1452 int t = -1; 1502 int t = -1;
1453 u16 scfcr = 0; 1503 u16 scfcr = 0;
@@ -1464,7 +1514,7 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1464 1514
1465 baud = uart_get_baud_rate(port, termios, old, 0, max_baud); 1515 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1466 if (likely(baud && port->uartclk)) 1516 if (likely(baud && port->uartclk))
1467 t = SCBRR_VALUE(baud, port->uartclk); 1517 t = sci_scbrr_calc(s->scbrr_algo_id, baud, port->uartclk);
1468 1518
1469 do { 1519 do {
1470 status = sci_in(port, SCxSR); 1520 status = sci_in(port, SCxSR);
@@ -1506,7 +1556,7 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1506 sci_init_pins(port, termios->c_cflag); 1556 sci_init_pins(port, termios->c_cflag);
1507 sci_out(port, SCFCR, scfcr | ((termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0)); 1557 sci_out(port, SCFCR, scfcr | ((termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0));
1508 1558
1509 sci_out(port, SCSCR, SCSCR_INIT(port)); 1559 sci_out(port, SCSCR, s->scscr);
1510 1560
1511#ifdef CONFIG_SERIAL_SH_SCI_DMA 1561#ifdef CONFIG_SERIAL_SH_SCI_DMA
1512 /* 1562 /*
@@ -1679,9 +1729,11 @@ static int __devinit sci_init_single(struct platform_device *dev,
1679 port->mapbase = p->mapbase; 1729 port->mapbase = p->mapbase;
1680 port->membase = p->membase; 1730 port->membase = p->membase;
1681 1731
1682 port->irq = p->irqs[SCIx_TXI_IRQ]; 1732 port->irq = p->irqs[SCIx_TXI_IRQ];
1683 port->flags = p->flags; 1733 port->flags = p->flags;
1684 sci_port->type = port->type = p->type; 1734 sci_port->type = port->type = p->type;
1735 sci_port->scscr = p->scscr;
1736 sci_port->scbrr_algo_id = p->scbrr_algo_id;
1685 1737
1686#ifdef CONFIG_SERIAL_SH_SCI_DMA 1738#ifdef CONFIG_SERIAL_SH_SCI_DMA
1687 sci_port->dma_dev = p->dma_dev; 1739 sci_port->dma_dev = p->dma_dev;
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index 4bc614e4221c..b223d6cbf33a 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -15,27 +15,17 @@
15 defined(CONFIG_CPU_SUBTYPE_SH7709) 15 defined(CONFIG_CPU_SUBTYPE_SH7709)
16# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ 16# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
17# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ 17# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
18# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
19#elif defined(CONFIG_CPU_SUBTYPE_SH7705) 18#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
20# define SCIF0 0xA4400000 19# define SCIF0 0xA4400000
21# define SCIF2 0xA4410000 20# define SCIF2 0xA4410000
22# define SCSMR_Ir 0xA44A0000
23# define IRDA_SCIF SCIF0
24# define SCPCR 0xA4000116 21# define SCPCR 0xA4000116
25# define SCPDR 0xA4000136 22# define SCPDR 0xA4000136
26
27/* Set the clock source,
28 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
29 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
30 */
31# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
32#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 23#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
33 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 24 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
34 defined(CONFIG_ARCH_SH73A0) || \ 25 defined(CONFIG_ARCH_SH73A0) || \
35 defined(CONFIG_ARCH_SH7367) || \ 26 defined(CONFIG_ARCH_SH7367) || \
36 defined(CONFIG_ARCH_SH7377) || \ 27 defined(CONFIG_ARCH_SH7377) || \
37 defined(CONFIG_ARCH_SH7372) 28 defined(CONFIG_ARCH_SH7372)
38# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
39# define PORT_PTCR 0xA405011EUL 29# define PORT_PTCR 0xA405011EUL
40# define PORT_PVCR 0xA4050122UL 30# define PORT_PVCR 0xA4050122UL
41# define SCIF_ORER 0x0200 /* overrun error bit */ 31# define SCIF_ORER 0x0200 /* overrun error bit */
@@ -43,7 +33,6 @@
43# define SCSPTR1 0xFFE0001C /* 8 bit SCIF */ 33# define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
44# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ 34# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
45# define SCIF_ORER 0x0001 /* overrun error bit */ 35# define SCIF_ORER 0x0001 /* overrun error bit */
46# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
47#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ 36#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
48 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ 37 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
49 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ 38 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
@@ -53,39 +42,31 @@
53# define SCSPTR1 0xffe0001c /* 8 bit SCI */ 42# define SCSPTR1 0xffe0001c /* 8 bit SCI */
54# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ 43# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
55# define SCIF_ORER 0x0001 /* overrun error bit */ 44# define SCIF_ORER 0x0001 /* overrun error bit */
56# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
57 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
58 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
59#elif defined(CONFIG_CPU_SUBTYPE_SH7760) 45#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
60# define SCSPTR0 0xfe600024 /* 16 bit SCIF */ 46# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
61# define SCSPTR1 0xfe610024 /* 16 bit SCIF */ 47# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
62# define SCSPTR2 0xfe620024 /* 16 bit SCIF */ 48# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
63# define SCIF_ORER 0x0001 /* overrun error bit */ 49# define SCIF_ORER 0x0001 /* overrun error bit */
64# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
65#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 50#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
66# define SCSPTR0 0xA4400000 /* 16 bit SCIF */ 51# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
67# define SCIF_ORER 0x0001 /* overrun error bit */ 52# define SCIF_ORER 0x0001 /* overrun error bit */
68# define PACR 0xa4050100 53# define PACR 0xa4050100
69# define PBCR 0xa4050102 54# define PBCR 0xa4050102
70# define SCSCR_INIT(port) 0x3B
71#elif defined(CONFIG_CPU_SUBTYPE_SH7343) 55#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
72# define SCSPTR0 0xffe00010 /* 16 bit SCIF */ 56# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
73# define SCSPTR1 0xffe10010 /* 16 bit SCIF */ 57# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
74# define SCSPTR2 0xffe20010 /* 16 bit SCIF */ 58# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
75# define SCSPTR3 0xffe30010 /* 16 bit SCIF */ 59# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
76# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
77#elif defined(CONFIG_CPU_SUBTYPE_SH7722) 60#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
78# define PADR 0xA4050120 61# define PADR 0xA4050120
79# define PSDR 0xA405013e 62# define PSDR 0xA405013e
80# define PWDR 0xA4050166 63# define PWDR 0xA4050166
81# define PSCR 0xA405011E 64# define PSCR 0xA405011E
82# define SCIF_ORER 0x0001 /* overrun error bit */ 65# define SCIF_ORER 0x0001 /* overrun error bit */
83# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
84#elif defined(CONFIG_CPU_SUBTYPE_SH7366) 66#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
85# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ 67# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
86# define SCSPTR0 SCPDR0 68# define SCSPTR0 SCPDR0
87# define SCIF_ORER 0x0001 /* overrun error bit */ 69# define SCIF_ORER 0x0001 /* overrun error bit */
88# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
89#elif defined(CONFIG_CPU_SUBTYPE_SH7723) 70#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
90# define SCSPTR0 0xa4050160 71# define SCSPTR0 0xa4050160
91# define SCSPTR1 0xa405013e 72# define SCSPTR1 0xa405013e
@@ -94,62 +75,38 @@
94# define SCSPTR4 0xa4050128 75# define SCSPTR4 0xa4050128
95# define SCSPTR5 0xa4050128 76# define SCSPTR5 0xa4050128
96# define SCIF_ORER 0x0001 /* overrun error bit */ 77# define SCIF_ORER 0x0001 /* overrun error bit */
97# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
98#elif defined(CONFIG_CPU_SUBTYPE_SH7724) 78#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
99# define SCIF_ORER 0x0001 /* overrun error bit */ 79# define SCIF_ORER 0x0001 /* overrun error bit */
100# define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \
101 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
102 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
103#elif defined(CONFIG_CPU_SUBTYPE_SH4_202) 80#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
104# define SCSPTR2 0xffe80020 /* 16 bit SCIF */ 81# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
105# define SCIF_ORER 0x0001 /* overrun error bit */ 82# define SCIF_ORER 0x0001 /* overrun error bit */
106# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
107#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) 83#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
108# define SCIF_BASE_ADDR 0x01030000
109# define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
110# define SCIF_PTR2_OFFS 0x0000020 84# define SCIF_PTR2_OFFS 0x0000020
111# define SCIF_LSR2_OFFS 0x0000024
112# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ 85# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
113# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
114# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
115#elif defined(CONFIG_H83007) || defined(CONFIG_H83068) 86#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
116# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
117# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) 87# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
118#elif defined(CONFIG_H8S2678) 88#elif defined(CONFIG_H8S2678)
119# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
120# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) 89# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
121#elif defined(CONFIG_CPU_SUBTYPE_SH7757) 90#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
122# define SCSPTR0 0xfe4b0020 91# define SCSPTR0 0xfe4b0020
123# define SCSPTR1 0xfe4b0020 92# define SCSPTR1 0xfe4b0020
124# define SCSPTR2 0xfe4b0020 93# define SCSPTR2 0xfe4b0020
125# define SCIF_ORER 0x0001 94# define SCIF_ORER 0x0001
126# define SCSCR_INIT(port) 0x38
127# define SCIF_ONLY 95# define SCIF_ONLY
128#elif defined(CONFIG_CPU_SUBTYPE_SH7763) 96#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
129# define SCSPTR0 0xffe00024 /* 16 bit SCIF */ 97# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
130# define SCSPTR1 0xffe08024 /* 16 bit SCIF */ 98# define SCSPTR1 0xffe08024 /* 16 bit SCIF */
131# define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */ 99# define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
132# define SCIF_ORER 0x0001 /* overrun error bit */ 100# define SCIF_ORER 0x0001 /* overrun error bit */
133# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
134#elif defined(CONFIG_CPU_SUBTYPE_SH7770) 101#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
135# define SCSPTR0 0xff923020 /* 16 bit SCIF */ 102# define SCSPTR0 0xff923020 /* 16 bit SCIF */
136# define SCSPTR1 0xff924020 /* 16 bit SCIF */ 103# define SCSPTR1 0xff924020 /* 16 bit SCIF */
137# define SCSPTR2 0xff925020 /* 16 bit SCIF */ 104# define SCSPTR2 0xff925020 /* 16 bit SCIF */
138# define SCIF_ORER 0x0001 /* overrun error bit */ 105# define SCIF_ORER 0x0001 /* overrun error bit */
139# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
140#elif defined(CONFIG_CPU_SUBTYPE_SH7780) 106#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
141# define SCSPTR0 0xffe00024 /* 16 bit SCIF */ 107# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
142# define SCSPTR1 0xffe10024 /* 16 bit SCIF */ 108# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
143# define SCIF_ORER 0x0001 /* Overrun error bit */ 109# define SCIF_ORER 0x0001 /* Overrun error bit */
144
145#if defined(CONFIG_SH_SH2007)
146/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=0 */
147# define SCSCR_INIT(port) 0x38
148#else
149/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */
150# define SCSCR_INIT(port) 0x3a
151#endif
152
153#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \ 110#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
154 defined(CONFIG_CPU_SUBTYPE_SH7786) 111 defined(CONFIG_CPU_SUBTYPE_SH7786)
155# define SCSPTR0 0xffea0024 /* 16 bit SCIF */ 112# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
@@ -159,7 +116,6 @@
159# define SCSPTR4 0xffee0024 /* 16 bit SCIF */ 116# define SCSPTR4 0xffee0024 /* 16 bit SCIF */
160# define SCSPTR5 0xffef0024 /* 16 bit SCIF */ 117# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
161# define SCIF_ORER 0x0001 /* Overrun error bit */ 118# define SCIF_ORER 0x0001 /* Overrun error bit */
162# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
163#elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \ 119#elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
164 defined(CONFIG_CPU_SUBTYPE_SH7203) || \ 120 defined(CONFIG_CPU_SUBTYPE_SH7203) || \
165 defined(CONFIG_CPU_SUBTYPE_SH7206) || \ 121 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
@@ -174,52 +130,21 @@
174# define SCSPTR6 0xfffeB020 /* 16 bit SCIF */ 130# define SCSPTR6 0xfffeB020 /* 16 bit SCIF */
175# define SCSPTR7 0xfffeB820 /* 16 bit SCIF */ 131# define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
176# endif 132# endif
177# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
178#elif defined(CONFIG_CPU_SUBTYPE_SH7619) 133#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
179# define SCSPTR0 0xf8400020 /* 16 bit SCIF */ 134# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
180# define SCSPTR1 0xf8410020 /* 16 bit SCIF */ 135# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
181# define SCSPTR2 0xf8420020 /* 16 bit SCIF */ 136# define SCSPTR2 0xf8420020 /* 16 bit SCIF */
182# define SCIF_ORER 0x0001 /* overrun error bit */ 137# define SCIF_ORER 0x0001 /* overrun error bit */
183# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
184#elif defined(CONFIG_CPU_SUBTYPE_SHX3) 138#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
185# define SCSPTR0 0xffc30020 /* 16 bit SCIF */ 139# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
186# define SCSPTR1 0xffc40020 /* 16 bit SCIF */ 140# define SCSPTR1 0xffc40020 /* 16 bit SCIF */
187# define SCSPTR2 0xffc50020 /* 16 bit SCIF */ 141# define SCSPTR2 0xffc50020 /* 16 bit SCIF */
188# define SCSPTR3 0xffc60020 /* 16 bit SCIF */ 142# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
189# define SCIF_ORER 0x0001 /* Overrun error bit */ 143# define SCIF_ORER 0x0001 /* Overrun error bit */
190# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
191#else 144#else
192# error CPU subtype not defined 145# error CPU subtype not defined
193#endif 146#endif
194 147
195/* SCSCR */
196#define SCI_CTRL_FLAGS_TIE 0x80 /* all */
197#define SCI_CTRL_FLAGS_RIE 0x40 /* all */
198#define SCI_CTRL_FLAGS_TE 0x20 /* all */
199#define SCI_CTRL_FLAGS_RE 0x10 /* all */
200#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
201 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
202 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
203 defined(CONFIG_CPU_SUBTYPE_SH7722) || \
204 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
205 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
206 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
207 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
208 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
209 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
210 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
211 defined(CONFIG_CPU_SUBTYPE_SHX3)
212#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
213#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
214#define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8)
215#else
216#define SCI_CTRL_FLAGS_REIE 0
217#endif
218/* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
219/* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
220/* SCI_CTRL_FLAGS_CKE1 0x02 * all */
221/* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
222
223/* SCxSR SCI */ 148/* SCxSR SCI */
224#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 149#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
225#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 150#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
@@ -300,23 +225,11 @@
300/* SCFCR */ 225/* SCFCR */
301#define SCFCR_RFRST 0x0002 226#define SCFCR_RFRST 0x0002
302#define SCFCR_TFRST 0x0004 227#define SCFCR_TFRST 0x0004
303#define SCFCR_TCRST 0x4000
304#define SCFCR_MCE 0x0008 228#define SCFCR_MCE 0x0008
305 229
306#define SCI_MAJOR 204 230#define SCI_MAJOR 204
307#define SCI_MINOR_START 8 231#define SCI_MINOR_START 8
308 232
309/* Generic serial flags */
310#define SCI_RX_THROTTLE 0x0000001
311
312#define SCI_MAGIC 0xbabeface
313
314/*
315 * Events are used to schedule things to happen at timer-interrupt
316 * time, instead of at rs interrupt time.
317 */
318#define SCI_EVENT_WRITE_WAKEUP 0
319
320#define SCI_IN(size, offset) \ 233#define SCI_IN(size, offset) \
321 if ((size) == 8) { \ 234 if ((size) == 8) { \
322 return ioread8(port->membase + (offset)); \ 235 return ioread8(port->membase + (offset)); \
@@ -445,8 +358,6 @@
445SCIF_FNS(SCSMR, 0x00, 16) 358SCIF_FNS(SCSMR, 0x00, 16)
446SCIF_FNS(SCBRR, 0x04, 8) 359SCIF_FNS(SCBRR, 0x04, 8)
447SCIF_FNS(SCSCR, 0x08, 16) 360SCIF_FNS(SCSCR, 0x08, 16)
448SCIF_FNS(SCTDSR, 0x0c, 8)
449SCIF_FNS(SCFER, 0x10, 16)
450SCIF_FNS(SCxSR, 0x14, 16) 361SCIF_FNS(SCxSR, 0x14, 16)
451SCIF_FNS(SCFCR, 0x18, 16) 362SCIF_FNS(SCFCR, 0x18, 16)
452SCIF_FNS(SCFDR, 0x1c, 16) 363SCIF_FNS(SCFDR, 0x1c, 16)
@@ -476,8 +387,6 @@ SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
476SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16) 387SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
477SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8) 388SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
478SCIx_FNS(SCSPTR, 0, 0, 0, 0) 389SCIx_FNS(SCSPTR, 0, 0, 0, 0)
479SCIF_FNS(SCTDSR, 0x0c, 8)
480SCIF_FNS(SCFER, 0x10, 16)
481SCIF_FNS(SCFCR, 0x18, 16) 390SCIF_FNS(SCFCR, 0x18, 16)
482SCIF_FNS(SCFDR, 0x1c, 16) 391SCIF_FNS(SCFDR, 0x1c, 16)
483SCIF_FNS(SCLSR, 0x24, 16) 392SCIF_FNS(SCLSR, 0x24, 16)
@@ -503,7 +412,6 @@ SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
503#elif defined(CONFIG_CPU_SUBTYPE_SH7763) 412#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
504SCIF_FNS(SCFDR, 0, 0, 0x1C, 16) 413SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
505SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16) 414SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16)
506SCIF_FNS(SCLSR2, 0, 0, 0x24, 16)
507SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) 415SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
508SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) 416SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
509SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) 417SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
@@ -597,64 +505,3 @@ static inline int sci_rxd_in(struct uart_port *port)
597 return 1; 505 return 1;
598} 506}
599#endif 507#endif
600
601/*
602 * Values for the BitRate Register (SCBRR)
603 *
604 * The values are actually divisors for a frequency which can
605 * be internal to the SH3 (14.7456MHz) or derived from an external
606 * clock source. This driver assumes the internal clock is used;
607 * to support using an external clock source, config options or
608 * possibly command-line options would need to be added.
609 *
610 * Also, to support speeds below 2400 (why?) the lower 2 bits of
611 * the SCSMR register would also need to be set to non-zero values.
612 *
613 * -- Greg Banks 27Feb2000
614 *
615 * Answer: The SCBRR register is only eight bits, and the value in
616 * it gets larger with lower baud rates. At around 2400 (depending on
617 * the peripherial module clock) you run out of bits. However the
618 * lower two bits of SCSMR allow the module clock to be divided down,
619 * scaling the value which is needed in SCBRR.
620 *
621 * -- Stuart Menefy - 23 May 2000
622 *
623 * I meant, why would anyone bother with bitrates below 2400.
624 *
625 * -- Greg Banks - 7Jul2000
626 *
627 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
628 * tape reader as a console!
629 *
630 * -- Mitch Davis - 15 Jul 2000
631 */
632
633#if (defined(CONFIG_CPU_SUBTYPE_SH7780) || \
634 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
635 defined(CONFIG_CPU_SUBTYPE_SH7786)) && \
636 !defined(CONFIG_SH_SH2007)
637#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
638#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
639 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
640 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
641 defined(CONFIG_ARCH_SH73A0) || \
642 defined(CONFIG_ARCH_SH7367) || \
643 defined(CONFIG_ARCH_SH7377) || \
644 defined(CONFIG_ARCH_SH7372)
645#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
646#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
647 defined(CONFIG_CPU_SUBTYPE_SH7724)
648static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
649{
650 if (port->type == PORT_SCIF)
651 return (clk+16*bps)/(32*bps)-1;
652 else
653 return ((clk*2)+16*bps)/(16*bps)-1;
654}
655#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
656#elif defined(__H8300H__) || defined(__H8300S__)
657#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
658#else /* Generic SH */
659#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
660#endif
diff --git a/include/linux/serial_sci.h b/include/linux/serial_sci.h
index baed2122c5a6..1630d9cae22a 100644
--- a/include/linux/serial_sci.h
+++ b/include/linux/serial_sci.h
@@ -8,6 +8,23 @@
8 * Generic header for SuperH SCI(F) (used by sh/sh64/h8300 and related parts) 8 * Generic header for SuperH SCI(F) (used by sh/sh64/h8300 and related parts)
9 */ 9 */
10 10
11enum {
12 SCBRR_ALGO_1, /* ((clk + 16 * bps) / (16 * bps) - 1) */
13 SCBRR_ALGO_2, /* ((clk + 16 * bps) / (32 * bps) - 1) */
14 SCBRR_ALGO_3, /* (((clk * 2) + 16 * bps) / (16 * bps) - 1) */
15 SCBRR_ALGO_4, /* (((clk * 2) + 16 * bps) / (32 * bps) - 1) */
16 SCBRR_ALGO_5, /* (((clk * 1000 / 32) / bps) - 1) */
17};
18
19#define SCSCR_TIE (1 << 7)
20#define SCSCR_RIE (1 << 6)
21#define SCSCR_TE (1 << 5)
22#define SCSCR_RE (1 << 4)
23#define SCSCR_REIE (1 << 3) /* not supported by all parts */
24#define SCSCR_TOIE (1 << 2) /* not supported by all parts */
25#define SCSCR_CKE1 (1 << 1)
26#define SCSCR_CKE0 (1 << 0)
27
11/* Offsets into the sci_port->irqs array */ 28/* Offsets into the sci_port->irqs array */
12enum { 29enum {
13 SCIx_ERI_IRQ, 30 SCIx_ERI_IRQ,
@@ -29,7 +46,12 @@ struct plat_sci_port {
29 unsigned int type; /* SCI / SCIF / IRDA */ 46 unsigned int type; /* SCI / SCIF / IRDA */
30 upf_t flags; /* UPF_* flags */ 47 upf_t flags; /* UPF_* flags */
31 char *clk; /* clock string */ 48 char *clk; /* clock string */
49
50 unsigned int scbrr_algo_id; /* SCBRR calculation algo */
51 unsigned int scscr; /* SCSCR initialization */
52
32 struct device *dma_dev; 53 struct device *dma_dev;
54
33#ifdef CONFIG_SERIAL_SH_SCI_DMA 55#ifdef CONFIG_SERIAL_SH_SCI_DMA
34 unsigned int dma_slave_tx; 56 unsigned int dma_slave_tx;
35 unsigned int dma_slave_rx; 57 unsigned int dma_slave_rx;
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-24 06:50:29 -0500