Merge tag 'sunxi-clk-for-4.16-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner

Pull Allwinner clock changes from Chen-Yu Tsai:

 - Fix hardware description for the DE2 clocks on the A64 and H5 SoCs
 - Support DE2 clocks on the H3
 - Fix description for the TCON1 clock on A83T

All these are non-critical, as they have no users.

* tag 'sunxi-clk-for-4.16-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: a83t: Add M divider to TCON1 clock
  clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCU
  clk: sunxi-ng: add support for Allwinner H3 DE2 CCU
  dt-bindings: fix the binding of Allwinner DE2 CCU of A83T and H3

3 files changed, 55 insertions, 7 deletions

diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt b/Documentation/devicetree/bindings/clock/sun8i-de2.txt
index 631d27cd89d6..f2fa87c4765c 100644
--- a/Documentation/devicetree/bindings/clock/sun8i-de2.txt
+++ b/Documentation/devicetree/bindings/clock/sun8i-de2.txt
@@ -4,13 +4,14 @@ Allwinner Display Engine 2.0 Clock Control Binding
 Required properties :
 - compatible: must contain one of the following compatibles:
                 - "allwinner,sun8i-a83t-de2-clk"
+                - "allwinner,sun8i-h3-de2-clk"
                 - "allwinner,sun8i-v3s-de2-clk"
                 - "allwinner,sun50i-h5-de2-clk"
 
 - reg: Must contain the registers base address and length
 - clocks: phandle to the clocks feeding the display engine subsystem.
           Three are needed:
-  - "mod": the display engine module clock
+  - "mod": the display engine module clock (on A83T it's the DE PLL)
   - "bus": the bus clock for the whole display engine subsystem
 - clock-names: Must contain the clock names described just above
 - resets: phandle to the reset control for the display engine subsystem.
@@ -19,7 +20,7 @@ Required properties :
 
 Example:
 de2_clocks: clock@1000000 {
-        compatible = "allwinner,sun8i-a83t-de2-clk";
+        compatible = "allwinner,sun8i-h3-de2-clk";
         reg = <0x01000000 0x100000>;
         clocks = <&ccu CLK_BUS_DE>,
                  <&ccu CLK_DE>;
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
index 04a9c33f53f0..7d08015b980d 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
@@ -504,8 +504,8 @@ static SUNXI_CCU_MUX_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents,
                                  0x118, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
 
 static const char * const tcon1_parents[] = { "pll-video1" };
-static SUNXI_CCU_MUX_WITH_GATE(tcon1_clk, "tcon1", tcon1_parents,
-                                 0x11c, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
+static SUNXI_CCU_M_WITH_MUX_GATE(tcon1_clk, "tcon1", tcon1_parents,
+                                 0x11c, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
 
 static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 0x130, BIT(16), 0);
 
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index 5cc9d9952121..468d1abaf0ee 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -41,6 +41,8 @@ static SUNXI_CCU_GATE(wb_clk,		"wb",		"wb-div",
 
 static SUNXI_CCU_M(mixer0_div_clk, "mixer0-div", "de", 0x0c, 0, 4,
                    CLK_SET_RATE_PARENT);
+static SUNXI_CCU_M(mixer1_div_clk, "mixer1-div", "de", 0x0c, 4, 4,
+                   CLK_SET_RATE_PARENT);
 static SUNXI_CCU_M(wb_div_clk, "wb-div", "de", 0x0c, 8, 4,
                    CLK_SET_RATE_PARENT);
 
@@ -65,6 +67,20 @@ static struct ccu_common *sun8i_a83t_de2_clks[] = {
         &wb_div_a83_clk.common,
 };
 
+static struct ccu_common *sun8i_h3_de2_clks[] = {
+        &mixer0_clk.common,
+        &mixer1_clk.common,
+        &wb_clk.common,
+
+        &bus_mixer0_clk.common,
+        &bus_mixer1_clk.common,
+        &bus_wb_clk.common,
+
+        &mixer0_div_clk.common,
+        &mixer1_div_clk.common,
+        &wb_div_clk.common,
+};
+
 static struct ccu_common *sun8i_v3s_de2_clks[] = {
         &mixer0_clk.common,
         &wb_clk.common,
@@ -93,6 +109,23 @@ static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = {
         .num    = CLK_NUMBER,
 };
 
+static struct clk_hw_onecell_data sun8i_h3_de2_hw_clks = {
+        .hws    = {
+                [CLK_MIXER0]            = &mixer0_clk.common.hw,
+                [CLK_MIXER1]            = &mixer1_clk.common.hw,
+                [CLK_WB]                = &wb_clk.common.hw,
+
+                [CLK_BUS_MIXER0]        = &bus_mixer0_clk.common.hw,
+                [CLK_BUS_MIXER1]        = &bus_mixer1_clk.common.hw,
+                [CLK_BUS_WB]            = &bus_wb_clk.common.hw,
+
+                [CLK_MIXER0_DIV]        = &mixer0_div_clk.common.hw,
+                [CLK_MIXER1_DIV]        = &mixer1_div_clk.common.hw,
+                [CLK_WB_DIV]            = &wb_div_clk.common.hw,
+        },
+        .num    = CLK_NUMBER,
+};
+
 static struct clk_hw_onecell_data sun8i_v3s_de2_hw_clks = {
         .hws    = {
                 [CLK_MIXER0]            = &mixer0_clk.common.hw,
@@ -133,11 +166,21 @@ static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = {
         .num_resets     = ARRAY_SIZE(sun8i_a83t_de2_resets),
 };
 
+static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = {
+        .ccu_clks       = sun8i_h3_de2_clks,
+        .num_ccu_clks   = ARRAY_SIZE(sun8i_h3_de2_clks),
+
+        .hw_clks        = &sun8i_h3_de2_hw_clks,
+
+        .resets         = sun8i_a83t_de2_resets,
+        .num_resets     = ARRAY_SIZE(sun8i_a83t_de2_resets),
+};
+
 static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
-        .ccu_clks       = sun8i_a83t_de2_clks,
-        .num_ccu_clks   = ARRAY_SIZE(sun8i_a83t_de2_clks),
+        .ccu_clks       = sun8i_h3_de2_clks,
+        .num_ccu_clks   = ARRAY_SIZE(sun8i_h3_de2_clks),
 
-        .hw_clks        = &sun8i_a83t_de2_hw_clks,
+        .hw_clks        = &sun8i_h3_de2_hw_clks,
 
         .resets         = sun50i_a64_de2_resets,
         .num_resets     = ARRAY_SIZE(sun50i_a64_de2_resets),
@@ -238,6 +281,10 @@ static const struct of_device_id sunxi_de2_clk_ids[] = {
                 .data = &sun8i_a83t_de2_clk_desc,
         },
         {
+                .compatible = "allwinner,sun8i-h3-de2-clk",
+                .data = &sun8i_h3_de2_clk_desc,
+        },
+        {
                 .compatible = "allwinner,sun8i-v3s-de2-clk",
                 .data = &sun8i_v3s_de2_clk_desc,
         },