diff options
author | Joe Perches <joe@perches.com> | 2017-02-27 20:31:03 -0500 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2017-03-29 23:53:24 -0400 |
commit | eeca2324900e922b693b2b6ddacc502c78f1c1ef (patch) | |
tree | 52fff5e661c81bd47a39c7995c482352ed9d68cf | |
parent | 9dc5a91e4d1cc7accd776f20198df48255de516f (diff) |
drm: Use pr_cont where appropriate
Using 'printk("\n")' is not preferred anymore and
using printk to continue logging messages now produces
multiple line logging output unless the continuations
use KERN_CONT.
Convert these uses to appropriately use pr_cont or a
single printk where possible.
Miscellanea:
o Use a temporary const char * instead of multiple printks
o Remove trailing space from logging by using a leading space instead
Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 70 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r600_dpm.c | 71 |
2 files changed, 73 insertions, 68 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c index 6ca0333ca4c0..38e9b0d3659a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | |||
@@ -31,86 +31,88 @@ | |||
31 | 31 | ||
32 | void amdgpu_dpm_print_class_info(u32 class, u32 class2) | 32 | void amdgpu_dpm_print_class_info(u32 class, u32 class2) |
33 | { | 33 | { |
34 | printk("\tui class: "); | 34 | const char *s; |
35 | |||
35 | switch (class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { | 36 | switch (class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { |
36 | case ATOM_PPLIB_CLASSIFICATION_UI_NONE: | 37 | case ATOM_PPLIB_CLASSIFICATION_UI_NONE: |
37 | default: | 38 | default: |
38 | printk("none\n"); | 39 | s = "none"; |
39 | break; | 40 | break; |
40 | case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY: | 41 | case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY: |
41 | printk("battery\n"); | 42 | s = "battery"; |
42 | break; | 43 | break; |
43 | case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED: | 44 | case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED: |
44 | printk("balanced\n"); | 45 | s = "balanced"; |
45 | break; | 46 | break; |
46 | case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE: | 47 | case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE: |
47 | printk("performance\n"); | 48 | s = "performance"; |
48 | break; | 49 | break; |
49 | } | 50 | } |
50 | printk("\tinternal class: "); | 51 | printk("\tui class: %s\n", s); |
52 | printk("\tinternal class:"); | ||
51 | if (((class & ~ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 0) && | 53 | if (((class & ~ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 0) && |
52 | (class2 == 0)) | 54 | (class2 == 0)) |
53 | printk("none"); | 55 | pr_cont(" none"); |
54 | else { | 56 | else { |
55 | if (class & ATOM_PPLIB_CLASSIFICATION_BOOT) | 57 | if (class & ATOM_PPLIB_CLASSIFICATION_BOOT) |
56 | printk("boot "); | 58 | pr_cont(" boot"); |
57 | if (class & ATOM_PPLIB_CLASSIFICATION_THERMAL) | 59 | if (class & ATOM_PPLIB_CLASSIFICATION_THERMAL) |
58 | printk("thermal "); | 60 | pr_cont(" thermal"); |
59 | if (class & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE) | 61 | if (class & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE) |
60 | printk("limited_pwr "); | 62 | pr_cont(" limited_pwr"); |
61 | if (class & ATOM_PPLIB_CLASSIFICATION_REST) | 63 | if (class & ATOM_PPLIB_CLASSIFICATION_REST) |
62 | printk("rest "); | 64 | pr_cont(" rest"); |
63 | if (class & ATOM_PPLIB_CLASSIFICATION_FORCED) | 65 | if (class & ATOM_PPLIB_CLASSIFICATION_FORCED) |
64 | printk("forced "); | 66 | pr_cont(" forced"); |
65 | if (class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) | 67 | if (class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) |
66 | printk("3d_perf "); | 68 | pr_cont(" 3d_perf"); |
67 | if (class & ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE) | 69 | if (class & ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE) |
68 | printk("ovrdrv "); | 70 | pr_cont(" ovrdrv"); |
69 | if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) | 71 | if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) |
70 | printk("uvd "); | 72 | pr_cont(" uvd"); |
71 | if (class & ATOM_PPLIB_CLASSIFICATION_3DLOW) | 73 | if (class & ATOM_PPLIB_CLASSIFICATION_3DLOW) |
72 | printk("3d_low "); | 74 | pr_cont(" 3d_low"); |
73 | if (class & ATOM_PPLIB_CLASSIFICATION_ACPI) | 75 | if (class & ATOM_PPLIB_CLASSIFICATION_ACPI) |
74 | printk("acpi "); | 76 | pr_cont(" acpi"); |
75 | if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) | 77 | if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) |
76 | printk("uvd_hd2 "); | 78 | pr_cont(" uvd_hd2"); |
77 | if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) | 79 | if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) |
78 | printk("uvd_hd "); | 80 | pr_cont(" uvd_hd"); |
79 | if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) | 81 | if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) |
80 | printk("uvd_sd "); | 82 | pr_cont(" uvd_sd"); |
81 | if (class2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2) | 83 | if (class2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2) |
82 | printk("limited_pwr2 "); | 84 | pr_cont(" limited_pwr2"); |
83 | if (class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) | 85 | if (class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) |
84 | printk("ulv "); | 86 | pr_cont(" ulv"); |
85 | if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) | 87 | if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) |
86 | printk("uvd_mvc "); | 88 | pr_cont(" uvd_mvc"); |
87 | } | 89 | } |
88 | printk("\n"); | 90 | pr_cont("\n"); |
89 | } | 91 | } |
90 | 92 | ||
91 | void amdgpu_dpm_print_cap_info(u32 caps) | 93 | void amdgpu_dpm_print_cap_info(u32 caps) |
92 | { | 94 | { |
93 | printk("\tcaps: "); | 95 | printk("\tcaps:"); |
94 | if (caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) | 96 | if (caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) |
95 | printk("single_disp "); | 97 | pr_cont(" single_disp"); |
96 | if (caps & ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK) | 98 | if (caps & ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK) |
97 | printk("video "); | 99 | pr_cont(" video"); |
98 | if (caps & ATOM_PPLIB_DISALLOW_ON_DC) | 100 | if (caps & ATOM_PPLIB_DISALLOW_ON_DC) |
99 | printk("no_dc "); | 101 | pr_cont(" no_dc"); |
100 | printk("\n"); | 102 | pr_cont("\n"); |
101 | } | 103 | } |
102 | 104 | ||
103 | void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev, | 105 | void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev, |
104 | struct amdgpu_ps *rps) | 106 | struct amdgpu_ps *rps) |
105 | { | 107 | { |
106 | printk("\tstatus: "); | 108 | printk("\tstatus:"); |
107 | if (rps == adev->pm.dpm.current_ps) | 109 | if (rps == adev->pm.dpm.current_ps) |
108 | printk("c "); | 110 | pr_cont(" c"); |
109 | if (rps == adev->pm.dpm.requested_ps) | 111 | if (rps == adev->pm.dpm.requested_ps) |
110 | printk("r "); | 112 | pr_cont(" r"); |
111 | if (rps == adev->pm.dpm.boot_ps) | 113 | if (rps == adev->pm.dpm.boot_ps) |
112 | printk("b "); | 114 | pr_cont(" b"); |
113 | printk("\n"); | 115 | pr_cont("\n"); |
114 | } | 116 | } |
115 | 117 | ||
116 | 118 | ||
diff --git a/drivers/gpu/drm/radeon/r600_dpm.c b/drivers/gpu/drm/radeon/r600_dpm.c index 5a26eb4545aa..c7fc1dbfd192 100644 --- a/drivers/gpu/drm/radeon/r600_dpm.c +++ b/drivers/gpu/drm/radeon/r600_dpm.c | |||
@@ -69,86 +69,89 @@ const u32 r600_dtc[R600_PM_NUMBER_OF_TC] = | |||
69 | 69 | ||
70 | void r600_dpm_print_class_info(u32 class, u32 class2) | 70 | void r600_dpm_print_class_info(u32 class, u32 class2) |
71 | { | 71 | { |
72 | printk("\tui class: "); | 72 | const char *s; |
73 | |||
73 | switch (class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { | 74 | switch (class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { |
74 | case ATOM_PPLIB_CLASSIFICATION_UI_NONE: | 75 | case ATOM_PPLIB_CLASSIFICATION_UI_NONE: |
75 | default: | 76 | default: |
76 | printk("none\n"); | 77 | s = "none"; |
77 | break; | 78 | break; |
78 | case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY: | 79 | case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY: |
79 | printk("battery\n"); | 80 | s = "battery"; |
80 | break; | 81 | break; |
81 | case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED: | 82 | case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED: |
82 | printk("balanced\n"); | 83 | s = "balanced"; |
83 | break; | 84 | break; |
84 | case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE: | 85 | case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE: |
85 | printk("performance\n"); | 86 | s = "performance"; |
86 | break; | 87 | break; |
87 | } | 88 | } |
88 | printk("\tinternal class: "); | 89 | printk("\tui class: %s\n", s); |
90 | |||
91 | printk("\tinternal class:"); | ||
89 | if (((class & ~ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 0) && | 92 | if (((class & ~ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 0) && |
90 | (class2 == 0)) | 93 | (class2 == 0)) |
91 | printk("none"); | 94 | pr_cont(" none"); |
92 | else { | 95 | else { |
93 | if (class & ATOM_PPLIB_CLASSIFICATION_BOOT) | 96 | if (class & ATOM_PPLIB_CLASSIFICATION_BOOT) |
94 | printk("boot "); | 97 | pr_cont(" boot"); |
95 | if (class & ATOM_PPLIB_CLASSIFICATION_THERMAL) | 98 | if (class & ATOM_PPLIB_CLASSIFICATION_THERMAL) |
96 | printk("thermal "); | 99 | pr_cont(" thermal"); |
97 | if (class & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE) | 100 | if (class & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE) |
98 | printk("limited_pwr "); | 101 | pr_cont(" limited_pwr"); |
99 | if (class & ATOM_PPLIB_CLASSIFICATION_REST) | 102 | if (class & ATOM_PPLIB_CLASSIFICATION_REST) |
100 | printk("rest "); | 103 | pr_cont(" rest"); |
101 | if (class & ATOM_PPLIB_CLASSIFICATION_FORCED) | 104 | if (class & ATOM_PPLIB_CLASSIFICATION_FORCED) |
102 | printk("forced "); | 105 | pr_cont(" forced"); |
103 | if (class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) | 106 | if (class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) |
104 | printk("3d_perf "); | 107 | pr_cont(" 3d_perf"); |
105 | if (class & ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE) | 108 | if (class & ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE) |
106 | printk("ovrdrv "); | 109 | pr_cont(" ovrdrv"); |
107 | if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) | 110 | if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) |
108 | printk("uvd "); | 111 | pr_cont(" uvd"); |
109 | if (class & ATOM_PPLIB_CLASSIFICATION_3DLOW) | 112 | if (class & ATOM_PPLIB_CLASSIFICATION_3DLOW) |
110 | printk("3d_low "); | 113 | pr_cont(" 3d_low"); |
111 | if (class & ATOM_PPLIB_CLASSIFICATION_ACPI) | 114 | if (class & ATOM_PPLIB_CLASSIFICATION_ACPI) |
112 | printk("acpi "); | 115 | pr_cont(" acpi"); |
113 | if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) | 116 | if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) |
114 | printk("uvd_hd2 "); | 117 | pr_cont(" uvd_hd2"); |
115 | if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) | 118 | if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) |
116 | printk("uvd_hd "); | 119 | pr_cont(" uvd_hd"); |
117 | if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) | 120 | if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) |
118 | printk("uvd_sd "); | 121 | pr_cont(" uvd_sd"); |
119 | if (class2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2) | 122 | if (class2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2) |
120 | printk("limited_pwr2 "); | 123 | pr_cont(" limited_pwr2"); |
121 | if (class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) | 124 | if (class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) |
122 | printk("ulv "); | 125 | pr_cont(" ulv"); |
123 | if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) | 126 | if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) |
124 | printk("uvd_mvc "); | 127 | pr_cont(" uvd_mvc"); |
125 | } | 128 | } |
126 | printk("\n"); | 129 | pr_cont("\n"); |
127 | } | 130 | } |
128 | 131 | ||
129 | void r600_dpm_print_cap_info(u32 caps) | 132 | void r600_dpm_print_cap_info(u32 caps) |
130 | { | 133 | { |
131 | printk("\tcaps: "); | 134 | printk("\tcaps:"); |
132 | if (caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) | 135 | if (caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) |
133 | printk("single_disp "); | 136 | pr_cont(" single_disp"); |
134 | if (caps & ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK) | 137 | if (caps & ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK) |
135 | printk("video "); | 138 | pr_cont(" video"); |
136 | if (caps & ATOM_PPLIB_DISALLOW_ON_DC) | 139 | if (caps & ATOM_PPLIB_DISALLOW_ON_DC) |
137 | printk("no_dc "); | 140 | pr_cont(" no_dc"); |
138 | printk("\n"); | 141 | pr_cont("\n"); |
139 | } | 142 | } |
140 | 143 | ||
141 | void r600_dpm_print_ps_status(struct radeon_device *rdev, | 144 | void r600_dpm_print_ps_status(struct radeon_device *rdev, |
142 | struct radeon_ps *rps) | 145 | struct radeon_ps *rps) |
143 | { | 146 | { |
144 | printk("\tstatus: "); | 147 | printk("\tstatus:"); |
145 | if (rps == rdev->pm.dpm.current_ps) | 148 | if (rps == rdev->pm.dpm.current_ps) |
146 | printk("c "); | 149 | pr_cont(" c"); |
147 | if (rps == rdev->pm.dpm.requested_ps) | 150 | if (rps == rdev->pm.dpm.requested_ps) |
148 | printk("r "); | 151 | pr_cont(" r"); |
149 | if (rps == rdev->pm.dpm.boot_ps) | 152 | if (rps == rdev->pm.dpm.boot_ps) |
150 | printk("b "); | 153 | pr_cont(" b"); |
151 | printk("\n"); | 154 | pr_cont("\n"); |
152 | } | 155 | } |
153 | 156 | ||
154 | u32 r600_dpm_get_vblank_time(struct radeon_device *rdev) | 157 | u32 r600_dpm_get_vblank_time(struct radeon_device *rdev) |