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author | Garlic Tseng <garlic.tseng@mediatek.com> | 2017-02-16 00:27:16 -0500 |
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committer | Mark Brown <broonie@kernel.org> | 2017-02-16 13:27:17 -0500 |
commit | ee9dc31962ac7141df6926b8696edf8831dde76c (patch) | |
tree | 15369fc0bdaabca5be144f537aab9aff39561c00 | |
parent | cc3e1ce2c73c0e44373eb364f94e4fefebf7719e (diff) |
ASoC: mediatek: add power-domains for mt2701-afe-pcm.txt
This add power-domains for mt2701-afe-pcm
Signed-off-by: Garlic Tseng <garlic.tseng@mediatek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r-- | Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt b/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt index 3e623a724e55..9800a560e0c2 100644 --- a/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt +++ b/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt | |||
@@ -4,6 +4,7 @@ Required properties: | |||
4 | - compatible = "mediatek,mt2701-audio"; | 4 | - compatible = "mediatek,mt2701-audio"; |
5 | - reg: register location and size | 5 | - reg: register location and size |
6 | - interrupts: Should contain AFE interrupt | 6 | - interrupts: Should contain AFE interrupt |
7 | - power-domains: should define the power domain | ||
7 | - clock-names: should have these clock names: | 8 | - clock-names: should have these clock names: |
8 | "infra_sys_audio_clk", | 9 | "infra_sys_audio_clk", |
9 | "top_audio_mux1_sel", | 10 | "top_audio_mux1_sel", |
@@ -58,6 +59,7 @@ Example: | |||
58 | <0 0x112A0000 0 0x20000>; | 59 | <0 0x112A0000 0 0x20000>; |
59 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, | 60 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, |
60 | <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; | 61 | <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; |
62 | power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; | ||
61 | clocks = <&infracfg CLK_INFRA_AUDIO>, | 63 | clocks = <&infracfg CLK_INFRA_AUDIO>, |
62 | <&topckgen CLK_TOP_AUD_MUX1_SEL>, | 64 | <&topckgen CLK_TOP_AUD_MUX1_SEL>, |
63 | <&topckgen CLK_TOP_AUD_MUX2_SEL>, | 65 | <&topckgen CLK_TOP_AUD_MUX2_SEL>, |