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authorLinus Torvalds <torvalds@linux-foundation.org>2017-04-13 02:36:23 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2017-04-13 02:36:23 -0400
commitee921c762cf90652add60ebacb5b90636ac108df (patch)
tree3a8d27550c38ee7ba8e5baf4f57c10cc3c4655c4
parent827c30a758392d00ce46d5d0c0a243cdecf5826e (diff)
parent2ca62d8a606a95e098799f128f6a40a6300d2a2a (diff)
Merge tag 'drm-fixes-for-v4.11-rc7' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie: "i915, gvt, nouveau, udl and etnaviv fixes. I was away the end of last week, so some of these would have been in rc6, and it's Easter from tomorrow, so I decided I better dequeue what I have now. The nouveau changes, just add a hw enable for GP107 display (like a pci id addition really), and fix a couple of regressions. i915 has some more gvt fixes, along with a few run of the mill ones, the rcu one seems like a few people have hit it. Otherwise a small udl and small etnaviv fix" * tag 'drm-fixes-for-v4.11-rc7' of git://people.freedesktop.org/~airlied/linux: (22 commits) drm/etnaviv: fix missing unlock on error in etnaviv_gpu_submit() drm/udl: Fix unaligned memory access in udl_render_hline drm/i915: Don't call synchronize_rcu_expedited under struct_mutex drm/i915: Suspend GuC prior to GPU Reset during GEM suspend drm/nouveau: initial support (display-only) for GP107 drm/nouveau/kms/nv50: fix double dma_fence_put() when destroying plane state drm/nouveau/kms/nv50: fix setting of HeadSetRasterVertBlankDmi method drm/nouveau/mmu/nv4a: use nv04 mmu rather than the nv44 one drm/nouveau/mpeg: mthd returns true on success now drm/i915/gvt: set the correct default value of CTX STATUS PTR drm/i915/gvt: Fix firmware loading interface for GVT-g golden HW state drm/i915: Use a dummy timeline name for a signaled fence drm/i915: Ironlake do_idle_maps w/a may be called w/o struct_mutex drm/i915/gvt: remove the redundant info NULL check drm/i915/gvt: adjust mem size for low resolution type drm/i915: Avoid lock dropping between rescheduling drm/i915/gvt: exclude cfg space from failsafe mode drm/i915/gvt: Activate/de-activate vGPU in mdev ops. drm/i915/execlists: Wrap tail pointer after reset tweaking drm/i915/perf: remove user triggerable warn ...
-rw-r--r--drivers/gpu/drm/etnaviv/etnaviv_gpu.c3
-rw-r--r--drivers/gpu/drm/i915/gvt/cfg_space.c3
-rw-r--r--drivers/gpu/drm/i915/gvt/execlist.c3
-rw-r--r--drivers/gpu/drm/i915/gvt/firmware.c9
-rw-r--r--drivers/gpu/drm/i915/gvt/gvt.c2
-rw-r--r--drivers/gpu/drm/i915/gvt/gvt.h5
-rw-r--r--drivers/gpu/drm/i915/gvt/kvmgt.c11
-rw-r--r--drivers/gpu/drm/i915/gvt/vgpu.c45
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c2
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h1
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c2
-rw-r--r--drivers/gpu/drm/i915/i915_gem_execbuffer.c4
-rw-r--r--drivers/gpu/drm/i915/i915_gem_gtt.c2
-rw-r--r--drivers/gpu/drm/i915/i915_gem_request.c11
-rw-r--r--drivers/gpu/drm/i915/i915_gem_shrinker.c26
-rw-r--r--drivers/gpu/drm/i915/i915_pci.c5
-rw-r--r--drivers/gpu/drm/i915/i915_perf.c11
-rw-r--r--drivers/gpu/drm/i915/intel_lrc.c57
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.h8
-rw-r--r--drivers/gpu/drm/nouveau/nv50_display.c10
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/base.c32
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c2
-rw-r--r--drivers/gpu/drm/udl/udl_transfer.c3
24 files changed, 180 insertions, 79 deletions
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index da48819ff2e6..b78d9239e48f 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -1317,7 +1317,7 @@ int etnaviv_gpu_submit(struct etnaviv_gpu *gpu,
1317 if (!fence) { 1317 if (!fence) {
1318 event_free(gpu, event); 1318 event_free(gpu, event);
1319 ret = -ENOMEM; 1319 ret = -ENOMEM;
1320 goto out_pm_put; 1320 goto out_unlock;
1321 } 1321 }
1322 1322
1323 gpu->event[event].fence = fence; 1323 gpu->event[event].fence = fence;
@@ -1357,6 +1357,7 @@ int etnaviv_gpu_submit(struct etnaviv_gpu *gpu,
1357 hangcheck_timer_reset(gpu); 1357 hangcheck_timer_reset(gpu);
1358 ret = 0; 1358 ret = 0;
1359 1359
1360out_unlock:
1360 mutex_unlock(&gpu->lock); 1361 mutex_unlock(&gpu->lock);
1361 1362
1362out_pm_put: 1363out_pm_put:
diff --git a/drivers/gpu/drm/i915/gvt/cfg_space.c b/drivers/gpu/drm/i915/gvt/cfg_space.c
index b7d7721e72fa..40af17ec6312 100644
--- a/drivers/gpu/drm/i915/gvt/cfg_space.c
+++ b/drivers/gpu/drm/i915/gvt/cfg_space.c
@@ -285,9 +285,6 @@ int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,
285{ 285{
286 int ret; 286 int ret;
287 287
288 if (vgpu->failsafe)
289 return 0;
290
291 if (WARN_ON(bytes > 4)) 288 if (WARN_ON(bytes > 4))
292 return -EINVAL; 289 return -EINVAL;
293 290
diff --git a/drivers/gpu/drm/i915/gvt/execlist.c b/drivers/gpu/drm/i915/gvt/execlist.c
index f1f426a97aa9..d186c157f65f 100644
--- a/drivers/gpu/drm/i915/gvt/execlist.c
+++ b/drivers/gpu/drm/i915/gvt/execlist.c
@@ -775,7 +775,8 @@ static void init_vgpu_execlist(struct intel_vgpu *vgpu, int ring_id)
775 _EL_OFFSET_STATUS_PTR); 775 _EL_OFFSET_STATUS_PTR);
776 776
777 ctx_status_ptr.dw = vgpu_vreg(vgpu, ctx_status_ptr_reg); 777 ctx_status_ptr.dw = vgpu_vreg(vgpu, ctx_status_ptr_reg);
778 ctx_status_ptr.read_ptr = ctx_status_ptr.write_ptr = 0x7; 778 ctx_status_ptr.read_ptr = 0;
779 ctx_status_ptr.write_ptr = 0x7;
779 vgpu_vreg(vgpu, ctx_status_ptr_reg) = ctx_status_ptr.dw; 780 vgpu_vreg(vgpu, ctx_status_ptr_reg) = ctx_status_ptr.dw;
780} 781}
781 782
diff --git a/drivers/gpu/drm/i915/gvt/firmware.c b/drivers/gpu/drm/i915/gvt/firmware.c
index 933a7c211a1c..dce8d15f706f 100644
--- a/drivers/gpu/drm/i915/gvt/firmware.c
+++ b/drivers/gpu/drm/i915/gvt/firmware.c
@@ -75,11 +75,11 @@ static int expose_firmware_sysfs(struct intel_gvt *gvt)
75 struct gvt_firmware_header *h; 75 struct gvt_firmware_header *h;
76 void *firmware; 76 void *firmware;
77 void *p; 77 void *p;
78 unsigned long size; 78 unsigned long size, crc32_start;
79 int i; 79 int i;
80 int ret; 80 int ret;
81 81
82 size = sizeof(*h) + info->mmio_size + info->cfg_space_size - 1; 82 size = sizeof(*h) + info->mmio_size + info->cfg_space_size;
83 firmware = vzalloc(size); 83 firmware = vzalloc(size);
84 if (!firmware) 84 if (!firmware)
85 return -ENOMEM; 85 return -ENOMEM;
@@ -112,6 +112,9 @@ static int expose_firmware_sysfs(struct intel_gvt *gvt)
112 112
113 memcpy(gvt->firmware.mmio, p, info->mmio_size); 113 memcpy(gvt->firmware.mmio, p, info->mmio_size);
114 114
115 crc32_start = offsetof(struct gvt_firmware_header, crc32) + 4;
116 h->crc32 = crc32_le(0, firmware + crc32_start, size - crc32_start);
117
115 firmware_attr.size = size; 118 firmware_attr.size = size;
116 firmware_attr.private = firmware; 119 firmware_attr.private = firmware;
117 120
@@ -234,7 +237,7 @@ int intel_gvt_load_firmware(struct intel_gvt *gvt)
234 237
235 firmware->mmio = mem; 238 firmware->mmio = mem;
236 239
237 sprintf(path, "%s/vid_0x%04x_did_0x%04x_rid_0x%04x.golden_hw_state", 240 sprintf(path, "%s/vid_0x%04x_did_0x%04x_rid_0x%02x.golden_hw_state",
238 GVT_FIRMWARE_PATH, pdev->vendor, pdev->device, 241 GVT_FIRMWARE_PATH, pdev->vendor, pdev->device,
239 pdev->revision); 242 pdev->revision);
240 243
diff --git a/drivers/gpu/drm/i915/gvt/gvt.c b/drivers/gpu/drm/i915/gvt/gvt.c
index 3b9d59e457ba..ef3baa0c4754 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.c
+++ b/drivers/gpu/drm/i915/gvt/gvt.c
@@ -52,6 +52,8 @@ static const struct intel_gvt_ops intel_gvt_ops = {
52 .vgpu_create = intel_gvt_create_vgpu, 52 .vgpu_create = intel_gvt_create_vgpu,
53 .vgpu_destroy = intel_gvt_destroy_vgpu, 53 .vgpu_destroy = intel_gvt_destroy_vgpu,
54 .vgpu_reset = intel_gvt_reset_vgpu, 54 .vgpu_reset = intel_gvt_reset_vgpu,
55 .vgpu_activate = intel_gvt_activate_vgpu,
56 .vgpu_deactivate = intel_gvt_deactivate_vgpu,
55}; 57};
56 58
57/** 59/**
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 6dfc48b63b71..becae2fa3b29 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -382,7 +382,8 @@ void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu);
382void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr, 382void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
383 unsigned int engine_mask); 383 unsigned int engine_mask);
384void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu); 384void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu);
385 385void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu);
386void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu);
386 387
387/* validating GM functions */ 388/* validating GM functions */
388#define vgpu_gmadr_is_aperture(vgpu, gmadr) \ 389#define vgpu_gmadr_is_aperture(vgpu, gmadr) \
@@ -449,6 +450,8 @@ struct intel_gvt_ops {
449 struct intel_vgpu_type *); 450 struct intel_vgpu_type *);
450 void (*vgpu_destroy)(struct intel_vgpu *); 451 void (*vgpu_destroy)(struct intel_vgpu *);
451 void (*vgpu_reset)(struct intel_vgpu *); 452 void (*vgpu_reset)(struct intel_vgpu *);
453 void (*vgpu_activate)(struct intel_vgpu *);
454 void (*vgpu_deactivate)(struct intel_vgpu *);
452}; 455};
453 456
454 457
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index d641214578a7..e466259034e2 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -544,6 +544,8 @@ static int intel_vgpu_open(struct mdev_device *mdev)
544 if (ret) 544 if (ret)
545 goto undo_group; 545 goto undo_group;
546 546
547 intel_gvt_ops->vgpu_activate(vgpu);
548
547 atomic_set(&vgpu->vdev.released, 0); 549 atomic_set(&vgpu->vdev.released, 0);
548 return ret; 550 return ret;
549 551
@@ -569,6 +571,8 @@ static void __intel_vgpu_release(struct intel_vgpu *vgpu)
569 if (atomic_cmpxchg(&vgpu->vdev.released, 0, 1)) 571 if (atomic_cmpxchg(&vgpu->vdev.released, 0, 1))
570 return; 572 return;
571 573
574 intel_gvt_ops->vgpu_deactivate(vgpu);
575
572 ret = vfio_unregister_notifier(mdev_dev(vgpu->vdev.mdev), VFIO_IOMMU_NOTIFY, 576 ret = vfio_unregister_notifier(mdev_dev(vgpu->vdev.mdev), VFIO_IOMMU_NOTIFY,
573 &vgpu->vdev.iommu_notifier); 577 &vgpu->vdev.iommu_notifier);
574 WARN(ret, "vfio_unregister_notifier for iommu failed: %d\n", ret); 578 WARN(ret, "vfio_unregister_notifier for iommu failed: %d\n", ret);
@@ -1340,13 +1344,6 @@ static int kvmgt_guest_init(struct mdev_device *mdev)
1340 1344
1341static bool kvmgt_guest_exit(struct kvmgt_guest_info *info) 1345static bool kvmgt_guest_exit(struct kvmgt_guest_info *info)
1342{ 1346{
1343 struct intel_vgpu *vgpu = info->vgpu;
1344
1345 if (!info) {
1346 gvt_vgpu_err("kvmgt_guest_info invalid\n");
1347 return false;
1348 }
1349
1350 kvm_page_track_unregister_notifier(info->kvm, &info->track_node); 1347 kvm_page_track_unregister_notifier(info->kvm, &info->track_node);
1351 kvm_put_kvm(info->kvm); 1348 kvm_put_kvm(info->kvm);
1352 kvmgt_protect_table_destroy(info); 1349 kvmgt_protect_table_destroy(info);
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index 41cfa5ccae84..649ef280cc9a 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -72,7 +72,7 @@ static struct {
72 char *name; 72 char *name;
73} vgpu_types[] = { 73} vgpu_types[] = {
74/* Fixed vGPU type table */ 74/* Fixed vGPU type table */
75 { MB_TO_BYTES(64), MB_TO_BYTES(512), 4, GVT_EDID_1024_768, "8" }, 75 { MB_TO_BYTES(64), MB_TO_BYTES(384), 4, GVT_EDID_1024_768, "8" },
76 { MB_TO_BYTES(128), MB_TO_BYTES(512), 4, GVT_EDID_1920_1200, "4" }, 76 { MB_TO_BYTES(128), MB_TO_BYTES(512), 4, GVT_EDID_1920_1200, "4" },
77 { MB_TO_BYTES(256), MB_TO_BYTES(1024), 4, GVT_EDID_1920_1200, "2" }, 77 { MB_TO_BYTES(256), MB_TO_BYTES(1024), 4, GVT_EDID_1920_1200, "2" },
78 { MB_TO_BYTES(512), MB_TO_BYTES(2048), 4, GVT_EDID_1920_1200, "1" }, 78 { MB_TO_BYTES(512), MB_TO_BYTES(2048), 4, GVT_EDID_1920_1200, "1" },
@@ -179,20 +179,34 @@ static void intel_gvt_update_vgpu_types(struct intel_gvt *gvt)
179} 179}
180 180
181/** 181/**
182 * intel_gvt_destroy_vgpu - destroy a virtual GPU 182 * intel_gvt_active_vgpu - activate a virtual GPU
183 * @vgpu: virtual GPU 183 * @vgpu: virtual GPU
184 * 184 *
185 * This function is called when user wants to destroy a virtual GPU. 185 * This function is called when user wants to activate a virtual GPU.
186 * 186 *
187 */ 187 */
188void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu) 188void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu)
189{
190 mutex_lock(&vgpu->gvt->lock);
191 vgpu->active = true;
192 mutex_unlock(&vgpu->gvt->lock);
193}
194
195/**
196 * intel_gvt_deactive_vgpu - deactivate a virtual GPU
197 * @vgpu: virtual GPU
198 *
199 * This function is called when user wants to deactivate a virtual GPU.
200 * All virtual GPU runtime information will be destroyed.
201 *
202 */
203void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu)
189{ 204{
190 struct intel_gvt *gvt = vgpu->gvt; 205 struct intel_gvt *gvt = vgpu->gvt;
191 206
192 mutex_lock(&gvt->lock); 207 mutex_lock(&gvt->lock);
193 208
194 vgpu->active = false; 209 vgpu->active = false;
195 idr_remove(&gvt->vgpu_idr, vgpu->id);
196 210
197 if (atomic_read(&vgpu->running_workload_num)) { 211 if (atomic_read(&vgpu->running_workload_num)) {
198 mutex_unlock(&gvt->lock); 212 mutex_unlock(&gvt->lock);
@@ -201,6 +215,26 @@ void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu)
201 } 215 }
202 216
203 intel_vgpu_stop_schedule(vgpu); 217 intel_vgpu_stop_schedule(vgpu);
218
219 mutex_unlock(&gvt->lock);
220}
221
222/**
223 * intel_gvt_destroy_vgpu - destroy a virtual GPU
224 * @vgpu: virtual GPU
225 *
226 * This function is called when user wants to destroy a virtual GPU.
227 *
228 */
229void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu)
230{
231 struct intel_gvt *gvt = vgpu->gvt;
232
233 mutex_lock(&gvt->lock);
234
235 WARN(vgpu->active, "vGPU is still active!\n");
236
237 idr_remove(&gvt->vgpu_idr, vgpu->id);
204 intel_vgpu_clean_sched_policy(vgpu); 238 intel_vgpu_clean_sched_policy(vgpu);
205 intel_vgpu_clean_gvt_context(vgpu); 239 intel_vgpu_clean_gvt_context(vgpu);
206 intel_vgpu_clean_execlist(vgpu); 240 intel_vgpu_clean_execlist(vgpu);
@@ -277,7 +311,6 @@ static struct intel_vgpu *__intel_gvt_create_vgpu(struct intel_gvt *gvt,
277 if (ret) 311 if (ret)
278 goto out_clean_shadow_ctx; 312 goto out_clean_shadow_ctx;
279 313
280 vgpu->active = true;
281 mutex_unlock(&gvt->lock); 314 mutex_unlock(&gvt->lock);
282 315
283 return vgpu; 316 return vgpu;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1c75402a59c1..5c089b3c2a7e 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1434,8 +1434,6 @@ static int i915_drm_suspend(struct drm_device *dev)
1434 goto out; 1434 goto out;
1435 } 1435 }
1436 1436
1437 intel_guc_suspend(dev_priv);
1438
1439 intel_display_suspend(dev); 1437 intel_display_suspend(dev);
1440 1438
1441 intel_dp_mst_suspend(dev); 1439 intel_dp_mst_suspend(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1e53c31b6826..46fcd8b7080a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -806,6 +806,7 @@ struct intel_csr {
806 func(has_resource_streamer); \ 806 func(has_resource_streamer); \
807 func(has_runtime_pm); \ 807 func(has_runtime_pm); \
808 func(has_snoop); \ 808 func(has_snoop); \
809 func(unfenced_needs_alignment); \
809 func(cursor_needs_physical); \ 810 func(cursor_needs_physical); \
810 func(hws_needs_physical); \ 811 func(hws_needs_physical); \
811 func(overlay_needs_physical); \ 812 func(overlay_needs_physical); \
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 67b1fc5a0331..fe531f904062 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4348,6 +4348,8 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
4348 i915_gem_context_lost(dev_priv); 4348 i915_gem_context_lost(dev_priv);
4349 mutex_unlock(&dev->struct_mutex); 4349 mutex_unlock(&dev->struct_mutex);
4350 4350
4351 intel_guc_suspend(dev_priv);
4352
4351 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); 4353 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4352 cancel_delayed_work_sync(&dev_priv->gt.retire_work); 4354 cancel_delayed_work_sync(&dev_priv->gt.retire_work);
4353 4355
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 30e0675fd7da..15a15d00a6bf 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -888,6 +888,7 @@ i915_gem_execbuffer_reserve(struct intel_engine_cs *engine,
888 struct list_head ordered_vmas; 888 struct list_head ordered_vmas;
889 struct list_head pinned_vmas; 889 struct list_head pinned_vmas;
890 bool has_fenced_gpu_access = INTEL_GEN(engine->i915) < 4; 890 bool has_fenced_gpu_access = INTEL_GEN(engine->i915) < 4;
891 bool needs_unfenced_map = INTEL_INFO(engine->i915)->unfenced_needs_alignment;
891 int retry; 892 int retry;
892 893
893 vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm; 894 vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm;
@@ -908,7 +909,8 @@ i915_gem_execbuffer_reserve(struct intel_engine_cs *engine,
908 if (!has_fenced_gpu_access) 909 if (!has_fenced_gpu_access)
909 entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE; 910 entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
910 need_fence = 911 need_fence =
911 entry->flags & EXEC_OBJECT_NEEDS_FENCE && 912 (entry->flags & EXEC_OBJECT_NEEDS_FENCE ||
913 needs_unfenced_map) &&
912 i915_gem_object_is_tiled(obj); 914 i915_gem_object_is_tiled(obj);
913 need_mappable = need_fence || need_reloc_mappable(vma); 915 need_mappable = need_fence || need_reloc_mappable(vma);
914 916
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 2801a4d56324..96e45a4d5441 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2704,7 +2704,7 @@ void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj,
2704 struct i915_ggtt *ggtt = &dev_priv->ggtt; 2704 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2705 2705
2706 if (unlikely(ggtt->do_idle_maps)) { 2706 if (unlikely(ggtt->do_idle_maps)) {
2707 if (i915_gem_wait_for_idle(dev_priv, I915_WAIT_LOCKED)) { 2707 if (i915_gem_wait_for_idle(dev_priv, 0)) {
2708 DRM_ERROR("Failed to wait for idle; VT'd may hang.\n"); 2708 DRM_ERROR("Failed to wait for idle; VT'd may hang.\n");
2709 /* Wait a bit, in hopes it avoids the hang */ 2709 /* Wait a bit, in hopes it avoids the hang */
2710 udelay(10); 2710 udelay(10);
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
index e7c3c0318ff6..da70bfe97ec5 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -37,6 +37,17 @@ static const char *i915_fence_get_driver_name(struct dma_fence *fence)
37 37
38static const char *i915_fence_get_timeline_name(struct dma_fence *fence) 38static const char *i915_fence_get_timeline_name(struct dma_fence *fence)
39{ 39{
40 /* The timeline struct (as part of the ppgtt underneath a context)
41 * may be freed when the request is no longer in use by the GPU.
42 * We could extend the life of a context to beyond that of all
43 * fences, possibly keeping the hw resource around indefinitely,
44 * or we just give them a false name. Since
45 * dma_fence_ops.get_timeline_name is a debug feature, the occasional
46 * lie seems justifiable.
47 */
48 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
49 return "signaled";
50
40 return to_request(fence)->timeline->common->name; 51 return to_request(fence)->timeline->common->name;
41} 52}
42 53
diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c b/drivers/gpu/drm/i915/i915_gem_shrinker.c
index d5d2b4c6ed38..70b3832a79dd 100644
--- a/drivers/gpu/drm/i915/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c
@@ -53,6 +53,17 @@ static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock)
53 BUG(); 53 BUG();
54} 54}
55 55
56static void i915_gem_shrinker_unlock(struct drm_device *dev, bool unlock)
57{
58 if (!unlock)
59 return;
60
61 mutex_unlock(&dev->struct_mutex);
62
63 /* expedite the RCU grace period to free some request slabs */
64 synchronize_rcu_expedited();
65}
66
56static bool any_vma_pinned(struct drm_i915_gem_object *obj) 67static bool any_vma_pinned(struct drm_i915_gem_object *obj)
57{ 68{
58 struct i915_vma *vma; 69 struct i915_vma *vma;
@@ -232,11 +243,8 @@ i915_gem_shrink(struct drm_i915_private *dev_priv,
232 intel_runtime_pm_put(dev_priv); 243 intel_runtime_pm_put(dev_priv);
233 244
234 i915_gem_retire_requests(dev_priv); 245 i915_gem_retire_requests(dev_priv);
235 if (unlock)
236 mutex_unlock(&dev_priv->drm.struct_mutex);
237 246
238 /* expedite the RCU grace period to free some request slabs */ 247 i915_gem_shrinker_unlock(&dev_priv->drm, unlock);
239 synchronize_rcu_expedited();
240 248
241 return count; 249 return count;
242} 250}
@@ -293,8 +301,7 @@ i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc)
293 count += obj->base.size >> PAGE_SHIFT; 301 count += obj->base.size >> PAGE_SHIFT;
294 } 302 }
295 303
296 if (unlock) 304 i915_gem_shrinker_unlock(dev, unlock);
297 mutex_unlock(&dev->struct_mutex);
298 305
299 return count; 306 return count;
300} 307}
@@ -321,8 +328,8 @@ i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc)
321 sc->nr_to_scan - freed, 328 sc->nr_to_scan - freed,
322 I915_SHRINK_BOUND | 329 I915_SHRINK_BOUND |
323 I915_SHRINK_UNBOUND); 330 I915_SHRINK_UNBOUND);
324 if (unlock) 331
325 mutex_unlock(&dev->struct_mutex); 332 i915_gem_shrinker_unlock(dev, unlock);
326 333
327 return freed; 334 return freed;
328} 335}
@@ -364,8 +371,7 @@ i915_gem_shrinker_unlock_uninterruptible(struct drm_i915_private *dev_priv,
364 struct shrinker_lock_uninterruptible *slu) 371 struct shrinker_lock_uninterruptible *slu)
365{ 372{
366 dev_priv->mm.interruptible = slu->was_interruptible; 373 dev_priv->mm.interruptible = slu->was_interruptible;
367 if (slu->unlock) 374 i915_gem_shrinker_unlock(&dev_priv->drm, slu->unlock);
368 mutex_unlock(&dev_priv->drm.struct_mutex);
369} 375}
370 376
371static int 377static int
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index ecb487b5356f..9bbbd4e83e3c 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -60,6 +60,7 @@
60 .has_overlay = 1, .overlay_needs_physical = 1, \ 60 .has_overlay = 1, .overlay_needs_physical = 1, \
61 .has_gmch_display = 1, \ 61 .has_gmch_display = 1, \
62 .hws_needs_physical = 1, \ 62 .hws_needs_physical = 1, \
63 .unfenced_needs_alignment = 1, \
63 .ring_mask = RENDER_RING, \ 64 .ring_mask = RENDER_RING, \
64 GEN_DEFAULT_PIPEOFFSETS, \ 65 GEN_DEFAULT_PIPEOFFSETS, \
65 CURSOR_OFFSETS 66 CURSOR_OFFSETS
@@ -101,6 +102,7 @@ static const struct intel_device_info intel_i915g_info = {
101 .platform = INTEL_I915G, .cursor_needs_physical = 1, 102 .platform = INTEL_I915G, .cursor_needs_physical = 1,
102 .has_overlay = 1, .overlay_needs_physical = 1, 103 .has_overlay = 1, .overlay_needs_physical = 1,
103 .hws_needs_physical = 1, 104 .hws_needs_physical = 1,
105 .unfenced_needs_alignment = 1,
104}; 106};
105 107
106static const struct intel_device_info intel_i915gm_info = { 108static const struct intel_device_info intel_i915gm_info = {
@@ -112,6 +114,7 @@ static const struct intel_device_info intel_i915gm_info = {
112 .supports_tv = 1, 114 .supports_tv = 1,
113 .has_fbc = 1, 115 .has_fbc = 1,
114 .hws_needs_physical = 1, 116 .hws_needs_physical = 1,
117 .unfenced_needs_alignment = 1,
115}; 118};
116 119
117static const struct intel_device_info intel_i945g_info = { 120static const struct intel_device_info intel_i945g_info = {
@@ -120,6 +123,7 @@ static const struct intel_device_info intel_i945g_info = {
120 .has_hotplug = 1, .cursor_needs_physical = 1, 123 .has_hotplug = 1, .cursor_needs_physical = 1,
121 .has_overlay = 1, .overlay_needs_physical = 1, 124 .has_overlay = 1, .overlay_needs_physical = 1,
122 .hws_needs_physical = 1, 125 .hws_needs_physical = 1,
126 .unfenced_needs_alignment = 1,
123}; 127};
124 128
125static const struct intel_device_info intel_i945gm_info = { 129static const struct intel_device_info intel_i945gm_info = {
@@ -130,6 +134,7 @@ static const struct intel_device_info intel_i945gm_info = {
130 .supports_tv = 1, 134 .supports_tv = 1,
131 .has_fbc = 1, 135 .has_fbc = 1,
132 .hws_needs_physical = 1, 136 .hws_needs_physical = 1,
137 .unfenced_needs_alignment = 1,
133}; 138};
134 139
135static const struct intel_device_info intel_g33_info = { 140static const struct intel_device_info intel_g33_info = {
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index a1b7eec58be2..70964ca9251e 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1705,7 +1705,7 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv,
1705 */ 1705 */
1706 if (WARN_ON(stream->sample_flags != props->sample_flags)) { 1706 if (WARN_ON(stream->sample_flags != props->sample_flags)) {
1707 ret = -ENODEV; 1707 ret = -ENODEV;
1708 goto err_alloc; 1708 goto err_flags;
1709 } 1709 }
1710 1710
1711 list_add(&stream->link, &dev_priv->perf.streams); 1711 list_add(&stream->link, &dev_priv->perf.streams);
@@ -1728,6 +1728,7 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv,
1728 1728
1729err_open: 1729err_open:
1730 list_del(&stream->link); 1730 list_del(&stream->link);
1731err_flags:
1731 if (stream->ops->destroy) 1732 if (stream->ops->destroy)
1732 stream->ops->destroy(stream); 1733 stream->ops->destroy(stream);
1733err_alloc: 1734err_alloc:
@@ -1793,6 +1794,11 @@ static int read_properties_unlocked(struct drm_i915_private *dev_priv,
1793 if (ret) 1794 if (ret)
1794 return ret; 1795 return ret;
1795 1796
1797 if (id == 0 || id >= DRM_I915_PERF_PROP_MAX) {
1798 DRM_DEBUG("Unknown i915 perf property ID\n");
1799 return -EINVAL;
1800 }
1801
1796 switch ((enum drm_i915_perf_property_id)id) { 1802 switch ((enum drm_i915_perf_property_id)id) {
1797 case DRM_I915_PERF_PROP_CTX_HANDLE: 1803 case DRM_I915_PERF_PROP_CTX_HANDLE:
1798 props->single_context = 1; 1804 props->single_context = 1;
@@ -1862,9 +1868,8 @@ static int read_properties_unlocked(struct drm_i915_private *dev_priv,
1862 props->oa_periodic = true; 1868 props->oa_periodic = true;
1863 props->oa_period_exponent = value; 1869 props->oa_period_exponent = value;
1864 break; 1870 break;
1865 default: 1871 case DRM_I915_PERF_PROP_MAX:
1866 MISSING_CASE(id); 1872 MISSING_CASE(id);
1867 DRM_DEBUG("Unknown i915 perf property ID\n");
1868 return -EINVAL; 1873 return -EINVAL;
1869 } 1874 }
1870 1875
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 471af3b480ad..47517a02f0a4 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -670,15 +670,14 @@ static void execlists_submit_request(struct drm_i915_gem_request *request)
670static struct intel_engine_cs * 670static struct intel_engine_cs *
671pt_lock_engine(struct i915_priotree *pt, struct intel_engine_cs *locked) 671pt_lock_engine(struct i915_priotree *pt, struct intel_engine_cs *locked)
672{ 672{
673 struct intel_engine_cs *engine; 673 struct intel_engine_cs *engine =
674 container_of(pt, struct drm_i915_gem_request, priotree)->engine;
675
676 GEM_BUG_ON(!locked);
674 677
675 engine = container_of(pt,
676 struct drm_i915_gem_request,
677 priotree)->engine;
678 if (engine != locked) { 678 if (engine != locked) {
679 if (locked) 679 spin_unlock(&locked->timeline->lock);
680 spin_unlock_irq(&locked->timeline->lock); 680 spin_lock(&engine->timeline->lock);
681 spin_lock_irq(&engine->timeline->lock);
682 } 681 }
683 682
684 return engine; 683 return engine;
@@ -686,7 +685,7 @@ pt_lock_engine(struct i915_priotree *pt, struct intel_engine_cs *locked)
686 685
687static void execlists_schedule(struct drm_i915_gem_request *request, int prio) 686static void execlists_schedule(struct drm_i915_gem_request *request, int prio)
688{ 687{
689 struct intel_engine_cs *engine = NULL; 688 struct intel_engine_cs *engine;
690 struct i915_dependency *dep, *p; 689 struct i915_dependency *dep, *p;
691 struct i915_dependency stack; 690 struct i915_dependency stack;
692 LIST_HEAD(dfs); 691 LIST_HEAD(dfs);
@@ -720,26 +719,23 @@ static void execlists_schedule(struct drm_i915_gem_request *request, int prio)
720 list_for_each_entry_safe(dep, p, &dfs, dfs_link) { 719 list_for_each_entry_safe(dep, p, &dfs, dfs_link) {
721 struct i915_priotree *pt = dep->signaler; 720 struct i915_priotree *pt = dep->signaler;
722 721
723 list_for_each_entry(p, &pt->signalers_list, signal_link) 722 /* Within an engine, there can be no cycle, but we may
723 * refer to the same dependency chain multiple times
724 * (redundant dependencies are not eliminated) and across
725 * engines.
726 */
727 list_for_each_entry(p, &pt->signalers_list, signal_link) {
728 GEM_BUG_ON(p->signaler->priority < pt->priority);
724 if (prio > READ_ONCE(p->signaler->priority)) 729 if (prio > READ_ONCE(p->signaler->priority))
725 list_move_tail(&p->dfs_link, &dfs); 730 list_move_tail(&p->dfs_link, &dfs);
731 }
726 732
727 list_safe_reset_next(dep, p, dfs_link); 733 list_safe_reset_next(dep, p, dfs_link);
728 if (!RB_EMPTY_NODE(&pt->node))
729 continue;
730
731 engine = pt_lock_engine(pt, engine);
732
733 /* If it is not already in the rbtree, we can update the
734 * priority inplace and skip over it (and its dependencies)
735 * if it is referenced *again* as we descend the dfs.
736 */
737 if (prio > pt->priority && RB_EMPTY_NODE(&pt->node)) {
738 pt->priority = prio;
739 list_del_init(&dep->dfs_link);
740 }
741 } 734 }
742 735
736 engine = request->engine;
737 spin_lock_irq(&engine->timeline->lock);
738
743 /* Fifo and depth-first replacement ensure our deps execute before us */ 739 /* Fifo and depth-first replacement ensure our deps execute before us */
744 list_for_each_entry_safe_reverse(dep, p, &dfs, dfs_link) { 740 list_for_each_entry_safe_reverse(dep, p, &dfs, dfs_link) {
745 struct i915_priotree *pt = dep->signaler; 741 struct i915_priotree *pt = dep->signaler;
@@ -751,16 +747,15 @@ static void execlists_schedule(struct drm_i915_gem_request *request, int prio)
751 if (prio <= pt->priority) 747 if (prio <= pt->priority)
752 continue; 748 continue;
753 749
754 GEM_BUG_ON(RB_EMPTY_NODE(&pt->node));
755
756 pt->priority = prio; 750 pt->priority = prio;
757 rb_erase(&pt->node, &engine->execlist_queue); 751 if (!RB_EMPTY_NODE(&pt->node)) {
758 if (insert_request(pt, &engine->execlist_queue)) 752 rb_erase(&pt->node, &engine->execlist_queue);
759 engine->execlist_first = &pt->node; 753 if (insert_request(pt, &engine->execlist_queue))
754 engine->execlist_first = &pt->node;
755 }
760 } 756 }
761 757
762 if (engine) 758 spin_unlock_irq(&engine->timeline->lock);
763 spin_unlock_irq(&engine->timeline->lock);
764 759
765 /* XXX Do we need to preempt to make room for us and our deps? */ 760 /* XXX Do we need to preempt to make room for us and our deps? */
766} 761}
@@ -1440,7 +1435,9 @@ static void reset_common_ring(struct intel_engine_cs *engine,
1440 GEM_BUG_ON(request->ctx != port[0].request->ctx); 1435 GEM_BUG_ON(request->ctx != port[0].request->ctx);
1441 1436
1442 /* Reset WaIdleLiteRestore:bdw,skl as well */ 1437 /* Reset WaIdleLiteRestore:bdw,skl as well */
1443 request->tail = request->wa_tail - WA_TAIL_DWORDS * sizeof(u32); 1438 request->tail =
1439 intel_ring_wrap(request->ring,
1440 request->wa_tail - WA_TAIL_DWORDS*sizeof(u32));
1444} 1441}
1445 1442
1446static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req) 1443static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 13dccb18cd43..8cb2078c5bfc 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -521,11 +521,17 @@ static inline void intel_ring_advance(struct intel_ring *ring)
521 */ 521 */
522} 522}
523 523
524static inline u32
525intel_ring_wrap(const struct intel_ring *ring, u32 pos)
526{
527 return pos & (ring->size - 1);
528}
529
524static inline u32 intel_ring_offset(struct intel_ring *ring, void *addr) 530static inline u32 intel_ring_offset(struct intel_ring *ring, void *addr)
525{ 531{
526 /* Don't write ring->size (equivalent to 0) as that hangs some GPUs. */ 532 /* Don't write ring->size (equivalent to 0) as that hangs some GPUs. */
527 u32 offset = addr - ring->vaddr; 533 u32 offset = addr - ring->vaddr;
528 return offset & (ring->size - 1); 534 return intel_ring_wrap(ring, offset);
529} 535}
530 536
531int __intel_ring_space(int head, int tail, int size); 537int __intel_ring_space(int head, int tail, int size);
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index 0b4440ffbeae..a9182d5e6011 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -995,7 +995,6 @@ nv50_wndw_atomic_destroy_state(struct drm_plane *plane,
995{ 995{
996 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state); 996 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
997 __drm_atomic_helper_plane_destroy_state(&asyw->state); 997 __drm_atomic_helper_plane_destroy_state(&asyw->state);
998 dma_fence_put(asyw->state.fence);
999 kfree(asyw); 998 kfree(asyw);
1000} 999}
1001 1000
@@ -1007,7 +1006,6 @@ nv50_wndw_atomic_duplicate_state(struct drm_plane *plane)
1007 if (!(asyw = kmalloc(sizeof(*asyw), GFP_KERNEL))) 1006 if (!(asyw = kmalloc(sizeof(*asyw), GFP_KERNEL)))
1008 return NULL; 1007 return NULL;
1009 __drm_atomic_helper_plane_duplicate_state(plane, &asyw->state); 1008 __drm_atomic_helper_plane_duplicate_state(plane, &asyw->state);
1010 asyw->state.fence = NULL;
1011 asyw->interval = 1; 1009 asyw->interval = 1;
1012 asyw->sema = armw->sema; 1010 asyw->sema = armw->sema;
1013 asyw->ntfy = armw->ntfy; 1011 asyw->ntfy = armw->ntfy;
@@ -2036,6 +2034,7 @@ nv50_head_atomic_check_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
2036 u32 vbackp = (mode->vtotal - mode->vsync_end) * vscan / ilace; 2034 u32 vbackp = (mode->vtotal - mode->vsync_end) * vscan / ilace;
2037 u32 hfrontp = mode->hsync_start - mode->hdisplay; 2035 u32 hfrontp = mode->hsync_start - mode->hdisplay;
2038 u32 vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace; 2036 u32 vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
2037 u32 blankus;
2039 struct nv50_head_mode *m = &asyh->mode; 2038 struct nv50_head_mode *m = &asyh->mode;
2040 2039
2041 m->h.active = mode->htotal; 2040 m->h.active = mode->htotal;
@@ -2049,9 +2048,10 @@ nv50_head_atomic_check_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
2049 m->v.blanks = m->v.active - vfrontp - 1; 2048 m->v.blanks = m->v.active - vfrontp - 1;
2050 2049
2051 /*XXX: Safe underestimate, even "0" works */ 2050 /*XXX: Safe underestimate, even "0" works */
2052 m->v.blankus = (m->v.active - mode->vdisplay - 2) * m->h.active; 2051 blankus = (m->v.active - mode->vdisplay - 2) * m->h.active;
2053 m->v.blankus *= 1000; 2052 blankus *= 1000;
2054 m->v.blankus /= mode->clock; 2053 blankus /= mode->clock;
2054 m->v.blankus = blankus;
2055 2055
2056 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 2056 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
2057 m->v.blank2e = m->v.active + m->v.synce + vbackp; 2057 m->v.blank2e = m->v.active + m->v.synce + vbackp;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
index 273562dd6bbd..3b86a7399567 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
@@ -714,7 +714,7 @@ nv4a_chipset = {
714 .i2c = nv04_i2c_new, 714 .i2c = nv04_i2c_new,
715 .imem = nv40_instmem_new, 715 .imem = nv40_instmem_new,
716 .mc = nv44_mc_new, 716 .mc = nv44_mc_new,
717 .mmu = nv44_mmu_new, 717 .mmu = nv04_mmu_new,
718 .pci = nv40_pci_new, 718 .pci = nv40_pci_new,
719 .therm = nv40_therm_new, 719 .therm = nv40_therm_new,
720 .timer = nv41_timer_new, 720 .timer = nv41_timer_new,
@@ -2271,6 +2271,35 @@ nv136_chipset = {
2271 .fifo = gp100_fifo_new, 2271 .fifo = gp100_fifo_new,
2272}; 2272};
2273 2273
2274static const struct nvkm_device_chip
2275nv137_chipset = {
2276 .name = "GP107",
2277 .bar = gf100_bar_new,
2278 .bios = nvkm_bios_new,
2279 .bus = gf100_bus_new,
2280 .devinit = gm200_devinit_new,
2281 .fb = gp102_fb_new,
2282 .fuse = gm107_fuse_new,
2283 .gpio = gk104_gpio_new,
2284 .i2c = gm200_i2c_new,
2285 .ibus = gm200_ibus_new,
2286 .imem = nv50_instmem_new,
2287 .ltc = gp100_ltc_new,
2288 .mc = gp100_mc_new,
2289 .mmu = gf100_mmu_new,
2290 .pci = gp100_pci_new,
2291 .pmu = gp102_pmu_new,
2292 .timer = gk20a_timer_new,
2293 .top = gk104_top_new,
2294 .ce[0] = gp102_ce_new,
2295 .ce[1] = gp102_ce_new,
2296 .ce[2] = gp102_ce_new,
2297 .ce[3] = gp102_ce_new,
2298 .disp = gp102_disp_new,
2299 .dma = gf119_dma_new,
2300 .fifo = gp100_fifo_new,
2301};
2302
2274static int 2303static int
2275nvkm_device_event_ctor(struct nvkm_object *object, void *data, u32 size, 2304nvkm_device_event_ctor(struct nvkm_object *object, void *data, u32 size,
2276 struct nvkm_notify *notify) 2305 struct nvkm_notify *notify)
@@ -2708,6 +2737,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
2708 case 0x132: device->chip = &nv132_chipset; break; 2737 case 0x132: device->chip = &nv132_chipset; break;
2709 case 0x134: device->chip = &nv134_chipset; break; 2738 case 0x134: device->chip = &nv134_chipset; break;
2710 case 0x136: device->chip = &nv136_chipset; break; 2739 case 0x136: device->chip = &nv136_chipset; break;
2740 case 0x137: device->chip = &nv137_chipset; break;
2711 default: 2741 default:
2712 nvdev_error(device, "unknown chipset (%08x)\n", boot0); 2742 nvdev_error(device, "unknown chipset (%08x)\n", boot0);
2713 goto done; 2743 goto done;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c
index 003ac915eaad..8a8895246d26 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c
@@ -198,7 +198,7 @@ nv31_mpeg_intr(struct nvkm_engine *engine)
198 } 198 }
199 199
200 if (type == 0x00000010) { 200 if (type == 0x00000010) {
201 if (!nv31_mpeg_mthd(mpeg, mthd, data)) 201 if (nv31_mpeg_mthd(mpeg, mthd, data))
202 show &= ~0x01000000; 202 show &= ~0x01000000;
203 } 203 }
204 } 204 }
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c
index e536f37e24b0..c3cf02ed468e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c
@@ -172,7 +172,7 @@ nv44_mpeg_intr(struct nvkm_engine *engine)
172 } 172 }
173 173
174 if (type == 0x00000010) { 174 if (type == 0x00000010) {
175 if (!nv44_mpeg_mthd(subdev->device, mthd, data)) 175 if (nv44_mpeg_mthd(subdev->device, mthd, data))
176 show &= ~0x01000000; 176 show &= ~0x01000000;
177 } 177 }
178 } 178 }
diff --git a/drivers/gpu/drm/udl/udl_transfer.c b/drivers/gpu/drm/udl/udl_transfer.c
index 917dcb978c2c..0c87b1ac6b68 100644
--- a/drivers/gpu/drm/udl/udl_transfer.c
+++ b/drivers/gpu/drm/udl/udl_transfer.c
@@ -14,6 +14,7 @@
14#include <linux/slab.h> 14#include <linux/slab.h>
15#include <linux/fb.h> 15#include <linux/fb.h>
16#include <linux/prefetch.h> 16#include <linux/prefetch.h>
17#include <asm/unaligned.h>
17 18
18#include <drm/drmP.h> 19#include <drm/drmP.h>
19#include "udl_drv.h" 20#include "udl_drv.h"
@@ -163,7 +164,7 @@ static void udl_compress_hline16(
163 const u8 *const start = pixel; 164 const u8 *const start = pixel;
164 const uint16_t repeating_pixel_val16 = pixel_val16; 165 const uint16_t repeating_pixel_val16 = pixel_val16;
165 166
166 *(uint16_t *)cmd = cpu_to_be16(pixel_val16); 167 put_unaligned_be16(pixel_val16, cmd);
167 168
168 cmd += 2; 169 cmd += 2;
169 pixel += bpp; 170 pixel += bpp;