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authorDavid S. Miller <davem@davemloft.net>2016-07-26 00:51:44 -0400
committerDavid S. Miller <davem@davemloft.net>2016-07-26 00:51:44 -0400
commitee591f46a5a0ca0caaeb72b79ec5e012c6e3c9ef (patch)
treeed3f955b3ce6ab5c4170b7c16a56915ef775c5c9
parentc43212bb7bebe24a93a7a7d86e767e1ce295d72a (diff)
parent2efccc601c1c139cb88e3e5d0a6f4402fd040c46 (diff)
Merge branch 'xgene-fix-mod-crash-and-1g-hotplug'
Iyappan Subramanian says: ==================== drivers: net: xgene: Fix module crash and 1G hot-plug This patchset addresses the following issues, 1. Fixes the kernel crash when the driver loaded as an kernel module - by fixing hardware cleanups and rearrange kernel API calls 2. Hot-plug issue on the SGMII 1G interface - by adding a driver for MDIO management Signed-off-by: Iyappan Subramanian <isubramanian@apm.com> Tested-by: Fushen Chen <fchen@apm.com> Tested-by: Toan Le <toanle@apm.com> --- v7: Address review comments from v6 - fixed kbuild warnings - unmapped DMA memory on xgene_enet_delete_bufpool() - delete descriptor rings and buffer pools on cle_init() failure - fixed error deconstruction path on probe v6: Address review comments from v5 - changed to use devm_ioremap_resource - changed to return PTR_ERR(clk) on failure - cleaned up and removed indirections - exported mdio read/write and phy_register functions - changed mii_bus is to indicate interface instance - changed to call the exported mdio read/write and phy_register functions v5: Address review comments from v4 - Fixed clock reset sequence by adding delay - Fixed clock count by adding clk_unprepare_disable() in port shutdown v4: Address review comments from v3 - Reorganized into smaller patches - Added wrapper functions for sgmii_control_reset and sgmii_tbi_control_reset - Removed clk_get warning info - mdio: Changed the order of 'if' statements and removed the 'else' statement - mdio: Removed the mdio_read(write) indirection wrapper functions - ethtool: Fixed SGMII 1G get_settings and set_settings - Documentation: dtb: Added MDIO node information - MAINTAINERS: Added MDIO driver and documentation path v3: Address review comments from v2 - Add comment about hardware clock reset sequence on xgene_mdio_reset v2: Address review comments from v1 - Fixed patch 1 compilation error - Fixed mdio@1f610000 xge0clk reference - Squashed dtb patches - Added PORT_OFFSET macro v1: - Initial version ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--Documentation/devicetree/bindings/net/apm-xgene-mdio.txt37
-rw-r--r--MAINTAINERS2
-rw-r--r--arch/arm64/boot/dts/apm/apm-merlin.dts6
-rw-r--r--arch/arm64/boot/dts/apm/apm-mustang.dts12
-rw-r--r--arch/arm64/boot/dts/apm/apm-shadowcat.dtsi11
-rw-r--r--arch/arm64/boot/dts/apm/apm-storm.dtsi26
-rw-r--r--drivers/net/ethernet/apm/xgene/Kconfig1
-rw-r--r--drivers/net/ethernet/apm/xgene/xgene_enet_ethtool.c22
-rw-r--r--drivers/net/ethernet/apm/xgene/xgene_enet_hw.c255
-rw-r--r--drivers/net/ethernet/apm/xgene/xgene_enet_hw.h11
-rw-r--r--drivers/net/ethernet/apm/xgene/xgene_enet_main.c215
-rw-r--r--drivers/net/ethernet/apm/xgene/xgene_enet_main.h33
-rw-r--r--drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.c239
-rw-r--r--drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.h8
-rw-r--r--drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c66
-rw-r--r--drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h3
-rw-r--r--drivers/net/phy/Kconfig6
-rw-r--r--drivers/net/phy/Makefile1
-rw-r--r--drivers/net/phy/mdio-xgene.c477
-rw-r--r--drivers/net/phy/mdio-xgene.h143
20 files changed, 1291 insertions, 283 deletions
diff --git a/Documentation/devicetree/bindings/net/apm-xgene-mdio.txt b/Documentation/devicetree/bindings/net/apm-xgene-mdio.txt
new file mode 100644
index 000000000000..78722d74cea8
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/apm-xgene-mdio.txt
@@ -0,0 +1,37 @@
1APM X-Gene SoC MDIO node
2
3MDIO node is defined to describe on-chip MDIO controller.
4
5Required properties:
6 - compatible: Must be "apm,xgene-mdio-rgmii" or "apm,xgene-mdio-xfi"
7 - #address-cells: Must be <1>.
8 - #size-cells: Must be <0>.
9 - reg: Address and length of the register set
10 - clocks: Reference to the clock entry
11
12For the phys on the mdio bus, there must be a node with the following fields:
13 - compatible: PHY identifier. Please refer ./phy.txt for the format.
14 - reg: The ID number for the phy.
15
16Example:
17
18 mdio: mdio@17020000 {
19 compatible = "apm,xgene-mdio-rgmii";
20 #address-cells = <1>;
21 #size-cells = <0>;
22 reg = <0x0 0x17020000 0x0 0xd100>;
23 clocks = <&menetclk 0>;
24 };
25
26 /* Board-specific peripheral configurations */
27 &mdio {
28 menetphy: phy@3 {
29 reg = <0x3>;
30 };
31 sgenet0phy: phy@4 {
32 reg = <0x4>;
33 };
34 sgenet1phy: phy@5 {
35 reg = <0x5>;
36 };
37 };
diff --git a/MAINTAINERS b/MAINTAINERS
index dc3481d7c80d..a9bdba0484d1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -839,7 +839,9 @@ M: Iyappan Subramanian <isubramanian@apm.com>
839M: Keyur Chudgar <kchudgar@apm.com> 839M: Keyur Chudgar <kchudgar@apm.com>
840S: Supported 840S: Supported
841F: drivers/net/ethernet/apm/xgene/ 841F: drivers/net/ethernet/apm/xgene/
842F: drivers/net/phy/mdio-xgene.c
842F: Documentation/devicetree/bindings/net/apm-xgene-enet.txt 843F: Documentation/devicetree/bindings/net/apm-xgene-enet.txt
844F: Documentation/devicetree/bindings/net/apm-xgene-mdio.txt
843 845
844APTINA CAMERA SENSOR PLL 846APTINA CAMERA SENSOR PLL
845M: Laurent Pinchart <Laurent.pinchart@ideasonboard.com> 847M: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
diff --git a/arch/arm64/boot/dts/apm/apm-merlin.dts b/arch/arm64/boot/dts/apm/apm-merlin.dts
index 387c6a8d0da9..b0f64414c1b0 100644
--- a/arch/arm64/boot/dts/apm/apm-merlin.dts
+++ b/arch/arm64/boot/dts/apm/apm-merlin.dts
@@ -83,3 +83,9 @@
83 status = "ok"; 83 status = "ok";
84 }; 84 };
85}; 85};
86
87&mdio {
88 sgenet0phy: phy@0 {
89 reg = <0x0>;
90 };
91};
diff --git a/arch/arm64/boot/dts/apm/apm-mustang.dts b/arch/arm64/boot/dts/apm/apm-mustang.dts
index 44db32ec5e9c..b7fb5d9295c2 100644
--- a/arch/arm64/boot/dts/apm/apm-mustang.dts
+++ b/arch/arm64/boot/dts/apm/apm-mustang.dts
@@ -79,3 +79,15 @@
79&mmc0 { 79&mmc0 {
80 status = "ok"; 80 status = "ok";
81}; 81};
82
83&mdio {
84 menet0phy: phy@3 {
85 reg = <0x3>;
86 };
87 sgenet0phy: phy@4 {
88 reg = <0x4>;
89 };
90 sgenet1phy: phy@5 {
91 reg = <0x5>;
92 };
93};
diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
index c569f761d090..2e1e5daa1dc7 100644
--- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
@@ -625,10 +625,18 @@
625 apm,irq-start = <8>; 625 apm,irq-start = <8>;
626 }; 626 };
627 627
628 mdio: mdio@1f610000 {
629 compatible = "apm,xgene-mdio-xfi";
630 #address-cells = <1>;
631 #size-cells = <0>;
632 reg = <0x0 0x1f610000 0x0 0xd100>;
633 clocks = <&xge0clk 0>;
634 };
635
628 sgenet0: ethernet@1f610000 { 636 sgenet0: ethernet@1f610000 {
629 compatible = "apm,xgene2-sgenet"; 637 compatible = "apm,xgene2-sgenet";
630 status = "disabled"; 638 status = "disabled";
631 reg = <0x0 0x1f610000 0x0 0x10000>, 639 reg = <0x0 0x1f610000 0x0 0xd100>,
632 <0x0 0x1f600000 0x0 0Xd100>, 640 <0x0 0x1f600000 0x0 0Xd100>,
633 <0x0 0x20000000 0x0 0X20000>; 641 <0x0 0x20000000 0x0 0X20000>;
634 interrupts = <0 96 4>, 642 interrupts = <0 96 4>,
@@ -637,6 +645,7 @@
637 clocks = <&xge0clk 0>; 645 clocks = <&xge0clk 0>;
638 local-mac-address = [00 01 73 00 00 01]; 646 local-mac-address = [00 01 73 00 00 01];
639 phy-connection-type = "sgmii"; 647 phy-connection-type = "sgmii";
648 phy-handle = <&sgenet0phy>;
640 }; 649 };
641 650
642 xgenet1: ethernet@1f620000 { 651 xgenet1: ethernet@1f620000 {
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index 5147d7698924..6bf7cbe2e72d 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -237,20 +237,11 @@
237 clocks = <&socplldiv2 0>; 237 clocks = <&socplldiv2 0>;
238 reg = <0x0 0x1f21c000 0x0 0x1000>; 238 reg = <0x0 0x1f21c000 0x0 0x1000>;
239 reg-names = "csr-reg"; 239 reg-names = "csr-reg";
240 csr-mask = <0x3>; 240 csr-mask = <0xa>;
241 enable-mask = <0xf>;
241 clock-output-names = "sge0clk"; 242 clock-output-names = "sge0clk";
242 }; 243 };
243 244
244 sge1clk: sge1clk@1f21c000 {
245 compatible = "apm,xgene-device-clock";
246 #clock-cells = <1>;
247 clocks = <&socplldiv2 0>;
248 reg = <0x0 0x1f21c000 0x0 0x1000>;
249 reg-names = "csr-reg";
250 csr-mask = <0xc>;
251 clock-output-names = "sge1clk";
252 };
253
254 xge0clk: xge0clk@1f61c000 { 245 xge0clk: xge0clk@1f61c000 {
255 compatible = "apm,xgene-device-clock"; 246 compatible = "apm,xgene-device-clock";
256 #clock-cells = <1>; 247 #clock-cells = <1>;
@@ -921,6 +912,14 @@
921 clocks = <&rtcclk 0>; 912 clocks = <&rtcclk 0>;
922 }; 913 };
923 914
915 mdio: mdio@17020000 {
916 compatible = "apm,xgene-mdio-rgmii";