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authorKuninori Morimoto <kuninori.morimoto.gx@renesas.com>2014-02-12 00:04:12 -0500
committerMark Brown <broonie@linaro.org>2014-02-12 06:59:35 -0500
commitee2c828d21b2381c813df257235d3c635269e435 (patch)
tree4e2196c072f1eb0da61124e374d4aa1786bc17dc
parent00463c113b6ba6506b4f1ebb9b3c5dd249f8750f (diff)
ASoC: rsnd: set DIV_EN register on rsnd_adg_set_convert_clk_gen2()
DIV_EN register enable bit is required when you use Gen2 SRC Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Mark Brown <broonie@linaro.org>
-rw-r--r--sound/soc/sh/rcar/adg.c16
-rw-r--r--sound/soc/sh/rcar/gen.c1
-rw-r--r--sound/soc/sh/rcar/rsnd.h1
3 files changed, 15 insertions, 3 deletions
diff --git a/sound/soc/sh/rcar/adg.c b/sound/soc/sh/rcar/adg.c
index bc8961c5e986..af9e4407aa89 100644
--- a/sound/soc/sh/rcar/adg.c
+++ b/sound/soc/sh/rcar/adg.c
@@ -111,8 +111,8 @@ int rsnd_adg_set_convert_clk_gen2(struct rsnd_mod *mod,
111 struct rsnd_priv *priv = rsnd_mod_to_priv(mod); 111 struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
112 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 112 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
113 struct device *dev = rsnd_priv_to_dev(priv); 113 struct device *dev = rsnd_priv_to_dev(priv);
114 int idx, sel, div, step; 114 int idx, sel, div, step, ret;
115 u32 val; 115 u32 val, en;
116 unsigned int min, diff; 116 unsigned int min, diff;
117 unsigned int sel_rate [] = { 117 unsigned int sel_rate [] = {
118 clk_get_rate(adg->clk[CLKA]), /* 0000: CLKA */ 118 clk_get_rate(adg->clk[CLKA]), /* 0000: CLKA */
@@ -124,6 +124,7 @@ int rsnd_adg_set_convert_clk_gen2(struct rsnd_mod *mod,
124 124
125 min = ~0; 125 min = ~0;
126 val = 0; 126 val = 0;
127 en = 0;
127 for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) { 128 for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
128 idx = 0; 129 idx = 0;
129 step = 2; 130 step = 2;
@@ -136,6 +137,7 @@ int rsnd_adg_set_convert_clk_gen2(struct rsnd_mod *mod,
136 if (min > diff) { 137 if (min > diff) {
137 val = (sel << 8) | idx; 138 val = (sel << 8) | idx;
138 min = diff; 139 min = diff;
140 en = 1 << (sel + 1); /* fixme */
139 } 141 }
140 142
141 /* 143 /*
@@ -157,7 +159,15 @@ int rsnd_adg_set_convert_clk_gen2(struct rsnd_mod *mod,
157 return -EIO; 159 return -EIO;
158 } 160 }
159 161
160 return rsnd_adg_set_src_timsel_gen2(rdai, mod, io, val); 162 ret = rsnd_adg_set_src_timsel_gen2(rdai, mod, io, val);
163 if (ret < 0) {
164 dev_err(dev, "timsel error\n");
165 return ret;
166 }
167
168 rsnd_mod_bset(mod, DIV_EN, en, en);
169
170 return 0;
161} 171}
162 172
163int rsnd_adg_set_convert_timing_gen2(struct rsnd_mod *mod, 173int rsnd_adg_set_convert_timing_gen2(struct rsnd_mod *mod,
diff --git a/sound/soc/sh/rcar/gen.c b/sound/soc/sh/rcar/gen.c
index 3e03a8bc4f75..0a43b906ffdf 100644
--- a/sound/soc/sh/rcar/gen.c
+++ b/sound/soc/sh/rcar/gen.c
@@ -253,6 +253,7 @@ static int rsnd_gen2_regmap_init(struct rsnd_priv *priv, struct rsnd_gen *gen)
253 RSND_GEN2_S_REG(gen, ADG, AUDIO_CLK_SEL0, 0x0c), 253 RSND_GEN2_S_REG(gen, ADG, AUDIO_CLK_SEL0, 0x0c),
254 RSND_GEN2_S_REG(gen, ADG, AUDIO_CLK_SEL1, 0x10), 254 RSND_GEN2_S_REG(gen, ADG, AUDIO_CLK_SEL1, 0x10),
255 RSND_GEN2_S_REG(gen, ADG, AUDIO_CLK_SEL2, 0x14), 255 RSND_GEN2_S_REG(gen, ADG, AUDIO_CLK_SEL2, 0x14),
256 RSND_GEN2_S_REG(gen, ADG, DIV_EN, 0x30),
256 RSND_GEN2_S_REG(gen, ADG, SRCIN_TIMSEL0, 0x34), 257 RSND_GEN2_S_REG(gen, ADG, SRCIN_TIMSEL0, 0x34),
257 RSND_GEN2_S_REG(gen, ADG, SRCIN_TIMSEL1, 0x38), 258 RSND_GEN2_S_REG(gen, ADG, SRCIN_TIMSEL1, 0x38),
258 RSND_GEN2_S_REG(gen, ADG, SRCIN_TIMSEL2, 0x3c), 259 RSND_GEN2_S_REG(gen, ADG, SRCIN_TIMSEL2, 0x3c),
diff --git a/sound/soc/sh/rcar/rsnd.h b/sound/soc/sh/rcar/rsnd.h
index 9e4efb40416b..d4093907dfd8 100644
--- a/sound/soc/sh/rcar/rsnd.h
+++ b/sound/soc/sh/rcar/rsnd.h
@@ -67,6 +67,7 @@ enum rsnd_reg {
67 RSND_REG_AUDIO_CLK_SEL3, /* for Gen1 */ 67 RSND_REG_AUDIO_CLK_SEL3, /* for Gen1 */
68 RSND_REG_AUDIO_CLK_SEL4, /* for Gen1 */ 68 RSND_REG_AUDIO_CLK_SEL4, /* for Gen1 */
69 RSND_REG_AUDIO_CLK_SEL5, /* for Gen1 */ 69 RSND_REG_AUDIO_CLK_SEL5, /* for Gen1 */
70 RSND_REG_DIV_EN, /* for Gen2 */
70 RSND_REG_SRCIN_TIMSEL0, /* for Gen2 */ 71 RSND_REG_SRCIN_TIMSEL0, /* for Gen2 */
71 RSND_REG_SRCIN_TIMSEL1, /* for Gen2 */ 72 RSND_REG_SRCIN_TIMSEL1, /* for Gen2 */
72 RSND_REG_SRCIN_TIMSEL2, /* for Gen2 */ 73 RSND_REG_SRCIN_TIMSEL2, /* for Gen2 */