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authorHauke Mehrtens <hauke@hauke-m.de>2012-02-27 18:56:04 -0500
committerJohn W. Linville <linville@tuxdriver.com>2012-03-05 15:20:48 -0500
commitedd8d90b624e97105d26615d1655da22a3605fff (patch)
tree7911b9b5b82db681be3567584522723c514f48c1
parent4e0ad2591adde7bec878a4b37a073427aec3e19c (diff)
ssb: sprom fix some sizes / signedness
Some parts of the sprom struct are bigger than needed. The leddc and maxpwr values are just 8 bit long and not 16. rxpo2g and rxpo5g are signed I got these information for the open source part of the Broadcom SDK covering sprom version 1 to 9. rxpo2g contained a negative number on my bcm5354 based device, this cased an error and Broadcom SDK says this is signed. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
-rw-r--r--include/linux/ssb/ssb.h16
1 files changed, 8 insertions, 8 deletions
diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h
index bbc2612cb64a..f1696213e3b5 100644
--- a/include/linux/ssb/ssb.h
+++ b/include/linux/ssb/ssb.h
@@ -33,8 +33,8 @@ struct ssb_sprom {
33 u8 et1mdcport; /* MDIO for enet1 */ 33 u8 et1mdcport; /* MDIO for enet1 */
34 u16 board_rev; /* Board revision number from SPROM. */ 34 u16 board_rev; /* Board revision number from SPROM. */
35 u8 country_code; /* Country Code */ 35 u8 country_code; /* Country Code */
36 u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */ 36 u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */
37 u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */ 37 u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
38 u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */ 38 u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
39 u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */ 39 u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
40 u16 pa0b0; 40 u16 pa0b0;
@@ -53,10 +53,10 @@ struct ssb_sprom {
53 u8 gpio1; /* GPIO pin 1 */ 53 u8 gpio1; /* GPIO pin 1 */
54 u8 gpio2; /* GPIO pin 2 */ 54 u8 gpio2; /* GPIO pin 2 */
55 u8 gpio3; /* GPIO pin 3 */ 55 u8 gpio3; /* GPIO pin 3 */
56 u16 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */ 56 u8 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
57 u16 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */ 57 u8 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
58 u16 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */ 58 u8 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
59 u16 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */ 59 u8 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
60 u8 itssi_a; /* Idle TSSI Target for A-PHY */ 60 u8 itssi_a; /* Idle TSSI Target for A-PHY */
61 u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */ 61 u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
62 u8 tri2g; /* 2.4GHz TX isolation */ 62 u8 tri2g; /* 2.4GHz TX isolation */
@@ -67,8 +67,8 @@ struct ssb_sprom {
67 u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */ 67 u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
68 u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */ 68 u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
69 u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */ 69 u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
70 u8 rxpo2g; /* 2GHz RX power offset */ 70 s8 rxpo2g; /* 2GHz RX power offset */
71 u8 rxpo5g; /* 5GHz RX power offset */ 71 s8 rxpo5g; /* 5GHz RX power offset */
72 u8 rssisav2g; /* 2GHz RSSI params */ 72 u8 rssisav2g; /* 2GHz RSSI params */
73 u8 rssismc2g; 73 u8 rssismc2g;
74 u8 rssismf2g; 74 u8 rssismf2g;