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authorKishon Vijay Abraham I <kishon@ti.com>2017-03-13 09:43:27 -0400
committerBjorn Helgaas <bhelgaas@google.com>2017-04-04 09:41:07 -0400
commitedd45e3968299f9b4635bdfeca1edab842d81eac (patch)
tree872903db5dea0ed2e851ddd3b5e95aca268a6258
parenta509d7d9af5ebf86ffbefa98e49761d813fb1d40 (diff)
PCI: dwc: designware: Move _unroll configurations to a separate function
No functional change. Rename dw_pcie_writel_unroll/dw_pcie_readl_unroll to dw_pcie_writel_ob_unroll/dw_pcie_readl_ob_unroll respectively as these functions are used to perform only outbound configurations. Also move these _unroll configurations to a separate function. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat
-rw-r--r--drivers/pci/dwc/pcie-designware.c97
1 files changed, 58 insertions, 39 deletions
diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
index 734acac1926d..54de468a745e 100644
--- a/drivers/pci/dwc/pcie-designware.c
+++ b/drivers/pci/dwc/pcie-designware.c
@@ -92,21 +92,56 @@ void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
92 dev_err(pci->dev, "write DBI address failed\n"); 92 dev_err(pci->dev, "write DBI address failed\n");
93} 93}
94 94
95static u32 dw_pcie_readl_unroll(struct dw_pcie *pci, u32 index, u32 reg) 95static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg)
96{ 96{
97 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); 97 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
98 98
99 return dw_pcie_readl_dbi(pci, offset + reg); 99 return dw_pcie_readl_dbi(pci, offset + reg);
100} 100}
101 101
102static void dw_pcie_writel_unroll(struct dw_pcie *pci, u32 index, u32 reg, 102static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg,
103 u32 val) 103 u32 val)
104{ 104{
105 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); 105 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
106 106
107 dw_pcie_writel_dbi(pci, offset + reg, val); 107 dw_pcie_writel_dbi(pci, offset + reg, val);
108} 108}
109 109
110void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index, int type,
111 u64 cpu_addr, u64 pci_addr, u32 size)
112{
113 u32 retries, val;
114
115 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
116 lower_32_bits(cpu_addr));
117 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE,
118 upper_32_bits(cpu_addr));
119 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT,
120 lower_32_bits(cpu_addr + size - 1));
121 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
122 lower_32_bits(pci_addr));
123 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
124 upper_32_bits(pci_addr));
125 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
126 type);
127 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
128 PCIE_ATU_ENABLE);
129
130 /*
131 * Make sure ATU enable takes effect before any subsequent config
132 * and I/O accesses.
133 */
134 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
135 val = dw_pcie_readl_ob_unroll(pci, index,
136 PCIE_ATU_UNR_REGION_CTRL2);
137 if (val & PCIE_ATU_ENABLE)
138 return;
139
140 usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
141 }
142 dev_err(pci->dev, "outbound iATU is not being enabled\n");
143}
144
110void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, 145void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
111 u64 cpu_addr, u64 pci_addr, u32 size) 146 u64 cpu_addr, u64 pci_addr, u32 size)
112{ 147{
@@ -116,54 +151,38 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
116 cpu_addr = pci->ops->cpu_addr_fixup(cpu_addr); 151 cpu_addr = pci->ops->cpu_addr_fixup(cpu_addr);
117 152
118 if (pci->iatu_unroll_enabled) { 153 if (pci->iatu_unroll_enabled) {
119 dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE, 154 dw_pcie_prog_outbound_atu_unroll(pci, index, type, cpu_addr,
120 lower_32_bits(cpu_addr)); 155 pci_addr, size);
121 dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE, 156 return;
122 upper_32_bits(cpu_addr));
123 dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LIMIT,
124 lower_32_bits(cpu_addr + size - 1));
125 dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
126 lower_32_bits(pci_addr));
127 dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
128 upper_32_bits(pci_addr));
129 dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
130 type);
131 dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
132 PCIE_ATU_ENABLE);
133 } else {
134 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT,
135 PCIE_ATU_REGION_OUTBOUND | index);
136 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE,
137 lower_32_bits(cpu_addr));
138 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_BASE,
139 upper_32_bits(cpu_addr));
140 dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
141 lower_32_bits(cpu_addr + size - 1));
142 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
143 lower_32_bits(pci_addr));
144 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
145 upper_32_bits(pci_addr));
146 dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type);
147 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
148 } 157 }
149 158
159 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT,
160 PCIE_ATU_REGION_OUTBOUND | index);
161 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE,
162 lower_32_bits(cpu_addr));
163 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_BASE,
164 upper_32_bits(cpu_addr));
165 dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
166 lower_32_bits(cpu_addr + size - 1));
167 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
168 lower_32_bits(pci_addr));
169 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
170 upper_32_bits(pci_addr));
171 dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type);
172 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
173
150 /* 174 /*
151 * Make sure ATU enable takes effect before any subsequent config 175 * Make sure ATU enable takes effect before any subsequent config
152 * and I/O accesses. 176 * and I/O accesses.
153 */ 177 */
154 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { 178 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
155 if (pci->iatu_unroll_enabled) 179 val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
156 val = dw_pcie_readl_unroll(pci, index,
157 PCIE_ATU_UNR_REGION_CTRL2);
158 else
159 val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
160
161 if (val == PCIE_ATU_ENABLE) 180 if (val == PCIE_ATU_ENABLE)
162 return; 181 return;
163 182
164 usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX); 183 usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
165 } 184 }
166 dev_err(pci->dev, "iATU is not being enabled\n"); 185 dev_err(pci->dev, "outbound iATU is not being enabled\n");
167} 186}
168 187
169int dw_pcie_wait_for_link(struct dw_pcie *pci) 188int dw_pcie_wait_for_link(struct dw_pcie *pci)
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-20 20:29:43 -0400