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authorLinus Torvalds <torvalds@linux-foundation.org>2016-08-01 18:47:01 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2016-08-01 18:47:01 -0400
commited780686de61ab27e65f1cfedeccd7b45667bd70 (patch)
treeac9d0047df09f963b50bc72944fdc43076a39e37
parent043248cd4e9603e2e8858c4e20810d8e40be7d9d (diff)
parent943283ee6b40b74a9d30ced8f23e90119e21dbb3 (diff)
Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull 64-bit ARM DT updates from Olof Johansson: "Just as the 32-bit contents, the 64-bit device tree branch also contains a number of additions this release cycle. New platforms: - LG LG1313 - Mediatek MT6755 - Renesas r8a7796 - Broadcom 2837 Other platforms with larger updates are: - Nvidia X1 platforms (USB 3.0, regulators, display subsystem) - Mediatek MT8173 (display subsystem added) - Rockchip RK3399 (a lot of new peripherals) - ARM Juno reference implementation (SCPI power domains, coresight, thermal)" * tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (118 commits) arm64: tegra: Enable HDMI on Jetson TX1 arm64: tegra: Add sor1_src clock arm64: tegra: Add XUSB powergates on Tegra210 arm64: tegra: Add DPAUX pinctrl bindings arm64: tegra: Add ACONNECT bus node for Tegra210 arm64: tegra: Add audio powergate node for Tegra210 arm64: tegra: Add regulators for Tegra210 Smaug arm64: tegra: Correct Tegra210 XUSB mailbox interrupt arm64: tegra: Enable XUSB controller on Jetson TX1 arm64: tegra: Enable debug serial on Jetson TX1 arm64: tegra: Add Tegra210 XUSB controller arm64: tegra: Add Tegra210 XUSB pad controller arm64: tegra: Add DSI panel on Jetson TX1 arm64: tegra: p2597: Add SDMMC power supplies arm64: tegra: Add PMIC support on Jetson TX1 Revert "ARM64: DTS: meson-gxbb: switch ethernet to real clock" arm64: dts: hi6220: Add pl031 RTC support arm64: dts: r8a7796/salvator-x: Enable watchdog timer arm64: dts: r8a7796: Add RWDT node arm64: dts: r8a7796: Use SYSC "always-on" PM Domain ...
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt4
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek.txt4
-rw-r--r--Documentation/devicetree/bindings/arm/shmobile.txt4
-rw-r--r--Documentation/devicetree/bindings/ata/ahci-platform.txt1
-rw-r--r--Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt1
-rw-r--r--Documentation/devicetree/bindings/net/apm-xgene-enet.txt4
-rw-r--r--Documentation/devicetree/bindings/pci/layerscape-pci.txt4
-rw-r--r--Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt2
-rw-r--r--Documentation/devicetree/bindings/rng/amlogic,meson-rng.txt14
-rw-r--r--Documentation/devicetree/bindings/serial/mtk-uart.txt1
-rw-r--r--arch/arm64/Kconfig.platforms6
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts20
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi9
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi3
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi170
-rw-r--r--arch/arm64/boot/dts/apm/apm-shadowcat.dtsi68
-rw-r--r--arch/arm64/boot/dts/apm/apm-storm.dtsi44
-rw-r--r--arch/arm64/boot/dts/arm/juno-base.dtsi357
-rw-r--r--arch/arm64/boot/dts/arm/juno-r1.dts40
-rw-r--r--arch/arm64/boot/dts/arm/juno-r2.dts40
-rw-r--r--arch/arm64/boot/dts/arm/juno.dts24
-rw-r--r--arch/arm64/boot/dts/broadcom/Makefile1
-rw-r--r--arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts30
-rw-r--r--arch/arm64/boot/dts/broadcom/bcm2837.dtsi76
-rw-r--r--arch/arm64/boot/dts/broadcom/ns2-svk.dts37
-rw-r--r--arch/arm64/boot/dts/broadcom/ns2.dtsi119
-rw-r--r--arch/arm64/boot/dts/exynos/exynos7-espresso.dts2
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi24
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi44
-rw-r--r--arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts143
-rw-r--r--arch/arm64/boot/dts/hisilicon/hi6220.dtsi16
-rw-r--r--arch/arm64/boot/dts/lg/Makefile1
-rw-r--r--arch/arm64/boot/dts/lg/lg1313-ref.dts36
-rw-r--r--arch/arm64/boot/dts/lg/lg1313.dtsi351
-rw-r--r--arch/arm64/boot/dts/marvell/armada-37xx.dtsi35
-rw-r--r--arch/arm64/boot/dts/marvell/armada-ap806.dtsi8
-rw-r--r--arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi18
-rw-r--r--arch/arm64/boot/dts/mediatek/Makefile1
-rw-r--r--arch/arm64/boot/dts/mediatek/mt6755-evb.dts38
-rw-r--r--arch/arm64/boot/dts/mediatek/mt6755.dtsi145
-rw-r--r--arch/arm64/boot/dts/mediatek/mt8173.dtsi223
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi249
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts45
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi319
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra210-smaug.dts314
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra210.dtsi292
-rw-r--r--arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi16
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916.dtsi78
-rw-r--r--arch/arm64/boot/dts/qcom/msm8996-pins.dtsi303
-rw-r--r--arch/arm64/boot/dts/qcom/msm8996.dtsi103
-rw-r--r--arch/arm64/boot/dts/renesas/Makefile1
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts14
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795.dtsi124
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts50
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7796.dtsi138
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3368-r88.dts16
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3368.dtsi16
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-evb.dts12
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399.dtsi313
-rw-r--r--arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi20
60 files changed, 4450 insertions, 141 deletions
diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt
index 11d3056dc2bd..6ffe08778465 100644
--- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt
+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt
@@ -30,6 +30,10 @@ Raspberry Pi 2 Model B
30Required root node properties: 30Required root node properties:
31compatible = "raspberrypi,2-model-b", "brcm,bcm2836"; 31compatible = "raspberrypi,2-model-b", "brcm,bcm2836";
32 32
33Raspberry Pi 3 Model B
34Required root node properties:
35compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
36
33Raspberry Pi Compute Module 37Raspberry Pi Compute Module
34Required root node properties: 38Required root node properties:
35compatible = "raspberrypi,compute-module", "brcm,bcm2835"; 39compatible = "raspberrypi,compute-module", "brcm,bcm2835";
diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt
index d9c2a37a4090..c860b245d8c8 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -10,6 +10,7 @@ compatible: Must contain one of
10 "mediatek,mt6580" 10 "mediatek,mt6580"
11 "mediatek,mt6589" 11 "mediatek,mt6589"
12 "mediatek,mt6592" 12 "mediatek,mt6592"
13 "mediatek,mt6755"
13 "mediatek,mt6795" 14 "mediatek,mt6795"
14 "mediatek,mt7623" 15 "mediatek,mt7623"
15 "mediatek,mt8127" 16 "mediatek,mt8127"
@@ -31,6 +32,9 @@ Supported boards:
31- Evaluation board for MT6592: 32- Evaluation board for MT6592:
32 Required root node properties: 33 Required root node properties:
33 - compatible = "mediatek,mt6592-evb", "mediatek,mt6592"; 34 - compatible = "mediatek,mt6592-evb", "mediatek,mt6592";
35- Evaluation phone for MT6755(Helio P10):
36 Required root node properties:
37 - compatible = "mediatek,mt6755-evb", "mediatek,mt6755";
34- Evaluation board for MT6795(Helio X10): 38- Evaluation board for MT6795(Helio X10):
35 Required root node properties: 39 Required root node properties:
36 - compatible = "mediatek,mt6795-evb", "mediatek,mt6795"; 40 - compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index 6adb9d549fce..1df32d339da5 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -29,6 +29,8 @@ SoCs:
29 compatible = "renesas,r8a7794" 29 compatible = "renesas,r8a7794"
30 - R-Car H3 (R8A77950) 30 - R-Car H3 (R8A77950)
31 compatible = "renesas,r8a7795" 31 compatible = "renesas,r8a7795"
32 - R-Car M3-W (R8A77960)
33 compatible = "renesas,r8a7796"
32 34
33 35
34Boards: 36Boards:
@@ -63,5 +65,7 @@ Boards:
63 compatible = "renesas,porter", "renesas,r8a7791" 65 compatible = "renesas,porter", "renesas,r8a7791"
64 - Salvator-X (RTP0RC7795SIPB0010S) 66 - Salvator-X (RTP0RC7795SIPB0010S)
65 compatible = "renesas,salvator-x", "renesas,r8a7795"; 67 compatible = "renesas,salvator-x", "renesas,r8a7795";
68 - Salvator-X
69 compatible = "renesas,salvator-x", "renesas,r8a7796";
66 - SILK (RTP0RC7794LCB00011S) 70 - SILK (RTP0RC7794LCB00011S)
67 compatible = "renesas,silk", "renesas,r8a7794" 71 compatible = "renesas,silk", "renesas,r8a7794"
diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt
index 87adfb227ca9..fedc213b5f1a 100644
--- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
@@ -10,6 +10,7 @@ PHYs.
10Required properties: 10Required properties:
11- compatible : compatible string, one of: 11- compatible : compatible string, one of:
12 - "allwinner,sun4i-a10-ahci" 12 - "allwinner,sun4i-a10-ahci"
13 - "brcm,iproc-ahci"
13 - "hisilicon,hisi-ahci" 14 - "hisilicon,hisi-ahci"
14 - "cavium,octeon-7130-ahci" 15 - "cavium,octeon-7130-ahci"
15 - "ibm,476gtr-ahci" 16 - "ibm,476gtr-ahci"
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
index 8cf564d083d2..9d1d72c65489 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
@@ -9,6 +9,7 @@ Required properties:
9 "mediatek,mt8135-sysirq" 9 "mediatek,mt8135-sysirq"
10 "mediatek,mt8127-sysirq" 10 "mediatek,mt8127-sysirq"
11 "mediatek,mt6795-sysirq" 11 "mediatek,mt6795-sysirq"
12 "mediatek,mt6755-sysirq"
12 "mediatek,mt6592-sysirq" 13 "mediatek,mt6592-sysirq"
13 "mediatek,mt6589-sysirq" 14 "mediatek,mt6589-sysirq"
14 "mediatek,mt6582-sysirq" 15 "mediatek,mt6582-sysirq"
diff --git a/Documentation/devicetree/bindings/net/apm-xgene-enet.txt b/Documentation/devicetree/bindings/net/apm-xgene-enet.txt
index 05f705e32a4a..e41b2d59ca7f 100644
--- a/Documentation/devicetree/bindings/net/apm-xgene-enet.txt
+++ b/Documentation/devicetree/bindings/net/apm-xgene-enet.txt
@@ -59,8 +59,8 @@ Example:
59 compatible = "apm,xgene-enet"; 59 compatible = "apm,xgene-enet";
60 status = "disabled"; 60 status = "disabled";
61 reg = <0x0 0x17020000 0x0 0xd100>, 61 reg = <0x0 0x17020000 0x0 0xd100>,
62 <0x0 0X17030000 0x0 0X400>, 62 <0x0 0x17030000 0x0 0x400>,
63 <0x0 0X10000000 0x0 0X200>; 63 <0x0 0x10000000 0x0 0x200>;
64 reg-names = "enet_csr", "ring_csr", "ring_cmd"; 64 reg-names = "enet_csr", "ring_csr", "ring_cmd";
65 interrupts = <0x0 0x3c 0x4>; 65 interrupts = <0x0 0x3c 0x4>;
66 port-id = <0>; 66 port-id = <0>;
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index ef683b2fd23a..41e9f55a1467 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -24,6 +24,9 @@ Required properties:
24 The first entry must be a link to the SCFG device node 24 The first entry must be a link to the SCFG device node
25 The second entry must be '0' or '1' based on physical PCIe controller index. 25 The second entry must be '0' or '1' based on physical PCIe controller index.
26 This is used to get SCFG PEXN registers 26 This is used to get SCFG PEXN registers
27- dma-coherent: Indicates that the hardware IP block can ensure the coherency
28 of the data transferred from/to the IP block. This can avoid the software
29 cache flush/invalid actions, and improve the performance significantly.
27 30
28Example: 31Example:
29 32
@@ -38,6 +41,7 @@ Example:
38 #address-cells = <3>; 41 #address-cells = <3>;
39 #size-cells = <2>; 42 #size-cells = <2>;
40 device_type = "pci"; 43 device_type = "pci";
44 dma-coherent;
41 num-lanes = <4>; 45 num-lanes = <4>;
42 bus-range = <0x0 0xff>; 46 bus-range = <0x0 0xff>;
43 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 47 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
diff --git a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
index 32f4a2d6d0b3..fe7fe0b03cfb 100644
--- a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
@@ -5,6 +5,8 @@ Required properties for the root node:
5 "amlogic,meson8b-cbus-pinctrl" 5 "amlogic,meson8b-cbus-pinctrl"
6 "amlogic,meson8-aobus-pinctrl" 6 "amlogic,meson8-aobus-pinctrl"
7 "amlogic,meson8b-aobus-pinctrl" 7 "amlogic,meson8b-aobus-pinctrl"
8 "amlogic,meson-gxbb-periphs-pinctrl"
9 "amlogic,meson-gxbb-aobus-pinctrl"
8 - reg: address and size of registers controlling irq functionality 10 - reg: address and size of registers controlling irq functionality
9 11
10=== GPIO sub-nodes === 12=== GPIO sub-nodes ===
diff --git a/Documentation/devicetree/bindings/rng/amlogic,meson-rng.txt b/Documentation/devicetree/bindings/rng/amlogic,meson-rng.txt
new file mode 100644
index 000000000000..202f2d09a23f
--- /dev/null
+++ b/Documentation/devicetree/bindings/rng/amlogic,meson-rng.txt
@@ -0,0 +1,14 @@
1Amlogic Meson Random number generator
2=====================================
3
4Required properties:
5
6- compatible : should be "amlogic,meson-rng"
7- reg : Specifies base physical address and size of the registers.
8
9Example:
10
11rng {
12 compatible = "amlogic,meson-rng";
13 reg = <0x0 0xc8834000 0x0 0x4>;
14};
diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt
index e99e10ab9ecb..0015c722be7b 100644
--- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
+++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
@@ -6,6 +6,7 @@ Required properties:
6 * "mediatek,mt6580-uart" for MT6580 compatible UARTS 6 * "mediatek,mt6580-uart" for MT6580 compatible UARTS
7 * "mediatek,mt6582-uart" for MT6582 compatible UARTS 7 * "mediatek,mt6582-uart" for MT6582 compatible UARTS
8 * "mediatek,mt6589-uart" for MT6589 compatible UARTS 8 * "mediatek,mt6589-uart" for MT6589 compatible UARTS
9 * "mediatek,mt6755-uart" for MT6755 compatible UARTS
9 * "mediatek,mt6795-uart" for MT6795 compatible UARTS 10 * "mediatek,mt6795-uart" for MT6795 compatible UARTS
10 * "mediatek,mt7623-uart" for MT7623 compatible UARTS 11 * "mediatek,mt7623-uart" for MT7623 compatible UARTS
11 * "mediatek,mt8127-uart" for MT8127 compatible UARTS 12 * "mediatek,mt8127-uart" for MT8127 compatible UARTS
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index ca196d8e76f2..bb2616b16157 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -140,6 +140,12 @@ config ARCH_R8A7795
140 help 140 help
141 This enables support for the Renesas R-Car H3 SoC. 141 This enables support for the Renesas R-Car H3 SoC.
142 142
143config ARCH_R8A7796
144 bool "Renesas R-Car M3-W SoC Platform"
145 depends on ARCH_RENESAS
146 help
147 This enables support for the Renesas R-Car M3-W SoC.
148
143config ARCH_STRATIX10 149config ARCH_STRATIX10
144 bool "Altera's Stratix 10 SoCFPGA Family" 150 bool "Altera's Stratix 10 SoCFPGA Family"
145 help 151 help
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
index 7f2c6747a71e..90a84c514d3d 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
@@ -45,6 +45,7 @@
45/dts-v1/; 45/dts-v1/;
46 46
47#include "meson-gxbb.dtsi" 47#include "meson-gxbb.dtsi"
48#include <dt-bindings/gpio/gpio.h>
48 49
49/ { 50/ {
50 compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb"; 51 compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
@@ -62,8 +63,27 @@
62 device_type = "memory"; 63 device_type = "memory";
63 reg = <0x0 0x0 0x0 0x80000000>; 64 reg = <0x0 0x0 0x0 0x80000000>;
64 }; 65 };
66
67 leds {
68 compatible = "gpio-leds";
69 blue {
70 label = "c2:blue:alive";
71 gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>;
72 linux,default-trigger = "heartbeat";
73 default-state = "off";
74 };
75 };
65}; 76};
66 77
67&uart_AO { 78&uart_AO {
68 status = "okay"; 79 status = "okay";
80 pinctrl-0 = <&uart_ao_a_pins>;
81 pinctrl-names = "default";
82};
83
84&ethmac {
85 status = "okay";
86 pinctrl-0 = <&eth_pins>;
87 pinctrl-names = "default";
69}; 88};
89
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
index bf7ff1d41851..f4f30f674b4c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
@@ -62,4 +62,13 @@
62/* This UART is brought out to the DB9 connector */ 62/* This UART is brought out to the DB9 connector */
63&uart_AO { 63&uart_AO {
64 status = "okay"; 64 status = "okay";
65 pinctrl-0 = <&uart_ao_a_pins>;
66 pinctrl-names = "default";
65}; 67};
68
69&ethmac {
70 status = "okay";
71 pinctrl-0 = <&eth_pins>;
72 pinctrl-names = "default";
73};
74
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
index 012cdccc8a35..54bb7c739089 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
@@ -56,4 +56,7 @@
56 56
57&uart_AO { 57&uart_AO {
58 status = "okay"; 58 status = "okay";
59 pinctrl-0 = <&uart_ao_a_pins>;
60 pinctrl-names = "default";
61
59}; 62};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 832815d80462..e502c24b0ac7 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -43,6 +43,8 @@
43#include <dt-bindings/gpio/gpio.h> 43#include <dt-bindings/gpio/gpio.h>
44#include <dt-bindings/interrupt-controller/irq.h> 44#include <dt-bindings/interrupt-controller/irq.h>
45#include <dt-bindings/interrupt-controller/arm-gic.h> 45#include <dt-bindings/interrupt-controller/arm-gic.h>
46#include <dt-bindings/gpio/meson-gxbb-gpio.h>
47#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
46 48
47/ { 49/ {
48 compatible = "amlogic,meson-gxbb"; 50 compatible = "amlogic,meson-gxbb";
@@ -129,13 +131,35 @@
129 #size-cells = <2>; 131 #size-cells = <2>;
130 ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>; 132 ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
131 133
134 reset: reset-controller@4404 {
135 compatible = "amlogic,meson-gxbb-reset";
136 reg = <0x0 0x04404 0x0 0x20>;
137 #reset-cells = <1>;
138 };
139
132 uart_A: serial@84c0 { 140 uart_A: serial@84c0 {
133 compatible = "amlogic,meson-uart"; 141 compatible = "amlogic,meson-uart";
134 reg = <0x0 0x084c0 0x0 0x14>; 142 reg = <0x0 0x84c0 0x0 0x14>;
135 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 143 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
136 clocks = <&xtal>; 144 clocks = <&xtal>;
137 status = "disabled"; 145 status = "disabled";
138 }; 146 };
147
148 uart_B: serial@84dc {
149 compatible = "amlogic,meson-uart";
150 reg = <0x0 0x84dc 0x0 0x14>;
151 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
152 clocks = <&xtal>;
153 status = "disabled";
154 };
155
156 uart_C: serial@8700 {
157 compatible = "amlogic,meson-uart";
158 reg = <0x0 0x8700 0x0 0x14>;
159 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
160 clocks = <&xtal>;
161 status = "disabled";
162 };
139 }; 163 };
140 164
141 gic: interrupt-controller@c4301000 { 165 gic: interrupt-controller@c4301000 {
@@ -158,6 +182,29 @@
158 #size-cells = <2>; 182 #size-cells = <2>;
159 ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>; 183 ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
160 184
185 pinctrl_aobus: pinctrl@14 {
186 compatible = "amlogic,meson-gxbb-aobus-pinctrl";
187 #address-cells = <2>;
188 #size-cells = <2>;
189 ranges;
190
191 gpio_ao: bank@14 {
192 reg = <0x0 0x00014 0x0 0x8>,
193 <0x0 0x0002c 0x0 0x4>,
194 <0x0 0x00024 0x0 0x8>;
195 reg-names = "mux", "pull", "gpio";
196 gpio-controller;
197 #gpio-cells = <2>;
198 };
199
200 uart_ao_a_pins: uart_ao_a {
201 mux {
202 groups = "uart_tx_ao_a", "uart_rx_ao_a";
203 function = "uart_ao";
204 };
205 };
206 };
207
161 uart_AO: serial@4c0 { 208 uart_AO: serial@4c0 {
162 compatible = "amlogic,meson-uart"; 209 compatible = "amlogic,meson-uart";
163 reg = <0x0 0x004c0 0x0 0x14>; 210 reg = <0x0 0x004c0 0x0 0x14>;
@@ -167,6 +214,115 @@
167 }; 214 };
168 }; 215 };
169 216
217 periphs: periphs@c8834000 {
218 compatible = "simple-bus";
219 reg = <0x0 0xc8834000 0x0 0x2000>;
220 #address-cells = <2>;
221 #size-cells = <2>;
222 ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
223
224 rng {
225 compatible = "amlogic,meson-rng";
226 reg = <0x0 0x0 0x0 0x4>;
227 };
228
229 pinctrl_periphs: pinctrl@4b0 {
230 compatible = "amlogic,meson-gxbb-periphs-pinctrl";
231 #address-cells = <2>;
232 #size-cells = <2>;
233 ranges;
234
235 gpio: bank@4b0 {
236 reg = <0x0 0x004b0 0x0 0x28>,
237 <0x0 0x004e8 0x0 0x14>,
238 <0x0 0x00120 0x0 0x14>,
239 <0x0 0x00430 0x0 0x40>;
240 reg-names = "mux", "pull", "pull-enable", "gpio";
241 gpio-controller;
242 #gpio-cells = <2>;
243 };
244
245 emmc_pins: emmc {
246 mux {
247 groups = "emmc_nand_d07",
248 "emmc_cmd",
249 "emmc_clk";
250 function = "emmc";
251 };
252 };
253
254 sdcard_pins: sdcard {
255 mux {
256 groups = "sdcard_d0",
257 "sdcard_d1",
258 "sdcard_d2",
259 "sdcard_d3",
260 "sdcard_cmd",
261 "sdcard_clk";
262 function = "sdcard";
263 };
264 };
265
266 uart_a_pins: uart_a {
267 mux {
268 groups = "uart_tx_a",
269 "uart_rx_a";
270 function = "uart_a";
271 };
272 };
273
274 uart_b_pins: uart_b {
275 mux {
276 groups = "uart_tx_b",
277 "uart_rx_b";
278 function = "uart_b";
279 };
280 };
281
282 uart_c_pins: uart_c {
283 mux {
284 groups = "uart_tx_c",
285 "uart_rx_c";
286 function = "uart_c";
287 };
288 };
289
290 eth_pins: eth_c {
291 mux {
292 groups = "eth_mdio",
293 "eth_mdc",
294 "eth_clk_rx_clk",
295 "eth_rx_dv",
296 "eth_rxd0",
297 "eth_rxd1",
298 "eth_rxd2",
299 "eth_rxd3",
300 "eth_rgmii_tx_clk",
301 "eth_tx_en",
302 "eth_txd0",
303 "eth_txd1",
304 "eth_txd2",
305 "eth_txd3";
306 function = "eth";
307 };
308 };
309 };
310 };
311
312 hiubus: hiubus@c883c000 {
313 compatible = "simple-bus";
314 reg = <0x0 0xc883c000 0x0 0x2000>;
315 #address-cells = <2>;
316 #size-cells = <2>;
317 ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
318
319 clkc: clock-controller@0 {
320 compatible = "amlogic,gxbb-clkc";
321 #clock-cells = <1>;
322 reg = <0x0 0x0 0x0 0x3db>;
323 };
324 };
325
170 apb: apb@d0000000 { 326 apb: apb@d0000000 {
171 compatible = "simple-bus"; 327 compatible = "simple-bus";
172 reg = <0x0 0xd0000000 0x0 0x200000>; 328 reg = <0x0 0xd0000000 0x0 0x200000>;
@@ -174,5 +330,17 @@
174 #size-cells = <2>; 330 #size-cells = <2>;
175 ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>; 331 ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
176 }; 332 };
333
334 ethmac: ethernet@c9410000 {
335 compatible = "amlogic,meson6-dwmac", "snps,dwmac";
336 reg = <0x0 0xc9410000 0x0 0x10000
337 0x0 0xc8834540 0x0 0x4>;
338 interrupts = <0 8 1>;
339 interrupt-names = "macirq";
340 clocks = <&xtal>;
341 clock-names = "stmmaceth";
342 phy-mode = "rgmii";
343 status = "disabled";
344 };
177 }; 345 };
178}; 346};
diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
index 2e1e5daa1dc7..1425ed41620c 100644
--- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
@@ -106,88 +106,88 @@
106 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ 106 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
107 ranges = <0 0 0 0x79000000 0x0 0x800000>; /* MSI Range */ 107 ranges = <0 0 0 0x79000000 0x0 0x800000>; /* MSI Range */
108 reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */ 108 reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */
109 <0x0 0x780A0000 0x0 0x20000>, /* GIC CPU */ 109 <0x0 0x780a0000 0x0 0x20000>, /* GIC CPU */
110 <0x0 0x780C0000 0x0 0x10000>, /* GIC VCPU Control */ 110 <0x0 0x780c0000 0x0 0x10000>, /* GIC VCPU Control */
111 <0x0 0x780E0000 0x0 0x20000>; /* GIC VCPU */ 111 <0x0 0x780e0000 0x0 0x20000>; /* GIC VCPU */
112 v2m0: v2m@0x00000 { 112 v2m0: v2m@00000 {
113 compatible = "arm,gic-v2m-frame"; 113 compatible = "arm,gic-v2m-frame";
114 msi-controller; 114 msi-controller;
115 reg = <0x0 0x0 0x0 0x1000>; 115 reg = <0x0 0x0 0x0 0x1000>;
116 }; 116 };
117 v2m1: v2m@0x10000 { 117 v2m1: v2m@10000 {
118 compatible = "arm,gic-v2m-frame"; 118 compatible = "arm,gic-v2m-frame";
119 msi-controller; 119 msi-controller;
120 reg = <0x0 0x10000 0x0 0x1000>; 120 reg = <0x0 0x10000 0x0 0x1000>;
121 }; 121 };
122 v2m2: v2m@0x20000 { 122 v2m2: v2m@20000 {
123 compatible = "arm,gic-v2m-frame"; 123 compatible = "arm,gic-v2m-frame";
124 msi-controller; 124 msi-controller;
125 reg = <0x0 0x20000 0x0 0x1000>; 125 reg = <0x0 0x20000 0x0 0x1000>;
126 }; 126 };
127 v2m3: v2m@0x30000 { 127 v2m3: v2m@30000 {
128 compatible = "arm,gic-v2m-frame"; 128 compatible = "arm,gic-v2m-frame";
129 msi-controller; 129 msi-controller;
130 reg = <0x0 0x30000 0x0 0x1000>; 130 reg = <0x0 0x30000 0x0 0x1000>;
131 }; 131 };
132 v2m4: v2m@0x40000 { 132 v2m4: v2m@40000 {
133 compatible = "arm,gic-v2m-frame"; 133 compatible = "arm,gic-v2m-frame";
134 msi-controller; 134 msi-controller;
135 reg = <0x0 0x40000 0x0 0x1000>; 135 reg = <0x0 0x40000 0x0 0x1000>;
136 }; 136 };
137 v2m5: v2m@0x50000 { 137 v2m5: v2m@50000 {
138 compatible = "arm,gic-v2m-frame"; 138 compatible = "arm,gic-v2m-frame";
139 msi-controller; 139 msi-controller;
140 reg = <0x0 0x50000 0x0 0x1000>; 140 reg = <0x0 0x50000 0x0 0x1000>;
141 }; 141 };
142 v2m6: v2m@0x60000 { 142 v2m6: v2m@60000 {
143 compatible = "arm,gic-v2m-frame"; 143 compatible = "arm,gic-v2m-frame";
144 msi-controller; 144 msi-controller;
145 reg = <0x0 0x60000 0x0 0x1000>; 145 reg = <0x0 0x60000 0x0 0x1000>;
146 }; 146 };
147 v2m7: v2m@0x70000 { 147 v2m7: v2m@70000 {
148 compatible = "arm,gic-v2m-frame"; 148 compatible = "arm,gic-v2m-frame";
149 msi-controller; 149 msi-controller;
150 reg = <0x0 0x70000 0x0 0x1000>; 150 reg = <0x0 0x70000 0x0 0x1000>;
151 }; 151 };
152 v2m8: v2m@0x80000 { 152 v2m8: v2m@80000 {
153 compatible = "arm,gic-v2m-frame"; 153 compatible = "arm,gic-v2m-frame";
154 msi-controller; 154 msi-controller;
155 reg = <0x0 0x80000 0x0 0x1000>; 155 reg = <0x0 0x80000 0x0 0x1000>;
156 }; 156 };
157 v2m9: v2m@0x90000 { 157 v2m9: v2m@90000 {
158 compatible = "arm,gic-v2m-frame"; 158 compatible = "arm,gic-v2m-frame";
159 msi-controller; 159 msi-controller;
160 reg = <0x0 0x90000 0x0 0x1000>; 160 reg = <0x0 0x90000 0x0 0x1000>;
161 }; 161 };
162 v2m10: v2m@0xA0000 { 162 v2m10: v2m@a0000 {
163 compatible = "arm,gic-v2m-frame"; 163 compatible = "arm,gic-v2m-frame";
164 msi-controller; 164 msi-controller;
165 reg = <0x0 0xA0000 0x0 0x1000>; 165 reg = <0x0 0xa0000 0x0 0x1000>;
166 }; 166 };
167 v2m11: v2m@0xB0000 { 167 v2m11: v2m@b0000 {
168 compatible = "arm,gic-v2m-frame"; 168 compatible = "arm,gic-v2m-frame";
169 msi-controller; 169 msi-controller;
170 reg = <0x0 0xB0000 0x0 0x1000>; 170 reg = <0x0 0xb0000 0x0 0x1000>;
171 }; 171 };
172 v2m12: v2m@0xC0000 { 172 v2m12: v2m@c0000 {
173 compatible = "arm,gic-v2m-frame"; 173 compatible = "arm,gic-v2m-frame";
174 msi-controller; 174 msi-controller;
175 reg = <0x0 0xC0000 0x0 0x1000>; 175 reg = <0x0 0xc0000 0x0 0x1000>;
176 }; 176 };
177 v2m13: v2m@0xD0000 { 177 v2m13: v2m@d0000 {
178 compatible = "arm,gic-v2m-frame"; 178 compatible = "arm,gic-v2m-frame";
179 msi-controller; 179 msi-controller;
180 reg = <0x0 0xD0000 0x0 0x1000>; 180 reg = <0x0 0xd0000 0x0 0x1000>;
181 }; 181 };
182 v2m14: v2m@0xE0000 { 182 v2m14: v2m@e0000 {
183 compatible = "arm,gic-v2m-frame"; 183 compatible = "arm,gic-v2m-frame";
184 msi-controller; 184 msi-controller;
185 reg = <0x0 0xE0000 0x0 0x1000>; 185 reg = <0x0 0xe0000 0x0 0x1000>;
186 }; 186 };
187 v2m15: v2m@0xF0000 { 187 v2m15: v2m@f0000 {
188 compatible = "arm,gic-v2m-frame"; 188 compatible = "arm,gic-v2m-frame";
189 msi-controller; 189 msi-controller;
190 reg = <0x0 0xF0000 0x0 0x1000>; 190 reg = <0x0 0xf0000 0x0 0x1000>;
191 }; 191 };
192 }; 192 };
193 193
@@ -198,10 +198,10 @@
198 198
199 timer { 199 timer {
200 compatible = "arm,armv8-timer"; 200 compatible = "arm,armv8-timer";
201 interrupts = <1 0 0xff04>, /* Secure Phys IRQ */ 201 interrupts = <1 0 0xff08>, /* Secure Phys IRQ */
202 <1 13 0xff04>, /* Non-secure Phys IRQ */ 202 <1 13 0xff08>, /* Non-secure Phys IRQ */
203 <1 14 0xff04>, /* Virt IRQ */ 203 <1 14 0xff08>, /* Virt IRQ */
204 <1 15 0xff04>; /* Hyp IRQ */ 204 <1 15 0xff08>; /* Hyp IRQ */
205 clock-frequency = <50000000>; 205 clock-frequency = <50000000>;
206 }; 206 };
207 207
@@ -637,8 +637,8 @@
637 compatible = "apm,xgene2-sgenet"; 637 compatible = "apm,xgene2-sgenet";
638 status = "disabled"; 638 status = "disabled";
639 reg = <0x0 0x1f610000 0x0 0xd100>, 639 reg = <0x0 0x1f610000 0x0 0xd100>,
640 <0x0 0x1f600000 0x0 0Xd100>, 640 <0x0 0x1f600000 0x0 0xd100>,
641 <0x0 0x20000000 0x0 0X20000>; 641 <0x0 0x20000000 0x0 0x20000>;
642 interrupts = <0 96 4>, 642 interrupts = <0 96 4>,
643 <0 97 4>; 643 <0 97 4>;
644 dma-coherent; 644 dma-coherent;
@@ -652,8 +652,8 @@
652 compatible = "apm,xgene2-xgenet"; 652 compatible = "apm,xgene2-xgenet";
653 status = "disabled"; 653 status = "disabled";
654 reg = <0x0 0x1f620000 0x0 0x10000>, 654 reg = <0x0 0x1f620000 0x0 0x10000>,
655 <0x0 0x1f600000 0x0 0Xd100>, 655 <0x0 0x1f600000 0x0 0xd100>,
656 <0x0 0x20000000 0x0 0X220000>; 656 <0x0 0x20000000 0x0 0x220000>;
657 interrupts = <0 108 4>, 657 interrupts = <0 108 4>,
658 <0 109 4>, 658 <0 109 4>,
659 <0 110 4>, 659 <0 110 4>,
@@ -693,7 +693,7 @@
693 #size-cells = <0>; 693 #size-cells = <0>;
694 compatible = "snps,designware-i2c"; 694 compatible = "snps,designware-i2c";
695 reg = <0x0 0x10640000 0x0 0x1000>; 695 reg = <0x0 0x10640000 0x0 0x1000>;
696 interrupts = <0 0x3A 0x4>; 696 interrupts = <0 0x3a 0x4>;
697 clocks = <&i2c4clk 0>; 697 clocks = <&i2c4clk 0>;
698 bus_num = <4>; 698 bus_num = <4>;
699 }; 699 };
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index 6bf7cbe2e72d..f1c2c713f9b0 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -199,16 +199,6 @@
199 clock-output-names = "sdioclk"; 199 clock-output-names = "sdioclk";
200 }; 200 };
201 201
202 qmlclk: qmlclk {
203 compatible = "apm,xgene-device-clock";
204 #clock-cells = <1>;
205 clocks = <&socplldiv2 0>;
206 clock-names = "qmlclk";
207 reg = <0x0 0x1703C000 0x0 0x1000>;
208 reg-names = "csr-reg";
209 clock-output-names = "qmlclk";
210 };
211
212 ethclk: ethclk { 202 ethclk: ethclk {
213 compatible = "apm,xgene-device-clock"; 203 compatible = "apm,xgene-device-clock";
214 #clock-cells = <1>; 204 #clock-cells = <1>;
@@ -226,7 +216,7 @@
226 compatible = "apm,xgene-device-clock"; 216 compatible = "apm,xgene-device-clock";
227 #clock-cells = <1>; 217 #clock-cells = <1>;
228 clocks = <&ethclk 0>; 218 clocks = <&ethclk 0>;
229 reg = <0x0 0x1702C000 0x0 0x1000>; 219 reg = <0x0 0x1702c000 0x0 0x1000>;
230 reg-names = "csr-reg"; 220 reg-names = "csr-reg";
231 clock-output-names = "menetclk"; 221 clock-output-names = "menetclk";
232 }; 222 };
@@ -924,8 +914,8 @@
924 compatible = "apm,xgene-enet"; 914 compatible = "apm,xgene-enet";
925 status = "disabled"; 915 status = "disabled";
926 reg = <0x0 0x17020000 0x0 0xd100>, 916 reg = <0x0 0x17020000 0x0 0xd100>,
927 <0x0 0X17030000 0x0 0Xc300>, 917 <0x0 0x17030000 0x0 0xc300>,
928 <0x0 0X10000000 0x0 0X200>; 918 <0x0 0x10000000 0x0 0x200>;
929 reg-names = "enet_csr", "ring_csr", "ring_cmd"; 919 reg-names = "enet_csr", "ring_csr", "ring_cmd";
930 interrupts = <0x0 0x3c 0x4>; 920 interrupts = <0x0 0x3c 0x4>;
931 dma-coherent; 921 dma-coherent;
@@ -950,11 +940,11 @@
950 compatible = "apm,xgene1-sgenet"; 940 compatible = "apm,xgene1-sgenet";
951 status = "disabled"; 941 status = "disabled";
952 reg = <0x0 0x1f210000 0x0 0xd100>, 942 reg = <0x0 0x1f210000 0x0 0xd100>,
953 <0x0 0x1f200000 0x0 0Xc300>, 943 <0x0 0x1f200000 0x0 0xc300>,
954 <0x0 0x1B000000 0x0 0X200>; 944 <0x0 0x1b000000 0x0 0x200>;
955 reg-names = "enet_csr", "ring_csr", "ring_cmd"; 945 reg-names = "enet_csr", "ring_csr", "ring_cmd";
956 interrupts = <0x0 0xA0 0x4>, 946 interrupts = <0x0 0xa0 0x4>,
957 <0x0 0xA1 0x4>; 947 <0x0 0xa1 0x4>;
958 dma-coherent; 948 dma-coherent;
959 clocks = <&sge0clk 0>; 949 clocks = <&sge0clk 0>;
960 local-mac-address = [00 00 00 00 00 00]; 950 local-mac-address = [00 00 00 00 00 00];
@@ -966,11 +956,11 @@
966 compatible = "apm,xgene1-sgenet"; 956 compatible = "apm,xgene1-sgenet";
967 status = "disabled"; 957 status = "disabled";
968 reg = <0x0 0x1f210030 0x0 0xd100>, 958 reg = <0x0 0x1f210030 0x0 0xd100>,
969 <0x0 0x1f200000 0x0 0Xc300>, 959 <0x0 0x1f200000 0x0 0xc300>,
970 <0x0 0x1B000000 0x0 0X8000>; 960 <0x0 0x1b000000 0x0 0x8000>;
971 reg-names = "enet_csr", "ring_csr", "ring_cmd"; 961 reg-names = "enet_csr", "ring_csr", "ring_cmd";
972 interrupts = <0x0 0xAC 0x4>, 962 interrupts = <0x0 0xac 0x4>,
973 <0x0 0xAD 0x4>; 963 <0x0 0xad 0x4>;
974 port-id = <1>; 964 port-id = <1>;
975 dma-coherent; 965 dma-coherent;
976 local-mac-address = [00 00 00 00 00 00]; 966 local-mac-address = [00 00 00 00 00 00];
@@ -982,8 +972,8 @@
982 compatible = "apm,xgene1-xgenet"; 972 compatible = "apm,xgene1-xgenet";
983 status = "disabled"; 973 status = "disabled";
984 reg = <0x0 0x1f610000 0x0 0xd100>, 974 reg = <0x0 0x1f610000 0x0 0xd100>,
985 <0x0 0x1f600000 0x0 0Xc300>, 975 <0x0 0x1f600000 0x0 0xc300>,
986 <0x0 0x18000000 0x0 0X200>; 976 <0x0 0x18000000 0x0 0x200>;
987 reg-names = "enet_csr", "ring_csr", "ring_cmd"; 977 reg-names = "enet_csr", "ring_csr", "ring_cmd";
988 interrupts = <0x0 0x60 0x4>, 978 interrupts = <0x0 0x60 0x4>,
989 <0x0 0x61 0x4>, 979 <0x0 0x61 0x4>,
@@ -1005,11 +995,11 @@
1005 compatible = "apm,xgene1-xgenet"; 995 compatible = "apm,xgene1-xgenet";
1006 status = "disabled"; 996 status = "disabled";
1007 reg = <0x0 0x1f620000 0x0 0xd100>, 997 reg = <0x0 0x1f620000 0x0 0xd100>,
1008 <0x0 0x1f600000 0x0 0Xc300>, 998 <0x0 0x1f600000 0x0 0xc300>,
1009 <0x0 0x18000000 0x0 0X8000>; 999 <0x0 0x18000000 0x0 0x8000>;
1010 reg-names = "enet_csr", "ring_csr", "ring_cmd"; 1000 reg-names = "enet_csr", "ring_csr", "ring_cmd";
1011 interrupts = <0x0 0x6C 0x4>, 1001 interrupts = <0x0 0x6c 0x4>,
1012 <0x0 0x6D 0x4>; 1002 <0x0 0x6d 0x4>;
1013 port-id = <1>; 1003 port-id = <1>;
1014 dma-coherent; 1004 dma-coherent;
1015 clocks = <&xge1clk 0>; 1005 clocks = <&xge1clk 0>;
diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index dee2386d3b9b..334271a25f70 100644
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -56,6 +56,315 @@
56 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 56 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
57 }; 57 };
58 58
59 /*
60 * Juno TRMs specify the size for these coresight components as 64K.
61 * The actual size is just 4K though 64K is reserved. Access to the
62 * unmapped reserved region results in a DECERR response.
63 */
64 etf@20010000 {
65 compatible = "arm,coresight-tmc", "arm,primecell";
66 reg = <0 0x20010000 0 0x1000>;
67
68 clocks = <&soc_smc50mhz>;
69 clock-names = "apb_pclk";
70 power-domains = <&scpi_devpd 0>;
71 ports {
72 #address-cells = <1>;
73 #size-cells = <0>;
74
75 /* input port */
76 port@0 {
77 reg = <0>;
78 etf_in_port: endpoint {
79 slave-mode;
80 remote-endpoint = <&main_funnel_out_port>;
81 };
82 };
83
84 /* output port */
85 port@1 {
86 reg = <0>;
87 etf_out_port: endpoint {
88 remote-endpoint = <&replicator_in_port0>;
89 };
90 };
91 };
92 };
93
94 tpiu@20030000 {
95 compatible = "arm,coresight-tpiu", "arm,primecell";
96 reg = <0 0x20030000 0 0x1000>;
97
98 clocks = <&soc_smc50mhz>;
99 clock-names = "apb_pclk";
100 power-domains = <&scpi_devpd 0>;
101 port {
102 tpiu_in_port: endpoint {
103 slave-mode;
104 remote-endpoint = <&replicator_out_port0>;
105 };
106 };
107 };
108
109 main-funnel@20040000 {
110 compatible = "arm,coresight-funnel", "arm,primecell";
111 reg = <0 0x20040000 0 0x1000>;
112
113 clocks = <&soc_smc50mhz>;
114 clock-names = "apb_pclk";
115 power-domains = <&scpi_devpd 0>;
116 ports {
117 #address-cells = <1>;
118 #size-cells = <0>;
119
120 port@0 {
121 reg = <0>;
122 main_funnel_out_port: endpoint {
123 remote-endpoint = <&etf_in_port>;
124 };
125 };
126
127 port@1 {
128 reg = <0>;
129 main_funnel_in_port0: endpoint {
130 slave-mode;
131 remote-endpoint = <&cluster0_funnel_out_port>;
132 };
133 };
134
135 port@2 {
136 reg = <1>;
137 main_funnel_in_port1: endpoint {
138 slave-mode;
139 remote-endpoint = <&cluster1_funnel_out_port>;
140 };
141 };
142
143 };
144 };
145
146 etr@20070000 {
147 compatible = "arm,coresight-tmc", "arm,primecell";
148 reg = <0 0x20070000 0 0x1000>;
149
150 clocks = <&soc_smc50mhz>;
151 clock-names = "apb_pclk";
152 power-domains = <&scpi_devpd 0>;
153 port {
154 etr_in_port: endpoint {
155 slave-mode;
156 remote-endpoint = <&replicator_out_port1>;
157 };
158 };
159 };
160
161 etm0: etm@22040000 {
162 compatible = "arm,coresight-etm4x", "arm,primecell";
163 reg = <0 0x22040000 0 0x1000>;
164
165 clocks = <&soc_smc50mhz>;
166 clock-names = "apb_pclk";
167 power-domains = <&scpi_devpd 0>;
168 port {
169 cluster0_etm0_out_port: endpoint {
170 remote-endpoint = <&cluster0_funnel_in_port0>;
171 };
172 };
173 };
174
175 cluster0-funnel@220c0000 {
176 compatible = "arm,coresight-funnel", "arm,primecell";
177 reg = <0 0x220c0000 0 0x1000>;
178
179 clocks = <&soc_smc50mhz>;
180 clock-names = "apb_pclk";
181 power-domains = <&scpi_devpd 0>;
182 ports {
183 #address-cells = <1>;
184 #size-cells = <0>;
185
186 port@0 {
187 reg = <0>;
188 cluster0_funnel_out_port: endpoint {
189 remote-endpoint = <&main_funnel_in_port0>;
190 };
191 };
192
193 port@1 {
194 reg = <0>;
195 cluster0_funnel_in_port0: endpoint {
196 slave-mode;
197 remote-endpoint = <&cluster0_etm0_out_port>;
198 };
199 };
200
201 port@2 {
202 reg = <1>;
203 cluster0_funnel_in_port1: endpoint {
204 slave-mode;
205 remote-endpoint = <&cluster0_etm1_out_port>;
206 };
207 };
208 };
209 };
210
211 etm1: etm@22140000 {
212 compatible = "arm,coresight-etm4x", "arm,primecell";
213 reg = <0 0x22140000 0 0x1000>;
214
215 clocks = <&soc_smc50mhz>;
216 clock-names = "apb_pclk";
217 power-domains = <&scpi_devpd 0>;
218 port {
219 cluster0_etm1_out_port: endpoint {
220 remote-endpoint = <&cluster0_funnel_in_port1>;
221 };
222 };
223 };
224
225 etm2: etm@23040000 {
226 compatible = "arm,coresight-etm4x", "arm,primecell";
227 reg = <0 0x23040000 0 0x1000>;
228
229 clocks = <&soc_smc50mhz>;
230 clock-names = "apb_pclk";
231 power-domains = <&scpi_devpd 0>;
232 port {
233 cluster1_etm0_out_port: endpoint {
234 remote-endpoint = <&cluster1_funnel_in_port0>;
235 };
236 };
237 };
238
239 cluster1-funnel@230c0000 {
240 compatible = "arm,coresight-funnel", "arm,primecell";
241 reg = <0 0x230c0000 0 0x1000>;
242
243 clocks = <&soc_smc50mhz>;
244 clock-names = "apb_pclk";
245 power-domains = <&scpi_devpd 0>;
246 ports {
247 #address-cells = <1>;
248 #size-cells = <0>;
249
250 port@0 {
251 reg = <0>;
252 cluster1_funnel_out_port: endpoint {
253 remote-endpoint = <&main_funnel_in_port1>;
254 };
255 };
256
257 port@1 {
258 reg = <0>;
259 cluster1_funnel_in_port0: endpoint {
260 slave-mode;
261 remote-endpoint = <&cluster1_etm0_out_port>;
262 };
263 };
264
265 port@2 {
266 reg = <1>;
267 cluster1_funnel_in_port1: endpoint {
268 slave-mode;
269 remote-endpoint = <&cluster1_etm1_out_port>;
270 };
271 };
272 port@3 {
273 reg = <2>;
274 cluster1_funnel_in_port2: endpoint {
275 slave-mode;
276 remote-endpoint = <&cluster1_etm2_out_port>;
277 };
278 };
279 port@4 {
280 reg = <3>;
281 cluster1_funnel_in_port3: endpoint {
282 slave-mode;
283 remote-endpoint = <&cluster1_etm3_out_port>;
284 };
285 };
286 };
287 };
288
289 etm3: etm@23140000 {
290 compatible = "arm,coresight-etm4x", "arm,primecell";
291 reg = <0 0x23140000 0 0x1000>;
292
293 clocks = <&soc_smc50mhz>;
294 clock-names = "apb_pclk";
295 power-domains = <&scpi_devpd 0>;
296 port {
297 cluster1_etm1_out_port: endpoint {
298 remote-endpoint = <&cluster1_funnel_in_port1>;
299 };
300 };
301 };
302
303 etm4: etm@23240000 {
304 compatible = "arm,coresight-etm4x", "arm,primecell";
305 reg = <0 0x23240000 0 0x1000>;
306
307 clocks = <&soc_smc50mhz>;
308 clock-names = "apb_pclk";
309 power-domains = <&scpi_devpd 0>;
310 port {
311 cluster1_etm2_out_port: endpoint {
312 remote-endpoint = <&cluster1_funnel_in_port2>;
313 };
314 };
315 };
316
317 etm5: etm@23340000 {
318 compatible = "arm,coresight-etm4x", "arm,primecell";
319 reg = <0 0x23340000 0 0x1000>;
320
321 clocks = <&soc_smc50mhz>;
322 clock-names = "apb_pclk";
323 power-domains = <&scpi_devpd 0>;
324 port {
325 cluster1_etm3_out_port: endpoint {
326 remote-endpoint = <&cluster1_funnel_in_port3>;
327 };
328 };
329 };
330
331 coresight-replicator {
332 /*
333 * Non-configurable replicators don't show up on the
334 * AMBA bus. As such no need to add "arm,primecell".
335 */
336 compatible = "arm,coresight-replicator";
337
338 ports {
339 #address-cells = <1>;
340 #size-cells = <0>;
341
342 /* replicator output ports */
343 port@0 {
344 reg = <0>;
345 replicator_out_port0: endpoint {
346 remote-endpoint = <&tpiu_in_port>;
347 };
348 };
349
350 port@1 {
351 reg = <1>;
352 replicator_out_port1: endpoint {
353 remote-endpoint = <&etr_in_port>;
354 };
355 };
356
357 /* replicator input port */
358 port@2 {
359 reg = <0>;
360 replicator_in_port0: endpoint {
361 slave-mode;
362 remote-endpoint = <&etf_out_port>;
363 };
364 };
365 };
366 };
367
59 sram: sram@2e000000 { 368 sram: sram@2e000000 {
60 compatible = "arm,juno-sram-ns", "mmio-sram"; 369 compatible = "arm,juno-sram-ns", "mmio-sram";
61 reg = <0x0 0x2e000000 0x0 0x8000>; 370 reg = <0x0 0x2e000000 0x0 0x8000>;
@@ -119,12 +428,60 @@
119 }; 428 };
120 }; 429 };
121 430
431 scpi_devpd: scpi-power-domains {
432 compatible = "arm,scpi-power-domains";
433 num-domains = <2>;
434 #power-domain-cells = <1>;
435 };
436
122 scpi_sensors0: sensors { 437 scpi_sensors0: sensors {
123 compatible = "arm,scpi-sensors"; 438 compatible = "arm,scpi-sensors";
124 #thermal-sensor-cells = <1>; 439 #thermal-sensor-cells = <1>;
125 }; 440 };
126 }; 441 };
127 442
443 thermal-zones {
444 pmic {
445 polling-delay = <1000>;
446 polling-delay-passive = <100>;
447 thermal-sensors = <&scpi_sensors0 0>;
448 };
449
450 soc {
451 polling-delay = <1000>;
452 polling-delay-passive = <100>;
453 thermal-sensors = <&scpi_sensors0 3>;
454 };
455
456 big_cluster_thermal_zone: big_cluster {
457 polling-delay = <1000>;
458 polling-delay-passive = <100>;
459 thermal-sensors = <&scpi_sensors0 21>;
460 status = "disabled";
461 };
462
463 little_cluster_thermal_zone: little_cluster {
464 polling-delay = <1000>;
465 polling-delay-passive = <100>;
466 thermal-sensors = <&scpi_sensors0 22>;
467 status = "disabled";
468 };
469
470 gpu0_thermal_zone: gpu0 {
471 polling-delay = <1000>;
472 polling-delay-passive = <100>;
473 thermal-sensors = <&scpi_sensors0 23>;
474 status = "disabled";
475 };
476
477 gpu1_thermal_zone: gpu1 {
478 polling-delay = <1000>;
479 polling-delay-passive = <100>;
480 thermal-sensors = <&scpi_sensors0 24>;
481 status = "disabled";
482 };
483 };
484
128 /include/ "juno-clocks.dtsi" 485 /include/ "juno-clocks.dtsi"
129 486
130 dma@7ff00000 { 487 dma@7ff00000 {
diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts
index d95d9e7e2dc0..123a58b29cbd 100644
--- a/arch/arm64/boot/dts/arm/juno-r1.dts
+++ b/arch/arm64/boot/dts/arm/juno-r1.dts
@@ -181,3 +181,43 @@
181&pcie_ctlr { 181&pcie_ctlr {
182 status = "okay"; 182 status = "okay";
183}; 183};
184
185&etm0 {
186 cpu = <&A57_0>;
187};
188
189&etm1 {
190 cpu = <&A57_1>;
191};
192
193&etm2 {
194 cpu = <&A53_0>;
195};
196
197&etm3 {
198 cpu = <&A53_1>;
199};
200
201&etm4 {
202 cpu = <&A53_2>;
203};
204
205&etm5 {
206 cpu = <&A53_3>;
207};
208
209&big_cluster_thermal_zone {
210 status = "okay";
211};
212
213&little_cluster_thermal_zone {
214 status = "okay";
215};
216
217&gpu0_thermal_zone {
218 status = "okay";
219};
220
221&gpu1_thermal_zone {
222 status = "okay";
223};
diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts
index 88ecd6182b67..007be826efce 100644
--- a/arch/arm64/boot/dts/arm/juno-r2.dts
+++ b/arch/arm64/boot/dts/arm/juno-r2.dts
@@ -181,3 +181,43 @@
181&pcie_ctlr { 181&pcie_ctlr {
182 status = "okay"; 182 status = "okay";
183}; 183};
184
185&etm0 {
186 cpu = <&A72_0>;
187};
188
189&etm1 {
190 cpu = <&A72_1>;
191};
192
193&etm2 {
194 cpu = <&A53_0>;
195};
196
197&etm3 {
198 cpu = <&A53_1>;
199};
200
201&etm4 {
202 cpu = <&A53_2>;
203};
204
205&etm5 {
206 cpu = <&A53_3>;
207};
208
209&big_cluster_thermal_zone {
210 status = "okay";
211};
212
213&little_cluster_thermal_zone {
214 status = "okay";
215};
216
217&gpu0_thermal_zone {
218 status = "okay";
219};
220
221&gpu1_thermal_zone {
222 status = "okay";
223};
diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
index dcfcf15a17f5..a7270eff6939 100644
--- a/arch/arm64/boot/dts/arm/juno.dts
+++ b/arch/arm64/boot/dts/arm/juno.dts
@@ -173,3 +173,27 @@
173 173
174 #include "juno-base.dtsi" 174 #include "juno-base.dtsi"
175}; 175};
176
177&etm0 {
178 cpu = <&A57_0>;
179};
180
181&etm1 {
182 cpu = <&A57_1>;
183};
184
185&etm2 {
186 cpu = <&A53_0>;
187};
188
189&etm3 {
190 cpu = <&A53_1>;
191};
192
193&etm4 {
194 cpu = <&A53_2>;
195};
196
197&etm5 {
198 cpu = <&A53_3>;
199};
diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile
index bec1f8b36f60..05faf2a8a35c 100644
--- a/arch/arm64/boot/dts/broadcom/Makefile
+++ b/arch/arm64/boot/dts/broadcom/Makefile
@@ -1,3 +1,4 @@
1dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-b.dtb
1dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb 2dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb
2dtb-$(CONFIG_ARCH_VULCAN) += vulcan-eval.dtb 3dtb-$(CONFIG_ARCH_VULCAN) += vulcan-eval.dtb
3 4
diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts
new file mode 100644
index 000000000000..6f47dd2bb1db
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts
@@ -0,0 +1,30 @@
1/dts-v1/;
2#include "bcm2837.dtsi"
3#include "../../../../arm/boot/dts/bcm2835-rpi.dtsi"
4#include "../../../../arm/boot/dts/bcm283x-rpi-smsc9514.dtsi"
5
6/ {
7 compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
8 model = "Raspberry Pi 3 Model B";
9
10 memory {
11 reg = <0 0x40000000>;
12 };
13
14 leds {
15 act {
16 gpios = <&gpio 47 0>;
17 };
18
19 pwr {
20 label = "PWR";
21 gpios = <&gpio 35 0>;
22 default-state = "keep";
23 linux,default-trigger = "default-on";
24 };
25 };
26};
27
28&uart1 {
29 status = "okay";
30};
diff --git a/arch/arm64/boot/dts/broadcom/bcm2837.dtsi b/arch/arm64/boot/dts/broadcom/bcm2837.dtsi
new file mode 100644
index 000000000000..f2a31d06845d
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/bcm2837.dtsi
@@ -0,0 +1,76 @@
1#include "../../../../arm/boot/dts/bcm283x.dtsi"
2
3/ {
4 compatible = "brcm,bcm2836";
5
6 soc {
7 ranges = <0x7e000000 0x3f000000 0x1000000>,
8 <0x40000000 0x40000000 0x00001000>;
9 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
10
11 local_intc: local_intc {
12 compatible = "brcm,bcm2836-l1-intc";
13 reg = <0x40000000 0x100>;
14 interrupt-controller;
15 #interrupt-cells = <1>;
16 interrupt-parent = <&local_intc>;
17 };
18 };
19
20 timer {
21 compatible = "arm,armv7-timer";
22 interrupt-parent = <&local_intc>;
23 interrupts = <0>, // PHYS_SECURE_PPI
24 <1>, // PHYS_NONSECURE_PPI
25 <3>, // VIRT_PPI
26 <2>; // HYP_PPI
27 always-on;
28 };
29
30 cpus: cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 cpu0: cpu@0 {
35 device_type = "cpu";
36 compatible = "arm,cortex-a53";
37 reg = <0>;
38 enable-method = "spin-table";
39 cpu-release-addr = <0x0 0x000000d8>;
40 };
41
42 cpu1: cpu@1 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a53";
45 reg = <1>;
46 enable-method = "spin-table";
47 cpu-release-addr = <0x0 0x000000e0>;
48 };
49
50 cpu2: cpu@2 {
51 device_type = "cpu";
52 compatible = "arm,cortex-a53";
53 reg = <2>;
54 enable-method = "spin-table";
55 cpu-release-addr = <0x0 0x000000e8>;
56 };
57
58 cpu3: cpu@3 {
59 device_type = "cpu";
60 compatible = "arm,cortex-a53";
61 reg = <3>;
62 enable-method = "spin-table";
63 cpu-release-addr = <0x0 0x000000f0>;
64 };
65 };
66};
67
68/* Make the BCM2835-style global interrupt controller be a child of the
69 * CPU-local interrupt controller.
70 */
71&intc {
72 compatible = "brcm,bcm2836-armctrl-ic";
73 reg = <0x7e00b200 0x200>;
74 interrupt-parent = <&local_intc>;
75 interrupts = <8>;
76};
diff --git a/arch/arm64/boot/dts/broadcom/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/ns2-svk.dts
index ea5603fd106a..2d7872a36b91 100644
--- a/arch/arm64/boot/dts/broadcom/ns2-svk.dts
+++ b/arch/arm64/boot/dts/broadcom/ns2-svk.dts
@@ -40,10 +40,14 @@
40 40
41 aliases { 41 aliases {
42 serial0 = &uart3; 42 serial0 = &uart3;
43 serial1 = &uart0;
44 serial2 = &uart1;
45 serial3 = &uart2;
43 }; 46 };
44 47
45 chosen { 48 chosen {
46 stdout-path = "serial0:115200n8"; 49 stdout-path = "serial0:115200n8";
50 bootargs = "earlycon=uart8250,mmio32,0x66130000";
47 }; 51 };
48 52
49 memory { 53 memory {
@@ -76,6 +80,18 @@
76 status = "ok"; 80 status = "ok";
77}; 81};
78 82
83&uart0 {
84 status = "ok";
85};
86
87&uart1 {
88 status = "ok";
89};
90
91&uart2 {
92 status = "ok";
93};
94
79&uart3 { 95&uart3 {
80 status = "ok"; 96 status = "ok";
81}; 97};
@@ -125,6 +141,18 @@
125 }; 141 };
126}; 142};
127 143
144&sata_phy0 {
145 status = "ok";
146};
147
148&sata_phy1 {
149 status = "ok";
150};
151
152&sata {
153 status = "ok";
154};
155
128&sdio0 { 156&sdio0 {
129 status = "ok"; 157 status = "ok";
130}; 158};
@@ -148,3 +176,12 @@
148 }; 176 };
149 }; 177 };
150}; 178};
179
180&pinctrl {
181 pinctrl-names = "default";
182 pinctrl-0 = <&nand_sel>;
183 nand_sel: nand_sel {
184 function = "nand";
185 groups = "nand_grp";
186 };
187};
diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi
index 46b78fa89f4c..f53b0955bfd3 100644
--- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
@@ -251,6 +251,22 @@
251 mmu-masters; 251 mmu-masters;
252 }; 252 };
253 253
254 pinctrl: pinctrl@6501d130 {
255 compatible = "brcm,ns2-pinmux";
256 reg = <0x6501d130 0x08>,
257 <0x660a0028 0x04>,
258 <0x660009b0 0x40>;
259 };
260
261 gpio_aon: gpio@65024800 {
262 compatible = "brcm,iproc-gpio";
263 reg = <0x65024800 0x50>,
264 <0x65024008 0x18>;
265 ngpios = <6>;
266 #gpio-cells = <2>;
267 gpio-controller;
268 };
269
254 gic: interrupt-controller@65210000 { 270 gic: interrupt-controller@65210000 {
255 compatible = "arm,gic-400"; 271 compatible = "arm,gic-400";
256 #interrupt-cells = <3>; 272 #interrupt-cells = <3>;
@@ -263,6 +279,26 @@
263 IRQ_TYPE_LEVEL_HIGH)>; 279 IRQ_TYPE_LEVEL_HIGH)>;
264 }; 280 };
265 281
282 cci@65590000 {
283 compatible = "arm,cci-400";
284 #address-cells = <1>;
285 #size-cells = <1>;
286 reg = <0x65590000 0x1000>;
287 ranges = <0 0x65590000 0x10000>;
288
289 pmu@9000 {
290 compatible = "arm,cci-400-pmu,r1",
291 "arm,cci-400-pmu";
292 reg = <0x9000 0x4000>;
293 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
299 };
300 };
301
266 mdio_mux_iproc: mdio-mux@6602023c { 302 mdio_mux_iproc: mdio-mux@6602023c {
267 compatible = "brcm,mdio-mux-iproc"; 303 compatible = "brcm,mdio-mux-iproc";
268 reg = <0x6602023c 0x14>; 304 reg = <0x6602023c 0x14>;
@@ -360,6 +396,16 @@
360 clock-names = "wdogclk", "apb_pclk"; 396 clock-names = "wdogclk", "apb_pclk";
361 }; 397 };
362 398
399 gpio_g: gpio@660a0000 {
400 compatible = "brcm,iproc-gpio";
401 reg = <0x660a0000 0x50>;
402 ngpios = <32>;
403 #gpio-cells = <2>;
404 gpio-controller;
405 interrupt-controller;
406 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
407 };
408
363 i2c1: i2c@660b0000 { 409 i2c1: i2c@660b0000 {
364 compatible = "brcm,iproc-i2c"; 410 compatible = "brcm,iproc-i2c";
365 reg = <0x660b0000 0x100>; 411 reg = <0x660b0000 0x100>;
@@ -370,6 +416,36 @@
370 status = "disabled"; 416 status = "disabled";
371 }; 417 };
372 418
419 uart0: serial@66100000 {
420 compatible = "snps,dw-apb-uart";
421 reg = <0x66100000 0x100>;
422 interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>;
423 clocks = <&iprocslow>;
424 reg-shift = <2>;
425 reg-io-width = <4>;
426 status = "disabled";
427 };
428
429 uart1: serial@66110000 {
430 compatible = "snps,dw-apb-uart";
431 reg = <0x66110000 0x100>;
432 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
433 clocks = <&iprocslow>;
434 reg-shift = <2>;
435 reg-io-width = <4>;
436 status = "disabled";
437 };
438
439 uart2: serial@66120000 {
440 compatible = "snps,dw-apb-uart";
441 reg = <0x66120000 0x100>;
442 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&iprocslow>;
444 reg-shift = <2>;
445 reg-io-width = <4>;
446 status = "disabled";
447 };
448
373 uart3: serial@66130000 { 449 uart3: serial@66130000 {
374 compatible = "snps,dw-apb-uart"; 450 compatible = "snps,dw-apb-uart";
375 reg = <0x66130000 0x100>; 451 reg = <0x66130000 0x100>;
@@ -407,6 +483,49 @@
407 reg = <0x66220000 0x28>; 483 reg = <0x66220000 0x28>;
408 }; 484 };
409 485
486 sata_phy: sata_phy@663f0100 {
487 compatible = "brcm,iproc-ns2-sata-phy";
488 reg = <0x663f0100 0x1f00>,
489 <0x663f004c 0x10>;
490 reg-names = "phy", "phy-ctrl";
491 #address-cells = <1>;
492 #size-cells = <0>;
493
494 sata_phy0: sata-phy@0 {
495 reg = <0>;
496 #phy-cells = <0>;
497 status = "disabled";
498 };
499
500 sata_phy1: sata-phy@1 {
501 reg = <1>;
502 #phy-cells = <0>;
503 status = "disabled";
504 };
505 };
506
507 sata: ahci@663f2000 {
508 compatible = "brcm,iproc-ahci", "generic-ahci";
509 reg = <0x663f2000 0x1000>;
510 reg-names = "ahci";
511 interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
512 #address-cells = <1>;
513 #size-cells = <0>;
514 status = "disabled";
515
516 sata0: sata-port@0 {
517 reg = <0>;
518 phys = <&sata_phy0>;
519 phy-names = "sata-phy";
520 };
521
522 sata1: sata-port@1 {
523 reg = <1>;
524 phys = <&sata_phy1>;
525 phy-names = "sata-phy";
526 };
527 };
528
410 sdio0: sdhci@66420000 { 529 sdio0: sdhci@66420000 {
411 compatible = "brcm,sdhci-iproc-cygnus"; 530 compatible = "brcm,sdhci-iproc-cygnus";
412 reg = <0x66420000 0x100>; 531 reg = <0x66420000 0x100>;
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index d8767b00862e..299f3ce969ab 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -249,7 +249,7 @@
249 249
250 buck2_reg: BUCK2 { 250 buck2_reg: BUCK2 {
251 regulator-name = "vdd_atlas"; 251 regulator-name = "vdd_atlas";
252 regulator-min-microvolt = <1200000>; 252 regulator-min-microvolt = <500000>;
253 regulator-max-microvolt = <1200000>; 253 regulator-max-microvolt = <1200000>;
254 regulator-always-on; 254 regulator-always-on;
255 regulator-boot-on; 255 regulator-boot-on;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 6bd46c133010..e669fbd7f9c3 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -51,7 +51,7 @@
51 #size-cells = <2>; 51 #size-cells = <2>;
52 52
53 cpus { 53 cpus {
54 #address-cells = <2>; 54 #address-cells = <1>;
55 #size-cells = <0>; 55 #size-cells = <0>;
56 56
57 /* 57 /*
@@ -63,29 +63,37 @@
63 cpu0: cpu@0 { 63 cpu0: cpu@0 {
64 device_type = "cpu"; 64 device_type = "cpu";
65 compatible = "arm,cortex-a53"; 65 compatible = "arm,cortex-a53";
66 reg = <0x0 0x0>; 66 reg = <0x0>;
67 clocks = <&clockgen 1 0>; 67 clocks = <&clockgen 1 0>;
68 next-level-cache = <&l2>;
68 }; 69 };
69 70
70 cpu1: cpu@1 { 71 cpu1: cpu@1 {
71 device_type = "cpu"; 72 device_type = "cpu";
72 compatible = "arm,cortex-a53"; 73 compatible = "arm,cortex-a53";
73 reg = <0x0 0x1>; 74 reg = <0x1>;
74 clocks = <&clockgen 1 0>; 75 clocks = <&clockgen 1 0>;
76 next-level-cache = <&l2>;
75 }; 77 };
76 78
77 cpu2: cpu@2 { 79 cpu2: cpu@2 {
78 device_type = "cpu"; 80 device_type = "cpu";
79 compatible = "arm,cortex-a53"; 81 compatible = "arm,cortex-a53";
80 reg = <0x0 0x2>; 82 reg = <0x2>;
81 clocks = <&clockgen 1 0>; 83 clocks = <&clockgen 1 0>;
84 next-level-cache = <&l2>;
82 }; 85 };
83 86
84 cpu3: cpu@3 { 87 cpu3: cpu@3 {
85 device_type = "cpu"; 88 device_type = "cpu";
86 compatible = "arm,cortex-a53"; 89 compatible = "arm,cortex-a53";
87 reg = <0x0 0x3>; 90 reg = <0x3>;
88 clocks = <&clockgen 1 0>; 91 clocks = <&clockgen 1 0>;
92 next-level-cache = <&l2>;
93 };
94
95 l2: l2-cache {
96 compatible = "cache";
89 }; 97 };
90 }; 98 };
91 99
@@ -465,6 +473,7 @@
465 interrupts = <0 60 0x4>; 473 interrupts = <0 60 0x4>;
466 dr_mode = "host"; 474 dr_mode = "host";
467 snps,quirk-frame-length-adjustment = <0x20>; 475 snps,quirk-frame-length-adjustment = <0x20>;
476 snps,dis_rxdet_inp3_quirk;
468 }; 477 };
469 478
470 usb1: usb3@3000000 { 479 usb1: usb3@3000000 {
@@ -473,6 +482,7 @@
473 interrupts = <0 61 0x4>; 482 interrupts = <0 61 0x4>;
474 dr_mode = "host"; 483 dr_mode = "host";
475 snps,quirk-frame-length-adjustment = <0x20>; 484 snps,quirk-frame-length-adjustment = <0x20>;
485 snps,dis_rxdet_inp3_quirk;
476 }; 486 };
477 487
478 usb2: usb3@3100000 { 488 usb2: usb3@3100000 {
@@ -481,6 +491,7 @@
481 interrupts = <0 63 0x4>; 491 interrupts = <0 63 0x4>;
482 dr_mode = "host"; 492 dr_mode = "host";
483 snps,quirk-frame-length-adjustment = <0x20>; 493 snps,quirk-frame-length-adjustment = <0x20>;
494 snps,dis_rxdet_inp3_quirk;
484 }; 495 };
485 496
486 sata: sata@3200000 { 497 sata: sata@3200000 {
@@ -522,6 +533,7 @@
522 #address-cells = <3>; 533 #address-cells = <3>;
523 #size-cells = <2>; 534 #size-cells = <2>;
524 device_type = "pci"; 535 device_type = "pci";
536 dma-coherent;
525 num-lanes = <4>; 537 num-lanes = <4>;
526 bus-range = <0x0 0xff>; 538 bus-range = <0x0 0xff>;
527 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 539 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
@@ -546,6 +558,7 @@
546 #address-cells = <3>; 558 #address-cells = <3>;
547 #size-cells = <2>; 559 #size-cells = <2>;
548 device_type = "pci"; 560 device_type = "pci";
561 dma-coherent;
549 num-lanes = <2>; 562 num-lanes = <2>;
550 bus-range = <0x0 0xff>; 563 bus-range = <0x0 0xff>;
551 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ 564 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
@@ -570,6 +583,7 @@
570 #address-cells = <3>; 583 #address-cells = <3>;
571 #size-cells = <2>; 584 #size-cells = <2>;
572 device_type = "pci"; 585 device_type = "pci";
586 dma-coherent;
573 num-lanes = <2>; 587 num-lanes = <2>;
574 bus-range = <0x0 0xff>; 588 bus-range = <0x0 0xff>;
575 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ 589 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index 3187c822afa3..21023a388c29 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -51,7 +51,7 @@
51 #size-cells = <2>; 51 #size-cells = <2>;
52 52
53 cpus { 53 cpus {
54 #address-cells = <2>; 54 #address-cells = <1>;
55 #size-cells = <0>; 55 #size-cells = <0>;
56 56
57 /* 57 /*
@@ -65,57 +65,81 @@
65 cpu@0 { 65 cpu@0 {
66 device_type = "cpu"; 66 device_type = "cpu";
67 compatible = "arm,cortex-a57"; 67 compatible = "arm,cortex-a57";
68 reg = <0x0 0x0>; 68 reg = <0x0>;
69 clocks = <&clockgen 1 0>; 69 clocks = <&clockgen 1 0>;
70 next-level-cache = <&cluster0_l2>;
70 }; 71 };
71 72
72 cpu@1 { 73 cpu@1 {
73 device_type = "cpu"; 74 device_type = "cpu";
74 compatible = "arm,cortex-a57"; 75 compatible = "arm,cortex-a57";
75 reg = <0x0 0x1>; 76 reg = <0x1>;
76 clocks = <&clockgen 1 0>; 77 clocks = <&clockgen 1 0>;
78 next-level-cache = <&cluster0_l2>;
77 }; 79 };
78 80
79 cpu@100 { 81 cpu@100 {
80 device_type = "cpu"; 82 device_type = "cpu";
81 compatible = "arm,cortex-a57"; 83 compatible = "arm,cortex-a57";
82 reg = <0x0 0x100>; 84 reg = <0x100>;
83 clocks = <&clockgen 1 1>; 85 clocks = <&clockgen 1 1>;
86 next-level-cache = <&cluster1_l2>;
84 }; 87 };
85 88
86 cpu@101 { 89 cpu@101 {
87 device_type = "cpu"; 90 device_type = "cpu";
88 compatible = "arm,cortex-a57"; 91 compatible = "arm,cortex-a57";
89 reg = <0x0 0x101>; 92 reg = <0x101>;
90 clocks = <&clockgen 1 1>; 93 clocks = <&clockgen 1 1>;
94 next-level-cache = <&cluster1_l2>;
91 }; 95 };
92 96
93 cpu@200 { 97 cpu@200 {
94 device_type = "cpu"; 98 device_type = "cpu";
95 compatible = "arm,cortex-a57"; 99 compatible = "arm,cortex-a57";
96 reg = <0x0 0x200>; 100 reg = <0x200>;
97 clocks = <&clockgen 1 2>; 101 clocks = <&clockgen 1 2>;
102 next-level-cache = <&cluster2_l2>;
98 }; 103 };
99 104
100 cpu@201 { 105 cpu@201 {
101 device_type = "cpu"; 106 device_type = "cpu";
102 compatible = "arm,cortex-a57"; 107 compatible = "arm,cortex-a57";
103 reg = <0x0 0x201>; 108 reg = <0x201>;
104 clocks = <&clockgen 1 2>; 109 clocks = <&clockgen 1 2>;
110 next-level-cache = <&cluster2_l2>;
105 }; 111 };
106 112
107 cpu@300 { 113 cpu@300 {
108 device_type = "cpu"; 114 device_type = "cpu";
109 compatible = "arm,cortex-a57"; 115 compatible = "arm,cortex-a57";
110 reg = <0x0 0x300>; 116 reg = <0x300>;
111 clocks = <&clockgen 1 3>; 117 clocks = <&clockgen 1 3>;
118 next-level-cache = <&cluster3_l2>;
112 }; 119 };
113 120
114 cpu@301 { 121 cpu@301 {
115 device_type = "cpu"; 122 device_type = "cpu";
116 compatible = "arm,cortex-a57"; 123 compatible = "arm,cortex-a57";
117 reg = <0x0 0x301>; 124 reg = <0x301>;
118 clocks = <&clockgen 1 3>; 125 clocks = <&clockgen 1 3>;
126 next-level-cache = <&cluster3_l2>;
127 };
128
129 cluster0_l2: l2-cache0 {
130 compatible = "cache";
131 };
132
133 cluster1_l2: l2-cache1 {
134 compatible = "cache";
135 };
136
137 cluster2_l2: l2-cache2 {
138 compatible = "cache";
139 };
140
141 cluster3_l2: l2-cache3 {
142 compatible = "cache";
119 }; 143 };
120 }; 144 };
121 145
@@ -672,6 +696,7 @@
672 interrupts = <0 80 0x4>; /* Level high type */ 696 interrupts = <0 80 0x4>; /* Level high type */
673 dr_mode = "host"; 697 dr_mode = "host";
674 snps,quirk-frame-length-adjustment = <0x20>; 698 snps,quirk-frame-length-adjustment = <0x20>;
699 snps,dis_rxdet_inp3_quirk;
675 }; 700 };
676 701
677 usb1: usb3@3110000 { 702 usb1: usb3@3110000 {
@@ -681,6 +706,7 @@
681 interrupts = <0 81 0x4>; /* Level high type */ 706 interrupts = <0 81 0x4>; /* Level high type */
682 dr_mode = "host"; 707 dr_mode = "host";
683 snps,quirk-frame-length-adjustment = <0x20>; 708 snps,quirk-frame-length-adjustment = <0x20>;
709 snps,dis_rxdet_inp3_quirk;
684 }; 710 };
685 711
686 ccn@4000000 { 712 ccn@4000000 {
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
index e92a30c87a82..593c7e43de79 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
@@ -66,6 +66,149 @@
66 status = "ok"; 66 status = "ok";
67 }; 67 };
68 68
69 /*
70 * Legend: proper name = the GPIO line is used as GPIO
71 * NC = not connected (not routed from the SoC)
72 * "[PER]" = pin is muxed for peripheral (not GPIO)
73 * "" = no idea, schematic doesn't say, could be
74 * unrouted (not connected to any external pin)
75 * LSEC = Low Speed External Connector
76 * HSEC = High Speed External Connector
77 *
78 * Pin assignments taken from LeMaker and CircuitCo Schematics
79 * Rev A1.
80 *
81 * For the lines routed to the external connectors the
82 * lines are named after the 96Boards CE Specification 1.0,
83 * Appendix "Expansion Connector Signal Description".
84 *
85 * When the 96Board naming of a line and the schematic name of
86 * the same line are in conflict, the 96Board specification
87 * takes precedence, which means that the external UART on the
88 * LSEC is named UART0 while the schematic and SoC names this
89 * UART2. This is only for the informational lines i.e. "[FOO]",
90 * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
91 * ones actually used for GPIO.
92 */
93 gpio0: gpio@f8011000 {
94 gpio-line-names = "PWR_HOLD", "DSI_SEL",
95 "USB_HUB_RESET_N", "USB_SEL", "HDMI_PD", "WL_REG_ON",
96 "PWRON_DET", "5V_HUB_EN";
97 };
98
99 gpio1: gpio@f8012000 {
100 gpio-line-names = "SD_DET", "HDMI_INT", "PMU_IRQ_N",
101 "WL_HOST_WAKE", "NC", "NC", "NC", "BT_REG_ON";
102 };
103
104 gpio2: gpio@f8013000 {
105 gpio-line-names =
106 "GPIO-A", /* LSEC Pin 23: GPIO2_0 */
107 "GPIO-B", /* LSEC Pin 24: GPIO2_1 */
108 "GPIO-C", /* LSEC Pin 25: GPIO2_2 */
109 "GPIO-D", /* LSEC Pin 26: GPIO2_3 */
110 "GPIO-E", /* LSEC Pin 27: GPIO2_4 */
111 "USB_ID_DET", "USB_VBUS_DET",
112 "GPIO-H"; /* LSEC Pin 30: GPIO2_7 */
113 };
114
115 gpio3: gpio@f8014000 {
116 gpio-line-names = "GPIO3_0", "NC", "NC", "", "NC", "",
117 "WLAN_ACTIVE", "NC", "NC";
118 };
119
120 gpio4: gpio@f7020000 {
121 gpio-line-names = "USER_LED1", "USER_LED2", "USER_LED3",
122 "USER_LED4", "SD_SEL", "NC", "NC", "BT_ACTIVE";
123 };
124
125 gpio5: gpio@f7021000 {
126 gpio-line-names = "NC", "NC",
127 "[UART1_RxD]", /* LSEC Pin 11: UART3_RX */
128 "[UART1_TxD]", /* LSEC Pin 13: UART3_TX */
129 "[AUX_SSI1]", "NC",
130 "[PCM_CLK]", /* LSEC Pin 18: MODEM_PCM_XCLK */
131 "[PCM_FS]"; /* LSEC Pin 16: MODEM_PCM_XFS */
132 };
133
134 gpio6: gpio@f7022000 {
135 gpio-line-names =
136 "[SPI0_DIN]", /* Pin 10: SPI0_DI */
137 "[SPI0_DOUT]", /* Pin 14: SPI0_DO */
138 "[SPI0_CS]", /* Pin 12: SPI0_CS_N */
139 "[SPI0_SCLK]", /* Pin 8: SPI0_SCLK */
140 "NC", "NC", "NC",
141 "GPIO-G"; /* Pin 29: GPIO6_7_DSI_TE0 */
142 };
143
144 gpio7: gpio@f7023000 {
145 gpio-line-names = "NC", "NC", "NC", "NC",
146 "[PCM_DI]", /* Pin 22: MODEM_PCM_DI */
147 "[PCM_DO]", /* Pin 20: MODEM_PCM_DO */
148 "NC", "NC";
149 };
150
151 gpio8: gpio@f7024000 {
152 gpio-line-names = "NC", "[CEC_CLK_19_2MHZ]", "NC",
153 "", "", "", "", "", "";
154 };
155
156 gpio9: gpio@f7025000 {
157 gpio-line-names = "",
158 "GPIO-J", /* LSEC Pin 32: ISP_PWDN0_GPIO9_1 */
159 "GPIO-L", /* LSEC Pin 34: ISP_PWDN1_GPIO9_2 */
160 "NC", "NC", "NC", "NC", "[ISP_CCLK0]";
161 };
162
163 gpio10: gpio@f7026000 {
164 gpio-line-names = "BOOT_SEL",
165 "[ISP_CCLK1]",
166 "GPIO-I", /* LSEC Pin 31: ISP_RSTB0_GPIO10_2 */
167 "GPIO-K", /* LSEC Pin 33: ISP_RSTB1_GPIO10_3 */
168 "NC", "NC",
169 "[I2C2_SDA]", /* HSEC Pin 34: ISP0_SDA */
170 "[I2C2_SCL]"; /* HSEC Pin 32: ISP0_SCL */
171 };
172
173 gpio11: gpio@f7027000 {
174 gpio-line-names =
175 "[I2C3_SDA]", /* HSEC Pin 38: ISP1_SDA */
176 "[I2C3_SCL]", /* HSEC Pin 36: ISP1_SCL */
177 "", "NC", "NC", "NC", "", "";
178 };
179
180 gpio12: gpio@f7028000 {
181 gpio-line-names = "[BT_PCM_XFS]", "[BT_PCM_DI]",
182 "[BT_PCM_DO]",
183 "NC", "NC", "NC", "NC",
184 "GPIO-F"; /* LSEC Pin 28: BL_PWM_GPIO12_7 */
185 };
186
187 gpio13: gpio@f7029000 {
188 gpio-line-names = "[UART0_RX]", "[UART0_TX]",
189 "[BT_UART1_CTS]", "[BT_UART1_RTS]",
190 "[BT_UART1_RX]", "[BT_UART1_TX]",
191 "[UART0_CTS]", /* LSEC Pin 3: UART2_CTS_N */
192 "[UART0_RTS]"; /* LSEC Pin 9: UART2_RTS_N */
193 };
194
195 gpio14: gpio@f702a000 {
196 gpio-line-names =
197 "[UART0_RxD]", /* LSEC Pin 7: UART2_RX */
198 "[UART0_TxD]", /* LSEC Pin 5: UART2_TX */
199 "[I2C0_SCL]", /* LSEC Pin 15: I2C0_SCL */
200 "[I2C0_SDA]", /* LSEC Pin 17: I2C0_SDA */
201 "[I2C1_SCL]", /* LSEC Pin 19: I2C1_SCL */
202 "[I2C1_SDA]", /* LSEC Pin 21: I2C1_SDA */
203 "[I2C2_SCL]", "[I2C2_SDA]";
204 };
205
206 gpio15: gpio@f702b000 {
207 gpio-line-names = "", "", "", "", "", "", "NC", "";
208 };
209
210 /* GPIO blocks 16 thru 19 do not appear to be routed to pins */
211
69 dwmmc_2: dwmmc2@f723f000 { 212 dwmmc_2: dwmmc2@f723f000 {
70 ti,non-removable; 213 ti,non-removable;
71 non-removable; 214 non-removable;
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index c19b82799a34..4f270410a5cb 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -338,6 +338,22 @@
338 clock-names = "timer1", "timer2", "apb_pclk"; 338 clock-names = "timer1", "timer2", "apb_pclk";
339 }; 339 };
340 340
341 rtc0: rtc@f8003000 {
342 compatible = "arm,pl031", "arm,primecell";
343 reg = <0x0 0xf8003000 0x0 0x1000>;
344 interrupts = <0 12 4>;
345 clocks = <&ao_ctrl HI6220_RTC0_PCLK>;
346 clock-names = "apb_pclk";
347 };
348
349 rtc1: rtc@f8004000 {
350 compatible = "arm,pl031", "arm,primecell";
351 reg = <0x0 0xf8004000 0x0 0x1000>;
352 interrupts = <0 8 4>;
353 clocks = <&ao_ctrl HI6220_RTC1_PCLK>;
354 clock-names = "apb_pclk";
355 };
356
341 pmx0: pinmux@f7010000 { 357 pmx0: pinmux@f7010000 {
342 compatible = "pinctrl-single"; 358 compatible = "pinctrl-single";
343 reg = <0x0 0xf7010000 0x0 0x27c>; 359 reg = <0x0 0xf7010000 0x0 0x27c>;
diff --git a/arch/arm64/boot/dts/lg/Makefile b/arch/arm64/boot/dts/lg/Makefile
index b0cc64964171..5c7b54c12adc 100644
--- a/arch/arm64/boot/dts/lg/Makefile
+++ b/arch/arm64/boot/dts/lg/Makefile
@@ -1,4 +1,5 @@
1dtb-$(CONFIG_ARCH_LG1K) += lg1312-ref.dtb 1dtb-$(CONFIG_ARCH_LG1K) += lg1312-ref.dtb
2dtb-$(CONFIG_ARCH_LG1K) += lg1313-ref.dtb
2 3
3always := $(dtb-y) 4always := $(dtb-y)
4subdir-y := $(dts-dirs) 5subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/lg/lg1313-ref.dts b/arch/arm64/boot/dts/lg/lg1313-ref.dts
new file mode 100644
index 000000000000..df0ece43cfbf
--- /dev/null
+++ b/arch/arm64/boot/dts/lg/lg1313-ref.dts
@@ -0,0 +1,36 @@
1/*
2 * dts file for lg1313 Reference Board.
3 *
4 * Copyright (C) 2016, LG Electronics
5 */
6
7/dts-v1/;
8
9#include "lg1313.dtsi"
10
11/ {
12 #address-cells = <2>;
13 #size-cells = <1>;
14
15 model = "LG Electronics, DTV SoC LG1313 Reference Board";
16 compatible = "lge,lg1313-ref", "lge,lg1313";
17
18 aliases {
19 serial0 = &uart0;
20 serial1 = &uart1;
21 serial2 = &uart2;
22 };
23
24 memory {
25 device_type = "memory";
26 reg = <0x0 0x00000000 0x20000000>;
27 };
28
29 chosen {
30 stdout-path = "serial0:115200n8";
31 };
32};
33
34&uart0 {
35 status = "okay";
36};
diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg1313.dtsi
new file mode 100644
index 000000000000..e703e1149c75
--- /dev/null
+++ b/arch/arm64/boot/dts/lg/lg1313.dtsi
@@ -0,0 +1,351 @@
1/*
2 * dts file for lg1313 SoC
3 *
4 * Copyright (C) 2016, LG Electronics
5 */
6
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9
10/ {
11 #address-cells = <2>;
12 #size-cells = <2>;
13
14 compatible = "lge,lg1313";
15 interrupt-parent = <&gic>;
16
17 cpus {
18 #address-cells = <2>;
19 #size-cells = <0>;
20
21 cpu0: cpu@0 {
22 device_type = "cpu";
23 compatible = "arm,cortex-a53", "arm,armv8";
24 reg = <0x0 0x0>;
25 next-level-cache = <&L2_0>;
26 };
27 cpu1: cpu@1 {
28 device_type = "cpu";
29 compatible = "arm,cortex-a53", "arm,armv8";
30 reg = <0x0 0x1>;
31 enable-method = "psci";
32 next-level-cache = <&L2_0>;
33 };
34 cpu2: cpu@2 {
35 device_type = "cpu";
36 compatible = "arm,cortex-a53", "arm,armv8";
37 reg = <0x0 0x2>;
38 enable-method = "psci";
39 next-level-cache = <&L2_0>;
40 };
41 cpu3: cpu@3 {
42 device_type = "cpu";
43 compatible = "arm,cortex-a53", "arm,armv8";
44 reg = <0x0 0x3>;
45 enable-method = "psci";
46 next-level-cache = <&L2_0>;
47 };
48 L2_0: l2-cache0 {
49 compatible = "cache";
50 };
51 };
52
53 psci {
54 compatible = "arm,psci-0.2", "arm,psci";
55 method = "smc";
56 cpu_suspend = <0x84000001>;
57 cpu_off = <0x84000002>;
58 cpu_on = <0x84000003>;
59 };
60
61 gic: interrupt-controller@c0001000 {
62 #interrupt-cells = <3>;
63 compatible = "arm,gic-400";
64 interrupt-controller;
65 reg = <0x0 0xc0001000 0x1000>,
66 <0x0 0xc0002000 0x2000>,
67 <0x0 0xc0004000 0x2000>,
68 <0x0 0xc0006000 0x2000>;
69 };
70
71 pmu {
72 compatible = "arm,cortex-a53-pmu";
73 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
74 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
75 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
77 interrupt-affinity = <&cpu0>,
78 <&cpu1>,
79 <&cpu2>,
80 <&cpu3>;
81 };
82
83 timer {
84 compatible = "arm,armv8-timer";
85 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x0f) |
86 IRQ_TYPE_LEVEL_LOW)>,
87 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x0f) |
88 IRQ_TYPE_LEVEL_LOW)>,
89 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x0f) |
90 IRQ_TYPE_LEVEL_LOW)>,
91 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x0f) |
92 IRQ_TYPE_LEVEL_LOW)>;
93 };
94
95 clk_bus: clk_bus {
96 #clock-cells = <0>;
97
98 compatible = "fixed-clock";
99 clock-frequency = <198000000>;
100 clock-output-names = "BUSCLK";
101 };
102
103 soc {
104 #address-cells = <2>;
105 #size-cells = <1>;
106
107 compatible = "simple-bus";
108 interrupt-parent = <&gic>;
109 ranges;
110
111 eth0: ethernet@c3700000 {
112 compatible = "cdns,gem";
113 reg = <0x0 0xc3700000 0x1000>;
114 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
115 clocks = <&clk_bus>, <&clk_bus>;
116 clock-names = "hclk", "pclk";
117 phy-mode = "rmii";
118 /* Filled in by boot */
119 mac-address = [ 00 00 00 00 00 00 ];
120 };
121 };
122
123 amba {
124 #address-cells = <2>;
125 #size-cells = <1>;
126 #interrupts-cells = <3>;
127
128 compatible = "simple-bus";
129 interrupt-parent = <&gic>;
130 ranges;
131
132 timers: timer@fd100000 {
133 compatible = "arm,sp804";
134 reg = <0x0 0xfd100000 0x1000>;
135 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
136 clocks = <&clk_bus>;
137 clock-names = "apb_pclk";
138 };
139 wdog: watchdog@fd200000 {
140 compatible = "arm,sp805", "arm,primecell";
141 reg = <0x0 0xfd200000 0x1000>;
142 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
143 clocks = <&clk_bus>;
144 clock-names = "apb_pclk";
145 };
146 uart0: serial@fe000000 {
147 compatible = "arm,pl011", "arm,primecell";
148 reg = <0x0 0xfe000000 0x1000>;
149 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
150 clocks = <&clk_bus>;
151 clock-names = "apb_pclk";
152 status="disabled";
153 };
154 uart1: serial@fe100000 {
155 compatible = "arm,pl011", "arm,primecell";
156 reg = <0x0 0xfe100000 0x1000>;
157 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
158 clocks = <&clk_bus>;
159 clock-names = "apb_pclk";
160 status="disabled";
161 };
162 uart2: serial@fe200000 {
163 compatible = "arm,pl011", "arm,primecell";
164 reg = <0x0 0xfe200000 0x1000>;
165 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
166 clocks = <&clk_bus>;
167 clock-names = "apb_pclk";
168 status="disabled";
169 };
170 spi0: ssp@fe800000 {
171 compatible = "arm,pl022", "arm,primecell";
172 reg = <0x0 0xfe800000 0x1000>;
173 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
174 clocks = <&clk_bus>;
175 clock-names = "apb_pclk";
176 };
177 spi1: ssp@fe900000 {
178 compatible = "arm,pl022", "arm,primecell";
179 reg = <0x0 0xfe900000 0x1000>;
180 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
181 clocks = <&clk_bus>;
182 clock-names = "apb_pclk";
183 };
184 dmac0: dma@c1128000 {
185 compatible = "arm,pl330", "arm,primecell";
186 reg = <0x0 0xc1128000 0x1000>;
187 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
188 clocks = <&clk_bus>;
189 clock-names = "apb_pclk";
190 };
191 gpio0: gpio@fd400000 {
192 #gpio-cells = <2>;
193 compatible = "arm,pl061", "arm,primecell";
194 gpio-controller;
195 reg = <0x0 0xfd400000 0x1000>;
196 clocks = <&clk_bus>;
197 clock-names = "apb_pclk";
198 status="disabled";
199 };
200 gpio1: gpio@fd410000 {
201 #gpio-cells = <2>;
202 compatible = "arm,pl061", "arm,primecell";
203 gpio-controller;
204 reg = <0x0 0xfd410000 0x1000>;
205 clocks = <&clk_bus>;
206 clock-names = "apb_pclk";
207 status="disabled";
208 };
209 gpio2: gpio@fd420000 {
210 #gpio-cells = <2>;
211 compatible = "arm,pl061", "arm,primecell";
212 gpio-controller;
213 reg = <0x0 0xfd420000 0x1000>;
214 clocks = <&clk_bus>;
215 clock-names = "apb_pclk";
216 status="disabled";
217 };
218 gpio3: gpio@fd430000 {
219 #gpio-cells = <2>;
220 compatible = "arm,pl061", "arm,primecell";
221 gpio-controller;
222 reg = <0x0 0xfd430000 0x1000>;
223 clocks = <&clk_bus>;
224 clock-names = "apb_pclk";
225 };
226 gpio4: gpio@fd440000 {
227 #gpio-cells = <2>;
228 compatible = "arm,pl061", "arm,primecell";
229 gpio-controller;
230 reg = <0x0 0xfd440000 0x1000>;
231 clocks = <&clk_bus>;
232 clock-names = "apb_pclk";
233 status="disabled";
234 };
235 gpio5: gpio@fd450000 {
236 #gpio-cells = <2>;
237 compatible = "arm,pl061", "arm,primecell";
238 gpio-controller;
239 reg = <0x0 0xfd450000 0x1000>;
240 clocks = <&clk_bus>;
241 clock-names = "apb_pclk";
242 status="disabled";
243 };
244 gpio6: gpio@fd460000 {
245 #gpio-cells = <2>;
246 compatible = "arm,pl061", "arm,primecell";
247 gpio-controller;
248 reg = <0x0 0xfd460000 0x1000>;
249 clocks = <&clk_bus>;
250 clock-names = "apb_pclk";
251 status="disabled";
252 };
253 gpio7: gpio@fd470000 {
254 #gpio-cells = <2>;
255 compatible = "arm,pl061", "arm,primecell";
256 gpio-controller;
257 reg = <0x0 0xfd470000 0x1000>;
258 clocks = <&clk_bus>;
259 clock-names = "apb_pclk";
260 status="disabled";
261 };
262 gpio8: gpio@fd480000 {
263 #gpio-cells = <2>;
264 compatible = "arm,pl061", "arm,primecell";
265 gpio-controller;
266 reg = <0x0 0xfd480000 0x1000>;
267 clocks = <&clk_bus>;
268 clock-names = "apb_pclk";
269 status="disabled";
270 };
271 gpio9: gpio@fd490000 {
272 #gpio-cells = <2>;
273 compatible = "arm,pl061", "arm,primecell";
274 gpio-controller;
275 reg = <0x0 0xfd490000 0x1000>;
276 clocks = <&clk_bus>;
277 clock-names = "apb_pclk";
278 status="disabled";
279 };
280 gpio10: gpio@fd4a0000 {
281 #gpio-cells = <2>;
282 compatible = "arm,pl061", "arm,primecell";
283 gpio-controller;
284 reg = <0x0 0xfd4a0000 0x1000>;
285 clocks = <&clk_bus>;
286 clock-names = "apb_pclk";
287 status="disabled";
288 };
289 gpio11: gpio@fd4b0000 {
290 #gpio-cells = <2>;
291 compatible = "arm,pl061", "arm,primecell";
292 gpio-controller;
293 reg = <0x0 0xfd4b0000 0x1000>;
294 clocks = <&clk_bus>;
295 clock-names = "apb_pclk";
296 };
297 gpio12: gpio@fd4c0000 {
298 #gpio-cells = <2>;
299 compatible = "arm,pl061", "arm,primecell";
300 gpio-controller;
301 reg = <0x0 0xfd4c0000 0x1000>;
302 clocks = <&clk_bus>;
303 clock-names = "apb_pclk";
304 status="disabled";
305 };
306 gpio13: gpio@fd4d0000 {
307 #gpio-cells = <2>;
308 compatible = "arm,pl061", "arm,primecell";
309 gpio-controller;
310 reg = <0x0 0xfd4d0000 0x1000>;
311 clocks = <&clk_bus>;
312 clock-names = "apb_pclk";
313 status="disabled";
314 };
315 gpio14: gpio@fd4e0000 {
316 #gpio-cells = <2>;
317 compatible = "arm,pl061", "arm,primecell";
318 gpio-controller;
319 reg = <0x0 0xfd4e0000 0x1000>;
320 clocks = <&clk_bus>;
321 clock-names = "apb_pclk";
322 status="disabled";
323 };
324 gpio15: gpio@fd4f0000 {
325 #gpio-cells = <2>;
326 compatible = "arm,pl061", "arm,primecell";
327 gpio-controller;
328 reg = <0x0 0xfd4f0000 0x1000>;
329 clocks = <&clk_bus>;
330 clock-names = "apb_pclk";
331 status="disabled";
332 };
333 gpio16: gpio@fd500000 {
334 #gpio-cells = <2>;
335 compatible = "arm,pl061", "arm,primecell";
336 gpio-controller;
337 reg = <0x0 0xfd500000 0x1000>;
338 clocks = <&clk_bus>;
339 clock-names = "apb_pclk";
340 status="disabled";
341 };
342 gpio17: gpio@fd510000 {
343 #gpio-cells = <2>;
344 compatible = "arm,pl061", "arm,primecell";
345 gpio-controller;
346 reg = <0x0 0xfd510000 0x1000>;
347 clocks = <&clk_bus>;
348 clock-names = "apb_pclk";
349 };
350 };
351};
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index 9e2efb882983..eb29280962d7 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -105,6 +105,41 @@
105 status = "disabled"; 105 status = "disabled";
106 }; 106 };
107 107
108 nb_perih_clk: nb-periph-clk@13000{
109 compatible = "marvell,armada-3700-periph-clock-nb";
110 reg = <0x13000 0x100>;
111 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
112 <&tbg 3>, <&xtalclk>;
113 #clock-cells = <1>;
114 };
115
116 sb_perih_clk: sb-periph-clk@18000{
117 compatible = "marvell,armada-3700-periph-clock-sb";
118 reg = <0x18000 0x100>;
119 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
120 <&tbg 3>, <&xtalclk>;
121 #clock-cells = <1>;
122 };
123
124 tbg: tbg@13200 {
125 compatible = "marvell,armada-3700-tbg-clock";
126 reg = <0x13200 0x100>;
127 clocks = <&xtalclk>;
128 #clock-cells = <1>;
129 };
130
131 gpio1: gpio@13800 {
132 compatible = "marvell,mvebu-gpio-3700",
133 "syscon", "simple-mfd";
134 reg = <0x13800 0x500>;
135
136 xtalclk: xtal-clk {
137 compatible = "marvell,armada-3700-xtal-clock";
138 clock-output-names = "xtal";
139 #clock-cells = <0>;
140 };
141 };
142
108 usb3: usb@58000 { 143 usb3: usb@58000 {
109 compatible = "marvell,armada3700-xhci", 144 compatible = "marvell,armada3700-xhci",
110 "generic-xhci"; 145 "generic-xhci";
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index 20d256b32670..eab1a42fb934 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -141,7 +141,7 @@
141 }; 141 };
142 142
143 xor@400000 { 143 xor@400000 {
144 compatible = "marvell,mv-xor-v2"; 144 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
145 reg = <0x400000 0x1000>, 145 reg = <0x400000 0x1000>,
146 <0x410000 0x1000>; 146 <0x410000 0x1000>;
147 msi-parent = <&gic_v2m0>; 147 msi-parent = <&gic_v2m0>;
@@ -149,7 +149,7 @@
149 }; 149 };
150 150
151 xor@420000 { 151 xor@420000 {
152 compatible = "marvell,mv-xor-v2"; 152 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
153 reg = <0x420000 0x1000>, 153 reg = <0x420000 0x1000>,
154 <0x430000 0x1000>; 154 <0x430000 0x1000>;
155 msi-parent = <&gic_v2m0>; 155 msi-parent = <&gic_v2m0>;
@@ -157,7 +157,7 @@
157 }; 157 };
158 158
159 xor@440000 { 159 xor@440000 {
160 compatible = "marvell,mv-xor-v2"; 160 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
161 reg = <0x440000 0x1000>, 161 reg = <0x440000 0x1000>,
162 <0x450000 0x1000>; 162 <0x450000 0x1000>;
163 msi-parent = <&gic_v2m0>; 163 msi-parent = <&gic_v2m0>;
@@ -165,7 +165,7 @@
165 }; 165 };
166 166
167 xor@460000 { 167 xor@460000 {
168 compatible = "marvell,mv-xor-v2"; 168 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
169 reg = <0x460000 0x1000>, 169 reg = <0x460000 0x1000>,
170 <0x470000 0x1000>; 170 <0x470000 0x1000>;
171 msi-parent = <&gic_v2m0>; 171 msi-parent = <&gic_v2m0>;
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
index 367138bae3e0..da31bbbbb59e 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
@@ -107,6 +107,24 @@
107 status = "disabled"; 107 status = "disabled";
108 }; 108 };
109 109
110 cpm_xor0: xor@6a0000 {
111 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
112 reg = <0x6a0000 0x1000>,
113 <0x6b0000 0x1000>;
114 dma-coherent;
115 msi-parent = <&gic_v2m0>;
116 clocks = <&cpm_syscon0 1 8>;
117 };
118
119 cpm_xor1: xor@6c0000 {
120 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
121 reg = <0x6c0000 0x1000>,
122 <0x6d0000 0x1000>;
123 dma-coherent;
124 msi-parent = <&gic_v2m0>;
125 clocks = <&cpm_syscon0 1 7>;
126 };
127
110 cpm_spi0: spi@700600 { 128 cpm_spi0: spi@700600 {
111 compatible = "marvell,armada-380-spi"; 129 compatible = "marvell,armada-380-spi";
112 reg = <0x700600 0x50>; 130 reg = <0x700600 0x50>;
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index e0a4bff2fc17..9fbfd3238469 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,3 +1,4 @@
1dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
1dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb 2dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
2dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb 3dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
3 4
diff --git a/arch/arm64/boot/dts/mediatek/mt6755-evb.dts b/arch/arm64/boot/dts/mediatek/mt6755-evb.dts
new file mode 100644
index 000000000000..c568d49235af
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6755-evb.dts
@@ -0,0 +1,38 @@
1/*
2 * Copyright (c) 2016 MediaTek Inc.
3 * Author: Mars.C <mars.cheng@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15/dts-v1/;
16#include "mt6755.dtsi"
17
18/ {
19 model = "MediaTek MT6755 EVB";
20 compatible = "mediatek,mt6755-evb", "mediatek,mt6755";
21
22 aliases {
23 serial0 = &uart0;
24 };
25
26 memory@40000000 {
27 device_type = "memory";
28 reg = <0 0x40000000 0 0x1e800000>;
29 };
30
31 chosen {
32 stdout-path = "serial0:921600n8";
33 };
34};
35
36&uart0 {
37 status = "okay";
38};
diff --git a/arch/arm64/boot/dts/mediatek/mt6755.dtsi b/arch/arm64/boot/dts/mediatek/mt6755.dtsi
new file mode 100644
index 000000000000..01ba77669717
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6755.dtsi
@@ -0,0 +1,145 @@
1/*
2 * Copyright (c) 2016 MediaTek Inc.
3 * Author: Mars.C <mars.cheng@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/interrupt-controller/arm-gic.h>
16
17/ {
18 compatible = "mediatek,mt6755";
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
21 #size-cells = <2>;
22
23 psci {
24 compatible = "arm,psci-0.2";
25 method = "smc";
26 };
27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 cpu0: cpu@0 {
33 device_type = "cpu";
34 compatible = "arm,cortex-a53";
35 enable-method = "psci";
36 reg = <0x000>;
37 };
38
39 cpu1: cpu@1 {
40 device_type = "cpu";
41 compatible = "arm,cortex-a53";
42 enable-method = "psci";
43 reg = <0x001>;
44 };
45
46 cpu2: cpu@2 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a53";
49 enable-method = "psci";
50 reg = <0x002>;
51 };
52
53 cpu3: cpu@3 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a53";
56 enable-method = "psci";
57 reg = <0x003>;
58 };
59
60 cpu4: cpu@100 {
61 device_type = "cpu";
62 compatible = "arm,cortex-a53";
63 enable-method = "psci";
64 reg = <0x100>;
65 };
66
67 cpu5: cpu@101 {
68 device_type = "cpu";
69 compatible = "arm,cortex-a53";
70 enable-method = "psci";
71 reg = <0x101>;
72 };
73
74 cpu6: cpu@102 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a53";
77 enable-method = "psci";
78 reg = <0x102>;
79 };
80
81 cpu7: cpu@103 {
82 device_type = "cpu";
83 compatible = "arm,cortex-a53";
84 enable-method = "psci";
85 reg = <0x103>;
86 };
87 };
88
89 uart_clk: dummy26m {
90 compatible = "fixed-clock";
91 clock-frequency = <26000000>;
92 #clock-cells = <0>;
93 };
94
95 timer {
96 compatible = "arm,armv8-timer";
97 interrupt-parent = <&gic>;
98 interrupts = <GIC_PPI 13
99 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
100 <GIC_PPI 14
101 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
102 <GIC_PPI 11
103 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
104 <GIC_PPI 10
105 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
106 };
107
108 sysirq: intpol-controller@10200620 {
109 compatible = "mediatek,mt6755-sysirq",
110 "mediatek,mt6577-sysirq";
111 interrupt-controller;
112 #interrupt-cells = <3>;
113 interrupt-parent = <&gic>;
114 reg = <0 0x10200620 0 0x20>;
115 };
116
117 gic: interrupt-controller@10231000 {
118 compatible = "arm,gic-400";
119 #interrupt-cells = <3>;
120 interrupt-parent = <&gic>;
121 interrupt-controller;
122 reg = <0 0x10231000 0 0x1000>,
123 <0 0x10232000 0 0x2000>,
124 <0 0x10234000 0 0x2000>,
125 <0 0x10236000 0 0x2000>;
126 };
127
128 uart0: serial@11002000 {
129 compatible = "mediatek,mt6755-uart",
130 "mediatek,mt6577-uart";
131 reg = <0 0x11002000 0 0x400>;
132 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
133 clocks = <&uart_clk>;
134 status = "disabled";
135 };
136
137 uart1: serial@11003000 {
138 compatible = "mediatek,mt6755-uart",
139 "mediatek,mt6577-uart";
140 reg = <0 0x11003000 0 0x400>;
141 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
142 clocks = <&uart_clk>;
143 status = "disabled";
144 };
145};
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 77b8c4e388ca..10f638f4e7d8 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -26,6 +26,23 @@
26 #address-cells = <2>; 26 #address-cells = <2>;
27 #size-cells = <2>; 27 #size-cells = <2>;
28 28
29 aliases {
30 ovl0 = &ovl0;
31 ovl1 = &ovl1;
32 rdma0 = &rdma0;
33 rdma1 = &rdma1;
34 rdma2 = &rdma2;
35 wdma0 = &wdma0;
36 wdma1 = &wdma1;
37 color0 = &color0;
38 color1 = &color1;
39 split0 = &split0;
40 split1 = &split1;
41 dpi0 = &dpi0;
42 dsi0 = &dsi0;
43 dsi1 = &dsi1;
44 };
45
29 cpus { 46 cpus {
30 #address-cells = <1>; 47 #address-cells = <1>;
31 #size-cells = <0>; 48 #size-cells = <0>;
@@ -366,6 +383,26 @@
366 #clock-cells = <1>; 383 #clock-cells = <1>;
367 }; 384 };
368 385
386 mipi_tx0: mipi-dphy@10215000 {
387 compatible = "mediatek,mt8173-mipi-tx";
388 reg = <0 0x10215000 0 0x1000>;
389 clocks = <&clk26m>;
390 clock-output-names = "mipi_tx0_pll";
391 #clock-cells = <0>;
392 #phy-cells = <0>;
393 status = "disabled";
394 };
395
396 mipi_tx1: mipi-dphy@10216000 {
397 compatible = "mediatek,mt8173-mipi-tx";
398 reg = <0 0x10216000 0 0x1000>;
399 clocks = <&clk26m>;
400 clock-output-names = "mipi_tx1_pll";
401 #clock-cells = <0>;
402 #phy-cells = <0>;
403 status = "disabled";
404 };
405
369 gic: interrupt-controller@10220000 { 406 gic: interrupt-controller@10220000 {
370 compatible = "arm,gic-400"; 407 compatible = "arm,gic-400";
371 #interrupt-cells = <3>; 408 #interrupt-cells = <3>;
@@ -675,9 +712,181 @@
675 mmsys: clock-controller@14000000 { 712 mmsys: clock-controller@14000000 {
676 compatible = "mediatek,mt8173-mmsys", "syscon"; 713 compatible = "mediatek,mt8173-mmsys", "syscon";
677 reg = <0 0x14000000 0 0x1000>; 714 reg = <0 0x14000000 0 0x1000>;
715 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
678 #clock-cells = <1>; 716 #clock-cells = <1>;
679 }; 717 };
680 718
719 ovl0: ovl@1400c000 {
720 compatible = "mediatek,mt8173-disp-ovl";
721 reg = <0 0x1400c000 0 0x1000>;
722 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
723 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
724 clocks = <&mmsys CLK_MM_DISP_OVL0>;
725 iommus = <&iommu M4U_PORT_DISP_OVL0>;
726 mediatek,larb = <&larb0>;
727 };
728
729 ovl1: ovl@1400d000 {
730 compatible = "mediatek,mt8173-disp-ovl";
731 reg = <0 0x1400d000 0 0x1000>;
732 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
733 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
734 clocks = <&mmsys CLK_MM_DISP_OVL1>;
735 iommus = <&iommu M4U_PORT_DISP_OVL1>;
736 mediatek,larb = <&larb4>;
737 };
738
739 rdma0: rdma@1400e000 {
740 compatible = "mediatek,mt8173-disp-rdma";
741 reg = <0 0x1400e000 0 0x1000>;
742 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
743 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
744 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
745 iommus = <&iommu M4U_PORT_DISP_RDMA0>;
746 mediatek,larb = <&larb0>;
747 };
748
749 rdma1: rdma@1400f000 {
750 compatible = "mediatek,mt8173-disp-rdma";
751 reg = <0 0x1400f000 0 0x1000>;
752 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
753 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
754 clocks = <&mmsys CLK_MM_DISP_RDMA1>;
755 iommus = <&iommu M4U_PORT_DISP_RDMA1>;
756 mediatek,larb = <&larb4>;
757 };
758
759 rdma2: rdma@14010000 {
760 compatible = "mediatek,mt8173-disp-rdma";
761 reg = <0 0x14010000 0 0x1000>;
762 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
763 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
764 clocks = <&mmsys CLK_MM_DISP_RDMA2>;
765 iommus = <&iommu M4U_PORT_DISP_RDMA2>;
766 mediatek,larb = <&larb4>;
767 };
768
769 wdma0: wdma@14011000 {
770 compatible = "mediatek,mt8173-disp-wdma";
771 reg = <0 0x14011000 0 0x1000>;
772 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
773 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
774 clocks = <&mmsys CLK_MM_DISP_WDMA0>;
775 iommus = <&iommu M4U_PORT_DISP_WDMA0>;
776 mediatek,larb = <&larb0>;
777 };
778
779 wdma1: wdma@14012000 {
780 compatible = "mediatek,mt8173-disp-wdma";
781 reg = <0 0x14012000 0 0x1000>;
782 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
783 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
784 clocks = <&mmsys CLK_MM_DISP_WDMA1>;
785 iommus = <&iommu M4U_PORT_DISP_WDMA1>;
786 mediatek,larb = <&larb4>;
787 };
788
789 color0: color@14013000 {
790 compatible = "mediatek,mt8173-disp-color";
791 reg = <0 0x14013000 0 0x1000>;
792 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
793 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
794 clocks = <&mmsys CLK_MM_DISP_COLOR0>;
795 };
796
797 color1: color@14014000 {
798 compatible = "mediatek,mt8173-disp-color";
799 reg = <0 0x14014000 0 0x1000>;
800 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
801 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
802 clocks = <&mmsys CLK_MM_DISP_COLOR1>;
803 };
804
805 aal@14015000 {
806 compatible = "mediatek,mt8173-disp-aal";
807 reg = <0 0x14015000 0 0x1000>;
808 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
809 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
810 clocks = <&mmsys CLK_MM_DISP_AAL>;
811 };
812
813 gamma@14016000 {
814 compatible = "mediatek,mt8173-disp-gamma";
815 reg = <0 0x14016000 0 0x1000>;
816 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
817 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
818 clocks = <&mmsys CLK_MM_DISP_GAMMA>;
819 };
820
821 merge@14017000 {
822 compatible = "mediatek,mt8173-disp-merge";
823 reg = <0 0x14017000 0 0x1000>;
824 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
825 clocks = <&mmsys CLK_MM_DISP_MERGE>;
826 };
827
828 split0: split@14018000 {
829 compatible = "mediatek,mt8173-disp-split";
830 reg = <0 0x14018000 0 0x1000>;
831 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
832 clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
833 };
834
835 split1: split@14019000 {
836 compatible = "mediatek,mt8173-disp-split";
837 reg = <0 0x14019000 0 0x1000>;
838 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
839 clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
840 };
841
842 ufoe@1401a000 {
843 compatible = "mediatek,mt8173-disp-ufoe";
844 reg = <0 0x1401a000 0 0x1000>;
845 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
846 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
847 clocks = <&mmsys CLK_MM_DISP_UFOE>;
848 };
849
850 dsi0: dsi@1401b000 {
851 compatible = "mediatek,mt8173-dsi";
852 reg = <0 0x1401b000 0 0x1000>;
853 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
854 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
855 clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
856 <&mmsys CLK_MM_DSI0_DIGITAL>,
857 <&mipi_tx0>;
858 clock-names = "engine", "digital", "hs";
859 phys = <&mipi_tx0>;
860 phy-names = "dphy";
861 status = "disabled";
862 };
863
864 dsi1: dsi@1401c000 {
865 compatible = "mediatek,mt8173-dsi";
866 reg = <0 0x1401c000 0 0x1000>;
867 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
868 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
869 clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
870 <&mmsys CLK_MM_DSI1_DIGITAL>,
871 <&mipi_tx1>;
872 clock-names = "engine", "digital", "hs";
873 phy = <&mipi_tx1>;
874 phy-names = "dphy";
875 status = "disabled";
876 };
877
878 dpi0: dpi@1401d000 {
879 compatible = "mediatek,mt8173-dpi";
880 reg = <0 0x1401d000 0 0x1000>;
881 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
882 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
883 clocks = <&mmsys CLK_MM_DPI_PIXEL>,
884 <&mmsys CLK_MM_DPI_ENGINE>,
885 <&apmixedsys CLK_APMIXED_TVDPLL>;
886 clock-names = "pixel", "engine", "pll";
887 status = "disabled";
888 };
889
681 pwm0: pwm@1401e000 { 890 pwm0: pwm@1401e000 {
682 compatible = "mediatek,mt8173-disp-pwm", 891 compatible = "mediatek,mt8173-disp-pwm",
683 "mediatek,mt6595-disp-pwm"; 892 "mediatek,mt6595-disp-pwm";
@@ -700,6 +909,14 @@
700 status = "disabled"; 909 status = "disabled";
701 }; 910 };
702 911
912 mutex: mutex@14020000 {
913 compatible = "mediatek,mt8173-disp-mutex";
914 reg = <0 0x14020000 0 0x1000>;
915 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
916 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
917 clocks = <&mmsys CLK_MM_MUTEX_32K>;
918 };
919
703 larb0: larb@14021000 { 920 larb0: larb@14021000 {
704 compatible = "mediatek,mt8173-smi-larb"; 921 compatible = "mediatek,mt8173-smi-larb";
705 reg = <0 0x14021000 0 0x1000>; 922 reg = <0 0x14021000 0 0x1000>;
@@ -719,6 +936,12 @@
719 clock-names = "apb", "smi"; 936 clock-names = "apb", "smi";
720 }; 937 };
721 938
939 od@14023000 {
940 compatible = "mediatek,mt8173-disp-od";
941 reg = <0 0x14023000 0 0x1000>;
942 clocks = <&mmsys CLK_MM_DISP_OD>;
943 };
944
722 larb4: larb@14027000 { 945 larb4: larb@14027000 {
723 compatible = "mediatek,mt8173-smi-larb"; 946 compatible = "mediatek,mt8173-smi-larb";
724 reg = <0 0x14027000 0 0x1000>; 947 reg = <0 0x14027000 0 0x1000>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
index 316c92c03821..5fda583351d7 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
@@ -1,3 +1,5 @@
1#include <dt-bindings/mfd/max77620.h>
2
1#include "tegra210.dtsi" 3#include "tegra210.dtsi"
2 4
3/ { 5/ {
@@ -5,10 +7,15 @@
5 compatible = "nvidia,p2180", "nvidia,tegra210"; 7 compatible = "nvidia,p2180", "nvidia,tegra210";
6 8
7 aliases { 9 aliases {
10 rtc0 = "/i2c@7000d000/pmic@3c";
8 rtc1 = "/rtc@7000e000"; 11 rtc1 = "/rtc@7000e000";
9 serial0 = &uarta; 12 serial0 = &uarta;
10 }; 13 };
11 14
15 chosen {
16 stdout-path = "serial0:115200n8";
17 };
18
12 memory { 19 memory {
13 device_type = "memory"; 20 device_type = "memory";
14 reg = <0x0 0x80000000 0x1 0x0>; 21 reg = <0x0 0x80000000 0x1 0x0>;
@@ -19,6 +26,248 @@
19 status = "okay"; 26 status = "okay";
20 }; 27 };
21 28
29 i2c@7000d000 {
30 status = "okay";
31 clock-frequency = <400000>;
32
33 pmic: pmic@3c {
34 compatible = "maxim,max77620";
35 reg = <0x3c>;
36 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
37
38 #interrupt-cells = <2>;
39 interrupt-controller;
40
41 #gpio-cells = <2>;
42 gpio-controller;
43
44 pinctrl-names = "default";
45 pinctrl-0 = <&max77620_default>;
46
47 max77620_default: pinmux {
48 gpio0 {
49 pins = "gpio0";
50 function = "gpio";
51 };
52
53 gpio1 {
54 pins = "gpio1";
55 function = "fps-out";
56 drive-push-pull = <1>;
57 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
58 maxim,active-fps-power-up-slot = <7>;
59 maxim,active-fps-power-down-slot = <0>;
60 };
61
62 gpio2_3 {
63 pins = "gpio2", "gpio3";
64 function = "fps-out";
65 drive-open-drain = <1>;
66 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
67 };
68
69 gpio4 {
70 pins = "gpio4";
71 function = "32k-out1";
72 };
73
74 gpio5_6_7 {
75 pins = "gpio5", "gpio6", "gpio7";
76 function = "gpio";
77 drive-push-pull = <1>;
78 };
79 };
80
81 fps {
82 fps0 {
83 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
84 maxim,suspend-fps-time-period-us = <1280>;
85 };
86
87 fps1 {
88 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
89 maxim,suspend-fps-time-period-us = <1280>;
90 };
91
92 fps2 {
93 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
94 };
95 };
96
97 regulators {
98 in-ldo0-1-supply = <&vdd_pre>;
99 in-ldo7-8-supply = <&vdd_pre>;
100 in-sd3-supply = <&vdd_5v0_sys>;
101
102 vdd_soc: sd0 {
103 regulator-name = "VDD_SOC";
104 regulator-min-microvolt = <600000>;
105 regulator-max-microvolt = <1400000>;
106 regulator-always-on;
107 regulator-boot-on;
108
109 regulator-enable-ramp-delay = <146>;
110 regulator-ramp-delay = <27500>;
111
112 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
113 };
114
115 vdd_ddr: sd1 {
116 regulator-name = "VDD_DDR_1V1_PMIC";
117 regulator-always-on;
118 regulator-boot-on;
119
120 regulator-enable-ramp-delay = <130>;
121 regulator-ramp-delay = <27500>;
122
123 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
124 };
125
126 vdd_pre: sd2 {
127 regulator-name = "VDD_PRE_REG_1V35";
128 regulator-min-microvolt = <1350000>;
129 regulator-max-microvolt = <1350000>;
130
131 regulator-enable-ramp-delay = <176>;
132 regulator-ramp-delay = <27500>;
133
134 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
135 };
136
137 vdd_1v8: sd3 {
138 regulator-name = "VDD_1V8";
139 regulator-min-microvolt = <1800000>;
140 regulator-max-microvolt = <1800000>;
141 regulator-always-on;
142 regulator-boot-on;
143
144 regulator-enable-ramp-delay = <242>;
145 regulator-ramp-delay = <27500>;
146
147 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
148 };
149
150 vdd_sys_1v2: ldo0 {
151 regulator-name = "AVDD_SYS_1V2";
152 regulator-min-microvolt = <1200000>;
153 regulator-max-microvolt = <1200000>;
154 regulator-always-on;
155 regulator-boot-on;
156
157 regulator-enable-ramp-delay = <26>;
158 regulator-ramp-delay = <100000>;
159
160 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
161 };
162
163 vdd_pex_1v05: ldo1 {
164 regulator-name = "VDD_PEX_1V05";
165 regulator-min-microvolt = <1050000>;
166 regulator-max-microvolt = <1050000>;
167
168 regulator-enable-ramp-delay = <22>;
169 regulator-ramp-delay = <100000>;
170
171 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
172 };
173
174 vddio_sdmmc: ldo2 {
175 regulator-name = "VDDIO_SDMMC";
176 /*
177 * Technically this supply should have
178 * a supported range from 1.8 - 3.3 V.
179 * However, that would cause the SDHCI
180 * driver to request 2.7 V upon access
181 * and that in turn will cause traffic
182 * to be broken. Leave it at 3.3 V for
183 * now.
184 */
185 regulator-min-microvolt = <3300000>;
186 regulator-max-microvolt = <3300000>;
187 regulator-always-on;
188 regulator-boot-on;
189
190 regulator-enable-ramp-delay = <62>;
191 regulator-ramp-delay = <100000>;
192
193 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
194 };
195
196 vdd_cam_hv: ldo3 {
197 regulator-name = "VDD_CAM_HV";
198 regulator-min-microvolt = <2800000>;
199 regulator-max-microvolt = <2800000>;
200
201 regulator-enable-ramp-delay = <50>;
202 regulator-ramp-delay = <100000>;
203
204 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
205 };
206
207 vdd_rtc: ldo4 {
208 regulator-name = "VDD_RTC";
209 regulator-min-microvolt = <850000>;
210 regulator-max-microvolt = <850000>;
211 regulator-always-on;
212 regulator-boot-on;
213
214 regulator-enable-ramp-delay = <22>;
215 regulator-ramp-delay = <100000>;
216
217 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
218 };
219
220 vdd_ts_hv: ldo5 {
221 regulator-name = "VDD_TS_HV";
222 regulator-min-microvolt = <3300000>;
223 regulator-max-microvolt = <3300000>;
224
225 regulator-enable-ramp-delay = <62>;
226 regulator-ramp-delay = <100000>;
227
228 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
229 };
230
231 vdd_ts: ldo6 {
232 regulator-name = "VDD_TS_1V8";
233 regulator-min-microvolt = <1800000>;
234 regulator-max-microvolt = <1800000>;
235
236 regulator-enable-ramp-delay = <36>;
237 regulator-ramp-delay = <100000>;
238
239 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
240 maxim,active-fps-power-up-slot = <7>;
241 maxim,active-fps-power-down-slot = <0>;
242 };
243
244 avdd_1v05_pll: ldo7 {
245 regulator-name = "AVDD_1V05_PLL";
246 regulator-min-microvolt = <1050000>;
247 regulator-max-microvolt = <1050000>;
248 regulator-always-on;
249 regulator-boot-on;
250
251 regulator-enable-ramp-delay = <24>;
252 regulator-ramp-delay = <100000>;
253
254 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
255 };
256
257 avdd_1v05: ldo8 {
258 regulator-name = "AVDD_SATA_HDMI_DP_1V05";
259 regulator-min-microvolt = <1050000>;
260 regulator-max-microvolt = <1050000>;
261
262 regulator-enable-ramp-delay = <22>;
263 regulator-ramp-delay = <100000>;
264
265 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
266 };
267 };
268 };
269 };
270
22 pmc@7000e400 { 271 pmc@7000e400 {
23 nvidia,invert-interrupt; 272 nvidia,invert-interrupt;
24 }; 273 };
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
index 683b339a980c..983775e637a4 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
@@ -6,4 +6,49 @@
6/ { 6/ {
7 model = "NVIDIA Jetson TX1 Developer Kit"; 7 model = "NVIDIA Jetson TX1 Developer Kit";
8 compatible = "nvidia,p2371-2180", "nvidia,tegra210"; 8 compatible = "nvidia,p2371-2180", "nvidia,tegra210";
9
10 host1x@50000000 {
11 dsi@54300000 {
12 status = "okay";
13
14 avdd-dsi-csi-supply = <&vdd_dsi_csi>;
15
16 panel@0 {
17 compatible = "auo,b080uan01";
18 reg = <0>;
19
20 enable-gpios = <&gpio TEGRA_GPIO(V, 2)
21 GPIO_ACTIVE_HIGH>;
22 power-supply = <&vdd_5v0_io>;
23 backlight = <&backlight>;
24 };
25 };
26 };
27
28 i2c@7000c400 {
29 backlight: backlight@2c {
30 compatible = "ti,lp8557";
31 reg = <0x2c>;
32
33 dev-ctrl = /bits/ 8 <0x80>;
34 init-brt = /bits/ 8 <0xff>;
35
36 pwm-period = <29334>;
37
38 pwms = <&pwm 0 29334>;
39 pwm-names = "lp8557";
40
41 /* 3 LED string */
42 rom_14h {
43 rom-addr = /bits/ 8 <0x14>;
44 rom-val = /bits/ 8 <0x87>;
45 };
46
47 /* boost frequency 1 MHz */
48 rom_13h {
49 rom-addr = /bits/ 8 <0x13>;
50 rom-val = /bits/ 8 <0x01>;
51 };
52 };
53 };
9}; 54};
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
index a2480c0c7e72..e5fc67bf46c2 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
@@ -4,6 +4,24 @@
4 model = "NVIDIA Tegra210 P2597 I/O board"; 4 model = "NVIDIA Tegra210 P2597 I/O board";
5 compatible = "nvidia,p2597", "nvidia,tegra210"; 5 compatible = "nvidia,p2597", "nvidia,tegra210";
6 6
7 host1x@50000000 {
8 dpaux@54040000 {
9 status = "okay";
10 };
11
12 sor@54580000 {
13 status = "okay";
14
15 avdd-io-supply = <&avdd_1v05>;
16 vdd-pll-supply = <&vdd_1v8>;
17 hdmi-supply = <&vdd_hdmi>;
18
19 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
20 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1)
21 GPIO_ACTIVE_LOW>;
22 };
23 };
24
7 pinmux: pinmux@700008d4 { 25 pinmux: pinmux@700008d4 {
8 pinctrl-names = "boot"; 26 pinctrl-names = "boot";
9 pinctrl-0 = <&state_boot>; 27 pinctrl-0 = <&state_boot>;
@@ -1261,6 +1279,169 @@
1261 }; 1279 };
1262 }; 1280 };
1263 1281
1282 pwm@7000a000 {
1283 status = "okay";
1284 };
1285
1286 i2c@7000c400 {
1287 status = "okay";
1288 clock-frequency = <100000>;
1289
1290 exp1: gpio@74 {
1291 compatible = "ti,tca9539";
1292 reg = <0x74>;
1293
1294 #gpio-cells = <2>;
1295 gpio-controller;
1296 };
1297 };
1298
1299 /* HDMI DDC */
1300 hdmi_ddc: i2c@7000c700 {
1301 status = "okay";
1302 clock-frequency = <100000>;
1303 };
1304
1305 usb@70090000 {
1306 phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
1307 <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
1308 <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
1309 <&{/padctl@7009f000/pads/usb2/lanes/usb2-3}>,
1310 <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>,
1311 <&{/padctl@7009f000/pads/pcie/lanes/pcie-5}>;
1312 phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3", "usb3-0",
1313 "usb3-1";
1314
1315 dvddio-pex-supply = <&vdd_pex_1v05>;
1316 hvddio-pex-supply = <&vdd_1v8>;
1317 avdd-usb-supply = <&vdd_3v3_sys>;
1318 /* XXX what are these? */
1319 avdd-pll-utmip-supply = <&vdd_1v8>;
1320 avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
1321 dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>;
1322 hvdd-usb-ss-pll-e-supply = <&vdd_1v8>;
1323
1324 status = "okay";
1325 };
1326
1327 padctl@7009f000 {
1328 status = "okay";
1329
1330 pads {
1331 usb2 {
1332 status = "okay";
1333
1334 lanes {
1335 usb2-0 {
1336 nvidia,function = "xusb";
1337 status = "okay";
1338 };
1339
1340 usb2-1 {
1341 nvidia,function = "xusb";
1342 status = "okay";
1343 };
1344
1345 usb2-2 {
1346 nvidia,function = "xusb";
1347 status = "okay";
1348 };
1349
1350 usb2-3 {
1351 nvidia,function = "xusb";
1352 status = "okay";
1353 };
1354 };
1355 };
1356
1357 pcie {
1358 status = "okay";
1359
1360 lanes {
1361 pcie-0 {
1362 nvidia,function = "pcie-x1";
1363 status = "okay";
1364 };
1365
1366 pcie-1 {
1367 nvidia,function = "pcie-x4";
1368 status = "okay";
1369 };
1370
1371 pcie-2 {
1372 nvidia,function = "pcie-x4";
1373 status = "okay";
1374 };
1375
1376 pcie-3 {
1377 nvidia,function = "pcie-x4";
1378 status = "okay";
1379 };
1380
1381 pcie-4 {
1382 nvidia,function = "pcie-x4";
1383 status = "okay";
1384 };
1385
1386 pcie-5 {
1387 nvidia,function = "usb3-ss";
1388 status = "okay";
1389 };
1390
1391 pcie-6 {
1392 nvidia,function = "usb3-ss";
1393 status = "okay";
1394 };
1395 };
1396 };
1397
1398 sata {
1399 status = "okay";
1400
1401 lanes {
1402 sata-0 {
1403 nvidia,function = "sata";
1404 status = "okay";
1405 };
1406 };
1407 };
1408 };
1409
1410 ports {
1411 usb2-0 {
1412 status = "okay";
1413 mode = "otg";
1414 };
1415
1416 usb2-1 {
1417 status = "okay";
1418 vbus-supply = <&vdd_5v0_rtl>;
1419 mode = "host";
1420 };
1421
1422 usb2-2 {
1423 status = "okay";
1424 vbus-supply = <&vdd_usb_vbus>;
1425 mode = "host";
1426 };
1427
1428 usb2-3 {
1429 status = "okay";
1430 mode = "host";
1431 };
1432
1433 usb3-0 {
1434 nvidia,usb2-companion = <1>;
1435 status = "okay";
1436 };
1437
1438 usb3-1 {
1439 nvidia,usb2-companion = <2>;
1440 status = "okay";
1441 };
1442 };
1443 };
1444
1264 /* MMC/SD */ 1445 /* MMC/SD */
1265 sdhci@700b0000 { 1446 sdhci@700b0000 {
1266 status = "okay"; 1447 status = "okay";
@@ -1268,6 +1449,144 @@
1268 no-1-8-v; 1449 no-1-8-v;
1269 1450
1270 cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; 1451 cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
1452
1453 vqmmc-supply = <&vddio_sdmmc>;
1454 vmmc-supply = <&vdd_3v3_sd>;
1455 };
1456
1457 regulators {
1458 compatible = "simple-bus";
1459 #address-cells = <1>;
1460 #size-cells = <0>;
1461
1462 vdd_sys_mux: regulator@0 {
1463 compatible = "regulator-fixed";
1464 reg = <0>;
1465 regulator-name = "VDD_SYS_MUX";
1466 regulator-min-microvolt = <5000000>;
1467 regulator-max-microvolt = <5000000>;
1468 regulator-always-on;
1469 regulator-boot-on;
1470 };
1471
1472 vdd_5v0_sys: regulator@1 {
1473 compatible = "regulator-fixed";
1474 reg = <1>;
1475 regulator-name = "VDD_5V0_SYS";
1476 regulator-min-microvolt = <5000000>;
1477 regulator-max-microvolt = <5000000>;
1478 regulator-always-on;
1479 regulator-boot-on;
1480 gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
1481 enable-active-high;
1482 vin-supply = <&vdd_sys_mux>;
1483 };
1484
1485 vdd_3v3_sys: regulator@2 {
1486 compatible = "regulator-fixed";
1487 reg = <2>;
1488 regulator-name = "VDD_3V3_SYS";
1489 regulator-min-microvolt = <3300000>;
1490 regulator-max-microvolt = <3300000>;
1491 regulator-always-on;
1492 regulator-boot-on;
1493 gpio = <&pmic 3 GPIO_ACTIVE_HIGH>;
1494 enable-active-high;
1495 vin-supply = <&vdd_sys_mux>;
1496
1497 regulator-enable-ramp-delay = <160>;
1498 regulator-disable-ramp-delay = <10000>;
1499 };
1500
1501 vdd_5v0_io: regulator@3 {
1502 compatible = "regulator-fixed";
1503 reg = <3>;
1504 regulator-name = "VDD_5V0_IO_SYS";
1505 regulator-min-microvolt = <5000000>;
1506 regulator-max-microvolt = <5000000>;
1507 regulator-always-on;
1508 regulator-boot-on;
1509 };
1510
1511 vdd_3v3_sd: regulator@4 {
1512 compatible = "regulator-fixed";
1513 reg = <4>;
1514 regulator-name = "VDD_3V3_SD";
1515 regulator-min-microvolt = <3300000>;
1516 regulator-max-microvolt = <3300000>;
1517 gpio = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
1518 enable-active-high;
1519 vin-supply = <&vdd_3v3_sys>;
1520
1521 regulator-enable-ramp-delay = <472>;
1522 regulator-disable-ramp-delay = <4880>;
1523 };
1524
1525 vdd_dsi_csi: regulator@5 {
1526 compatible = "regulator-fixed";
1527 reg = <5>;
1528 regulator-name = "AVDD_DSI_CSI_1V2";
1529 regulator-min-microvolt = <1200000>;
1530 regulator-max-microvolt = <1200000>;
1531 vin-supply = <&vdd_sys_1v2>;
1532 };
1533
1534 vdd_3v3_dis: regulator@6 {
1535 compatible = "regulator-fixed";
1536 reg = <6>;
1537 regulator-name = "VDD_DIS_3V3_LCD";
1538 regulator-min-microvolt = <3300000>;
1539 regulator-max-microvolt = <3300000>;
1540 regulator-always-on;
1541 gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
1542 enable-active-high;
1543 vin-supply = <&vdd_3v3_sys>;
1544 };
1545
1546 vdd_1v8_dis: regulator@7 {
1547 compatible = "regulator-fixed";
1548 reg = <7>;
1549 regulator-name = "VDD_LCD_1V8_DIS";
1550 regulator-min-microvolt = <1800000>;
1551 regulator-max-microvolt = <1800000>;
1552 regulator-always-on;
1553 gpio = <&exp1 14 GPIO_ACTIVE_HIGH>;
1554 enable-active-high;
1555 vin-supply = <&vdd_1v8>;
1556 };
1557
1558 vdd_5v0_rtl: regulator@8 {
1559 compatible = "regulator-fixed";
1560 reg = <8>;
1561 regulator-name = "RTL_5V";
1562 regulator-min-microvolt = <5000000>;
1563 regulator-max-microvolt = <5000000>;
1564 gpio = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
1565 enable-active-high;
1566 vin-supply = <&vdd_5v0_sys>;
1567 };
1568
1569 vdd_usb_vbus: regulator@9 {
1570 compatible = "regulator-fixed";
1571 reg = <9>;
1572 regulator-name = "USB_VBUS_EN1";
1573 regulator-min-microvolt = <5000000>;
1574 regulator-max-microvolt = <5000000>;
1575 gpio = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>;
1576 enable-active-high;
1577 vin-supply = <&vdd_5v0_sys>;
1578 };
1579
1580 vdd_hdmi: regulator@10 {
1581 compatible = "regulator-fixed";
1582 reg = <10>;
1583 regulator-name = "VDD_HDMI_5V0";
1584 regulator-min-microvolt = <5000000>;
1585 regulator-max-microvolt = <5000000>;
1586 gpio = <&exp1 12 GPIO_ACTIVE_LOW>;
1587 enable-active-high;
1588 vin-supply = <&vdd_5v0_sys>;
1589 };
1271 }; 1590 };
1272 1591
1273 gpio-keys { 1592 gpio-keys {
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
index 4d89f4e02d98..431266a48e9c 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
@@ -1,6 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3#include <dt-bindings/input/input.h> 3#include <dt-bindings/input/input.h>
4#include <dt-bindings/mfd/max77620.h>
4#include <dt-bindings/pinctrl/pinctrl-tegra.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 6
6#include "tegra210.dtsi" 7#include "tegra210.dtsi"
@@ -1327,6 +1328,234 @@
1327 }; 1328 };
1328 }; 1329 };
1329 1330
1331 i2c@7000d000 {
1332 status = "okay";
1333 clock-frequency = <1000000>;
1334
1335 max77620: max77620@3c {
1336 compatible = "maxim,max77620";
1337 reg = <0x3c>;
1338 interrupts = <0 86 IRQ_TYPE_NONE>;
1339
1340 #interrupt-cells = <2>;
1341 interrupt-controller;
1342
1343 gpio-controller;
1344 #gpio-cells = <2>;
1345
1346 pinctrl-names = "default";
1347 pinctrl-0 = <&max77620_default>;
1348
1349 max77620_default: pinmux@0 {
1350 pin_gpio {
1351 pins = "gpio0", "gpio1", "gpio2", "gpio7";
1352 function = "gpio";
1353 };
1354
1355 /*
1356 * GPIO3 is used to en_pp3300, and it is part of power
1357 * sequence, So it must be sequenced up (automatically
1358 * set by OTP) and down properly.
1359 */
1360 pin_gpio3 {
1361 pins = "gpio3";
1362 function = "fps-out";
1363 drive-open-drain = <1>;
1364 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
1365 maxim,active-fps-power-up-slot = <4>;
1366 maxim,active-fps-power-down-slot = <2>;
1367 };
1368
1369 pin_gpio5_6 {
1370 pins = "gpio5", "gpio6";
1371 function = "gpio";
1372 drive-push-pull = <1>;
1373 };
1374
1375 pin_32k {
1376 pins = "gpio4";
1377 function = "32k-out1";
1378 };
1379 };
1380
1381 fps {
1382 fps0 {
1383 maxim,shutdown-fps-time-period-us = <5120>;
1384 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
1385 };
1386
1387 fps1 {
1388 maxim,shutdown-fps-time-period-us = <5120>;
1389 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
1390 maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>;
1391 };
1392
1393 fps2 {
1394 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
1395 };
1396 };
1397
1398 regulators {
1399 in-ldo0-1-supply = <&pp1350>;
1400 in-ldo2-supply = <&pp3300>;
1401 in-ldo3-5-supply = <&pp3300>;
1402 in-ldo7-8-supply = <&pp1350>;
1403
1404 ppvar_soc: sd0 {
1405 regulator-name = "PPVAR_SOC";
1406 regulator-min-microvolt = <825000>;
1407 regulator-max-microvolt = <1125000>;
1408 regulator-always-on;
1409 regulator-boot-on;
1410 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
1411 maxim,active-fps-power-up-slot = <1>;
1412 maxim,active-fps-power-down-slot = <7>;
1413 };
1414
1415 pp1100_sd1: sd1 {
1416 regulator-name = "PP1100";
1417 regulator-min-microvolt = <1125000>;
1418 regulator-max-microvolt = <1125000>;
1419 regulator-always-on;
1420 regulator-boot-on;
1421 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
1422 maxim,active-fps-power-up-slot = <5>;
1423 maxim,active-fps-power-down-slot = <1>;
1424 };
1425
1426 pp1350: sd2 {
1427 regulator-name = "PP1350";
1428 regulator-min-microvolt = <1350000>;
1429 regulator-max-microvolt = <1350000>;
1430 regulator-always-on;
1431 regulator-boot-on;
1432 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
1433 maxim,active-fps-power-up-slot = <2>;
1434 maxim,active-fps-power-down-slot = <5>;
1435 };
1436
1437 pp1800: sd3 {
1438 regulator-name = "PP1800";
1439 regulator-min-microvolt = <1800000>;
1440 regulator-max-microvolt = <1800000>;
1441 regulator-always-on;
1442 regulator-boot-on;
1443 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
1444 maxim,active-fps-power-up-slot = <3>;
1445 maxim,active-fps-power-down-slot = <3>;
1446 };
1447
1448 pp1200_avdd: ldo0 {
1449 regulator-name = "PP1200_AVDD";
1450 regulator-min-microvolt = <1200000>;
1451 regulator-max-microvolt = <1200000>;
1452 regulator-enable-ramp-delay = <26>;
1453 regulator-ramp-delay = <100000>;
1454 regulator-boot-on;
1455 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
1456 maxim,active-fps-power-up-slot = <0>;
1457 maxim,active-fps-power-down-slot = <7>;
1458 };
1459
1460 pp1200_rcam: ldo1 {
1461 regulator-name = "PP1200_RCAM";
1462 regulator-min-microvolt = <1200000>;
1463 regulator-max-microvolt = <1200000>;
1464 regulator-enable-ramp-delay = <22>;
1465 regulator-ramp-delay = <100000>;
1466 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
1467 maxim,active-fps-power-up-slot = <0>;
1468 maxim,active-fps-power-down-slot = <7>;
1469 };
1470
1471 pp_ldo2: ldo2 {
1472 regulator-name = "PP_LDO2";
1473 regulator-min-microvolt = <1800000>;
1474 regulator-max-microvolt = <1800000>;
1475 regulator-enable-ramp-delay = <62>;
1476 regulator-ramp-delay = <11000>;
1477 regulator-always-on;
1478 regulator-boot-on;
1479 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
1480 maxim,active-fps-power-up-slot = <0>;
1481 maxim,active-fps-power-down-slot = <7>;
1482 };
1483
1484 pp2800l_rcam: ldo3 {
1485 regulator-name = "PP2800L_RCAM";
1486 regulator-min-microvolt = <2800000>;
1487 regulator-max-microvolt = <2800000>;
1488 regulator-enable-ramp-delay = <50>;
1489 regulator-ramp-delay = <100000>;
1490 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
1491 maxim,active-fps-power-up-slot = <0>;
1492 maxim,active-fps-power-down-slot = <7>;
1493 };
1494
1495 pp100_soc_rtc: ldo4 {
1496 regulator-name = "PP1100_SOC_RTC";
1497 regulator-min-microvolt = <850000>;
1498 regulator-max-microvolt = <850000>;
1499 regulator-enable-ramp-delay = <22>;
1500 regulator-ramp-delay = <100000>;
1501 regulator-always-on; /* Check this */
1502 regulator-boot-on;
1503 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
1504 maxim,active-fps-power-up-slot = <1>;
1505 maxim,active-fps-power-down-slot = <7>;
1506 };
1507
1508 pp2800l_fcam: ldo5 {
1509 regulator-name = "PP2800L_FCAM";
1510 regulator-min-microvolt = <2800000>;
1511 regulator-max-microvolt = <2800000>;
1512 regulator-enable-ramp-delay = <62>;
1513 regulator-ramp-delay = <100000>;
1514 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
1515 maxim,active-fps-power-up-slot = <0>;
1516 maxim,active-fps-power-down-slot = <7>;
1517 };
1518
1519 ldo6 {
1520 /* Unused. */
1521 regulator-name = "PP_LDO6";
1522 regulator-min-microvolt = <1800000>;
1523 regulator-max-microvolt = <1800000>;
1524 regulator-enable-ramp-delay = <36>;
1525 regulator-ramp-delay = <100000>;
1526 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
1527 maxim,active-fps-power-up-slot = <0>;
1528 maxim,active-fps-power-down-slot = <7>;
1529 };
1530
1531 pp1050_avdd: ldo7 {
1532 regulator-name = "PP1050_AVDD";
1533 regulator-min-microvolt = <1050000>;
1534 regulator-max-microvolt = <1050000>;
1535 regulator-enable-ramp-delay = <24>;
1536 regulator-ramp-delay = <100000>;
1537 regulator-always-on;
1538 regulator-boot-on;
1539 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
1540 maxim,active-fps-power-up-slot = <3>;
1541 maxim,active-fps-power-down-slot = <4>;
1542 };
1543
1544 avddio_1v05: ldo8 {
1545 regulator-name = "AVDDIO_1V05";
1546 regulator-min-microvolt = <1050000>;
1547 regulator-max-microvolt = <1050000>;
1548 regulator-enable-ramp-delay = <22>;
1549 regulator-ramp-delay = <100000>;
1550 regulator-boot-on;
1551 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
1552 maxim,active-fps-power-up-slot = <0>;
1553 maxim,active-fps-power-down-slot = <7>;
1554 };
1555 };
1556 };
1557 };
1558
1330 pmc@7000e400 { 1559 pmc@7000e400 {
1331 nvidia,invert-interrupt; 1560 nvidia,invert-interrupt;
1332 nvidia,suspend-mode = <0>; 1561 nvidia,suspend-mode = <0>;
@@ -1421,4 +1650,89 @@
1421 compatible = "arm,psci-1.0"; 1650 compatible = "arm,psci-1.0";
1422 method = "smc"; 1651 method = "smc";
1423 }; 1652 };
1653
1654 regulators {
1655 compatible = "simple-bus";
1656 device_type = "fixed-regulators";
1657 #address-cells = <1>;
1658 #size-cells = <0>;
1659
1660 ppvar_sys: regulator@0 {
1661 compatible = "regulator-fixed";
1662 reg = <0>;
1663 regulator-name = "PPVAR_SYS";
1664 regulator-min-microvolt = <4400000>;
1665 regulator-max-microvolt = <4400000>;
1666 regulator-always-on;
1667 };
1668
1669 pplcd_vdd: regulator@1 {
1670 compatible = "regulator-fixed";
1671 reg = <1>;
1672 regulator-name = "PPLCD_VDD";
1673 regulator-min-microvolt = <4400000>;
1674 regulator-max-microvolt = <4400000>;
1675 gpio = <&gpio TEGRA_GPIO(V, 4) 0>;
1676 enable-active-high;
1677 regulator-boot-on;
1678 };
1679
1680 pp3000_always: regulator@2 {
1681 compatible = "regulator-fixed";
1682 reg = <2>;
1683 regulator-name = "PP3000_ALWAYS";
1684 regulator-min-microvolt = <3000000>;
1685 regulator-max-microvolt = <3000000>;
1686 regulator-always-on;
1687 };
1688
1689 pp3300: regulator@3 {
1690 compatible = "regulator-fixed";
1691 reg = <3>;
1692 regulator-name = "PP3300";
1693 regulator-min-microvolt = <3300000>;
1694 regulator-max-microvolt = <3300000>;
1695 regulator-boot-on;
1696 regulator-always-on;
1697 enable-active-high;
1698 };
1699
1700 pp5000: regulator@4 {
1701 compatible = "regulator-fixed";
1702 reg = <4>;
1703 regulator-name = "PP5000";
1704 regulator-min-microvolt = <5000000>;
1705 regulator-max-microvolt = <5000000>;
1706 regulator-always-on;
1707 };
1708
1709 pp1800_lcdio: regulator@5 {
1710 compatible = "regulator-fixed";
1711 reg = <5>;
1712 regulator-name = "PP1800_LCDIO";
1713 regulator-min-microvolt = <1800000>;
1714 regulator-max-microvolt = <1800000>;
1715 gpio = <&gpio TEGRA_GPIO(V, 3) 0>;
1716 enable-active-high;
1717 regulator-boot-on;
1718 };
1719
1720 pp1800_cam: regulator@6 {
1721 compatible = "regulator-fixed";
1722 reg= <6>;
1723 regulator-name = "PP1800_CAM";
1724 regulator-min-microvolt = <1800000>;
1725 regulator-max-microvolt = <1800000>;
1726 gpio = <&gpio TEGRA_GPIO(K, 3) 0>;
1727 enable-active-high;
1728 };
1729
1730 usbc_vbus: regulator@7 {
1731 compatible = "regulator-fixed";
1732 reg = <7>;
1733 regulator-name = "USBC_VBUS";
1734 regulator-min-microvolt = <5000000>;
1735 regulator-max-microvolt = <5000000>;
1736 };
1737 };
1424}; 1738};
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 76fe31faa1a5..c4cfdcf60d26 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -35,6 +35,26 @@
35 resets = <&tegra_car 207>; 35 resets = <&tegra_car 207>;
36 reset-names = "dpaux"; 36 reset-names = "dpaux";
37 status = "disabled"; 37 status = "disabled";
38
39 state_dpaux1_aux: pinmux-aux {
40 groups = "dpaux-io";
41 function = "aux";
42 };
43
44 state_dpaux1_i2c: pinmux-i2c {
45 groups = "dpaux-io";
46 function = "i2c";
47 };
48
49 state_dpaux1_off: pinmux-off {
50 groups = "dpaux-io";
51 function = "off";
52 };
53
54 i2c-bus {
55 #address-cells = <1>;
56 #size-cells = <0>;
57 };
38 }; 58 };
39 59
40 vi@54080000 { 60 vi@54080000 {
@@ -154,6 +174,10 @@
154 clock-names = "sor", "parent", "dp", "safe"; 174 clock-names = "sor", "parent", "dp", "safe";
155 resets = <&tegra_car 182>; 175 resets = <&tegra_car 182>;
156 reset-names = "sor"; 176 reset-names = "sor";
177 pinctrl-0 = <&state_dpaux_aux>;
178 pinctrl-1 = <&state_dpaux_i2c>;
179 pinctrl-2 = <&state_dpaux_off>;
180 pinctrl-names = "aux", "i2c", "off";
157 status = "disabled"; 181 status = "disabled";
158 }; 182 };
159 183
@@ -162,12 +186,17 @@
162 reg = <0x0 0x54580000 0x0 0x00040000>; 186 reg = <0x0 0x54580000 0x0 0x00040000>;
163 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 187 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
164 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 188 clocks = <&tegra_car TEGRA210_CLK_SOR1>,
189 <&tegra_car TEGRA210_CLK_SOR1_SRC>,
165 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 190 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
166 <&tegra_car TEGRA210_CLK_PLL_DP>, 191 <&tegra_car TEGRA210_CLK_PLL_DP>,
167 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 192 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
168 clock-names = "sor", "parent", "dp", "safe"; 193 clock-names = "sor", "source", "parent", "dp", "safe";
169 resets = <&tegra_car 183>; 194 resets = <&tegra_car 183>;
170 reset-names = "sor"; 195 reset-names = "sor";
196 pinctrl-0 = <&state_dpaux1_aux>;
197 pinctrl-1 = <&state_dpaux1_i2c>;
198 pinctrl-2 = <&state_dpaux1_off>;
199 pinctrl-names = "aux", "i2c", "off";
171 status = "disabled"; 200 status = "disabled";
172 }; 201 };
173 202
@@ -181,6 +210,26 @@
181 resets = <&tegra_car 181>; 210 resets = <&tegra_car 181>;
182 reset-names = "dpaux"; 211 reset-names = "dpaux";
183 status = "disabled"; 212 status = "disabled";
213
214 state_dpaux_aux: pinmux-aux {
215 groups = "dpaux-io";
216 function = "aux";
217 };
218
219 state_dpaux_i2c: pinmux-i2c {
220 groups = "dpaux-io";
221 function = "i2c";
222 };
223
224 state_dpaux_off: pinmux-off {
225 groups = "dpaux-io";
226 function = "off";
227 };
228
229 i2c-bus {
230 #address-cells = <1>;
231 #size-cells = <0>;
232 };
184 }; 233 };
185 234
186 isp@54600000 { 235 isp@54600000 {
@@ -478,6 +527,9 @@
478 reset-names = "i2c"; 527 reset-names = "i2c";
479 dmas = <&apbdma 26>, <&apbdma 26>; 528 dmas = <&apbdma 26>, <&apbdma 26>;
480 dma-names = "rx", "tx"; 529 dma-names = "rx", "tx";
530 pinctrl-0 = <&state_dpaux1_i2c>;
531 pinctrl-1 = <&state_dpaux1_off>;
532 pinctrl-names = "default", "idle";
481 status = "disabled"; 533 status = "disabled";
482 }; 534 };
483 535
@@ -508,6 +560,9 @@
508 reset-names = "i2c"; 560 reset-names = "i2c";
509 dmas = <&apbdma 30>, <&apbdma 30>; 561 dmas = <&apbdma 30>, <&apbdma 30>;
510 dma-names = "rx", "tx"; 562 dma-names = "rx", "tx";
563 pinctrl-0 = <&state_dpaux_i2c>;
564 pinctrl-1 = <&state_dpaux_off>;
565 pinctrl-names = "default", "idle";
511 status = "disabled"; 566 status = "disabled";
512 }; 567 };
513 568
@@ -584,6 +639,39 @@
584 reg = <0x0 0x7000e400 0x0 0x400>; 639 reg = <0x0 0x7000e400 0x0 0x400>;
585 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 640 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
586 clock-names = "pclk", "clk32k_in"; 641 clock-names = "pclk", "clk32k_in";
642
643 powergates {
644 pd_audio: aud {
645 clocks = <&tegra_car TEGRA210_CLK_APE>,
646 <&tegra_car TEGRA210_CLK_APB2APE>;
647 resets = <&tegra_car 198>;
648 #power-domain-cells = <0>;
649 };
650
651 pd_xusbss: xusba {
652 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
653 clock-names = "xusb-ss";
654 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
655 reset-names = "xusb-ss";
656 #power-domain-cells = <0>;
657 };
658
659 pd_xusbdev: xusbb {
660 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>;
661 clock-names = "xusb-dev";
662 resets = <&tegra_car 95>;
663 reset-names = "xusb-dev";
664 #power-domain-cells = <0>;
665 };
666
667 pd_xusbhost: xusbc {
668 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
669 clock-names = "xusb-host";
670 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
671 reset-names = "xusb-host";
672 #power-domain-cells = <0>;
673 };
674 };
587 }; 675 };
588 676
589 fuse@7000f800 { 677 fuse@7000f800 {
@@ -621,6 +709,196 @@
621 status = "disabled"; 709 status = "disabled";
622 }; 710 };
623 711
712 usb@70090000 {
713 compatible = "nvidia,tegra210-xusb";
714 reg = <0x0 0x70090000 0x0 0x8000>,
715 <0x0 0x70098000 0x0 0x1000>,
716 <0x0 0x70099000 0x0 0x1000>;
717 reg-names = "hcd", "fpci", "ipfs";
718
719 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
720 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
721
722 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
723 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
724 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
725 <&tegra_car TEGRA210_CLK_XUSB_SS>,
726 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
727 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
728 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
729 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
730 <&tegra_car TEGRA210_CLK_PLL_U_480M>,
731 <&tegra_car TEGRA210_CLK_CLK_M>,
732 <&tegra_car TEGRA210_CLK_PLL_E>;
733 clock-names = "xusb_host", "xusb_host_src",
734 "xusb_falcon_src", "xusb_ss",
735 "xusb_ss_div2", "xusb_ss_src",
736 "xusb_hs_src", "xusb_fs_src",
737 "pll_u_480m", "clk_m", "pll_e";
738 resets = <&tegra_car 89>, <&tegra_car 156>,
739 <&tegra_car 143>;
740 reset-names = "xusb_host", "xusb_ss", "xusb_src";
741
742 nvidia,xusb-padctl = <&padctl>;
743
744 status = "disabled";
745 };
746
747 padctl: padctl@7009f000 {
748 compatible = "nvidia,tegra210-xusb-padctl";
749 reg = <0x0 0x7009f000 0x0 0x1000>;
750 resets = <&tegra_car 142>;
751 reset-names = "padctl";
752
753 status = "disabled";
754
755 pads {
756 usb2 {
757 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
758 clock-names = "trk";
759 status = "disabled";
760
761 lanes {
762 usb2-0 {
763 status = "disabled";
764 #phy-cells = <0>;
765 };
766
767 usb2-1 {
768 status = "disabled";
769 #phy-cells = <0>;
770 };
771
772 usb2-2 {
773 status = "disabled";
774 #phy-cells = <0>;
775 };
776
777 usb2-3 {
778 status = "disabled";
779 #phy-cells = <0>;
780 };
781 };
782 };
783
784 hsic {
785 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
786 clock-names = "trk";
787 status = "disabled";
788
789 lanes {
790 hsic-0 {
791 status = "disabled";
792 #phy-cells = <0>;
793 };
794
795 hsic-1 {
796 status = "disabled";
797 #phy-cells = <0>;
798 };
799 };
800 };
801
802 pcie {
803 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
804 clock-names = "pll";
805 resets = <&tegra_car 205>;
806 reset-names = "phy";
807 status = "disabled";
808
809 lanes {
810 pcie-0 {
811 status = "disabled";
812 #phy-cells = <0>;
813 };
814
815 pcie-1 {
816 status = "disabled";
817 #phy-cells = <0>;
818 };
819
820 pcie-2 {
821 status = "disabled";
822 #phy-cells = <0>;
823 };
824
825 pcie-3 {
826 status = "disabled";
827 #phy-cells = <0>;
828 };
829
830 pcie-4 {
831 status = "disabled";
832 #phy-cells = <0>;
833 };
834
835 pcie-5 {
836 status = "disabled";
837 #phy-cells = <0>;
838 };
839
840 pcie-6 {
841 status = "disabled";
842 #phy-cells = <0>;
843 };
844 };
845 };
846
847 sata {
848 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
849 clock-names = "pll";
850 resets = <&tegra_car 204>;
851 reset-names = "phy";
852 status = "disabled";
853
854 lanes {
855 sata-0 {
856 status = "disabled";
857 #phy-cells = <0>;
858 };
859 };
860 };
861 };
862
863 ports {
864 usb2-0 {
865 status = "disabled";
866 };
867
868 usb2-1 {
869 status = "disabled";
870 };
871
872 usb2-2 {
873 status = "disabled";
874 };
875
876 usb2-3 {
877 status = "disabled";
878 };
879
880 hsic-0 {
881 status = "disabled";
882 };
883
884 usb3-0 {
885 status = "disabled";
886 };
887
888 usb3-1 {
889 status = "disabled";
890 };
891
892 usb3-2 {
893 status = "disabled";
894 };
895
896 usb3-3 {
897 status = "disabled";
898 };
899 };
900 };
901
624 sdhci@700b0000 { 902 sdhci@700b0000 {
625 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 903 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
626 reg = <0x0 0x700b0000 0x0 0x200>; 904 reg = <0x0 0x700b0000 0x0 0x200>;
@@ -673,6 +951,18 @@
673 #nvidia,mipi-calibrate-cells = <1>; 951 #nvidia,mipi-calibrate-cells = <1>;
674 }; 952 };
675 953
954 aconnect@702c0000 {
955 compatible = "nvidia,tegra210-aconnect";
956 clocks = <&tegra_car TEGRA210_CLK_APE>,
957 <&tegra_car TEGRA210_CLK_APB2APE>;
958 clock-names = "ape", "apb2ape";
959 power-domains = <&pd_audio>;
960 #address-cells = <1>;
961 #size-cells = <1>;
962 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
963 status = "disabled";
964 };
965
676 spi@70410000 { 966 spi@70410000 {
677 compatible = "nvidia,tegra210-qspi"; 967 compatible = "nvidia,tegra210-qspi";
678 reg = <0x0 0x70410000 0x0 0x1000>; 968 reg = <0x0 0x70410000 0x0 0x1000>;
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
index 205ef89b8ca0..18639bc0a506 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
@@ -33,6 +33,10 @@
33 }; 33 };
34 34
35 soc { 35 soc {
36 dma@7884000 {
37 status = "okay";
38 };
39
36 serial@78af000 { 40 serial@78af000 {
37 label = "LS-UART0"; 41 label = "LS-UART0";
38 status = "okay"; 42 status = "okay";
@@ -140,6 +144,18 @@
140 status = "okay"; 144 status = "okay";
141 }; 145 };
142 146
147 sdhci@07864000 {
148 vmmc-supply = <&pm8916_l11>;
149 vqmmc-supply = <&pm8916_l12>;
150
151 pinctrl-names = "default", "sleep";
152 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
153 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
154
155 cd-gpios = <&msmgpio 38 0x1>;
156 status = "okay";
157 };
158
143 usb@78d9000 { 159 usb@78d9000 {
144 extcon = <&usb_id>, <&usb_id>; 160 extcon = <&usb_id>, <&usb_id>;
145 status = "okay"; 161 status = "okay";
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 96812007850e..11bdc24cfc74 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -42,13 +42,48 @@
42 #size-cells = <2>; 42 #size-cells = <2>;
43 ranges; 43 ranges;
44 44
45 reserve_aligned@86000000 { 45 tz-apps@86000000 {
46 reg = <0x0 0x86000000 0x0 0x0300000>; 46 reg = <0x0 0x86000000 0x0 0x300000>;
47 no-map; 47 no-map;
48 }; 48 };
49 49
50 smem_mem: smem_region@86300000 { 50 smem_mem: smem_region@86300000 {
51 reg = <0x0 0x86300000 0x0 0x0100000>; 51 reg = <0x0 0x86300000 0x0 0x100000>;
52 no-map;
53 };
54
55 hypervisor@86400000 {
56 reg = <0x0 0x86400000 0x0 0x100000>;
57 no-map;
58 };
59
60 tz@86500000 {
61 reg = <0x0 0x86500000 0x0 0x180000>;
62 no-map;
63 };
64
65 reserved@8668000 {
66 reg = <0x0 0x86680000 0x0 0x80000>;
67 no-map;
68 };
69
70 rmtfs@86700000 {
71 reg = <0x0 0x86700000 0x0 0xe0000>;
72 no-map;
73 };
74
75 rfsa@867e00000 {
76 reg = <0x0 0x867e0000 0x0 0x20000>;
77 no-map;
78 };
79
80 mpss@86800000 {
81 reg = <0x0 0x86800000 0x0 0x2b00000>;
82 no-map;
83 };
84
85 wcnss@89300000 {
86 reg = <0x0 0x89300000 0x0 0x600000>;
52 no-map; 87 no-map;
53 }; 88 };
54 }; 89 };
@@ -62,6 +97,8 @@
62 compatible = "arm,cortex-a53", "arm,armv8"; 97 compatible = "arm,cortex-a53", "arm,armv8";
63 reg = <0x0>; 98 reg = <0x0>;
64 next-level-cache = <&L2_0>; 99 next-level-cache = <&L2_0>;
100 enable-method = "psci";
101 cpu-idle-states = <&CPU_SPC>;
65 }; 102 };
66 103
67 CPU1: cpu@1 { 104 CPU1: cpu@1 {
@@ -69,6 +106,8 @@
69 compatible = "arm,cortex-a53", "arm,armv8"; 106 compatible = "arm,cortex-a53", "arm,armv8";
70 reg = <0x1>; 107 reg = <0x1>;
71 next-level-cache = <&L2_0>; 108 next-level-cache = <&L2_0>;
109 enable-method = "psci";
110 cpu-idle-states = <&CPU_SPC>;
72 }; 111 };
73 112
74 CPU2: cpu@2 { 113 CPU2: cpu@2 {
@@ -76,6 +115,8 @@
76 compatible = "arm,cortex-a53", "arm,armv8"; 115 compatible = "arm,cortex-a53", "arm,armv8";
77 reg = <0x2>; 116 reg = <0x2>;
78 next-level-cache = <&L2_0>; 117 next-level-cache = <&L2_0>;
118 enable-method = "psci";
119 cpu-idle-states = <&CPU_SPC>;
79 }; 120 };
80 121
81 CPU3: cpu@3 { 122 CPU3: cpu@3 {
@@ -83,12 +124,35 @@
83 compatible = "arm,cortex-a53", "arm,armv8"; 124 compatible = "arm,cortex-a53", "arm,armv8";
84 reg = <0x3>; 125 reg = <0x3>;
85 next-level-cache = <&L2_0>; 126 next-level-cache = <&L2_0>;
127 enable-method = "psci";
128 cpu-idle-states = <&CPU_SPC>;
86 }; 129 };
87 130
88 L2_0: l2-cache { 131 L2_0: l2-cache {
89 compatible = "cache"; 132 compatible = "cache";
90 cache-level = <2>; 133 cache-level = <2>;
91 }; 134 };
135
136 idle-states {
137 CPU_SPC: spc {
138 compatible = "arm,idle-state";
139 arm,psci-suspend-param = <0x40000002>;
140 entry-latency-us = <130>;
141 exit-latency-us = <150>;
142 min-residency-us = <2000>;
143 local-timer-stop;
144 };
145 };
146 };
147
148 psci {
149 compatible = "arm,psci-1.0";
150 method = "smc";
151 };
152
153 pmu {
154 compatible = "arm,armv8-pmuv3";
155 interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
92 }; 156 };
93 157
94 timer { 158 timer {
@@ -122,6 +186,14 @@
122 hwlocks = <&tcsr_mutex 3>; 186 hwlocks = <&tcsr_mutex 3>;
123 }; 187 };
124 188
189 firmware {
190 scm {
191 compatible = "qcom,scm";
192 clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
193 clock-names = "core", "bus", "iface";
194 };
195 };
196
125 soc: soc { 197 soc: soc {
126 #address-cells = <1>; 198 #address-cells = <1>;
127 #size-cells = <1>; 199 #size-cells = <1>;
diff --git a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi
new file mode 100644
index 000000000000..659940434842
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi
@@ -0,0 +1,303 @@
1/*
2 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14&msmgpio {
15
16 blsp1_spi0_default: blsp1_spi0_default {
17 pinmux {
18 function = "blsp_spi1";
19 pins = "gpio0", "gpio1", "gpio3";
20 };
21 pinmux_cs {
22 function = "gpio";
23 pins = "gpio2";
24 };
25 pinconf {
26 pins = "gpio0", "gpio1", "gpio3";
27 drive-strength = <12>;
28 bias-disable;
29 };
30 pinconf_cs {
31 pins = "gpio2";
32 drive-strength = <16>;
33 bias-disable;
34 output-high;
35 };
36 };
37
38 blsp1_spi0_sleep: blsp1_spi0_sleep {
39 pinmux {
40 function = "gpio";
41 pins = "gpio0", "gpio1", "gpio2", "gpio3";
42 };
43 pinconf {
44 pins = "gpio0", "gpio1", "gpio2", "gpio3";
45 drive-strength = <2>;
46 bias-pull-down;
47 };
48 };
49
50 blsp1_i2c2_default: blsp1_i2c2_default {
51 pinmux {
52 function = "blsp_i2c3";
53 pins = "gpio47", "gpio48";
54 };
55 pinconf {
56 pins = "gpio47", "gpio48";
57 drive-strength = <16>;
58 bias-disable = <0>;
59 };
60 };
61
62 blsp1_i2c2_sleep: blsp1_i2c2_sleep {
63 pinmux {
64 function = "gpio";
65 pins = "gpio47", "gpio48";
66 };
67 pinconf {
68 pins = "gpio47", "gpio48";
69 drive-strength = <2>;
70 bias-disable = <0>;
71 };
72 };
73
74 blsp2_i2c0_default: blsp2_i2c0 {
75 pinmux {
76 function = "blsp_i2c7";
77 pins = "gpio55", "gpio56";
78 };
79 pinconf {
80 pins = "gpio55", "gpio56";
81 drive-strength = <16>;
82 bias-disable;
83 };
84 };
85
86 blsp2_i2c0_sleep: blsp2_i2c0_sleep {
87 pinmux {
88 function = "gpio";
89 pins = "gpio55", "gpio56";
90 };
91 pinconf {
92 pins = "gpio55", "gpio56";
93 drive-strength = <2>;
94 bias-disable;
95 };
96 };
97
98 blsp2_uart1_2pins_default: blsp2_uart1_2pins {
99 pinmux {
100 function = "blsp_uart8";
101 pins = "gpio4", "gpio5";
102 };
103 pinconf {
104 pins = "gpio4", "gpio5";
105 drive-strength = <16>;
106 bias-disable;
107 };
108 };
109
110 blsp2_uart1_2pins_sleep: blsp2_uart1_2pins_sleep {
111 pinmux {
112 function = "gpio";
113 pins = "gpio4", "gpio5";
114 };
115 pinconf {
116 pins = "gpio4", "gpio5";
117 drive-strength = <2>;
118 bias-disable;
119 };
120 };
121
122 blsp2_uart1_4pins_default: blsp2_uart1_4pins {
123 pinmux {
124 function = "blsp_uart8";
125 pins = "gpio4", "gpio5", "gpio6", "gpio7";
126 };
127
128 pinconf {
129 pins = "gpio4", "gpio5", "gpio6", "gpio7";
130 drive-strength = <16>;
131 bias-disable;
132 };
133 };
134
135 blsp2_uart1_4pins_sleep: blsp2_uart1_4pins_sleep {
136 pinmux {
137 function = "gpio";
138 pins = "gpio4", "gpio5", "gpio6", "gpio7";
139 };
140
141 pinconf {
142 pins = "gpio4", "gpiio5", "gpio6", "gpio7";
143 drive-strength = <2>;
144 bias-disable;
145 };
146 };
147
148 blsp2_i2c1_default: blsp2_i2c1 {
149 pinmux {
150 function = "blsp_i2c8";
151 pins = "gpio6", "gpio7";
152 };
153 pinconf {
154 pins = "gpio6", "gpio7";
155 drive-strength = <16>;
156 bias-disable;
157 };
158 };
159
160 blsp2_i2c1_sleep: blsp2_i2c1_sleep {
161 pinmux {
162 function = "gpio";
163 pins = "gpio6", "gpio7";
164 };
165 pinconf {
166 pins = "gpio6", "gpio7";
167 drive-strength = <2>;
168 bias-disable;
169 };
170 };
171
172 blsp2_uart2_2pins_default: blsp2_uart2_2pins {
173 pinmux {
174 function = "blsp_uart9";
175 pins = "gpio49", "gpio50";
176 };
177 pinconf {
178 pins = "gpio49", "gpio50";
179 drive-strength = <16>;
180 bias-disable;
181 };
182 };
183
184 blsp2_uart2_2pins_sleep: blsp2_uart2_2pins_sleep {
185 pinmux {
186 function = "gpio";
187 pins = "gpio49", "gpio50";
188 };
189 pinconf {
190 pins = "gpio49", "gpio50";
191 drive-strength = <2>;
192 bias-disable;
193 };
194 };
195
196 blsp2_uart2_4pins_default: blsp2_uart2_4pins {
197 pinmux {
198 function = "blsp_uart9";
199 pins = "gpio49", "gpio50", "gpio51", "gpio52";
200 };
201
202 pinconf {
203 pins = "gpio49", "gpio50", "gpio51", "gpio52";
204 drive-strength = <16>;
205 bias-disable;
206 };
207 };
208
209 blsp2_uart2_4pins_sleep: blsp2_uart2_4pins_sleep {
210 pinmux {
211 function = "gpio";
212 pins = "gpio49", "gpio50", "gpio51", "gpio52";
213 };
214
215 pinconf {
216 pins = "gpio49", "gpio50", "gpio51", "gpio52";
217 drive-strength = <2>;
218 bias-disable;
219 };
220 };
221
222 blsp2_spi5_default: blsp2_spi5_default {
223 pinmux {
224 function = "blsp_spi12";
225 pins = "gpio85", "gpio86", "gpio88";
226 };
227 pinmux_cs {
228 function = "gpio";
229 pins = "gpio87";
230 };
231 pinconf {
232 pins = "gpio85", "gpio86", "gpio88";
233 drive-strength = <12>;
234 bias-disable;
235 };
236 pinconf_cs {
237 pins = "gpio87";
238 drive-strength = <16>;
239 bias-disable;
240 output-high;
241 };
242 };
243
244 blsp2_spi5_sleep: blsp2_spi5_sleep {
245 pinmux {
246 function = "gpio";
247 pins = "gpio85", "gpio86", "gpio87", "gpio88";
248 };
249 pinconf {
250 pins = "gpio85", "gpio86", "gpio87", "gpio88";
251 drive-strength = <2>;
252 bias-pull-down;
253 };
254 };
255
256 sdc2_clk_on: sdc2_clk_on {
257 config {
258 pins = "sdc2_clk";
259 bias-disable; /* NO pull */
260 drive-strength = <16>; /* 16 MA */
261 };
262 };
263
264 sdc2_clk_off: sdc2_clk_off {
265 config {
266 pins = "sdc2_clk";
267 bias-disable; /* NO pull */
268 drive-strength = <2>; /* 2 MA */
269 };
270 };
271
272 sdc2_cmd_on: sdc2_cmd_on {
273 config {
274 pins = "sdc2_cmd";
275 bias-pull-up; /* pull up */
276 drive-strength = <10>; /* 10 MA */
277 };
278 };
279
280 sdc2_cmd_off: sdc2_cmd_off {
281 config {
282 pins = "sdc2_cmd";
283 bias-pull-up; /* pull up */
284 drive-strength = <2>; /* 2 MA */
285 };
286 };
287
288 sdc2_data_on: sdc2_data_on {
289 config {
290 pins = "sdc2_data";
291 bias-pull-up; /* pull up */
292 drive-strength = <10>; /* 10 MA */
293 };
294 };
295
296 sdc2_data_off: sdc2_data_off {
297 config {
298 pins = "sdc2_data";
299 bias-pull-up; /* pull up */
300 drive-strength = <2>; /* 2 MA */
301 };
302 };
303};
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 0506fb808c56..55ec3e8326b7 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -151,6 +151,36 @@
151 reg = <0x300000 0x90000>; 151 reg = <0x300000 0x90000>;
152 }; 152 };
153 153
154 blsp1_spi0: spi@07575000 {
155 compatible = "qcom,spi-qup-v2.2.1";
156 reg = <0x07575000 0x600>;
157 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
158 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
159 <&gcc GCC_BLSP1_AHB_CLK>;
160 clock-names = "core", "iface";
161 pinctrl-names = "default", "sleep";
162 pinctrl-0 = <&blsp1_spi0_default>;
163 pinctrl-1 = <&blsp1_spi0_sleep>;
164 #address-cells = <1>;
165 #size-cells = <0>;
166 status = "disabled";
167 };
168
169 blsp2_i2c0: i2c@075b5000 {
170 compatible = "qcom,i2c-qup-v2.2.1";
171 reg = <0x075b5000 0x1000>;
172 interrupts = <GIC_SPI 101 0>;
173 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
174 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
175 clock-names = "iface", "core";
176 pinctrl-names = "default", "sleep";
177 pinctrl-0 = <&blsp2_i2c0_default>;
178 pinctrl-1 = <&blsp2_i2c0_sleep>;
179 #address-cells = <1>;
180 #size-cells = <0>;
181 status = "disabled";
182 };
183
154 blsp2_uart1: serial@75b0000 { 184 blsp2_uart1: serial@75b0000 {
155 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 185 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
156 reg = <0x75b0000 0x1000>; 186 reg = <0x75b0000 0x1000>;
@@ -161,7 +191,77 @@
161 status = "disabled"; 191 status = "disabled";
162 }; 192 };
163 193
164 pinctrl@1010000 { 194 blsp2_i2c1: i2c@075b6000 {
195 compatible = "qcom,i2c-qup-v2.2.1";
196 reg = <0x075b6000 0x1000>;
197 interrupts = <GIC_SPI 102 0>;
198 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
199 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
200 clock-names = "iface", "core";
201 pinctrl-names = "default", "sleep";
202 pinctrl-0 = <&blsp2_i2c1_default>;
203 pinctrl-1 = <&blsp2_i2c1_sleep>;
204 #address-cells = <1>;
205 #size-cells = <0>;
206 status = "disabled";
207 };
208
209 blsp2_uart2: serial@75b1000 {
210 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
211 reg = <0x075b1000 0x1000>;
212 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
213 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
214 <&gcc GCC_BLSP2_AHB_CLK>;
215 clock-names = "core", "iface";
216 status = "disabled";
217 };
218
219 blsp1_i2c2: i2c@07577000 {
220 compatible = "qcom,i2c-qup-v2.2.1";
221 reg = <0x07577000 0x1000>;
222 interrupts = <GIC_SPI 97 0>;
223 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
224 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
225 clock-names = "iface", "core";
226 pinctrl-names = "default", "sleep";
227 pinctrl-0 = <&blsp1_i2c2_default>;
228 pinctrl-1 = <&blsp1_i2c2_sleep>;
229 #address-cells = <1>;
230 #size-cells = <0>;
231 status = "disabled";
232 };
233
234 blsp2_spi5: spi@075ba000{
235 compatible = "qcom,spi-qup-v2.2.1";
236 reg = <0x075ba000 0x600>;
237 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>,
239 <&gcc GCC_BLSP2_AHB_CLK>;
240 clock-names = "core", "iface";
241 pinctrl-names = "default", "sleep";
242 pinctrl-0 = <&blsp2_spi5_default>;
243 pinctrl-1 = <&blsp2_spi5_sleep>;
244 #address-cells = <1>;
245 #size-cells = <0>;
246 status = "disabled";
247 };
248
249 sdhc2: sdhci@74a4900 {
250 status = "disabled";
251 compatible = "qcom,sdhci-msm-v4";
252 reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
253 reg-names = "hc_mem", "core_mem";
254
255 interrupts = <0 125 0>, <0 221 0>;
256 interrupt-names = "hc_irq", "pwr_irq";
257
258 clock-names = "iface", "core";
259 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
260 <&gcc GCC_SDCC2_APPS_CLK>;
261 bus-width = <4>;
262 };
263
264 msmgpio: pinctrl@1010000 {
165 compatible = "qcom,msm8996-pinctrl"; 265 compatible = "qcom,msm8996-pinctrl";
166 reg = <0x01010000 0x300000>; 266 reg = <0x01010000 0x300000>;
167 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 267 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
@@ -267,3 +367,4 @@
267 }; 367 };
268 }; 368 };
269}; 369};
370#include "msm8996-pins.dtsi"
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 9ce1890a650e..17139f7003a6 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -1,4 +1,5 @@
1dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb 1dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb
2dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb
2 3
3always := $(dtb-y) 4always := $(dtb-y)
4clean-files := *.dtb 5clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
index 9f561c943f6f..98f02631a0f0 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
@@ -62,7 +62,7 @@
62 clock-frequency = <24576000>; 62 clock-frequency = <24576000>;
63 }; 63 };
64 64
65 vcc_sdhi0: regulator@1 { 65 vcc_sdhi0: regulator-vcc-sdhi0 {
66 compatible = "regulator-fixed"; 66 compatible = "regulator-fixed";
67 67
68 regulator-name = "SDHI0 Vcc"; 68 regulator-name = "SDHI0 Vcc";
@@ -73,7 +73,7 @@
73 enable-active-high; 73 enable-active-high;
74 }; 74 };
75 75
76 vccq_sdhi0: regulator@2 { 76 vccq_sdhi0: regulator-vccq-sdhi0 {
77 compatible = "regulator-gpio"; 77 compatible = "regulator-gpio";
78 78
79 regulator-name = "SDHI0 VccQ"; 79 regulator-name = "SDHI0 VccQ";
@@ -86,7 +86,7 @@
86 1800000 0>; 86 1800000 0>;
87 }; 87 };
88 88
89 vcc_sdhi3: regulator@3 { 89 vcc_sdhi3: regulator-vcc-sdhi3 {
90 compatible = "regulator-fixed"; 90 compatible = "regulator-fixed";
91 91
92 regulator-name = "SDHI3 Vcc"; 92 regulator-name = "SDHI3 Vcc";
@@ -97,7 +97,7 @@
97 enable-active-high; 97 enable-active-high;
98 }; 98 };
99 99
100 vccq_sdhi3: regulator@4 { 100 vccq_sdhi3: regulator-vccq-sdhi3 {
101 compatible = "regulator-gpio"; 101 compatible = "regulator-gpio";
102 102
103 regulator-name = "SDHI3 VccQ"; 103 regulator-name = "SDHI3 VccQ";
@@ -208,6 +208,7 @@
208 pinctrl-0 = <&scif1_pins>; 208 pinctrl-0 = <&scif1_pins>;
209 pinctrl-names = "default"; 209 pinctrl-names = "default";
210 210
211 uart-has-rtscts;
211 status = "okay"; 212 status = "okay";
212}; 213};
213 214
@@ -329,6 +330,11 @@
329 shared-pin; 330 shared-pin;
330}; 331};
331 332
333&wdt0 {
334 timeout-sec = <60>;
335 status = "okay";
336};
337
332&audio_clk_a { 338&audio_clk_a {
333 clock-frequency = <22579200>; 339 clock-frequency = <22579200>;
334}; 340};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 3285a9286786..b902356873c2 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -53,6 +53,7 @@
53 next-level-cache = <&L2_CA57>; 53 next-level-cache = <&L2_CA57>;
54 enable-method = "psci"; 54 enable-method = "psci";
55 }; 55 };
56
56 a57_2: cpu@2 { 57 a57_2: cpu@2 {
57 compatible = "arm,cortex-a57","arm,armv8"; 58 compatible = "arm,cortex-a57","arm,armv8";
58 reg = <0x2>; 59 reg = <0x2>;
@@ -61,6 +62,7 @@
61 next-level-cache = <&L2_CA57>; 62 next-level-cache = <&L2_CA57>;
62 enable-method = "psci"; 63 enable-method = "psci";
63 }; 64 };
65
64 a57_3: cpu@3 { 66 a57_3: cpu@3 {
65 compatible = "arm,cortex-a57","arm,armv8"; 67 compatible = "arm,cortex-a57","arm,armv8";
66 reg = <0x3>; 68 reg = <0x3>;
@@ -69,20 +71,22 @@
69 next-level-cache = <&L2_CA57>; 71 next-level-cache = <&L2_CA57>;
70 enable-method = "psci"; 72 enable-method = "psci";
71 }; 73 };
72 };
73 74
74 L2_CA57: cache-controller@0 { 75 L2_CA57: cache-controller@0 {
75 compatible = "cache"; 76 compatible = "cache";
76 power-domains = <&sysc R8A7795_PD_CA57_SCU>; 77 reg = <0>;
77 cache-unified; 78 power-domains = <&sysc R8A7795_PD_CA57_SCU>;
78 cache-level = <2>; 79 cache-unified;
79 }; 80 cache-level = <2>;
81 };
80 82
81 L2_CA53: cache-controller@1 { 83 L2_CA53: cache-controller@100 {
82 compatible = "cache"; 84 compatible = "cache";
83 power-domains = <&sysc R8A7795_PD_CA53_SCU>; 85 reg = <0x100>;
84 cache-unified; 86 power-domains = <&sysc R8A7795_PD_CA53_SCU>;
85 cache-level = <2>; 87 cache-unified;
88 cache-level = <2>;
89 };
86 }; 90 };
87 91
88 extal_clk: extal { 92 extal_clk: extal {
@@ -151,19 +155,27 @@
151 #size-cells = <2>; 155 #size-cells = <2>;
152 ranges; 156 ranges;
153 157
154 gic: interrupt-controller@0xf1010000 { 158 gic: interrupt-controller@f1010000 {
155 compatible = "arm,gic-400"; 159 compatible = "arm,gic-400";
156 #interrupt-cells = <3>; 160 #interrupt-cells = <3>;
157 #address-cells = <0>; 161 #address-cells = <0>;
158 interrupt-controller; 162 interrupt-controller;
159 reg = <0x0 0xf1010000 0 0x1000>, 163 reg = <0x0 0xf1010000 0 0x1000>,
160 <0x0 0xf1020000 0 0x2000>, 164 <0x0 0xf1020000 0 0x20000>,
161 <0x0 0xf1040000 0 0x20000>, 165 <0x0 0xf1040000 0 0x20000>,
162 <0x0 0xf1060000 0 0x2000>; 166 <0x0 0xf1060000 0 0x20000>;
163 interrupts = <GIC_PPI 9 167 interrupts = <GIC_PPI 9
164 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 168 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
165 }; 169 };
166 170
171 wdt0: watchdog@e6020000 {
172 compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt";
173 reg = <0 0xe6020000 0 0x0c>;
174 clocks = <&cpg CPG_MOD 402>;
175 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
176 status = "disabled";
177 };
178
167 gpio0: gpio@e6050000 { 179 gpio0: gpio@e6050000 {
168 compatible = "renesas,gpio-r8a7795", 180 compatible = "renesas,gpio-r8a7795",
169 "renesas,gpio-rcar"; 181 "renesas,gpio-rcar";
@@ -571,6 +583,30 @@
571 status = "disabled"; 583 status = "disabled";
572 }; 584 };
573 585
586 canfd: can@e66c0000 {
587 compatible = "renesas,r8a7795-canfd",
588 "renesas,rcar-gen3-canfd";
589 reg = <0 0xe66c0000 0 0x8000>;
590 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
592 clocks = <&cpg CPG_MOD 914>,
593 <&cpg CPG_CORE R8A7795_CLK_CANFD>,
594 <&can_clk>;
595 clock-names = "fck", "canfd", "can_clk";
596 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
597 assigned-clock-rates = <40000000>;
598 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
599 status = "disabled";
600
601 channel0 {
602 status = "disabled";
603 };
604
605 channel1 {
606 status = "disabled";
607 };
608 };
609
574 hscif0: serial@e6540000 { 610 hscif0: serial@e6540000 {
575 compatible = "renesas,hscif-r8a7795", 611 compatible = "renesas,hscif-r8a7795",
576 "renesas,rcar-gen3-hscif", 612 "renesas,rcar-gen3-hscif",
@@ -749,6 +785,8 @@
749 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 785 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
750 clocks = <&cpg CPG_MOD 931>; 786 clocks = <&cpg CPG_MOD 931>;
751 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 787 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
788 dmas = <&dmac1 0x91>, <&dmac1 0x90>;
789 dma-names = "tx", "rx";
752 i2c-scl-internal-delay-ns = <110>; 790 i2c-scl-internal-delay-ns = <110>;
753 status = "disabled"; 791 status = "disabled";
754 }; 792 };
@@ -761,6 +799,8 @@
761 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 799 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
762 clocks = <&cpg CPG_MOD 930>; 800 clocks = <&cpg CPG_MOD 930>;
763 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 801 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
802 dmas = <&dmac1 0x93>, <&dmac1 0x92>;
803 dma-names = "tx", "rx";
764 i2c-scl-internal-delay-ns = <6>; 804 i2c-scl-internal-delay-ns = <6>;
765 status = "disabled"; 805 status = "disabled";
766 }; 806 };
@@ -773,6 +813,8 @@
773 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 813 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
774 clocks = <&cpg CPG_MOD 929>; 814 clocks = <&cpg CPG_MOD 929>;
775 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 815 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
816 dmas = <&dmac1 0x95>, <&dmac1 0x94>;
817 dma-names = "tx", "rx";
776 i2c-scl-internal-delay-ns = <6>; 818 i2c-scl-internal-delay-ns = <6>;
777 status = "disabled"; 819 status = "disabled";
778 }; 820 };
@@ -785,6 +827,8 @@
785 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 827 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&cpg CPG_MOD 928>; 828 clocks = <&cpg CPG_MOD 928>;
787 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 829 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
830 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
831 dma-names = "tx", "rx";
788 i2c-scl-internal-delay-ns = <110>; 832 i2c-scl-internal-delay-ns = <110>;
789 status = "disabled"; 833 status = "disabled";
790 }; 834 };
@@ -797,6 +841,8 @@
797 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 841 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
798 clocks = <&cpg CPG_MOD 927>; 842 clocks = <&cpg CPG_MOD 927>;
799 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 843 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
844 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
845 dma-names = "tx", "rx";
800 i2c-scl-internal-delay-ns = <110>; 846 i2c-scl-internal-delay-ns = <110>;
801 status = "disabled"; 847 status = "disabled";
802 }; 848 };
@@ -809,6 +855,8 @@
809 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 855 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
810 clocks = <&cpg CPG_MOD 919>; 856 clocks = <&cpg CPG_MOD 919>;
811 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 857 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
858 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
859 dma-names = "tx", "rx";
812 i2c-scl-internal-delay-ns = <110>; 860 i2c-scl-internal-delay-ns = <110>;
813 status = "disabled"; 861 status = "disabled";
814 }; 862 };
@@ -821,6 +869,8 @@
821 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 869 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
822 clocks = <&cpg CPG_MOD 918>; 870 clocks = <&cpg CPG_MOD 918>;
823 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 871 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
872 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
873 dma-names = "tx", "rx";
824 i2c-scl-internal-delay-ns = <6>; 874 i2c-scl-internal-delay-ns = <6>;
825 status = "disabled"; 875 status = "disabled";
826 }; 876 };
@@ -874,63 +924,63 @@
874 status = "disabled"; 924 status = "disabled";
875 925
876 rcar_sound,dvc { 926 rcar_sound,dvc {
877 dvc0: dvc@0 { 927 dvc0: dvc-0 {
878 dmas = <&audma0 0xbc>; 928 dmas = <&audma0 0xbc>;
879 dma-names = "tx"; 929 dma-names = "tx";
880 }; 930 };
881 dvc1: dvc@1 { 931 dvc1: dvc-1 {
882 dmas = <&audma0 0xbe>; 932 dmas = <&audma0 0xbe>;
883 dma-names = "tx"; 933 dma-names = "tx";
884 }; 934 };
885 }; 935 };
886 936
887 rcar_sound,src { 937 rcar_sound,src {
888 src0: src@0 { 938 src0: src-0 {
889 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 939 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
890 dmas = <&audma0 0x85>, <&audma1 0x9a>; 940 dmas = <&audma0 0x85>, <&audma1 0x9a>;
891 dma-names = "rx", "tx"; 941 dma-names = "rx", "tx";
892 }; 942 };
893 src1: src@1 { 943 src1: src-1 {
894 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 944 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
895 dmas = <&audma0 0x87>, <&audma1 0x9c>; 945 dmas = <&audma0 0x87>, <&audma1 0x9c>;
896 dma-names = "rx", "tx"; 946 dma-names = "rx", "tx";
897 }; 947 };
898 src2: src@2 { 948 src2: src-2 {
899 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 949 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
900 dmas = <&audma0 0x89>, <&audma1 0x9e>; 950 dmas = <&audma0 0x89>, <&audma1 0x9e>;
901 dma-names = "rx", "tx"; 951 dma-names = "rx", "tx";
902 }; 952 };
903 src3: src@3 { 953 src3: src-3 {
904 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 954 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
905 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 955 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
906 dma-names = "rx", "tx"; 956 dma-names = "rx", "tx";
907 }; 957 };
908 src4: src@4 { 958 src4: src-4 {
909 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 959 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
910 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 960 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
911 dma-names = "rx", "tx"; 961 dma-names = "rx", "tx";
912 }; 962 };
913 src5: src@5 { 963 src5: src-5 {
914 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 964 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
915 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 965 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
916 dma-names = "rx", "tx"; 966 dma-names = "rx", "tx";
917 }; 967 };
918 src6: src@6 { 968 src6: src-6 {
919 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 969 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
920 dmas = <&audma0 0x91>, <&audma1 0xb4>; 970 dmas = <&audma0 0x91>, <&audma1 0xb4>;
921 dma-names = "rx", "tx"; 971 dma-names = "rx", "tx";
922 }; 972 };
923 src7: src@7 { 973 src7: src-7 {
924 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 974 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
925 dmas = <&audma0 0x93>, <&audma1 0xb6>; 975 dmas = <&audma0 0x93>, <&audma1 0xb6>;
926 dma-names = "rx", "tx"; 976 dma-names = "rx", "tx";
927 }; 977 };
928 src8: src@8 { 978 src8: src-8 {
929 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 979 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
930 dmas = <&audma0 0x95>, <&audma1 0xb8>; 980 dmas = <&audma0 0x95>, <&audma1 0xb8>;
931 dma-names = "rx", "tx"; 981 dma-names = "rx", "tx";
932 }; 982 };
933 src9: src@9 { 983 src9: src-9 {
934 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 984 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
935 dmas = <&audma0 0x97>, <&audma1 0xba>; 985 dmas = <&audma0 0x97>, <&audma1 0xba>;
936 dma-names = "rx", "tx"; 986 dma-names = "rx", "tx";
@@ -938,52 +988,52 @@
938 }; 988 };
939 989
940 rcar_sound,ssi { 990 rcar_sound,ssi {
941 ssi0: ssi@0 { 991 ssi0: ssi-0 {
942 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 992 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
943 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; 993 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
944 dma-names = "rx", "tx", "rxu", "txu"; 994 dma-names = "rx", "tx", "rxu", "txu";
945 }; 995 };
946 ssi1: ssi@1 { 996 ssi1: ssi-1 {
947 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 997 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
948 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; 998 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
949 dma-names = "rx", "tx", "rxu", "txu"; 999 dma-names = "rx", "tx", "rxu", "txu";
950 }; 1000 };
951 ssi2: ssi@2 { 1001 ssi2: ssi-2 {
952 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1002 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
953 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; 1003 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
954 dma-names = "rx", "tx", "rxu", "txu"; 1004 dma-names = "rx", "tx", "rxu", "txu";
955 }; 1005 };
956 ssi3: ssi@3 { 1006 ssi3: ssi-3 {
957 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1007 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
958 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; 1008 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
959 dma-names = "rx", "tx", "rxu", "txu"; 1009 dma-names = "rx", "tx", "rxu", "txu";
960 }; 1010 };
961 ssi4: ssi@4 { 1011 ssi4: ssi-4 {
962 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1012 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
963 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; 1013 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
964 dma-names = "rx", "tx", "rxu", "txu"; 1014 dma-names = "rx", "tx", "rxu", "txu";
965 }; 1015 };
966 ssi5: ssi@5 { 1016 ssi5: ssi-5 {
967 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1017 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
968 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; 1018 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
969 dma-names = "rx", "tx", "rxu", "txu"; 1019 dma-names = "rx", "tx", "rxu", "txu";
970 }; 1020 };
971 ssi6: ssi@6 { 1021 ssi6: ssi-6 {
972 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1022 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
973 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; 1023 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
974 dma-names = "rx", "tx", "rxu", "txu"; 1024 dma-names = "rx", "tx", "rxu", "txu";
975 }; 1025 };
976 ssi7: ssi@7 { 1026 ssi7: ssi-7 {
977 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1027 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
978 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; 1028 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
979 dma-names = "rx", "tx", "rxu", "txu"; 1029 dma-names = "rx", "tx", "rxu", "txu";
980 }; 1030 };
981 ssi8: ssi@8 { 1031 ssi8: ssi-8 {
982 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1032 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
983 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; 1033 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
984 dma-names = "rx", "tx", "rxu", "txu"; 1034 dma-names = "rx", "tx", "rxu", "txu";
985 }; 1035 };
986 ssi9: ssi@9 { 1036 ssi9: ssi-9 {
987 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1037 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
988 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; 1038 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
989 dma-names = "rx", "tx", "rxu", "txu"; 1039 dma-names = "rx", "tx", "rxu", "txu";
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
new file mode 100644
index 000000000000..e72be3856d79
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
@@ -0,0 +1,50 @@
1/*
2 * Device Tree Source for the Salvator-X board
3 *
4 * Copyright (C) 2016 Renesas Electronics Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/dts-v1/;
12#include "r8a7796.dtsi"
13
14/ {
15 model = "Renesas Salvator-X board based on r8a7796";
16 compatible = "renesas,salvator-x", "renesas,r8a7796";
17
18 aliases {
19 serial0 = &scif2;
20 };
21
22 chosen {
23 bootargs = "ignore_loglevel";
24 stdout-path = "serial0:115200n8";
25 };
26
27 memory@48000000 {
28 device_type = "memory";
29 /* first 128MB is reserved for secure area. */
30 reg = <0x0 0x48000000 0x0 0x78000000>;
31 };
32};
33
34&extal_clk {
35 clock-frequency = <16666666>;
36};
37
38&scif2 {
39 status = "okay";
40};
41
42&scif_clk {
43 clock-frequency = <14745600>;
44 status = "okay";
45};
46
47&wdt0 {
48 timeout-sec = <60>;
49 status = "okay";
50};
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
new file mode 100644
index 000000000000..1edf82440d78
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -0,0 +1,138 @@
1/*
2 * Device Tree Source for the r8a7796 SoC
3 *
4 * Copyright (C) 2016 Renesas Electronics Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/power/r8a7796-sysc.h>
14
15/ {
16 compatible = "renesas,r8a7796";
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 psci {
21 compatible = "arm,psci-0.2";
22 method = "smc";
23 };
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 /* 1 core only at this point */
30 a57_0: cpu@0 {
31 compatible = "arm,cortex-a57", "arm,armv8";
32 reg = <0x0>;
33 device_type = "cpu";
34 power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
35 next-level-cache = <&L2_CA57>;
36 enable-method = "psci";
37 };
38
39 L2_CA57: cache-controller@0 {
40 compatible = "cache";
41 reg = <0>;
42 power-domains = <&sysc R8A7796_PD_CA57_SCU>;
43 cache-unified;
44 cache-level = <2>;
45 };
46 };
47
48 extal_clk: extal {
49 compatible = "fixed-clock";
50 #clock-cells = <0>;
51 /* This value must be overridden by the board */
52 clock-frequency = <0>;
53 };
54
55 extalr_clk: extalr {
56 compatible = "fixed-clock";
57 #clock-cells = <0>;
58 /* This value must be overridden by the board */
59 clock-frequency = <0>;
60 };
61
62 /* External SCIF clock - to be overridden by boards that provide it */
63 scif_clk: scif {
64 compatible = "fixed-clock";
65 #clock-cells = <0>;
66 clock-frequency = <0>;
67 };
68
69 soc {
70 compatible = "simple-bus";
71 interrupt-parent = <&gic>;
72 #address-cells = <2>;
73 #size-cells = <2>;
74 ranges;
75
76 gic: interrupt-controller@f1010000 {
77 compatible = "arm,gic-400";
78 #interrupt-cells = <3>;
79 #address-cells = <0>;
80 interrupt-controller;
81 reg = <0x0 0xf1010000 0 0x1000>,
82 <0x0 0xf1020000 0 0x20000>,
83 <0x0 0xf1040000 0 0x20000>,
84 <0x0 0xf1060000 0 0x20000>;
85 interrupts = <GIC_PPI 9
86 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
87 };
88
89 timer {
90 compatible = "arm,armv8-timer";
91 interrupts = <GIC_PPI 13
92 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
93 <GIC_PPI 14
94 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
95 <GIC_PPI 11
96 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
97 <GIC_PPI 10
98 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
99 };
100
101 wdt0: watchdog@e6020000 {
102 compatible = "renesas,r8a7796-wdt",
103 "renesas,rcar-gen3-wdt";
104 reg = <0 0xe6020000 0 0x0c>;
105 clocks = <&cpg CPG_MOD 402>;
106 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
107 status = "disabled";
108 };
109
110 cpg: clock-controller@e6150000 {
111 compatible = "renesas,r8a7796-cpg-mssr";
112 reg = <0 0xe6150000 0 0x1000>;
113 clocks = <&extal_clk>, <&extalr_clk>;
114 clock-names = "extal", "extalr";
115 #clock-cells = <2>;
116 #power-domain-cells = <0>;
117 };
118
119 sysc: system-controller@e6180000 {
120 compatible = "renesas,r8a7796-sysc";
121 reg = <0 0xe6180000 0 0x0400>;
122 #power-domain-cells = <1>;
123 };
124
125 scif2: serial@e6e88000 {
126 compatible = "renesas,scif-r8a7796",
127 "renesas,rcar-gen3-scif", "renesas,scif";
128 reg = <0 0xe6e88000 0 64>;
129 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
130 clocks = <&cpg CPG_MOD 310>,
131 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
132 <&scif_clk>;
133 clock-names = "fck", "brg_int", "scif_clk";
134 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
135 status = "disabled";
136 };
137 };
138};
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
index b56b7205e39b..82a32e5591e2 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
@@ -236,6 +236,15 @@
236 }; 236 };
237}; 237};
238 238
239&io_domains {
240 status = "ok";
241
242 audio-supply = <&vcc_io>;
243 gpio30-supply = <&vcc_io>;
244 gpio1830-supply = <&vcc_io>;
245 wifi-supply = <&vccio_wl>;
246};
247
239&sdio0 { 248&sdio0 {
240 assigned-clocks = <&cru SCLK_SDIO0>; 249 assigned-clocks = <&cru SCLK_SDIO0>;
241 assigned-clock-parents = <&cru PLL_CPLL>; 250 assigned-clock-parents = <&cru PLL_CPLL>;
@@ -329,6 +338,13 @@
329 }; 338 };
330}; 339};
331 340
341&pmu_io_domains {
342 status = "okay";
343
344 pmu-supply = <&vcc_io>;
345 vop-supply = <&vcc_io>;
346};
347
332&saradc { 348&saradc {
333 vref-supply = <&vcc_18>; 349 vref-supply = <&vcc_18>;
334 status = "okay"; 350 status = "okay";
diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 8b4a7c9154e9..d02a900378e1 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -632,8 +632,13 @@
632 }; 632 };
633 633
634 pmugrf: syscon@ff738000 { 634 pmugrf: syscon@ff738000 {
635 compatible = "rockchip,rk3368-pmugrf", "syscon"; 635 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
636 reg = <0x0 0xff738000 0x0 0x1000>; 636 reg = <0x0 0xff738000 0x0 0x1000>;
637
638 pmu_io_domains: io-domains {
639 compatible = "rockchip,rk3368-pmu-io-voltage-domain";
640 status = "disabled";
641 };
637 }; 642 };
638 643
639 cru: clock-controller@ff760000 { 644 cru: clock-controller@ff760000 {
@@ -645,8 +650,13 @@
645 }; 650 };
646 651
647 grf: syscon@ff770000 { 652 grf: syscon@ff770000 {
648 compatible = "rockchip,rk3368-grf", "syscon"; 653 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
649 reg = <0x0 0xff770000 0x0 0x1000>; 654 reg = <0x0 0xff770000 0x0 0x1000>;
655
656 io_domains: io-domains {
657 compatible = "rockchip,rk3368-io-voltage-domain";
658 status = "disabled";
659 };
650 }; 660 };
651 661
652 wdt: watchdog@ff800000 { 662 wdt: watchdog@ff800000 {
@@ -670,7 +680,7 @@
670 #address-cells = <0>; 680 #address-cells = <0>;
671 681
672 reg = <0x0 0xffb71000 0x0 0x1000>, 682 reg = <0x0 0xffb71000 0x0 0x1000>,
673 <0x0 0xffb72000 0x0 0x1000>, 683 <0x0 0xffb72000 0x0 0x2000>,
674 <0x0 0xffb74000 0x0 0x2000>, 684 <0x0 0xffb74000 0x0 0x2000>,
675 <0x0 0xffb76000 0x0 0x2000>; 685 <0x0 0xffb76000 0x0 0x2000>;
676 interrupts = <GIC_PPI 9 686 interrupts = <GIC_PPI 9
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
index 1a3eb1482050..d33aa06d46f5 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
@@ -77,6 +77,10 @@
77 }; 77 };
78}; 78};
79 79
80&emmc_phy {
81 status = "okay";
82};
83
80&pwm0 { 84&pwm0 {
81 status = "okay"; 85 status = "okay";
82}; 86};
@@ -89,6 +93,14 @@
89 status = "okay"; 93 status = "okay";
90}; 94};
91 95
96&sdhci {
97 bus-width = <8>;
98 mmc-hs400-1_8v;
99 mmc-hs400-enhanced-strobe;
100 non-removable;
101 status = "okay";
102};
103
92&uart2 { 104&uart2 {
93 status = "okay"; 105 status = "okay";
94}; 106};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 188bbeab92b9..a6dd623a8845 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -45,6 +45,7 @@
45#include <dt-bindings/interrupt-controller/arm-gic.h> 45#include <dt-bindings/interrupt-controller/arm-gic.h>
46#include <dt-bindings/interrupt-controller/irq.h> 46#include <dt-bindings/interrupt-controller/irq.h>
47#include <dt-bindings/pinctrl/rockchip.h> 47#include <dt-bindings/pinctrl/rockchip.h>
48#include <dt-bindings/thermal/thermal.h>
48 49
49/ { 50/ {
50 compatible = "rockchip,rk3399"; 51 compatible = "rockchip,rk3399";
@@ -54,6 +55,15 @@
54 #size-cells = <2>; 55 #size-cells = <2>;
55 56
56 aliases { 57 aliases {
58 i2c0 = &i2c0;
59 i2c1 = &i2c1;
60 i2c2 = &i2c2;
61 i2c3 = &i2c3;
62 i2c4 = &i2c4;
63 i2c5 = &i2c5;
64 i2c6 = &i2c6;
65 i2c7 = &i2c7;
66 i2c8 = &i2c8;
57 serial0 = &uart0; 67 serial0 = &uart0;
58 serial1 = &uart1; 68 serial1 = &uart1;
59 serial2 = &uart2; 69 serial2 = &uart2;
@@ -215,6 +225,22 @@
215 status = "disabled"; 225 status = "disabled";
216 }; 226 };
217 227
228 sdhci: sdhci@fe330000 {
229 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
230 reg = <0x0 0xfe330000 0x0 0x10000>;
231 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
232 arasan,soc-ctl-syscon = <&grf>;
233 assigned-clocks = <&cru SCLK_EMMC>;
234 assigned-clock-rates = <200000000>;
235 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
236 clock-names = "clk_xin", "clk_ahb";
237 clock-output-names = "emmc_cardclock";
238 #clock-cells = <0>;
239 phys = <&emmc_phy>;
240 phy-names = "phy_arasan";
241 status = "disabled";
242 };
243
218 usb_host0_ehci: usb@fe380000 { 244 usb_host0_ehci: usb@fe380000 {
219 compatible = "generic-ehci"; 245 compatible = "generic-ehci";
220 reg = <0x0 0xfe380000 0x0 0x20000>; 246 reg = <0x0 0xfe380000 0x0 0x20000>;
@@ -272,6 +298,96 @@
272 }; 298 };
273 }; 299 };
274 300
301 i2c1: i2c@ff110000 {
302 compatible = "rockchip,rk3399-i2c";
303 reg = <0x0 0xff110000 0x0 0x1000>;
304 assigned-clocks = <&cru SCLK_I2C1>;
305 assigned-clock-rates = <200000000>;
306 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
307 clock-names = "i2c", "pclk";
308 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&i2c1_xfer>;
311 #address-cells = <1>;
312 #size-cells = <0>;
313 status = "disabled";
314 };
315
316 i2c2: i2c@ff120000 {
317 compatible = "rockchip,rk3399-i2c";
318 reg = <0x0 0xff120000 0x0 0x1000>;
319 assigned-clocks = <&cru SCLK_I2C2>;
320 assigned-clock-rates = <200000000>;
321 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
322 clock-names = "i2c", "pclk";
323 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
324 pinctrl-names = "default";
325 pinctrl-0 = <&i2c2_xfer>;
326 #address-cells = <1>;
327 #size-cells = <0>;
328 status = "disabled";
329 };
330
331 i2c3: i2c@ff130000 {
332 compatible = "rockchip,rk3399-i2c";
333 reg = <0x0 0xff130000 0x0 0x1000>;
334 assigned-clocks = <&cru SCLK_I2C3>;
335 assigned-clock-rates = <200000000>;
336 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
337 clock-names = "i2c", "pclk";
338 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
339 pinctrl-names = "default";
340 pinctrl-0 = <&i2c3_xfer>;
341 #address-cells = <1>;
342 #size-cells = <0>;
343 status = "disabled";
344 };
345
346 i2c5: i2c@ff140000 {
347 compatible = "rockchip,rk3399-i2c";
348 reg = <0x0 0xff140000 0x0 0x1000>;
349 assigned-clocks = <&cru SCLK_I2C5>;
350 assigned-clock-rates = <200000000>;
351 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
352 clock-names = "i2c", "pclk";
353 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
354 pinctrl-names = "default";
355 pinctrl-0 = <&i2c5_xfer>;
356 #address-cells = <1>;
357 #size-cells = <0>;
358 status = "disabled";
359 };
360
361 i2c6: i2c@ff150000 {
362 compatible = "rockchip,rk3399-i2c";
363 reg = <0x0 0xff150000 0x0 0x1000>;
364 assigned-clocks = <&cru SCLK_I2C6>;
365 assigned-clock-rates = <200000000>;
366 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
367 clock-names = "i2c", "pclk";
368 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
369 pinctrl-names = "default";
370 pinctrl-0 = <&i2c6_xfer>;
371 #address-cells = <1>;
372 #size-cells = <0>;
373 status = "disabled";
374 };
375
376 i2c7: i2c@ff160000 {
377 compatible = "rockchip,rk3399-i2c";
378 reg = <0x0 0xff160000 0x0 0x1000>;
379 assigned-clocks = <&cru SCLK_I2C7>;
380 assigned-clock-rates = <200000000>;
381 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
382 clock-names = "i2c", "pclk";
383 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
384 pinctrl-names = "default";
385 pinctrl-0 = <&i2c7_xfer>;
386 #address-cells = <1>;
387 #size-cells = <0>;
388 status = "disabled";
389 };
390
275 uart0: serial@ff180000 { 391 uart0: serial@ff180000 {
276 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 392 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
277 reg = <0x0 0xff180000 0x0 0x100>; 393 reg = <0x0 0xff180000 0x0 0x100>;
@@ -389,9 +505,105 @@
389 status = "disabled"; 505 status = "disabled";
390 }; 506 };
391 507
508 thermal-zones {
509 cpu_thermal: cpu {
510 polling-delay-passive = <100>;
511 polling-delay = <1000>;
512
513 thermal-sensors = <&tsadc 0>;
514
515 trips {
516 cpu_alert0: cpu_alert0 {
517 temperature = <70000>;
518 hysteresis = <2000>;
519 type = "passive";
520 };
521 cpu_alert1: cpu_alert1 {
522 temperature = <75000>;
523 hysteresis = <2000>;
524 type = "passive";
525 };
526 cpu_crit: cpu_crit {
527 temperature = <95000>;
528 hysteresis = <2000>;
529 type = "critical";
530 };
531 };
532
533 cooling-maps {
534 map0 {
535 trip = <&cpu_alert0>;
536 cooling-device =
537 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
538 };
539 map1 {
540 trip = <&cpu_alert1>;
541 cooling-device =
542 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
543 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
544 };
545 };
546 };
547
548 gpu_thermal: gpu {
549 polling-delay-passive = <100>;
550 polling-delay = <1000>;
551
552 thermal-sensors = <&tsadc 1>;
553
554 trips {
555 gpu_alert0: gpu_alert0 {
556 temperature = <75000>;
557 hysteresis = <2000>;
558 type = "passive";
559 };
560 gpu_crit: gpu_crit {
561 temperature = <95000>;
562 hysteresis = <2000>;
563 type = "critical";
564 };
565 };
566
567 cooling-maps {
568 map0 {
569 trip = <&gpu_alert0>;
570 cooling-device =
571 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
572 };
573 };
574 };
575 };
576
577 tsadc: tsadc@ff260000 {
578 compatible = "rockchip,rk3399-tsadc";
579 reg = <0x0 0xff260000 0x0 0x100>;
580 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
581 assigned-clocks = <&cru SCLK_TSADC>;
582 assigned-clock-rates = <750000>;
583 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
584 clock-names = "tsadc", "apb_pclk";
585 resets = <&cru SRST_TSADC>;
586 reset-names = "tsadc-apb";
587 rockchip,grf = <&grf>;
588 rockchip,hw-tshut-temp = <95000>;
589 pinctrl-names = "init", "default", "sleep";
590 pinctrl-0 = <&otp_gpio>;
591 pinctrl-1 = <&otp_out>;
592 pinctrl-2 = <&otp_gpio>;
593 #thermal-sensor-cells = <1>;
594 status = "disabled";
595 };
596
392 pmugrf: syscon@ff320000 { 597 pmugrf: syscon@ff320000 {
393 compatible = "rockchip,rk3399-pmugrf", "syscon"; 598 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
394 reg = <0x0 0xff320000 0x0 0x1000>; 599 reg = <0x0 0xff320000 0x0 0x1000>;
600 #address-cells = <1>;
601 #size-cells = <1>;
602
603 pmu_io_domains: io-domains {
604 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
605 status = "disabled";
606 };
395 }; 607 };
396 608
397 spi3: spi@ff350000 { 609 spi3: spi@ff350000 {
@@ -420,6 +632,51 @@
420 status = "disabled"; 632 status = "disabled";
421 }; 633 };
422 634
635 i2c0: i2c@ff3c0000 {
636 compatible = "rockchip,rk3399-i2c";
637 reg = <0x0 0xff3c0000 0x0 0x1000>;
638 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
639 assigned-clock-rates = <200000000>;
640 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
641 clock-names = "i2c", "pclk";
642 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
643 pinctrl-names = "default";
644 pinctrl-0 = <&i2c0_xfer>;
645 #address-cells = <1>;
646 #size-cells = <0>;
647 status = "disabled";
648 };
649
650 i2c4: i2c@ff3d0000 {
651 compatible = "rockchip,rk3399-i2c";
652 reg = <0x0 0xff3d0000 0x0 0x1000>;
653 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
654 assigned-clock-rates = <200000000>;
655 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
656 clock-names = "i2c", "pclk";
657 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
658 pinctrl-names = "default";
659 pinctrl-0 = <&i2c4_xfer>;
660 #address-cells = <1>;
661 #size-cells = <0>;
662 status = "disabled";
663 };
664
665 i2c8: i2c@ff3e0000 {
666 compatible = "rockchip,rk3399-i2c";
667 reg = <0x0 0xff3e0000 0x0 0x1000>;
668 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
669 assigned-clock-rates = <200000000>;
670 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
671 clock-names = "i2c", "pclk";
672 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
673 pinctrl-names = "default";
674 pinctrl-0 = <&i2c8_xfer>;
675 #address-cells = <1>;
676 #size-cells = <0>;
677 status = "disabled";
678 };
679
423 pwm0: pwm@ff420000 { 680 pwm0: pwm@ff420000 {
424 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 681 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
425 reg = <0x0 0xff420000 0x0 0x10>; 682 reg = <0x0 0xff420000 0x0 0x10>;
@@ -478,11 +735,43 @@
478 reg = <0x0 0xff760000 0x0 0x1000>; 735 reg = <0x0 0xff760000 0x0 0x1000>;
479 #clock-cells = <1>; 736 #clock-cells = <1>;
480 #reset-cells = <1>; 737 #reset-cells = <1>;
738 assigned-clocks =
739 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
740 <&cru PLL_NPLL>,
741 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
742 <&cru PCLK_PERIHP>,
743 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
744 <&cru PCLK_PERILP0>,
745 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
746 assigned-clock-rates =
747 <594000000>, <800000000>,
748 <1000000000>,
749 <150000000>, <75000000>,
750 <37500000>,
751 <100000000>, <100000000>,
752 <50000000>,
753 <100000000>, <50000000>;
481 }; 754 };
482 755
483 grf: syscon@ff770000 { 756 grf: syscon@ff770000 {
484 compatible = "rockchip,rk3399-grf", "syscon"; 757 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
485 reg = <0x0 0xff770000 0x0 0x10000>; 758 reg = <0x0 0xff770000 0x0 0x10000>;
759 #address-cells = <1>;
760 #size-cells = <1>;
761
762 io_domains: io-domains {
763 compatible = "rockchip,rk3399-io-voltage-domain";
764 status = "disabled";
765 };
766
767 emmc_phy: phy@f780 {
768 compatible = "rockchip,rk3399-emmc-phy";
769 reg = <0xf780 0x24>;
770 clocks = <&sdhci>;
771 clock-names = "emmcclk";
772 #phy-cells = <0>;
773 status = "disabled";
774 };
486 }; 775 };
487 776
488 watchdog@ff840000 { 777 watchdog@ff840000 {
@@ -764,6 +1053,16 @@
764 }; 1053 };
765 }; 1054 };
766 1055
1056 sleep {
1057 ap_pwroff: ap-pwroff {
1058 rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>;
1059 };
1060
1061 ddrio_pwroff: ddrio-pwroff {
1062 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1063 };
1064 };
1065
767 spdif { 1066 spdif {
768 spdif_bus: spdif-bus { 1067 spdif_bus: spdif-bus {
769 rockchip,pins = 1068 rockchip,pins =
@@ -889,6 +1188,16 @@
889 }; 1188 };
890 }; 1189 };
891 1190
1191 tsadc {
1192 otp_gpio: otp-gpio {
1193 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1194 };
1195
1196 otp_out: otp-out {
1197 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1198 };
1199 };
1200
892 uart0 { 1201 uart0 {
893 uart0_xfer: uart0-xfer { 1202 uart0_xfer: uart0-xfer {
894 rockchip,pins = 1203 rockchip,pins =
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
index 95328808e3c1..c223915f0907 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
@@ -42,6 +42,8 @@
42 * OTHER DEALINGS IN THE SOFTWARE. 42 * OTHER DEALINGS IN THE SOFTWARE.
43 */ 43 */
44 44
45/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */
46
45/ { 47/ {
46 compatible = "socionext,ph1-ld20"; 48 compatible = "socionext,ph1-ld20";
47 #address-cells = <2>; 49 #address-cells = <2>;
@@ -77,7 +79,7 @@
77 compatible = "arm,cortex-a72", "arm,armv8"; 79 compatible = "arm,cortex-a72", "arm,armv8";
78 reg = <0 0x000>; 80 reg = <0 0x000>;
79 enable-method = "spin-table"; 81 enable-method = "spin-table";
80 cpu-release-addr = <0 0x80000100>; 82 cpu-release-addr = <0 0x80000000>;
81 }; 83 };
82 84
83 cpu1: cpu@1 { 85 cpu1: cpu@1 {
@@ -85,7 +87,7 @@
85 compatible = "arm,cortex-a72", "arm,armv8"; 87 compatible = "arm,cortex-a72", "arm,armv8";
86 reg = <0 0x001>; 88 reg = <0 0x001>;
87 enable-method = "spin-table"; 89 enable-method = "spin-table";
88 cpu-release-addr = <0 0x80000100>; 90 cpu-release-addr = <0 0x80000000>;
89 }; 91 };
90 92
91 cpu2: cpu@100 { 93 cpu2: cpu@100 {
@@ -93,7 +95,7 @@
93 compatible = "arm,cortex-a53", "arm,armv8"; 95 compatible = "arm,cortex-a53", "arm,armv8";
94 reg = <0 0x100>; 96 reg = <0 0x100>;
95 enable-method = "spin-table"; 97 enable-method = "spin-table";
96 cpu-release-addr = <0 0x80000100>; 98 cpu-release-addr = <0 0x80000000>;
97 }; 99 };
98 100
99 cpu3: cpu@101 { 101 cpu3: cpu@101 {
@@ -101,7 +103,7 @@
101 compatible = "arm,cortex-a53", "arm,armv8"; 103 compatible = "arm,cortex-a53", "arm,armv8";
102 reg = <0 0x101>; 104 reg = <0 0x101>;
103 enable-method = "spin-table"; 105 enable-method = "spin-table";
104 cpu-release-addr = <0 0x80000100>; 106 cpu-release-addr = <0 0x80000000>;
105 }; 107 };
106 }; 108 };
107 109
@@ -264,9 +266,13 @@
264 reg = <0x59801000 0x400>; 266 reg = <0x59801000 0x400>;
265 }; 267 };
266 268
267 pinctrl: pinctrl@5f801000 { 269 soc-glue@5f800000 {
268 compatible = "socionext,ph1-ld20-pinctrl", "syscon"; 270 compatible = "simple-mfd", "syscon";
269 reg = <0x5f801000 0xe00>; 271 reg = <0x5f800000 0x2000>;
272
273 pinctrl: pinctrl {
274 compatible = "socionext,uniphier-ld20-pinctrl";
275 };
270 }; 276 };
271 277
272 gic: interrupt-controller@5fe00000 { 278 gic: interrupt-controller@5fe00000 {
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-11 07:04:25 -0400